4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
23 #include "cpu_loop-common.h"
27 # ifdef TARGET_ABI_MIPSO32
28 # define MIPS_SYSCALL_NUMBER_UNUSED -1
29 static const int8_t mips_syscall_args
[] = {
30 #include "syscall-args-o32.c.inc"
40 static int do_break(CPUMIPSState
*env
, target_siginfo_t
*info
,
48 info
->si_signo
= TARGET_SIGFPE
;
50 info
->si_code
= (code
== BRK_OVERFLOW
) ? FPE_INTOVF
: FPE_INTDIV
;
51 queue_signal(env
, info
->si_signo
, QEMU_SI_FAULT
, &*info
);
55 info
->si_signo
= TARGET_SIGTRAP
;
57 queue_signal(env
, info
->si_signo
, QEMU_SI_FAULT
, &*info
);
65 void cpu_loop(CPUMIPSState
*env
)
67 CPUState
*cs
= env_cpu(env
);
68 target_siginfo_t info
;
71 # ifdef TARGET_ABI_MIPSO32
72 unsigned int syscall_num
;
77 trapnr
= cpu_exec(cs
);
79 process_queued_cpu_work(cs
);
83 env
->active_tc
.PC
+= 4;
84 # ifdef TARGET_ABI_MIPSO32
85 syscall_num
= env
->active_tc
.gpr
[2] - 4000;
86 if (syscall_num
>= sizeof(mips_syscall_args
)) {
87 /* syscall_num is larger that any defined for MIPS O32 */
89 } else if (mips_syscall_args
[syscall_num
] ==
90 MIPS_SYSCALL_NUMBER_UNUSED
) {
91 /* syscall_num belongs to the range not defined for MIPS O32 */
94 /* syscall_num is valid */
97 abi_ulong arg5
= 0, arg6
= 0, arg7
= 0, arg8
= 0;
99 nb_args
= mips_syscall_args
[syscall_num
];
100 sp_reg
= env
->active_tc
.gpr
[29];
102 /* these arguments are taken from the stack */
104 if ((ret
= get_user_ual(arg8
, sp_reg
+ 28)) != 0) {
109 if ((ret
= get_user_ual(arg7
, sp_reg
+ 24)) != 0) {
114 if ((ret
= get_user_ual(arg6
, sp_reg
+ 20)) != 0) {
119 if ((ret
= get_user_ual(arg5
, sp_reg
+ 16)) != 0) {
126 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
127 env
->active_tc
.gpr
[4],
128 env
->active_tc
.gpr
[5],
129 env
->active_tc
.gpr
[6],
130 env
->active_tc
.gpr
[7],
131 arg5
, arg6
, arg7
, arg8
);
135 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
136 env
->active_tc
.gpr
[4], env
->active_tc
.gpr
[5],
137 env
->active_tc
.gpr
[6], env
->active_tc
.gpr
[7],
138 env
->active_tc
.gpr
[8], env
->active_tc
.gpr
[9],
139 env
->active_tc
.gpr
[10], env
->active_tc
.gpr
[11]);
141 if (ret
== -TARGET_ERESTARTSYS
) {
142 env
->active_tc
.PC
-= 4;
145 if (ret
== -TARGET_QEMU_ESIGRETURN
) {
146 /* Returning from a successful sigreturn syscall.
147 Avoid clobbering register state. */
150 if ((abi_ulong
)ret
>= (abi_ulong
)-1133) {
151 env
->active_tc
.gpr
[7] = 1; /* error flag */
154 env
->active_tc
.gpr
[7] = 0; /* error flag */
156 env
->active_tc
.gpr
[2] = ret
;
162 info
.si_signo
= TARGET_SIGSEGV
;
164 /* XXX: check env->error_code */
165 info
.si_code
= TARGET_SEGV_MAPERR
;
166 info
._sifields
._sigfault
._addr
= env
->CP0_BadVAddr
;
167 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
171 info
.si_signo
= TARGET_SIGILL
;
174 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
177 /* just indicate that signals should be handled asap */
180 info
.si_signo
= TARGET_SIGTRAP
;
182 info
.si_code
= TARGET_TRAP_BRKPT
;
183 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
186 info
.si_signo
= TARGET_SIGILL
;
188 info
.si_code
= TARGET_ILL_ILLOPC
;
189 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
192 info
.si_signo
= TARGET_SIGFPE
;
194 info
.si_code
= TARGET_FPE_FLTUNK
;
195 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_INVALID
) {
196 info
.si_code
= TARGET_FPE_FLTINV
;
197 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_DIV0
) {
198 info
.si_code
= TARGET_FPE_FLTDIV
;
199 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_OVERFLOW
) {
200 info
.si_code
= TARGET_FPE_FLTOVF
;
201 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_UNDERFLOW
) {
202 info
.si_code
= TARGET_FPE_FLTUND
;
203 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_INEXACT
) {
204 info
.si_code
= TARGET_FPE_FLTRES
;
206 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
208 /* The code below was inspired by the MIPS Linux kernel trap
209 * handling code in arch/mips/kernel/traps.c.
213 abi_ulong trap_instr
;
216 if (env
->hflags
& MIPS_HFLAG_M16
) {
217 if (env
->insn_flags
& ASE_MICROMIPS
) {
219 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
224 if ((trap_instr
>> 10) == 0x11) {
225 /* 16-bit instruction */
226 code
= trap_instr
& 0xf;
228 /* 32-bit instruction */
231 ret
= get_user_u16(instr_lo
,
232 env
->active_tc
.PC
+ 2);
236 trap_instr
= (trap_instr
<< 16) | instr_lo
;
237 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
238 /* Unfortunately, microMIPS also suffers from
239 the old assembler bug... */
240 if (code
>= (1 << 10)) {
246 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
250 code
= (trap_instr
>> 6) & 0x3f;
253 ret
= get_user_u32(trap_instr
, env
->active_tc
.PC
);
258 /* As described in the original Linux kernel code, the
259 * below checks on 'code' are to work around an old
262 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
263 if (code
>= (1 << 10)) {
268 if (do_break(env
, &info
, code
) != 0) {
275 abi_ulong trap_instr
;
276 unsigned int code
= 0;
278 if (env
->hflags
& MIPS_HFLAG_M16
) {
282 ret
= get_user_u16(instr
[0], env
->active_tc
.PC
) ||
283 get_user_u16(instr
[1], env
->active_tc
.PC
+ 2);
285 trap_instr
= (instr
[0] << 16) | instr
[1];
287 ret
= get_user_u32(trap_instr
, env
->active_tc
.PC
);
294 /* The immediate versions don't provide a code. */
295 if (!(trap_instr
& 0xFC000000)) {
296 if (env
->hflags
& MIPS_HFLAG_M16
) {
298 code
= ((trap_instr
>> 12) & ((1 << 4) - 1));
300 code
= ((trap_instr
>> 6) & ((1 << 10) - 1));
304 if (do_break(env
, &info
, code
) != 0) {
310 cpu_exec_step_atomic(cs
);
314 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
317 process_pending_signals(env
);
321 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
323 CPUState
*cpu
= env_cpu(env
);
324 TaskState
*ts
= cpu
->opaque
;
325 struct image_info
*info
= ts
->info
;
336 static const struct mode_req fpu_reqs
[] = {
337 [MIPS_ABI_FP_ANY
] = { true, true, true, true, true },
338 [MIPS_ABI_FP_DOUBLE
] = { false, false, false, true, true },
339 [MIPS_ABI_FP_SINGLE
] = { true, false, false, false, false },
340 [MIPS_ABI_FP_SOFT
] = { false, true, false, false, false },
341 [MIPS_ABI_FP_OLD_64
] = { false, false, false, false, false },
342 [MIPS_ABI_FP_XX
] = { false, false, true, true, true },
343 [MIPS_ABI_FP_64
] = { false, false, true, false, false },
344 [MIPS_ABI_FP_64A
] = { false, false, true, false, true }
348 * Mode requirements when .MIPS.abiflags is not present in the ELF.
349 * Not present means that everything is acceptable except FR1.
351 static struct mode_req none_req
= { true, true, false, true, true };
353 struct mode_req prog_req
;
354 struct mode_req interp_req
;
356 for(i
= 0; i
< 32; i
++) {
357 env
->active_tc
.gpr
[i
] = regs
->regs
[i
];
359 env
->active_tc
.PC
= regs
->cp0_epc
& ~(target_ulong
)1;
360 if (regs
->cp0_epc
& 1) {
361 env
->hflags
|= MIPS_HFLAG_M16
;
364 #ifdef TARGET_ABI_MIPSO32
365 # define MAX_FP_ABI MIPS_ABI_FP_64A
367 # define MAX_FP_ABI MIPS_ABI_FP_SOFT
369 if ((info
->fp_abi
> MAX_FP_ABI
&& info
->fp_abi
!= MIPS_ABI_FP_UNKNOWN
)
370 || (info
->interp_fp_abi
> MAX_FP_ABI
&&
371 info
->interp_fp_abi
!= MIPS_ABI_FP_UNKNOWN
)) {
372 fprintf(stderr
, "qemu: Unexpected FPU mode\n");
376 prog_req
= (info
->fp_abi
== MIPS_ABI_FP_UNKNOWN
) ? none_req
377 : fpu_reqs
[info
->fp_abi
];
378 interp_req
= (info
->interp_fp_abi
== MIPS_ABI_FP_UNKNOWN
) ? none_req
379 : fpu_reqs
[info
->interp_fp_abi
];
381 prog_req
.single
&= interp_req
.single
;
382 prog_req
.soft
&= interp_req
.soft
;
383 prog_req
.fr1
&= interp_req
.fr1
;
384 prog_req
.frdefault
&= interp_req
.frdefault
;
385 prog_req
.fre
&= interp_req
.fre
;
387 bool cpu_has_mips_r2_r6
= env
->insn_flags
& ISA_MIPS32R2
||
388 env
->insn_flags
& ISA_MIPS64R2
||
389 env
->insn_flags
& ISA_MIPS32R6
||
390 env
->insn_flags
& ISA_MIPS64R6
;
392 if (prog_req
.fre
&& !prog_req
.frdefault
&& !prog_req
.fr1
) {
393 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
394 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
395 env
->hflags
|= MIPS_HFLAG_FRE
;
397 } else if ((prog_req
.fr1
&& prog_req
.frdefault
) ||
398 (prog_req
.single
&& !prog_req
.frdefault
)) {
399 if ((env
->active_fpu
.fcr0
& (1 << FCR0_F64
)
400 && cpu_has_mips_r2_r6
) || prog_req
.fr1
) {
401 env
->CP0_Status
|= (1 << CP0St_FR
);
402 env
->hflags
|= MIPS_HFLAG_F64
;
404 } else if (!prog_req
.fre
&& !prog_req
.frdefault
&&
405 !prog_req
.fr1
&& !prog_req
.single
&& !prog_req
.soft
) {
406 fprintf(stderr
, "qemu: Can't find a matching FPU mode\n");
410 if (env
->insn_flags
& ISA_NANOMIPS32
) {
413 if (((info
->elf_flags
& EF_MIPS_NAN2008
) != 0) !=
414 ((env
->active_fpu
.fcr31
& (1 << FCR31_NAN2008
)) != 0)) {
415 if ((env
->active_fpu
.fcr31_rw_bitmask
&
416 (1 << FCR31_NAN2008
)) == 0) {
417 fprintf(stderr
, "ELF binary's NaN mode not supported by CPU\n");
420 if ((info
->elf_flags
& EF_MIPS_NAN2008
) != 0) {
421 env
->active_fpu
.fcr31
|= (1 << FCR31_NAN2008
);
423 env
->active_fpu
.fcr31
&= ~(1 << FCR31_NAN2008
);
425 restore_snan_bit_mode(env
);