2 * device quirks for PCI devices
4 * Copyright Red Hat, Inc. 2012-2015
7 * Alex Williamson <alex.williamson@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include CONFIG_DEVICES
15 #include "exec/memop.h"
16 #include "qemu/units.h"
17 #include "qemu/error-report.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/module.h"
20 #include "qemu/range.h"
21 #include "qapi/error.h"
22 #include "qapi/visitor.h"
23 #include <sys/ioctl.h>
25 #include "hw/nvram/fw_cfg.h"
26 #include "hw/qdev-properties.h"
31 * List of device ids/vendor ids for which to disable
32 * option rom loading. This avoids the guest hangs during rom
33 * execution as noticed with the BCM 57810 card for lack of a
34 * more better way to handle such issues.
35 * The user can still override by specifying a romfile or
37 * Please see https://bugs.launchpad.net/qemu/+bug/1284874
38 * for an analysis of the 57810 card hang. When adding
39 * a new vendor id/device id combination below, please also add
40 * your card/environment details and information that could
41 * help in debugging to the bug tracking this issue
47 { 0x14e4, 0x168e }, /* Broadcom BCM 57810 */
50 bool vfio_blacklist_opt_rom(VFIOPCIDevice
*vdev
)
54 for (i
= 0 ; i
< ARRAY_SIZE(romblacklist
); i
++) {
55 if (vfio_pci_is(vdev
, romblacklist
[i
].vendor
, romblacklist
[i
].device
)) {
56 trace_vfio_quirk_rom_blacklisted(vdev
->vbasedev
.name
,
57 romblacklist
[i
].vendor
,
58 romblacklist
[i
].device
);
66 * Device specific region quirks (mostly backdoors to PCI config space)
70 * The generic window quirks operate on an address and data register,
71 * vfio_generic_window_address_quirk handles the address register and
72 * vfio_generic_window_data_quirk handles the data register. These ops
73 * pass reads and writes through to hardware until a value matching the
74 * stored address match/mask is written. When this occurs, the data
75 * register access emulated PCI config space for the device rather than
76 * passing through accesses. This enables devices where PCI config space
77 * is accessible behind a window register to maintain the virtualization
78 * provided through vfio.
80 typedef struct VFIOConfigWindowMatch
{
83 } VFIOConfigWindowMatch
;
85 typedef struct VFIOConfigWindowQuirk
{
86 struct VFIOPCIDevice
*vdev
;
90 uint32_t address_offset
;
96 MemoryRegion
*addr_mem
;
97 MemoryRegion
*data_mem
;
100 VFIOConfigWindowMatch matches
[];
101 } VFIOConfigWindowQuirk
;
103 static uint64_t vfio_generic_window_quirk_address_read(void *opaque
,
107 VFIOConfigWindowQuirk
*window
= opaque
;
108 VFIOPCIDevice
*vdev
= window
->vdev
;
110 return vfio_region_read(&vdev
->bars
[window
->bar
].region
,
111 addr
+ window
->address_offset
, size
);
114 static void vfio_generic_window_quirk_address_write(void *opaque
, hwaddr addr
,
118 VFIOConfigWindowQuirk
*window
= opaque
;
119 VFIOPCIDevice
*vdev
= window
->vdev
;
122 window
->window_enabled
= false;
124 vfio_region_write(&vdev
->bars
[window
->bar
].region
,
125 addr
+ window
->address_offset
, data
, size
);
127 for (i
= 0; i
< window
->nr_matches
; i
++) {
128 if ((data
& ~window
->matches
[i
].mask
) == window
->matches
[i
].match
) {
129 window
->window_enabled
= true;
130 window
->address_val
= data
& window
->matches
[i
].mask
;
131 trace_vfio_quirk_generic_window_address_write(vdev
->vbasedev
.name
,
132 memory_region_name(window
->addr_mem
), data
);
138 static const MemoryRegionOps vfio_generic_window_address_quirk
= {
139 .read
= vfio_generic_window_quirk_address_read
,
140 .write
= vfio_generic_window_quirk_address_write
,
141 .endianness
= DEVICE_LITTLE_ENDIAN
,
144 static uint64_t vfio_generic_window_quirk_data_read(void *opaque
,
145 hwaddr addr
, unsigned size
)
147 VFIOConfigWindowQuirk
*window
= opaque
;
148 VFIOPCIDevice
*vdev
= window
->vdev
;
151 /* Always read data reg, discard if window enabled */
152 data
= vfio_region_read(&vdev
->bars
[window
->bar
].region
,
153 addr
+ window
->data_offset
, size
);
155 if (window
->window_enabled
) {
156 data
= vfio_pci_read_config(&vdev
->pdev
, window
->address_val
, size
);
157 trace_vfio_quirk_generic_window_data_read(vdev
->vbasedev
.name
,
158 memory_region_name(window
->data_mem
), data
);
164 static void vfio_generic_window_quirk_data_write(void *opaque
, hwaddr addr
,
165 uint64_t data
, unsigned size
)
167 VFIOConfigWindowQuirk
*window
= opaque
;
168 VFIOPCIDevice
*vdev
= window
->vdev
;
170 if (window
->window_enabled
) {
171 vfio_pci_write_config(&vdev
->pdev
, window
->address_val
, data
, size
);
172 trace_vfio_quirk_generic_window_data_write(vdev
->vbasedev
.name
,
173 memory_region_name(window
->data_mem
), data
);
177 vfio_region_write(&vdev
->bars
[window
->bar
].region
,
178 addr
+ window
->data_offset
, data
, size
);
181 static const MemoryRegionOps vfio_generic_window_data_quirk
= {
182 .read
= vfio_generic_window_quirk_data_read
,
183 .write
= vfio_generic_window_quirk_data_write
,
184 .endianness
= DEVICE_LITTLE_ENDIAN
,
188 * The generic mirror quirk handles devices which expose PCI config space
189 * through a region within a BAR. When enabled, reads and writes are
190 * redirected through to emulated PCI config space. XXX if PCI config space
191 * used memory regions, this could just be an alias.
193 typedef struct VFIOConfigMirrorQuirk
{
194 struct VFIOPCIDevice
*vdev
;
199 } VFIOConfigMirrorQuirk
;
201 static uint64_t vfio_generic_quirk_mirror_read(void *opaque
,
202 hwaddr addr
, unsigned size
)
204 VFIOConfigMirrorQuirk
*mirror
= opaque
;
205 VFIOPCIDevice
*vdev
= mirror
->vdev
;
208 /* Read and discard in case the hardware cares */
209 (void)vfio_region_read(&vdev
->bars
[mirror
->bar
].region
,
210 addr
+ mirror
->offset
, size
);
212 data
= vfio_pci_read_config(&vdev
->pdev
, addr
, size
);
213 trace_vfio_quirk_generic_mirror_read(vdev
->vbasedev
.name
,
214 memory_region_name(mirror
->mem
),
219 static void vfio_generic_quirk_mirror_write(void *opaque
, hwaddr addr
,
220 uint64_t data
, unsigned size
)
222 VFIOConfigMirrorQuirk
*mirror
= opaque
;
223 VFIOPCIDevice
*vdev
= mirror
->vdev
;
225 vfio_pci_write_config(&vdev
->pdev
, addr
, data
, size
);
226 trace_vfio_quirk_generic_mirror_write(vdev
->vbasedev
.name
,
227 memory_region_name(mirror
->mem
),
231 static const MemoryRegionOps vfio_generic_mirror_quirk
= {
232 .read
= vfio_generic_quirk_mirror_read
,
233 .write
= vfio_generic_quirk_mirror_write
,
234 .endianness
= DEVICE_LITTLE_ENDIAN
,
237 /* Is range1 fully contained within range2? */
238 static bool vfio_range_contained(uint64_t first1
, uint64_t len1
,
239 uint64_t first2
, uint64_t len2
) {
240 return (first1
>= first2
&& first1
+ len1
<= first2
+ len2
);
243 #define PCI_VENDOR_ID_ATI 0x1002
246 * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
247 * through VGA register 0x3c3. On newer cards, the I/O port BAR is always
248 * BAR4 (older cards like the X550 used BAR1, but we don't care to support
249 * those). Note that on bare metal, a read of 0x3c3 doesn't always return the
250 * I/O port BAR address. Originally this was coded to return the virtual BAR
251 * address only if the physical register read returns the actual BAR address,
252 * but users have reported greater success if we return the virtual address
255 static uint64_t vfio_ati_3c3_quirk_read(void *opaque
,
256 hwaddr addr
, unsigned size
)
258 VFIOPCIDevice
*vdev
= opaque
;
259 uint64_t data
= vfio_pci_read_config(&vdev
->pdev
,
260 PCI_BASE_ADDRESS_4
+ 1, size
);
262 trace_vfio_quirk_ati_3c3_read(vdev
->vbasedev
.name
, data
);
267 static const MemoryRegionOps vfio_ati_3c3_quirk
= {
268 .read
= vfio_ati_3c3_quirk_read
,
269 .endianness
= DEVICE_LITTLE_ENDIAN
,
272 VFIOQuirk
*vfio_quirk_alloc(int nr_mem
)
274 VFIOQuirk
*quirk
= g_new0(VFIOQuirk
, 1);
275 QLIST_INIT(&quirk
->ioeventfds
);
276 quirk
->mem
= g_new0(MemoryRegion
, nr_mem
);
277 quirk
->nr_mem
= nr_mem
;
282 static void vfio_ioeventfd_exit(VFIOPCIDevice
*vdev
, VFIOIOEventFD
*ioeventfd
)
284 QLIST_REMOVE(ioeventfd
, next
);
285 memory_region_del_eventfd(ioeventfd
->mr
, ioeventfd
->addr
, ioeventfd
->size
,
286 true, ioeventfd
->data
, &ioeventfd
->e
);
288 if (ioeventfd
->vfio
) {
289 struct vfio_device_ioeventfd vfio_ioeventfd
;
291 vfio_ioeventfd
.argsz
= sizeof(vfio_ioeventfd
);
292 vfio_ioeventfd
.flags
= ioeventfd
->size
;
293 vfio_ioeventfd
.data
= ioeventfd
->data
;
294 vfio_ioeventfd
.offset
= ioeventfd
->region
->fd_offset
+
295 ioeventfd
->region_addr
;
296 vfio_ioeventfd
.fd
= -1;
298 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_IOEVENTFD
, &vfio_ioeventfd
)) {
299 error_report("Failed to remove vfio ioeventfd for %s+0x%"
300 HWADDR_PRIx
"[%d]:0x%"PRIx64
" (%m)",
301 memory_region_name(ioeventfd
->mr
), ioeventfd
->addr
,
302 ioeventfd
->size
, ioeventfd
->data
);
305 qemu_set_fd_handler(event_notifier_get_fd(&ioeventfd
->e
),
309 event_notifier_cleanup(&ioeventfd
->e
);
310 trace_vfio_ioeventfd_exit(memory_region_name(ioeventfd
->mr
),
311 (uint64_t)ioeventfd
->addr
, ioeventfd
->size
,
316 static void vfio_drop_dynamic_eventfds(VFIOPCIDevice
*vdev
, VFIOQuirk
*quirk
)
318 VFIOIOEventFD
*ioeventfd
, *tmp
;
320 QLIST_FOREACH_SAFE(ioeventfd
, &quirk
->ioeventfds
, next
, tmp
) {
321 if (ioeventfd
->dynamic
) {
322 vfio_ioeventfd_exit(vdev
, ioeventfd
);
327 static void vfio_ioeventfd_handler(void *opaque
)
329 VFIOIOEventFD
*ioeventfd
= opaque
;
331 if (event_notifier_test_and_clear(&ioeventfd
->e
)) {
332 vfio_region_write(ioeventfd
->region
, ioeventfd
->region_addr
,
333 ioeventfd
->data
, ioeventfd
->size
);
334 trace_vfio_ioeventfd_handler(memory_region_name(ioeventfd
->mr
),
335 (uint64_t)ioeventfd
->addr
, ioeventfd
->size
,
340 static VFIOIOEventFD
*vfio_ioeventfd_init(VFIOPCIDevice
*vdev
,
341 MemoryRegion
*mr
, hwaddr addr
,
342 unsigned size
, uint64_t data
,
344 hwaddr region_addr
, bool dynamic
)
346 VFIOIOEventFD
*ioeventfd
;
348 if (vdev
->no_kvm_ioeventfd
) {
352 ioeventfd
= g_malloc0(sizeof(*ioeventfd
));
354 if (event_notifier_init(&ioeventfd
->e
, 0)) {
360 * MemoryRegion and relative offset, plus additional ioeventfd setup
361 * parameters for configuring and later tearing down KVM ioeventfd.
364 ioeventfd
->addr
= addr
;
365 ioeventfd
->size
= size
;
366 ioeventfd
->data
= data
;
367 ioeventfd
->dynamic
= dynamic
;
369 * VFIORegion and relative offset for implementing the userspace
370 * handler. data & size fields shared for both uses.
372 ioeventfd
->region
= region
;
373 ioeventfd
->region_addr
= region_addr
;
375 if (!vdev
->no_vfio_ioeventfd
) {
376 struct vfio_device_ioeventfd vfio_ioeventfd
;
378 vfio_ioeventfd
.argsz
= sizeof(vfio_ioeventfd
);
379 vfio_ioeventfd
.flags
= ioeventfd
->size
;
380 vfio_ioeventfd
.data
= ioeventfd
->data
;
381 vfio_ioeventfd
.offset
= ioeventfd
->region
->fd_offset
+
382 ioeventfd
->region_addr
;
383 vfio_ioeventfd
.fd
= event_notifier_get_fd(&ioeventfd
->e
);
385 ioeventfd
->vfio
= !ioctl(vdev
->vbasedev
.fd
,
386 VFIO_DEVICE_IOEVENTFD
, &vfio_ioeventfd
);
389 if (!ioeventfd
->vfio
) {
390 qemu_set_fd_handler(event_notifier_get_fd(&ioeventfd
->e
),
391 vfio_ioeventfd_handler
, NULL
, ioeventfd
);
394 memory_region_add_eventfd(ioeventfd
->mr
, ioeventfd
->addr
, ioeventfd
->size
,
395 true, ioeventfd
->data
, &ioeventfd
->e
);
396 trace_vfio_ioeventfd_init(memory_region_name(mr
), (uint64_t)addr
,
397 size
, data
, ioeventfd
->vfio
);
402 static void vfio_vga_probe_ati_3c3_quirk(VFIOPCIDevice
*vdev
)
407 * As long as the BAR is >= 256 bytes it will be aligned such that the
408 * lower byte is always zero. Filter out anything else, if it exists.
410 if (!vfio_pci_is(vdev
, PCI_VENDOR_ID_ATI
, PCI_ANY_ID
) ||
411 !vdev
->bars
[4].ioport
|| vdev
->bars
[4].region
.size
< 256) {
415 quirk
= vfio_quirk_alloc(1);
417 memory_region_init_io(quirk
->mem
, OBJECT(vdev
), &vfio_ati_3c3_quirk
, vdev
,
418 "vfio-ati-3c3-quirk", 1);
419 memory_region_add_subregion(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
].mem
,
420 3 /* offset 3 bytes from 0x3c0 */, quirk
->mem
);
422 QLIST_INSERT_HEAD(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
].quirks
,
425 trace_vfio_quirk_ati_3c3_probe(vdev
->vbasedev
.name
);
429 * Newer ATI/AMD devices, including HD5450 and HD7850, have a mirror to PCI
430 * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
431 * the MMIO space directly, but a window to this space is provided through
432 * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
433 * data register. When the address is programmed to a range of 0x4000-0x4fff
434 * PCI configuration space is available. Experimentation seems to indicate
435 * that read-only may be provided by hardware.
437 static void vfio_probe_ati_bar4_quirk(VFIOPCIDevice
*vdev
, int nr
)
440 VFIOConfigWindowQuirk
*window
;
442 /* This windows doesn't seem to be used except by legacy VGA code */
443 if (!vfio_pci_is(vdev
, PCI_VENDOR_ID_ATI
, PCI_ANY_ID
) ||
444 !vdev
->vga
|| nr
!= 4) {
448 quirk
= vfio_quirk_alloc(2);
449 window
= quirk
->data
= g_malloc0(sizeof(*window
) +
450 sizeof(VFIOConfigWindowMatch
));
452 window
->address_offset
= 0;
453 window
->data_offset
= 4;
454 window
->nr_matches
= 1;
455 window
->matches
[0].match
= 0x4000;
456 window
->matches
[0].mask
= vdev
->config_size
- 1;
458 window
->addr_mem
= &quirk
->mem
[0];
459 window
->data_mem
= &quirk
->mem
[1];
461 memory_region_init_io(window
->addr_mem
, OBJECT(vdev
),
462 &vfio_generic_window_address_quirk
, window
,
463 "vfio-ati-bar4-window-address-quirk", 4);
464 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
465 window
->address_offset
,
466 window
->addr_mem
, 1);
468 memory_region_init_io(window
->data_mem
, OBJECT(vdev
),
469 &vfio_generic_window_data_quirk
, window
,
470 "vfio-ati-bar4-window-data-quirk", 4);
471 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
473 window
->data_mem
, 1);
475 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
477 trace_vfio_quirk_ati_bar4_probe(vdev
->vbasedev
.name
);
481 * Trap the BAR2 MMIO mirror to config space as well.
483 static void vfio_probe_ati_bar2_quirk(VFIOPCIDevice
*vdev
, int nr
)
486 VFIOConfigMirrorQuirk
*mirror
;
488 /* Only enable on newer devices where BAR2 is 64bit */
489 if (!vfio_pci_is(vdev
, PCI_VENDOR_ID_ATI
, PCI_ANY_ID
) ||
490 !vdev
->vga
|| nr
!= 2 || !vdev
->bars
[2].mem64
) {
494 quirk
= vfio_quirk_alloc(1);
495 mirror
= quirk
->data
= g_malloc0(sizeof(*mirror
));
496 mirror
->mem
= quirk
->mem
;
498 mirror
->offset
= 0x4000;
501 memory_region_init_io(mirror
->mem
, OBJECT(vdev
),
502 &vfio_generic_mirror_quirk
, mirror
,
503 "vfio-ati-bar2-4000-quirk", PCI_CONFIG_SPACE_SIZE
);
504 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
505 mirror
->offset
, mirror
->mem
, 1);
507 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
509 trace_vfio_quirk_ati_bar2_probe(vdev
->vbasedev
.name
);
513 * Older ATI/AMD cards like the X550 have a similar window to that above.
514 * I/O port BAR1 provides a window to a mirror of PCI config space located
515 * in BAR2 at offset 0xf00. We don't care to support such older cards, but
516 * note it for future reference.
520 * Nvidia has several different methods to get to config space, the
521 * nouveu project has several of these documented here:
522 * https://github.com/pathscale/envytools/tree/master/hwdocs
524 * The first quirk is actually not documented in envytools and is found
525 * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an
526 * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access
527 * the mirror of PCI config space found at BAR0 offset 0x1800. The access
528 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
529 * then written to 0x3d0. Finally 0x538 is written for a read and 0x738
530 * is written for a write to 0x3d4. The BAR0 offset is then accessible
531 * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
532 * that use the I/O port BAR5 window but it doesn't hurt to leave it.
534 typedef enum {NONE
= 0, SELECT
, WINDOW
, READ
, WRITE
} VFIONvidia3d0State
;
535 static const char *nv3d0_states
[] = { "NONE", "SELECT",
536 "WINDOW", "READ", "WRITE" };
538 typedef struct VFIONvidia3d0Quirk
{
540 VFIONvidia3d0State state
;
542 } VFIONvidia3d0Quirk
;
544 static uint64_t vfio_nvidia_3d4_quirk_read(void *opaque
,
545 hwaddr addr
, unsigned size
)
547 VFIONvidia3d0Quirk
*quirk
= opaque
;
548 VFIOPCIDevice
*vdev
= quirk
->vdev
;
552 return vfio_vga_read(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
],
556 static void vfio_nvidia_3d4_quirk_write(void *opaque
, hwaddr addr
,
557 uint64_t data
, unsigned size
)
559 VFIONvidia3d0Quirk
*quirk
= opaque
;
560 VFIOPCIDevice
*vdev
= quirk
->vdev
;
561 VFIONvidia3d0State old_state
= quirk
->state
;
567 if (old_state
== NONE
) {
568 quirk
->state
= SELECT
;
569 trace_vfio_quirk_nvidia_3d0_state(vdev
->vbasedev
.name
,
570 nv3d0_states
[quirk
->state
]);
574 if (old_state
== WINDOW
) {
576 trace_vfio_quirk_nvidia_3d0_state(vdev
->vbasedev
.name
,
577 nv3d0_states
[quirk
->state
]);
581 if (old_state
== WINDOW
) {
582 quirk
->state
= WRITE
;
583 trace_vfio_quirk_nvidia_3d0_state(vdev
->vbasedev
.name
,
584 nv3d0_states
[quirk
->state
]);
589 vfio_vga_write(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
],
590 addr
+ 0x14, data
, size
);
593 static const MemoryRegionOps vfio_nvidia_3d4_quirk
= {
594 .read
= vfio_nvidia_3d4_quirk_read
,
595 .write
= vfio_nvidia_3d4_quirk_write
,
596 .endianness
= DEVICE_LITTLE_ENDIAN
,
599 static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque
,
600 hwaddr addr
, unsigned size
)
602 VFIONvidia3d0Quirk
*quirk
= opaque
;
603 VFIOPCIDevice
*vdev
= quirk
->vdev
;
604 VFIONvidia3d0State old_state
= quirk
->state
;
605 uint64_t data
= vfio_vga_read(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
],
610 if (old_state
== READ
&&
611 (quirk
->offset
& ~(PCI_CONFIG_SPACE_SIZE
- 1)) == 0x1800) {
612 uint8_t offset
= quirk
->offset
& (PCI_CONFIG_SPACE_SIZE
- 1);
614 data
= vfio_pci_read_config(&vdev
->pdev
, offset
, size
);
615 trace_vfio_quirk_nvidia_3d0_read(vdev
->vbasedev
.name
,
622 static void vfio_nvidia_3d0_quirk_write(void *opaque
, hwaddr addr
,
623 uint64_t data
, unsigned size
)
625 VFIONvidia3d0Quirk
*quirk
= opaque
;
626 VFIOPCIDevice
*vdev
= quirk
->vdev
;
627 VFIONvidia3d0State old_state
= quirk
->state
;
631 if (old_state
== SELECT
) {
632 quirk
->offset
= (uint32_t)data
;
633 quirk
->state
= WINDOW
;
634 trace_vfio_quirk_nvidia_3d0_state(vdev
->vbasedev
.name
,
635 nv3d0_states
[quirk
->state
]);
636 } else if (old_state
== WRITE
) {
637 if ((quirk
->offset
& ~(PCI_CONFIG_SPACE_SIZE
- 1)) == 0x1800) {
638 uint8_t offset
= quirk
->offset
& (PCI_CONFIG_SPACE_SIZE
- 1);
640 vfio_pci_write_config(&vdev
->pdev
, offset
, data
, size
);
641 trace_vfio_quirk_nvidia_3d0_write(vdev
->vbasedev
.name
,
647 vfio_vga_write(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
],
648 addr
+ 0x10, data
, size
);
651 static const MemoryRegionOps vfio_nvidia_3d0_quirk
= {
652 .read
= vfio_nvidia_3d0_quirk_read
,
653 .write
= vfio_nvidia_3d0_quirk_write
,
654 .endianness
= DEVICE_LITTLE_ENDIAN
,
657 static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice
*vdev
)
660 VFIONvidia3d0Quirk
*data
;
662 if (vdev
->no_geforce_quirks
||
663 !vfio_pci_is(vdev
, PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
) ||
664 !vdev
->bars
[1].region
.size
) {
668 quirk
= vfio_quirk_alloc(2);
669 quirk
->data
= data
= g_malloc0(sizeof(*data
));
672 memory_region_init_io(&quirk
->mem
[0], OBJECT(vdev
), &vfio_nvidia_3d4_quirk
,
673 data
, "vfio-nvidia-3d4-quirk", 2);
674 memory_region_add_subregion(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
].mem
,
675 0x14 /* 0x3c0 + 0x14 */, &quirk
->mem
[0]);
677 memory_region_init_io(&quirk
->mem
[1], OBJECT(vdev
), &vfio_nvidia_3d0_quirk
,
678 data
, "vfio-nvidia-3d0-quirk", 2);
679 memory_region_add_subregion(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
].mem
,
680 0x10 /* 0x3c0 + 0x10 */, &quirk
->mem
[1]);
682 QLIST_INSERT_HEAD(&vdev
->vga
->region
[QEMU_PCI_VGA_IO_HI
].quirks
,
685 trace_vfio_quirk_nvidia_3d0_probe(vdev
->vbasedev
.name
);
689 * The second quirk is documented in envytools. The I/O port BAR5 is just
690 * a set of address/data ports to the MMIO BARs. The BAR we care about is
691 * again BAR0. This backdoor is apparently a bit newer than the one above
692 * so we need to not only trap 256 bytes @0x1800, but all of PCI config
693 * space, including extended space is available at the 4k @0x88000.
695 typedef struct VFIONvidiaBAR5Quirk
{
698 MemoryRegion
*addr_mem
;
699 MemoryRegion
*data_mem
;
701 VFIOConfigWindowQuirk window
; /* last for match data */
702 } VFIONvidiaBAR5Quirk
;
704 static void vfio_nvidia_bar5_enable(VFIONvidiaBAR5Quirk
*bar5
)
706 VFIOPCIDevice
*vdev
= bar5
->window
.vdev
;
708 if (((bar5
->master
& bar5
->enable
) & 0x1) == bar5
->enabled
) {
712 bar5
->enabled
= !bar5
->enabled
;
713 trace_vfio_quirk_nvidia_bar5_state(vdev
->vbasedev
.name
,
714 bar5
->enabled
? "Enable" : "Disable");
715 memory_region_set_enabled(bar5
->addr_mem
, bar5
->enabled
);
716 memory_region_set_enabled(bar5
->data_mem
, bar5
->enabled
);
719 static uint64_t vfio_nvidia_bar5_quirk_master_read(void *opaque
,
720 hwaddr addr
, unsigned size
)
722 VFIONvidiaBAR5Quirk
*bar5
= opaque
;
723 VFIOPCIDevice
*vdev
= bar5
->window
.vdev
;
725 return vfio_region_read(&vdev
->bars
[5].region
, addr
, size
);
728 static void vfio_nvidia_bar5_quirk_master_write(void *opaque
, hwaddr addr
,
729 uint64_t data
, unsigned size
)
731 VFIONvidiaBAR5Quirk
*bar5
= opaque
;
732 VFIOPCIDevice
*vdev
= bar5
->window
.vdev
;
734 vfio_region_write(&vdev
->bars
[5].region
, addr
, data
, size
);
737 vfio_nvidia_bar5_enable(bar5
);
740 static const MemoryRegionOps vfio_nvidia_bar5_quirk_master
= {
741 .read
= vfio_nvidia_bar5_quirk_master_read
,
742 .write
= vfio_nvidia_bar5_quirk_master_write
,
743 .endianness
= DEVICE_LITTLE_ENDIAN
,
746 static uint64_t vfio_nvidia_bar5_quirk_enable_read(void *opaque
,
747 hwaddr addr
, unsigned size
)
749 VFIONvidiaBAR5Quirk
*bar5
= opaque
;
750 VFIOPCIDevice
*vdev
= bar5
->window
.vdev
;
752 return vfio_region_read(&vdev
->bars
[5].region
, addr
+ 4, size
);
755 static void vfio_nvidia_bar5_quirk_enable_write(void *opaque
, hwaddr addr
,
756 uint64_t data
, unsigned size
)
758 VFIONvidiaBAR5Quirk
*bar5
= opaque
;
759 VFIOPCIDevice
*vdev
= bar5
->window
.vdev
;
761 vfio_region_write(&vdev
->bars
[5].region
, addr
+ 4, data
, size
);
764 vfio_nvidia_bar5_enable(bar5
);
767 static const MemoryRegionOps vfio_nvidia_bar5_quirk_enable
= {
768 .read
= vfio_nvidia_bar5_quirk_enable_read
,
769 .write
= vfio_nvidia_bar5_quirk_enable_write
,
770 .endianness
= DEVICE_LITTLE_ENDIAN
,
773 static void vfio_probe_nvidia_bar5_quirk(VFIOPCIDevice
*vdev
, int nr
)
776 VFIONvidiaBAR5Quirk
*bar5
;
777 VFIOConfigWindowQuirk
*window
;
779 if (vdev
->no_geforce_quirks
||
780 !vfio_pci_is(vdev
, PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
) ||
781 !vdev
->vga
|| nr
!= 5 || !vdev
->bars
[5].ioport
) {
785 quirk
= vfio_quirk_alloc(4);
786 bar5
= quirk
->data
= g_malloc0(sizeof(*bar5
) +
787 (sizeof(VFIOConfigWindowMatch
) * 2));
788 window
= &bar5
->window
;
791 window
->address_offset
= 0x8;
792 window
->data_offset
= 0xc;
793 window
->nr_matches
= 2;
794 window
->matches
[0].match
= 0x1800;
795 window
->matches
[0].mask
= PCI_CONFIG_SPACE_SIZE
- 1;
796 window
->matches
[1].match
= 0x88000;
797 window
->matches
[1].mask
= vdev
->config_size
- 1;
799 window
->addr_mem
= bar5
->addr_mem
= &quirk
->mem
[0];
800 window
->data_mem
= bar5
->data_mem
= &quirk
->mem
[1];
802 memory_region_init_io(window
->addr_mem
, OBJECT(vdev
),
803 &vfio_generic_window_address_quirk
, window
,
804 "vfio-nvidia-bar5-window-address-quirk", 4);
805 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
806 window
->address_offset
,
807 window
->addr_mem
, 1);
808 memory_region_set_enabled(window
->addr_mem
, false);
810 memory_region_init_io(window
->data_mem
, OBJECT(vdev
),
811 &vfio_generic_window_data_quirk
, window
,
812 "vfio-nvidia-bar5-window-data-quirk", 4);
813 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
815 window
->data_mem
, 1);
816 memory_region_set_enabled(window
->data_mem
, false);
818 memory_region_init_io(&quirk
->mem
[2], OBJECT(vdev
),
819 &vfio_nvidia_bar5_quirk_master
, bar5
,
820 "vfio-nvidia-bar5-master-quirk", 4);
821 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
822 0, &quirk
->mem
[2], 1);
824 memory_region_init_io(&quirk
->mem
[3], OBJECT(vdev
),
825 &vfio_nvidia_bar5_quirk_enable
, bar5
,
826 "vfio-nvidia-bar5-enable-quirk", 4);
827 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
828 4, &quirk
->mem
[3], 1);
830 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
832 trace_vfio_quirk_nvidia_bar5_probe(vdev
->vbasedev
.name
);
835 typedef struct LastDataSet
{
844 #define MAX_DYN_IOEVENTFD 10
845 #define HITS_FOR_IOEVENTFD 10
848 * Finally, BAR0 itself. We want to redirect any accesses to either
849 * 0x1800 or 0x88000 through the PCI config space access functions.
851 static void vfio_nvidia_quirk_mirror_write(void *opaque
, hwaddr addr
,
852 uint64_t data
, unsigned size
)
854 VFIOConfigMirrorQuirk
*mirror
= opaque
;
855 VFIOPCIDevice
*vdev
= mirror
->vdev
;
856 PCIDevice
*pdev
= &vdev
->pdev
;
857 LastDataSet
*last
= (LastDataSet
*)&mirror
->data
;
859 vfio_generic_quirk_mirror_write(opaque
, addr
, data
, size
);
862 * Nvidia seems to acknowledge MSI interrupts by writing 0xff to the
863 * MSI capability ID register. Both the ID and next register are
864 * read-only, so we allow writes covering either of those to real hw.
866 if ((pdev
->cap_present
& QEMU_PCI_CAP_MSI
) &&
867 vfio_range_contained(addr
, size
, pdev
->msi_cap
, PCI_MSI_FLAGS
)) {
868 vfio_region_write(&vdev
->bars
[mirror
->bar
].region
,
869 addr
+ mirror
->offset
, data
, size
);
870 trace_vfio_quirk_nvidia_bar0_msi_ack(vdev
->vbasedev
.name
);
874 * Automatically add an ioeventfd to handle any repeated write with the
875 * same data and size above the standard PCI config space header. This is
876 * primarily expected to accelerate the MSI-ACK behavior, such as noted
877 * above. Current hardware/drivers should trigger an ioeventfd at config
878 * offset 0x704 (region offset 0x88704), with data 0x0, size 4.
880 * The criteria of 10 successive hits is arbitrary but reliably adds the
881 * MSI-ACK region. Note that as some writes are bypassed via the ioeventfd,
882 * the remaining ones have a greater chance of being seen successively.
883 * To avoid the pathological case of burning up all of QEMU's open file
884 * handles, arbitrarily limit this algorithm from adding no more than 10
885 * ioeventfds, print an error if we would have added an 11th, and then
888 if (!vdev
->no_kvm_ioeventfd
&&
889 addr
>= PCI_STD_HEADER_SIZEOF
&& last
->added
<= MAX_DYN_IOEVENTFD
) {
890 if (addr
!= last
->addr
|| data
!= last
->data
|| size
!= last
->size
) {
895 } else if (++last
->hits
>= HITS_FOR_IOEVENTFD
) {
896 if (last
->added
< MAX_DYN_IOEVENTFD
) {
897 VFIOIOEventFD
*ioeventfd
;
898 ioeventfd
= vfio_ioeventfd_init(vdev
, mirror
->mem
, addr
, size
,
899 data
, &vdev
->bars
[mirror
->bar
].region
,
900 mirror
->offset
+ addr
, true);
902 VFIOQuirk
*quirk
= last
->quirk
;
904 QLIST_INSERT_HEAD(&quirk
->ioeventfds
, ioeventfd
, next
);
909 warn_report("NVIDIA ioeventfd queue full for %s, unable to "
910 "accelerate 0x%"HWADDR_PRIx
", data 0x%"PRIx64
", "
911 "size %u", vdev
->vbasedev
.name
, addr
, data
, size
);
917 static const MemoryRegionOps vfio_nvidia_mirror_quirk
= {
918 .read
= vfio_generic_quirk_mirror_read
,
919 .write
= vfio_nvidia_quirk_mirror_write
,
920 .endianness
= DEVICE_LITTLE_ENDIAN
,
923 static void vfio_nvidia_bar0_quirk_reset(VFIOPCIDevice
*vdev
, VFIOQuirk
*quirk
)
925 VFIOConfigMirrorQuirk
*mirror
= quirk
->data
;
926 LastDataSet
*last
= (LastDataSet
*)&mirror
->data
;
928 last
->addr
= last
->data
= last
->size
= last
->hits
= last
->added
= 0;
930 vfio_drop_dynamic_eventfds(vdev
, quirk
);
933 static void vfio_probe_nvidia_bar0_quirk(VFIOPCIDevice
*vdev
, int nr
)
936 VFIOConfigMirrorQuirk
*mirror
;
939 if (vdev
->no_geforce_quirks
||
940 !vfio_pci_is(vdev
, PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
) ||
941 !vfio_is_vga(vdev
) || nr
!= 0) {
945 quirk
= vfio_quirk_alloc(1);
946 quirk
->reset
= vfio_nvidia_bar0_quirk_reset
;
947 mirror
= quirk
->data
= g_malloc0(sizeof(*mirror
) + sizeof(LastDataSet
));
948 mirror
->mem
= quirk
->mem
;
950 mirror
->offset
= 0x88000;
952 last
= (LastDataSet
*)&mirror
->data
;
955 memory_region_init_io(mirror
->mem
, OBJECT(vdev
),
956 &vfio_nvidia_mirror_quirk
, mirror
,
957 "vfio-nvidia-bar0-88000-mirror-quirk",
959 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
960 mirror
->offset
, mirror
->mem
, 1);
962 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
964 /* The 0x1800 offset mirror only seems to get used by legacy VGA */
966 quirk
= vfio_quirk_alloc(1);
967 quirk
->reset
= vfio_nvidia_bar0_quirk_reset
;
968 mirror
= quirk
->data
= g_malloc0(sizeof(*mirror
) + sizeof(LastDataSet
));
969 mirror
->mem
= quirk
->mem
;
971 mirror
->offset
= 0x1800;
973 last
= (LastDataSet
*)&mirror
->data
;
976 memory_region_init_io(mirror
->mem
, OBJECT(vdev
),
977 &vfio_nvidia_mirror_quirk
, mirror
,
978 "vfio-nvidia-bar0-1800-mirror-quirk",
979 PCI_CONFIG_SPACE_SIZE
);
980 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
981 mirror
->offset
, mirror
->mem
, 1);
983 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
986 trace_vfio_quirk_nvidia_bar0_probe(vdev
->vbasedev
.name
);
990 * TODO - Some Nvidia devices provide config access to their companion HDA
991 * device and even to their parent bridge via these config space mirrors.
992 * Add quirks for those regions.
995 #define PCI_VENDOR_ID_REALTEK 0x10ec
998 * RTL8168 devices have a backdoor that can access the MSI-X table. At BAR2
999 * offset 0x70 there is a dword data register, offset 0x74 is a dword address
1000 * register. According to the Linux r8169 driver, the MSI-X table is addressed
1001 * when the "type" portion of the address register is set to 0x1. This appears
1002 * to be bits 16:30. Bit 31 is both a write indicator and some sort of
1003 * "address latched" indicator. Bits 12:15 are a mask field, which we can
1004 * ignore because the MSI-X table should always be accessed as a dword (full
1005 * mask). Bits 0:11 is offset within the type.
1009 * Read from MSI-X table offset 0
1010 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x1f000, 4) // store read addr
1011 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x8001f000 // latch
1012 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x70, 4) = 0xfee00398 // read data
1014 * Write 0xfee00000 to MSI-X table offset 0
1015 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x70, 0xfee00000, 4) // write data
1016 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x8001f000, 4) // do write
1017 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x1f000 // complete
1019 typedef struct VFIOrtl8168Quirk
{
1020 VFIOPCIDevice
*vdev
;
1026 static uint64_t vfio_rtl8168_quirk_address_read(void *opaque
,
1027 hwaddr addr
, unsigned size
)
1029 VFIOrtl8168Quirk
*rtl
= opaque
;
1030 VFIOPCIDevice
*vdev
= rtl
->vdev
;
1031 uint64_t data
= vfio_region_read(&vdev
->bars
[2].region
, addr
+ 0x74, size
);
1034 data
= rtl
->addr
^ 0x80000000U
; /* latch/complete */
1035 trace_vfio_quirk_rtl8168_fake_latch(vdev
->vbasedev
.name
, data
);
1041 static void vfio_rtl8168_quirk_address_write(void *opaque
, hwaddr addr
,
1042 uint64_t data
, unsigned size
)
1044 VFIOrtl8168Quirk
*rtl
= opaque
;
1045 VFIOPCIDevice
*vdev
= rtl
->vdev
;
1047 rtl
->enabled
= false;
1049 if ((data
& 0x7fff0000) == 0x10000) { /* MSI-X table */
1050 rtl
->enabled
= true;
1051 rtl
->addr
= (uint32_t)data
;
1053 if (data
& 0x80000000U
) { /* Do write */
1054 if (vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
) {
1055 hwaddr offset
= data
& 0xfff;
1056 uint64_t val
= rtl
->data
;
1058 trace_vfio_quirk_rtl8168_msix_write(vdev
->vbasedev
.name
,
1059 (uint16_t)offset
, val
);
1061 /* Write to the proper guest MSI-X table instead */
1062 memory_region_dispatch_write(&vdev
->pdev
.msix_table_mmio
,
1064 size_memop(size
) | MO_LE
,
1065 MEMTXATTRS_UNSPECIFIED
);
1067 return; /* Do not write guest MSI-X data to hardware */
1071 vfio_region_write(&vdev
->bars
[2].region
, addr
+ 0x74, data
, size
);
1074 static const MemoryRegionOps vfio_rtl_address_quirk
= {
1075 .read
= vfio_rtl8168_quirk_address_read
,
1076 .write
= vfio_rtl8168_quirk_address_write
,
1078 .min_access_size
= 4,
1079 .max_access_size
= 4,
1082 .endianness
= DEVICE_LITTLE_ENDIAN
,
1085 static uint64_t vfio_rtl8168_quirk_data_read(void *opaque
,
1086 hwaddr addr
, unsigned size
)
1088 VFIOrtl8168Quirk
*rtl
= opaque
;
1089 VFIOPCIDevice
*vdev
= rtl
->vdev
;
1090 uint64_t data
= vfio_region_read(&vdev
->bars
[2].region
, addr
+ 0x70, size
);
1092 if (rtl
->enabled
&& (vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
)) {
1093 hwaddr offset
= rtl
->addr
& 0xfff;
1094 memory_region_dispatch_read(&vdev
->pdev
.msix_table_mmio
, offset
,
1095 &data
, size_memop(size
) | MO_LE
,
1096 MEMTXATTRS_UNSPECIFIED
);
1097 trace_vfio_quirk_rtl8168_msix_read(vdev
->vbasedev
.name
, offset
, data
);
1103 static void vfio_rtl8168_quirk_data_write(void *opaque
, hwaddr addr
,
1104 uint64_t data
, unsigned size
)
1106 VFIOrtl8168Quirk
*rtl
= opaque
;
1107 VFIOPCIDevice
*vdev
= rtl
->vdev
;
1109 rtl
->data
= (uint32_t)data
;
1111 vfio_region_write(&vdev
->bars
[2].region
, addr
+ 0x70, data
, size
);
1114 static const MemoryRegionOps vfio_rtl_data_quirk
= {
1115 .read
= vfio_rtl8168_quirk_data_read
,
1116 .write
= vfio_rtl8168_quirk_data_write
,
1118 .min_access_size
= 4,
1119 .max_access_size
= 4,
1122 .endianness
= DEVICE_LITTLE_ENDIAN
,
1125 static void vfio_probe_rtl8168_bar2_quirk(VFIOPCIDevice
*vdev
, int nr
)
1128 VFIOrtl8168Quirk
*rtl
;
1130 if (!vfio_pci_is(vdev
, PCI_VENDOR_ID_REALTEK
, 0x8168) || nr
!= 2) {
1134 quirk
= vfio_quirk_alloc(2);
1135 quirk
->data
= rtl
= g_malloc0(sizeof(*rtl
));
1138 memory_region_init_io(&quirk
->mem
[0], OBJECT(vdev
),
1139 &vfio_rtl_address_quirk
, rtl
,
1140 "vfio-rtl8168-window-address-quirk", 4);
1141 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
1142 0x74, &quirk
->mem
[0], 1);
1144 memory_region_init_io(&quirk
->mem
[1], OBJECT(vdev
),
1145 &vfio_rtl_data_quirk
, rtl
,
1146 "vfio-rtl8168-window-data-quirk", 4);
1147 memory_region_add_subregion_overlap(vdev
->bars
[nr
].region
.mem
,
1148 0x70, &quirk
->mem
[1], 1);
1150 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1152 trace_vfio_quirk_rtl8168_probe(vdev
->vbasedev
.name
);
1155 #define IGD_ASLS 0xfc /* ASL Storage Register */
1158 * The OpRegion includes the Video BIOS Table, which seems important for
1159 * telling the driver what sort of outputs it has. Without this, the device
1160 * may work in the guest, but we may not get output. This also requires BIOS
1161 * support to reserve and populate a section of guest memory sufficient for
1162 * the table and to write the base address of that memory to the ASLS register
1163 * of the IGD device.
1165 int vfio_pci_igd_opregion_init(VFIOPCIDevice
*vdev
,
1166 struct vfio_region_info
*info
, Error
**errp
)
1170 vdev
->igd_opregion
= g_malloc0(info
->size
);
1171 ret
= pread(vdev
->vbasedev
.fd
, vdev
->igd_opregion
,
1172 info
->size
, info
->offset
);
1173 if (ret
!= info
->size
) {
1174 error_setg(errp
, "failed to read IGD OpRegion");
1175 g_free(vdev
->igd_opregion
);
1176 vdev
->igd_opregion
= NULL
;
1181 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to
1182 * allocate 32bit reserved memory for, copy these contents into, and write
1183 * the reserved memory base address to the device ASLS register at 0xFC.
1184 * Alignment of this reserved region seems flexible, but using a 4k page
1185 * alignment seems to work well. This interface assumes a single IGD
1186 * device, which may be at VM address 00:02.0 in legacy mode or another
1187 * address in UPT mode.
1189 * NB, there may be future use cases discovered where the VM should have
1190 * direct interaction with the host OpRegion, in which case the write to
1191 * the ASLS register would trigger MemoryRegion setup to enable that.
1193 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion",
1194 vdev
->igd_opregion
, info
->size
);
1196 trace_vfio_pci_igd_opregion_enabled(vdev
->vbasedev
.name
);
1198 pci_set_long(vdev
->pdev
.config
+ IGD_ASLS
, 0);
1199 pci_set_long(vdev
->pdev
.wmask
+ IGD_ASLS
, ~0);
1200 pci_set_long(vdev
->emulated_config_bits
+ IGD_ASLS
, ~0);
1206 * Common quirk probe entry points.
1208 void vfio_vga_quirk_setup(VFIOPCIDevice
*vdev
)
1210 vfio_vga_probe_ati_3c3_quirk(vdev
);
1211 vfio_vga_probe_nvidia_3d0_quirk(vdev
);
1214 void vfio_vga_quirk_exit(VFIOPCIDevice
*vdev
)
1219 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
->region
); i
++) {
1220 QLIST_FOREACH(quirk
, &vdev
->vga
->region
[i
].quirks
, next
) {
1221 for (j
= 0; j
< quirk
->nr_mem
; j
++) {
1222 memory_region_del_subregion(&vdev
->vga
->region
[i
].mem
,
1229 void vfio_vga_quirk_finalize(VFIOPCIDevice
*vdev
)
1233 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
->region
); i
++) {
1234 while (!QLIST_EMPTY(&vdev
->vga
->region
[i
].quirks
)) {
1235 VFIOQuirk
*quirk
= QLIST_FIRST(&vdev
->vga
->region
[i
].quirks
);
1236 QLIST_REMOVE(quirk
, next
);
1237 for (j
= 0; j
< quirk
->nr_mem
; j
++) {
1238 object_unparent(OBJECT(&quirk
->mem
[j
]));
1241 g_free(quirk
->data
);
1247 void vfio_bar_quirk_setup(VFIOPCIDevice
*vdev
, int nr
)
1249 vfio_probe_ati_bar4_quirk(vdev
, nr
);
1250 vfio_probe_ati_bar2_quirk(vdev
, nr
);
1251 vfio_probe_nvidia_bar5_quirk(vdev
, nr
);
1252 vfio_probe_nvidia_bar0_quirk(vdev
, nr
);
1253 vfio_probe_rtl8168_bar2_quirk(vdev
, nr
);
1254 #ifdef CONFIG_VFIO_IGD
1255 vfio_probe_igd_bar4_quirk(vdev
, nr
);
1259 void vfio_bar_quirk_exit(VFIOPCIDevice
*vdev
, int nr
)
1261 VFIOBAR
*bar
= &vdev
->bars
[nr
];
1265 QLIST_FOREACH(quirk
, &bar
->quirks
, next
) {
1266 while (!QLIST_EMPTY(&quirk
->ioeventfds
)) {
1267 vfio_ioeventfd_exit(vdev
, QLIST_FIRST(&quirk
->ioeventfds
));
1270 for (i
= 0; i
< quirk
->nr_mem
; i
++) {
1271 memory_region_del_subregion(bar
->region
.mem
, &quirk
->mem
[i
]);
1276 void vfio_bar_quirk_finalize(VFIOPCIDevice
*vdev
, int nr
)
1278 VFIOBAR
*bar
= &vdev
->bars
[nr
];
1281 while (!QLIST_EMPTY(&bar
->quirks
)) {
1282 VFIOQuirk
*quirk
= QLIST_FIRST(&bar
->quirks
);
1283 QLIST_REMOVE(quirk
, next
);
1284 for (i
= 0; i
< quirk
->nr_mem
; i
++) {
1285 object_unparent(OBJECT(&quirk
->mem
[i
]));
1288 g_free(quirk
->data
);
1296 void vfio_quirk_reset(VFIOPCIDevice
*vdev
)
1300 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
1302 VFIOBAR
*bar
= &vdev
->bars
[i
];
1304 QLIST_FOREACH(quirk
, &bar
->quirks
, next
) {
1306 quirk
->reset(vdev
, quirk
);
1313 * AMD Radeon PCI config reset, based on Linux:
1314 * drivers/gpu/drm/radeon/ci_smc.c:ci_is_smc_running()
1315 * drivers/gpu/drm/radeon/radeon_device.c:radeon_pci_config_reset
1316 * drivers/gpu/drm/radeon/ci_smc.c:ci_reset_smc()
1317 * drivers/gpu/drm/radeon/ci_smc.c:ci_stop_smc_clock()
1318 * IDs: include/drm/drm_pciids.h
1319 * Registers: http://cgit.freedesktop.org/~agd5f/linux/commit/?id=4e2aa447f6f0
1321 * Bonaire and Hawaii GPUs do not respond to a bus reset. This is a bug in the
1322 * hardware that should be fixed on future ASICs. The symptom of this is that
1323 * once the accerlated driver loads, Windows guests will bsod on subsequent
1324 * attmpts to load the driver, such as after VM reset or shutdown/restart. To
1325 * work around this, we do an AMD specific PCI config reset, followed by an SMC
1326 * reset. The PCI config reset only works if SMC firmware is running, so we
1327 * have a dependency on the state of the device as to whether this reset will
1328 * be effective. There are still cases where we won't be able to kick the
1329 * device into working, but this greatly improves the usability overall. The
1330 * config reset magic is relatively common on AMD GPUs, but the setup and SMC
1331 * poking is largely ASIC specific.
1333 static bool vfio_radeon_smc_is_running(VFIOPCIDevice
*vdev
)
1338 * Registers 200h and 204h are index and data registers for accessing
1339 * indirect configuration registers within the device.
1341 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000004, 4);
1342 clk
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
1343 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000370, 4);
1344 pc_c
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
1346 return (!(clk
& 1) && (0x20100 <= pc_c
));
1350 * The scope of a config reset is controlled by a mode bit in the misc register
1351 * and a fuse, exposed as a bit in another register. The fuse is the default
1352 * (0 = GFX, 1 = whole GPU), the misc bit is a toggle, with the forumula
1353 * scope = !(misc ^ fuse), where the resulting scope is defined the same as
1354 * the fuse. A truth table therefore tells us that if misc == fuse, we need
1355 * to flip the value of the bit in the misc register.
1357 static void vfio_radeon_set_gfx_only_reset(VFIOPCIDevice
*vdev
)
1359 uint32_t misc
, fuse
;
1362 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0xc00c0000, 4);
1363 fuse
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
1366 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0xc0000010, 4);
1367 misc
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
1371 vfio_region_write(&vdev
->bars
[5].region
, 0x204, misc
^ 2, 4);
1372 vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4); /* flush */
1376 static int vfio_radeon_reset(VFIOPCIDevice
*vdev
)
1378 PCIDevice
*pdev
= &vdev
->pdev
;
1382 /* Defer to a kernel implemented reset */
1383 if (vdev
->vbasedev
.reset_works
) {
1384 trace_vfio_quirk_ati_bonaire_reset_skipped(vdev
->vbasedev
.name
);
1388 /* Enable only memory BAR access */
1389 vfio_pci_write_config(pdev
, PCI_COMMAND
, PCI_COMMAND_MEMORY
, 2);
1391 /* Reset only works if SMC firmware is loaded and running */
1392 if (!vfio_radeon_smc_is_running(vdev
)) {
1394 trace_vfio_quirk_ati_bonaire_reset_no_smc(vdev
->vbasedev
.name
);
1398 /* Make sure only the GFX function is reset */
1399 vfio_radeon_set_gfx_only_reset(vdev
);
1401 /* AMD PCI config reset */
1402 vfio_pci_write_config(pdev
, 0x7c, 0x39d5e86b, 4);
1405 /* Read back the memory size to make sure we're out of reset */
1406 for (i
= 0; i
< 100000; i
++) {
1407 if (vfio_region_read(&vdev
->bars
[5].region
, 0x5428, 4) != 0xffffffff) {
1413 trace_vfio_quirk_ati_bonaire_reset_timeout(vdev
->vbasedev
.name
);
1417 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000000, 4);
1418 data
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
1420 vfio_region_write(&vdev
->bars
[5].region
, 0x204, data
, 4);
1422 /* Disable SMC clock */
1423 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000004, 4);
1424 data
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
1426 vfio_region_write(&vdev
->bars
[5].region
, 0x204, data
, 4);
1428 trace_vfio_quirk_ati_bonaire_reset_done(vdev
->vbasedev
.name
);
1431 /* Restore PCI command register */
1432 vfio_pci_write_config(pdev
, PCI_COMMAND
, 0, 2);
1437 void vfio_setup_resetfn_quirk(VFIOPCIDevice
*vdev
)
1439 switch (vdev
->vendor_id
) {
1441 switch (vdev
->device_id
) {
1443 case 0x6649: /* Bonaire [FirePro W5100] */
1446 case 0x6658: /* Bonaire XTX [Radeon R7 260X] */
1447 case 0x665c: /* Bonaire XT [Radeon HD 7790/8770 / R9 260 OEM] */
1448 case 0x665d: /* Bonaire [Radeon R7 200 Series] */
1450 case 0x67A0: /* Hawaii XT GL [FirePro W9100] */
1451 case 0x67A1: /* Hawaii PRO GL [FirePro W8100] */
1456 case 0x67B0: /* Hawaii XT [Radeon R9 290X] */
1457 case 0x67B1: /* Hawaii PRO [Radeon R9 290] */
1462 vdev
->resetfn
= vfio_radeon_reset
;
1463 trace_vfio_quirk_ati_bonaire_reset(vdev
->vbasedev
.name
);
1471 * The NVIDIA GPUDirect P2P Vendor capability allows the user to specify
1472 * devices as a member of a clique. Devices within the same clique ID
1473 * are capable of direct P2P. It's the user's responsibility that this
1474 * is correct. The spec says that this may reside at any unused config
1475 * offset, but reserves and recommends hypervisors place this at C8h.
1476 * The spec also states that the hypervisor should place this capability
1477 * at the end of the capability list, thus next is defined as 0h.
1479 * +----------------+----------------+----------------+----------------+
1480 * | sig 7:0 ('P') | vndr len (8h) | next (0h) | cap id (9h) |
1481 * +----------------+----------------+----------------+----------------+
1482 * | rsvd 15:7(0h),id 6:3,ver 2:0(0h)| sig 23:8 ('P2') |
1483 * +---------------------------------+---------------------------------+
1485 * https://lists.gnu.org/archive/html/qemu-devel/2017-08/pdfUda5iEpgOS.pdf
1487 static void get_nv_gpudirect_clique_id(Object
*obj
, Visitor
*v
,
1488 const char *name
, void *opaque
,
1491 Property
*prop
= opaque
;
1492 uint8_t *ptr
= qdev_get_prop_ptr(obj
, prop
);
1494 visit_type_uint8(v
, name
, ptr
, errp
);
1497 static void set_nv_gpudirect_clique_id(Object
*obj
, Visitor
*v
,
1498 const char *name
, void *opaque
,
1501 DeviceState
*dev
= DEVICE(obj
);
1502 Property
*prop
= opaque
;
1503 uint8_t value
, *ptr
= qdev_get_prop_ptr(obj
, prop
);
1505 if (dev
->realized
) {
1506 qdev_prop_set_after_realize(dev
, name
, errp
);
1510 if (!visit_type_uint8(v
, name
, &value
, errp
)) {
1515 error_setg(errp
, "Property %s: valid range 0-15", name
);
1522 const PropertyInfo qdev_prop_nv_gpudirect_clique
= {
1524 .description
= "NVIDIA GPUDirect Clique ID (0 - 15)",
1525 .get
= get_nv_gpudirect_clique_id
,
1526 .set
= set_nv_gpudirect_clique_id
,
1529 static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice
*vdev
, Error
**errp
)
1531 PCIDevice
*pdev
= &vdev
->pdev
;
1532 int ret
, pos
= 0xC8;
1534 if (vdev
->nv_gpudirect_clique
== 0xFF) {
1538 if (!vfio_pci_is(vdev
, PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
)) {
1539 error_setg(errp
, "NVIDIA GPUDirect Clique ID: invalid device vendor");
1543 if (pci_get_byte(pdev
->config
+ PCI_CLASS_DEVICE
+ 1) !=
1544 PCI_BASE_CLASS_DISPLAY
) {
1545 error_setg(errp
, "NVIDIA GPUDirect Clique ID: unsupported PCI class");
1549 ret
= pci_add_capability(pdev
, PCI_CAP_ID_VNDR
, pos
, 8, errp
);
1551 error_prepend(errp
, "Failed to add NVIDIA GPUDirect cap: ");
1555 memset(vdev
->emulated_config_bits
+ pos
, 0xFF, 8);
1556 pos
+= PCI_CAP_FLAGS
;
1557 pci_set_byte(pdev
->config
+ pos
++, 8);
1558 pci_set_byte(pdev
->config
+ pos
++, 'P');
1559 pci_set_byte(pdev
->config
+ pos
++, '2');
1560 pci_set_byte(pdev
->config
+ pos
++, 'P');
1561 pci_set_byte(pdev
->config
+ pos
++, vdev
->nv_gpudirect_clique
<< 3);
1562 pci_set_byte(pdev
->config
+ pos
, 0);
1567 static void vfio_pci_nvlink2_get_tgt(Object
*obj
, Visitor
*v
,
1569 void *opaque
, Error
**errp
)
1571 uint64_t tgt
= (uintptr_t) opaque
;
1572 visit_type_uint64(v
, name
, &tgt
, errp
);
1575 static void vfio_pci_nvlink2_get_link_speed(Object
*obj
, Visitor
*v
,
1577 void *opaque
, Error
**errp
)
1579 uint32_t link_speed
= (uint32_t)(uintptr_t) opaque
;
1580 visit_type_uint32(v
, name
, &link_speed
, errp
);
1583 int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice
*vdev
, Error
**errp
)
1587 struct vfio_region_info
*nv2reg
= NULL
;
1588 struct vfio_info_cap_header
*hdr
;
1589 struct vfio_region_info_cap_nvlink2_ssatgt
*cap
;
1592 ret
= vfio_get_dev_region_info(&vdev
->vbasedev
,
1593 VFIO_REGION_TYPE_PCI_VENDOR_TYPE
|
1594 PCI_VENDOR_ID_NVIDIA
,
1595 VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM
,
1601 hdr
= vfio_get_region_info_cap(nv2reg
, VFIO_REGION_INFO_CAP_NVLINK2_SSATGT
);
1608 p
= mmap(NULL
, nv2reg
->size
, PROT_READ
| PROT_WRITE
,
1609 MAP_SHARED
, vdev
->vbasedev
.fd
, nv2reg
->offset
);
1610 if (p
== MAP_FAILED
) {
1615 quirk
= vfio_quirk_alloc(1);
1616 memory_region_init_ram_ptr(&quirk
->mem
[0], OBJECT(vdev
), "nvlink2-mr",
1618 QLIST_INSERT_HEAD(&vdev
->bars
[0].quirks
, quirk
, next
);
1620 object_property_add(OBJECT(vdev
), "nvlink2-tgt", "uint64",
1621 vfio_pci_nvlink2_get_tgt
, NULL
, NULL
,
1622 (void *) (uintptr_t) cap
->tgt
);
1623 trace_vfio_pci_nvidia_gpu_setup_quirk(vdev
->vbasedev
.name
, cap
->tgt
,
1631 int vfio_pci_nvlink2_init(VFIOPCIDevice
*vdev
, Error
**errp
)
1635 struct vfio_region_info
*atsdreg
= NULL
;
1636 struct vfio_info_cap_header
*hdr
;
1637 struct vfio_region_info_cap_nvlink2_ssatgt
*captgt
;
1638 struct vfio_region_info_cap_nvlink2_lnkspd
*capspeed
;
1641 ret
= vfio_get_dev_region_info(&vdev
->vbasedev
,
1642 VFIO_REGION_TYPE_PCI_VENDOR_TYPE
|
1644 VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD
,
1650 hdr
= vfio_get_region_info_cap(atsdreg
,
1651 VFIO_REGION_INFO_CAP_NVLINK2_SSATGT
);
1656 captgt
= (void *) hdr
;
1658 hdr
= vfio_get_region_info_cap(atsdreg
,
1659 VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD
);
1664 capspeed
= (void *) hdr
;
1666 /* Some NVLink bridges may not have assigned ATSD */
1667 if (atsdreg
->size
) {
1668 p
= mmap(NULL
, atsdreg
->size
, PROT_READ
| PROT_WRITE
,
1669 MAP_SHARED
, vdev
->vbasedev
.fd
, atsdreg
->offset
);
1670 if (p
== MAP_FAILED
) {
1675 quirk
= vfio_quirk_alloc(1);
1676 memory_region_init_ram_device_ptr(&quirk
->mem
[0], OBJECT(vdev
),
1677 "nvlink2-atsd-mr", atsdreg
->size
, p
);
1678 QLIST_INSERT_HEAD(&vdev
->bars
[0].quirks
, quirk
, next
);
1681 object_property_add(OBJECT(vdev
), "nvlink2-tgt", "uint64",
1682 vfio_pci_nvlink2_get_tgt
, NULL
, NULL
,
1683 (void *) (uintptr_t) captgt
->tgt
);
1684 trace_vfio_pci_nvlink2_setup_quirk_ssatgt(vdev
->vbasedev
.name
, captgt
->tgt
,
1687 object_property_add(OBJECT(vdev
), "nvlink2-link-speed", "uint32",
1688 vfio_pci_nvlink2_get_link_speed
, NULL
, NULL
,
1689 (void *) (uintptr_t) capspeed
->link_speed
);
1690 trace_vfio_pci_nvlink2_setup_quirk_lnkspd(vdev
->vbasedev
.name
,
1691 capspeed
->link_speed
);
1699 * The VMD endpoint provides a real PCIe domain to the guest and the guest
1700 * kernel performs enumeration of the VMD sub-device domain. Guest transactions
1701 * to VMD sub-devices go through MMU translation from guest addresses to
1702 * physical addresses. When MMIO goes to an endpoint after being translated to
1703 * physical addresses, the bridge rejects the transaction because the window
1704 * has been programmed with guest addresses.
1706 * VMD can use the Host Physical Address in order to correctly program the
1707 * bridge windows in its PCIe domain. VMD device 28C0 has HPA shadow registers
1708 * located at offset 0x2000 in MEMBAR2 (BAR 4). This quirk provides the HPA
1709 * shadow registers in a vendor-specific capability register for devices
1710 * without native support. The position of 0xE8-0xFF is in the reserved range
1711 * of the VMD device capability space following the Power Management
1714 #define VMD_SHADOW_CAP_VER 1
1715 #define VMD_SHADOW_CAP_LEN 24
1716 static int vfio_add_vmd_shadow_cap(VFIOPCIDevice
*vdev
, Error
**errp
)
1718 uint8_t membar_phys
[16];
1719 int ret
, pos
= 0xE8;
1721 if (!(vfio_pci_is(vdev
, PCI_VENDOR_ID_INTEL
, 0x201D) ||
1722 vfio_pci_is(vdev
, PCI_VENDOR_ID_INTEL
, 0x467F) ||
1723 vfio_pci_is(vdev
, PCI_VENDOR_ID_INTEL
, 0x4C3D) ||
1724 vfio_pci_is(vdev
, PCI_VENDOR_ID_INTEL
, 0x9A0B))) {
1728 ret
= pread(vdev
->vbasedev
.fd
, membar_phys
, 16,
1729 vdev
->config_offset
+ PCI_BASE_ADDRESS_2
);
1731 error_report("VMD %s cannot read MEMBARs (%d)",
1732 vdev
->vbasedev
.name
, ret
);
1736 ret
= pci_add_capability(&vdev
->pdev
, PCI_CAP_ID_VNDR
, pos
,
1737 VMD_SHADOW_CAP_LEN
, errp
);
1739 error_prepend(errp
, "Failed to add VMD MEMBAR Shadow cap: ");
1743 memset(vdev
->emulated_config_bits
+ pos
, 0xFF, VMD_SHADOW_CAP_LEN
);
1744 pos
+= PCI_CAP_FLAGS
;
1745 pci_set_byte(vdev
->pdev
.config
+ pos
++, VMD_SHADOW_CAP_LEN
);
1746 pci_set_byte(vdev
->pdev
.config
+ pos
++, VMD_SHADOW_CAP_VER
);
1747 pci_set_long(vdev
->pdev
.config
+ pos
, 0x53484457); /* SHDW */
1748 memcpy(vdev
->pdev
.config
+ pos
+ 4, membar_phys
, 16);
1753 int vfio_add_virt_caps(VFIOPCIDevice
*vdev
, Error
**errp
)
1757 ret
= vfio_add_nv_gpudirect_cap(vdev
, errp
);
1762 ret
= vfio_add_vmd_shadow_cap(vdev
, errp
);