4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 static void arm_cpu_reset(DeviceState
*dev
)
160 CPUState
*s
= CPU(dev
);
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(dev
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
179 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
180 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
183 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
184 /* 64 bit CPUs always start in 64 bit mode */
186 #if defined(CONFIG_USER_ONLY)
187 env
->pstate
= PSTATE_MODE_EL0t
;
188 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
189 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
190 /* Enable all PAC keys. */
191 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
192 SCTLR_EnDA
| SCTLR_EnDB
);
193 /* and to the FP/Neon instructions */
194 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
195 /* and to the SVE instructions */
196 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
197 /* with reasonable vector length */
198 if (cpu_isar_feature(aa64_sve
, cpu
)) {
199 env
->vfp
.zcr_el
[1] = MIN(cpu
->sve_max_vq
- 1, 3);
202 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
203 * turning on both here will produce smaller code and otherwise
204 * make no difference to the user-level emulation.
206 * In sve_probe_page, we assume that this is set.
207 * Do not modify this without other changes.
209 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
211 /* Reset into the highest available EL */
212 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
213 env
->pstate
= PSTATE_MODE_EL3h
;
214 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
215 env
->pstate
= PSTATE_MODE_EL2h
;
217 env
->pstate
= PSTATE_MODE_EL1h
;
219 env
->pc
= cpu
->rvbar
;
222 #if defined(CONFIG_USER_ONLY)
223 /* Userspace expects access to cp10 and cp11 for FP/Neon */
224 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
228 #if defined(CONFIG_USER_ONLY)
229 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
230 /* For user mode we must enable access to coprocessors */
231 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
232 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
233 env
->cp15
.c15_cpar
= 3;
234 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
235 env
->cp15
.c15_cpar
= 1;
240 * If the highest available EL is EL2, AArch32 will start in Hyp
241 * mode; otherwise it starts in SVC. Note that if we start in
242 * AArch64 then these values in the uncached_cpsr will be ignored.
244 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
245 !arm_feature(env
, ARM_FEATURE_EL3
)) {
246 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
248 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
250 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
252 if (arm_feature(env
, ARM_FEATURE_M
)) {
253 uint32_t initial_msp
; /* Loaded from 0x0 */
254 uint32_t initial_pc
; /* Loaded from 0x4 */
258 if (cpu_isar_feature(aa32_lob
, cpu
)) {
260 * LTPSIZE is constant 4 if MVE not implemented, and resets
261 * to an UNKNOWN value if MVE is implemented. We choose to
264 env
->v7m
.ltpsize
= 4;
267 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
268 env
->v7m
.secure
= true;
270 /* This bit resets to 0 if security is supported, but 1 if
271 * it is not. The bit is not present in v7M, but we set it
272 * here so we can avoid having to make checks on it conditional
273 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
275 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
277 * Set NSACR to indicate "NS access permitted to everything";
278 * this avoids having to have all the tests of it being
279 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
280 * v8.1M the guest-visible value of NSACR in a CPU without the
281 * Security Extension is 0xcff.
283 env
->v7m
.nsacr
= 0xcff;
286 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
287 * that it resets to 1, so QEMU always does that rather than making
288 * it dependent on CPU model. In v8M it is RES1.
290 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
291 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
292 if (arm_feature(env
, ARM_FEATURE_V8
)) {
293 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
294 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
295 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
297 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
298 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
299 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
302 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
303 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
304 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
305 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
307 /* Unlike A/R profile, M profile defines the reset LR value */
308 env
->regs
[14] = 0xffffffff;
310 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
312 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
313 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
314 rom
= rom_ptr(vecbase
, 8);
316 /* Address zero is covered by ROM which hasn't yet been
317 * copied into physical memory.
319 initial_msp
= ldl_p(rom
);
320 initial_pc
= ldl_p(rom
+ 4);
322 /* Address zero not covered by a ROM blob, or the ROM blob
323 * is in non-modifiable memory and this is a second reset after
324 * it got copied into memory. In the latter case, rom_ptr
325 * will return a NULL pointer and we should use ldl_phys instead.
327 initial_msp
= ldl_phys(s
->as
, vecbase
);
328 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
331 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
332 env
->regs
[15] = initial_pc
& ~1;
333 env
->thumb
= initial_pc
& 1;
336 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
337 * executing as AArch32 then check if highvecs are enabled and
338 * adjust the PC accordingly.
340 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
341 env
->regs
[15] = 0xFFFF0000;
344 /* M profile requires that reset clears the exclusive monitor;
345 * A profile does not, but clearing it makes more sense than having it
346 * set with an exclusive access on address zero.
348 arm_clear_exclusive(env
);
350 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
353 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
354 if (cpu
->pmsav7_dregion
> 0) {
355 if (arm_feature(env
, ARM_FEATURE_V8
)) {
356 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
357 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
358 * cpu
->pmsav7_dregion
);
359 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
360 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
361 * cpu
->pmsav7_dregion
);
362 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
363 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
364 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
365 * cpu
->pmsav7_dregion
);
366 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
367 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
368 * cpu
->pmsav7_dregion
);
370 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
371 memset(env
->pmsav7
.drbar
, 0,
372 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
373 memset(env
->pmsav7
.drsr
, 0,
374 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
375 memset(env
->pmsav7
.dracr
, 0,
376 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
379 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
380 env
->pmsav7
.rnr
[M_REG_S
] = 0;
381 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
382 env
->pmsav8
.mair0
[M_REG_S
] = 0;
383 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
384 env
->pmsav8
.mair1
[M_REG_S
] = 0;
387 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
388 if (cpu
->sau_sregion
> 0) {
389 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
390 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
393 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
394 * the Cortex-M33 does.
399 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
400 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
401 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
402 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
403 set_float_detect_tininess(float_tininess_before_rounding
,
404 &env
->vfp
.fp_status
);
405 set_float_detect_tininess(float_tininess_before_rounding
,
406 &env
->vfp
.standard_fp_status
);
407 set_float_detect_tininess(float_tininess_before_rounding
,
408 &env
->vfp
.fp_status_f16
);
409 set_float_detect_tininess(float_tininess_before_rounding
,
410 &env
->vfp
.standard_fp_status_f16
);
411 #ifndef CONFIG_USER_ONLY
413 kvm_arm_reset_vcpu(cpu
);
417 hw_breakpoint_update_all(cpu
);
418 hw_watchpoint_update_all(cpu
);
419 arm_rebuild_hflags(env
);
422 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
423 unsigned int target_el
,
424 unsigned int cur_el
, bool secure
,
427 CPUARMState
*env
= cs
->env_ptr
;
428 bool pstate_unmasked
;
429 bool unmasked
= false;
432 * Don't take exceptions if they target a lower EL.
433 * This check should catch any exceptions that would not be taken
436 if (cur_el
> target_el
) {
442 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
446 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
450 if (secure
|| !(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
451 /* VFIQs are only taken when hypervized and non-secure. */
454 return !(env
->daif
& PSTATE_F
);
456 if (secure
|| !(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
457 /* VIRQs are only taken when hypervized and non-secure. */
460 return !(env
->daif
& PSTATE_I
);
462 g_assert_not_reached();
466 * Use the target EL, current execution state and SCR/HCR settings to
467 * determine whether the corresponding CPSR bit is used to mask the
470 if ((target_el
> cur_el
) && (target_el
!= 1)) {
471 /* Exceptions targeting a higher EL may not be maskable */
472 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
474 * 64-bit masking rules are simple: exceptions to EL3
475 * can't be masked, and exceptions to EL2 can only be
476 * masked from Secure state. The HCR and SCR settings
477 * don't affect the masking logic, only the interrupt routing.
479 if (target_el
== 3 || !secure
) {
484 * The old 32-bit-only environment has a more complicated
485 * masking setup. HCR and SCR bits not only affect interrupt
486 * routing but also change the behaviour of masking.
493 * If FIQs are routed to EL3 or EL2 then there are cases where
494 * we override the CPSR.F in determining if the exception is
495 * masked or not. If neither of these are set then we fall back
496 * to the CPSR.F setting otherwise we further assess the state
499 hcr
= hcr_el2
& HCR_FMO
;
500 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
503 * When EL3 is 32-bit, the SCR.FW bit controls whether the
504 * CPSR.F bit masks FIQ interrupts when taken in non-secure
505 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
506 * when non-secure but only when FIQs are only routed to EL3.
508 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
512 * When EL3 execution state is 32-bit, if HCR.IMO is set then
513 * we may override the CPSR.I masking when in non-secure state.
514 * The SCR.IRQ setting has already been taken into consideration
515 * when setting the target EL, so it does not have a further
518 hcr
= hcr_el2
& HCR_IMO
;
522 g_assert_not_reached();
525 if ((scr
|| hcr
) && !secure
) {
532 * The PSTATE bits only mask the interrupt if we have not overriden the
535 return unmasked
|| pstate_unmasked
;
538 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
540 CPUClass
*cc
= CPU_GET_CLASS(cs
);
541 CPUARMState
*env
= cs
->env_ptr
;
542 uint32_t cur_el
= arm_current_el(env
);
543 bool secure
= arm_is_secure(env
);
544 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
548 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
550 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
552 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
553 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
554 cur_el
, secure
, hcr_el2
)) {
558 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
560 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
561 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
562 cur_el
, secure
, hcr_el2
)) {
566 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
567 excp_idx
= EXCP_VIRQ
;
569 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
570 cur_el
, secure
, hcr_el2
)) {
574 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
575 excp_idx
= EXCP_VFIQ
;
577 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
578 cur_el
, secure
, hcr_el2
)) {
585 cs
->exception_index
= excp_idx
;
586 env
->exception
.target_el
= target_el
;
587 cc
->do_interrupt(cs
);
591 void arm_cpu_update_virq(ARMCPU
*cpu
)
594 * Update the interrupt level for VIRQ, which is the logical OR of
595 * the HCR_EL2.VI bit and the input line level from the GIC.
597 CPUARMState
*env
= &cpu
->env
;
598 CPUState
*cs
= CPU(cpu
);
600 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
601 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
603 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
605 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
607 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
612 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
615 * Update the interrupt level for VFIQ, which is the logical OR of
616 * the HCR_EL2.VF bit and the input line level from the GIC.
618 CPUARMState
*env
= &cpu
->env
;
619 CPUState
*cs
= CPU(cpu
);
621 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
622 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
624 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
626 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
628 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
633 #ifndef CONFIG_USER_ONLY
634 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
636 ARMCPU
*cpu
= opaque
;
637 CPUARMState
*env
= &cpu
->env
;
638 CPUState
*cs
= CPU(cpu
);
639 static const int mask
[] = {
640 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
641 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
642 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
643 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
647 env
->irq_line_state
|= mask
[irq
];
649 env
->irq_line_state
&= ~mask
[irq
];
654 assert(arm_feature(env
, ARM_FEATURE_EL2
));
655 arm_cpu_update_virq(cpu
);
658 assert(arm_feature(env
, ARM_FEATURE_EL2
));
659 arm_cpu_update_vfiq(cpu
);
664 cpu_interrupt(cs
, mask
[irq
]);
666 cpu_reset_interrupt(cs
, mask
[irq
]);
670 g_assert_not_reached();
674 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
677 ARMCPU
*cpu
= opaque
;
678 CPUARMState
*env
= &cpu
->env
;
679 CPUState
*cs
= CPU(cpu
);
680 uint32_t linestate_bit
;
685 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
686 linestate_bit
= CPU_INTERRUPT_HARD
;
689 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
690 linestate_bit
= CPU_INTERRUPT_FIQ
;
693 g_assert_not_reached();
697 env
->irq_line_state
|= linestate_bit
;
699 env
->irq_line_state
&= ~linestate_bit
;
701 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
705 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
707 ARMCPU
*cpu
= ARM_CPU(cs
);
708 CPUARMState
*env
= &cpu
->env
;
710 cpu_synchronize_state(cs
);
711 return arm_cpu_data_is_big_endian(env
);
717 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
719 return print_insn_arm(pc
| 1, info
);
722 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
724 ARMCPU
*ac
= ARM_CPU(cpu
);
725 CPUARMState
*env
= &ac
->env
;
729 /* We might not be compiled with the A64 disassembler
730 * because it needs a C++ compiler. Leave print_insn
731 * unset in this case to use the caller default behaviour.
733 #if defined(CONFIG_ARM_A64_DIS)
734 info
->print_insn
= print_insn_arm_a64
;
736 info
->cap_arch
= CS_ARCH_ARM64
;
737 info
->cap_insn_unit
= 4;
738 info
->cap_insn_split
= 4;
742 info
->print_insn
= print_insn_thumb1
;
743 info
->cap_insn_unit
= 2;
744 info
->cap_insn_split
= 4;
745 cap_mode
= CS_MODE_THUMB
;
747 info
->print_insn
= print_insn_arm
;
748 info
->cap_insn_unit
= 4;
749 info
->cap_insn_split
= 4;
750 cap_mode
= CS_MODE_ARM
;
752 if (arm_feature(env
, ARM_FEATURE_V8
)) {
753 cap_mode
|= CS_MODE_V8
;
755 if (arm_feature(env
, ARM_FEATURE_M
)) {
756 cap_mode
|= CS_MODE_MCLASS
;
758 info
->cap_arch
= CS_ARCH_ARM
;
759 info
->cap_mode
= cap_mode
;
762 sctlr_b
= arm_sctlr_b(env
);
763 if (bswap_code(sctlr_b
)) {
764 #ifdef TARGET_WORDS_BIGENDIAN
765 info
->endian
= BFD_ENDIAN_LITTLE
;
767 info
->endian
= BFD_ENDIAN_BIG
;
770 info
->flags
&= ~INSN_ARM_BE32
;
771 #ifndef CONFIG_USER_ONLY
773 info
->flags
|= INSN_ARM_BE32
;
778 #ifdef TARGET_AARCH64
780 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
782 ARMCPU
*cpu
= ARM_CPU(cs
);
783 CPUARMState
*env
= &cpu
->env
;
784 uint32_t psr
= pstate_read(env
);
786 int el
= arm_current_el(env
);
787 const char *ns_status
;
789 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
790 for (i
= 0; i
< 32; i
++) {
792 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
794 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
795 (i
+ 2) % 3 ? " " : "\n");
799 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
800 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
804 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
806 psr
& PSTATE_N
? 'N' : '-',
807 psr
& PSTATE_Z
? 'Z' : '-',
808 psr
& PSTATE_C
? 'C' : '-',
809 psr
& PSTATE_V
? 'V' : '-',
812 psr
& PSTATE_SP
? 'h' : 't');
814 if (cpu_isar_feature(aa64_bti
, cpu
)) {
815 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
817 if (!(flags
& CPU_DUMP_FPU
)) {
818 qemu_fprintf(f
, "\n");
821 if (fp_exception_el(env
, el
) != 0) {
822 qemu_fprintf(f
, " FPU disabled\n");
825 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
826 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
828 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
829 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
831 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
833 if (i
== FFR_PRED_NUM
) {
834 qemu_fprintf(f
, "FFR=");
835 /* It's last, so end the line. */
838 qemu_fprintf(f
, "P%02d=", i
);
851 /* More than one quadword per predicate. */
856 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
858 if (j
* 4 + 4 <= zcr_len
+ 1) {
861 digits
= (zcr_len
% 4 + 1) * 4;
863 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
864 env
->vfp
.pregs
[i
].p
[j
],
865 j
? ":" : eol
? "\n" : " ");
869 for (i
= 0; i
< 32; i
++) {
871 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
872 i
, env
->vfp
.zregs
[i
].d
[1],
873 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
874 } else if (zcr_len
== 1) {
875 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
876 ":%016" PRIx64
":%016" PRIx64
"\n",
877 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
878 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
880 for (j
= zcr_len
; j
>= 0; j
--) {
881 bool odd
= (zcr_len
- j
) % 2 != 0;
883 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
886 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
888 qemu_fprintf(f
, " [%x]=", j
);
891 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
892 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
893 env
->vfp
.zregs
[i
].d
[j
* 2],
894 odd
|| j
== 0 ? "\n" : ":");
899 for (i
= 0; i
< 32; i
++) {
900 uint64_t *q
= aa64_vfp_qreg(env
, i
);
901 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
902 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
909 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
911 g_assert_not_reached();
916 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
918 ARMCPU
*cpu
= ARM_CPU(cs
);
919 CPUARMState
*env
= &cpu
->env
;
923 aarch64_cpu_dump_state(cs
, f
, flags
);
927 for (i
= 0; i
< 16; i
++) {
928 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
930 qemu_fprintf(f
, "\n");
932 qemu_fprintf(f
, " ");
936 if (arm_feature(env
, ARM_FEATURE_M
)) {
937 uint32_t xpsr
= xpsr_read(env
);
939 const char *ns_status
= "";
941 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
942 ns_status
= env
->v7m
.secure
? "S " : "NS ";
945 if (xpsr
& XPSR_EXCP
) {
948 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
949 mode
= "unpriv-thread";
951 mode
= "priv-thread";
955 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
957 xpsr
& XPSR_N
? 'N' : '-',
958 xpsr
& XPSR_Z
? 'Z' : '-',
959 xpsr
& XPSR_C
? 'C' : '-',
960 xpsr
& XPSR_V
? 'V' : '-',
961 xpsr
& XPSR_T
? 'T' : 'A',
965 uint32_t psr
= cpsr_read(env
);
966 const char *ns_status
= "";
968 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
969 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
970 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
973 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
975 psr
& CPSR_N
? 'N' : '-',
976 psr
& CPSR_Z
? 'Z' : '-',
977 psr
& CPSR_C
? 'C' : '-',
978 psr
& CPSR_V
? 'V' : '-',
979 psr
& CPSR_T
? 'T' : 'A',
981 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
984 if (flags
& CPU_DUMP_FPU
) {
986 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
988 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
991 for (i
= 0; i
< numvfpregs
; i
++) {
992 uint64_t v
= *aa32_vfp_dreg(env
, i
);
993 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
995 i
* 2 + 1, (uint32_t)(v
>> 32),
998 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1002 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1004 uint32_t Aff1
= idx
/ clustersz
;
1005 uint32_t Aff0
= idx
% clustersz
;
1006 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1009 static void cpreg_hashtable_data_destroy(gpointer data
)
1012 * Destroy function for cpu->cp_regs hashtable data entries.
1013 * We must free the name string because it was g_strdup()ed in
1014 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1015 * from r->name because we know we definitely allocated it.
1017 ARMCPRegInfo
*r
= data
;
1019 g_free((void *)r
->name
);
1023 static void arm_cpu_initfn(Object
*obj
)
1025 ARMCPU
*cpu
= ARM_CPU(obj
);
1027 cpu_set_cpustate_pointers(cpu
);
1028 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1029 g_free
, cpreg_hashtable_data_destroy
);
1031 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1032 QLIST_INIT(&cpu
->el_change_hooks
);
1034 #ifndef CONFIG_USER_ONLY
1035 /* Our inbound IRQ and FIQ lines */
1036 if (kvm_enabled()) {
1037 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1038 * the same interface as non-KVM CPUs.
1040 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1042 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1045 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1046 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1048 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1049 "gicv3-maintenance-interrupt", 1);
1050 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1051 "pmu-interrupt", 1);
1054 /* DTB consumers generally don't in fact care what the 'compatible'
1055 * string is, so always provide some string and trust that a hypothetical
1056 * picky DTB consumer will also provide a helpful error message.
1058 cpu
->dtb_compatible
= "qemu,unknown";
1059 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1060 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1062 if (tcg_enabled()) {
1063 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1067 static Property arm_cpu_gt_cntfrq_property
=
1068 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1069 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1071 static Property arm_cpu_reset_cbar_property
=
1072 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1074 static Property arm_cpu_reset_hivecs_property
=
1075 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1077 static Property arm_cpu_rvbar_property
=
1078 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1080 #ifndef CONFIG_USER_ONLY
1081 static Property arm_cpu_has_el2_property
=
1082 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1084 static Property arm_cpu_has_el3_property
=
1085 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1088 static Property arm_cpu_cfgend_property
=
1089 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1091 static Property arm_cpu_has_vfp_property
=
1092 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1094 static Property arm_cpu_has_neon_property
=
1095 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1097 static Property arm_cpu_has_dsp_property
=
1098 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1100 static Property arm_cpu_has_mpu_property
=
1101 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1103 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1104 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1105 * the right value for that particular CPU type, and we don't want
1106 * to override that with an incorrect constant value.
1108 static Property arm_cpu_pmsav7_dregion_property
=
1109 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1111 qdev_prop_uint32
, uint32_t);
1113 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1115 ARMCPU
*cpu
= ARM_CPU(obj
);
1117 return cpu
->has_pmu
;
1120 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1122 ARMCPU
*cpu
= ARM_CPU(obj
);
1125 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1126 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1129 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1131 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1133 cpu
->has_pmu
= value
;
1136 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1139 * The exact approach to calculating guest ticks is:
1141 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1142 * NANOSECONDS_PER_SECOND);
1144 * We don't do that. Rather we intentionally use integer division
1145 * truncation below and in the caller for the conversion of host monotonic
1146 * time to guest ticks to provide the exact inverse for the semantics of
1147 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1148 * it loses precision when representing frequencies where
1149 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1150 * provide an exact inverse leads to scheduling timers with negative
1151 * periods, which in turn leads to sticky behaviour in the guest.
1153 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1154 * cannot become zero.
1156 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1157 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1160 void arm_cpu_post_init(Object
*obj
)
1162 ARMCPU
*cpu
= ARM_CPU(obj
);
1164 /* M profile implies PMSA. We have to do this here rather than
1165 * in realize with the other feature-implication checks because
1166 * we look at the PMSA bit to see if we should add some properties.
1168 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1169 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1172 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1173 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1174 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1177 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1178 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1181 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1182 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1185 #ifndef CONFIG_USER_ONLY
1186 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1187 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1188 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1190 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1192 object_property_add_link(obj
, "secure-memory",
1194 (Object
**)&cpu
->secure_memory
,
1195 qdev_prop_allow_set_link_before_realize
,
1196 OBJ_PROP_LINK_STRONG
);
1199 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1200 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1204 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1205 cpu
->has_pmu
= true;
1206 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1210 * Allow user to turn off VFP and Neon support, but only for TCG --
1211 * KVM does not currently allow us to lie to the guest about its
1212 * ID/feature registers, so the guest always sees what the host has.
1214 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1215 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1216 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1217 cpu
->has_vfp
= true;
1218 if (!kvm_enabled()) {
1219 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1223 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1224 cpu
->has_neon
= true;
1225 if (!kvm_enabled()) {
1226 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1230 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1231 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1232 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1235 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1236 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1237 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1238 qdev_property_add_static(DEVICE(obj
),
1239 &arm_cpu_pmsav7_dregion_property
);
1243 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1244 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1245 qdev_prop_allow_set_link_before_realize
,
1246 OBJ_PROP_LINK_STRONG
);
1248 * M profile: initial value of the Secure VTOR. We can't just use
1249 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1250 * the property to be set after realize.
1252 object_property_add_uint32_ptr(obj
, "init-svtor",
1254 OBJ_PROP_FLAG_READWRITE
);
1257 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1259 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1260 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1263 if (kvm_enabled()) {
1264 kvm_arm_add_vcpu_properties(obj
);
1267 #ifndef CONFIG_USER_ONLY
1268 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1269 cpu_isar_feature(aa64_mte
, cpu
)) {
1270 object_property_add_link(obj
, "tag-memory",
1272 (Object
**)&cpu
->tag_memory
,
1273 qdev_prop_allow_set_link_before_realize
,
1274 OBJ_PROP_LINK_STRONG
);
1276 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1277 object_property_add_link(obj
, "secure-tag-memory",
1279 (Object
**)&cpu
->secure_tag_memory
,
1280 qdev_prop_allow_set_link_before_realize
,
1281 OBJ_PROP_LINK_STRONG
);
1287 static void arm_cpu_finalizefn(Object
*obj
)
1289 ARMCPU
*cpu
= ARM_CPU(obj
);
1290 ARMELChangeHook
*hook
, *next
;
1292 g_hash_table_destroy(cpu
->cp_regs
);
1294 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1295 QLIST_REMOVE(hook
, node
);
1298 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1299 QLIST_REMOVE(hook
, node
);
1302 #ifndef CONFIG_USER_ONLY
1303 if (cpu
->pmu_timer
) {
1304 timer_del(cpu
->pmu_timer
);
1305 timer_deinit(cpu
->pmu_timer
);
1306 timer_free(cpu
->pmu_timer
);
1311 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1313 Error
*local_err
= NULL
;
1315 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1316 arm_cpu_sve_finalize(cpu
, &local_err
);
1317 if (local_err
!= NULL
) {
1318 error_propagate(errp
, local_err
);
1323 if (kvm_enabled()) {
1324 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1325 if (local_err
!= NULL
) {
1326 error_propagate(errp
, local_err
);
1332 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1334 CPUState
*cs
= CPU(dev
);
1335 ARMCPU
*cpu
= ARM_CPU(dev
);
1336 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1337 CPUARMState
*env
= &cpu
->env
;
1339 Error
*local_err
= NULL
;
1340 bool no_aa32
= false;
1342 /* If we needed to query the host kernel for the CPU features
1343 * then it's possible that might have failed in the initfn, but
1344 * this is the first point where we can report it.
1346 if (cpu
->host_cpu_probe_failed
) {
1347 if (!kvm_enabled()) {
1348 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1350 error_setg(errp
, "Failed to retrieve host CPU features");
1355 #ifndef CONFIG_USER_ONLY
1356 /* The NVIC and M-profile CPU are two halves of a single piece of
1357 * hardware; trying to use one without the other is a command line
1358 * error and will result in segfaults if not caught here.
1360 if (arm_feature(env
, ARM_FEATURE_M
)) {
1362 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1367 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1375 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1376 if (!cpu
->gt_cntfrq_hz
) {
1377 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1381 scale
= gt_cntfrq_period_ns(cpu
);
1383 scale
= GTIMER_SCALE
;
1386 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1387 arm_gt_ptimer_cb
, cpu
);
1388 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1389 arm_gt_vtimer_cb
, cpu
);
1390 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1391 arm_gt_htimer_cb
, cpu
);
1392 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1393 arm_gt_stimer_cb
, cpu
);
1394 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1395 arm_gt_hvtimer_cb
, cpu
);
1399 cpu_exec_realizefn(cs
, &local_err
);
1400 if (local_err
!= NULL
) {
1401 error_propagate(errp
, local_err
);
1405 arm_cpu_finalize_features(cpu
, &local_err
);
1406 if (local_err
!= NULL
) {
1407 error_propagate(errp
, local_err
);
1411 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1412 cpu
->has_vfp
!= cpu
->has_neon
) {
1414 * This is an architectural requirement for AArch64; AArch32 is
1415 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1418 "AArch64 CPUs must have both VFP and Neon or neither");
1422 if (!cpu
->has_vfp
) {
1426 t
= cpu
->isar
.id_aa64isar1
;
1427 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1428 cpu
->isar
.id_aa64isar1
= t
;
1430 t
= cpu
->isar
.id_aa64pfr0
;
1431 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1432 cpu
->isar
.id_aa64pfr0
= t
;
1434 u
= cpu
->isar
.id_isar6
;
1435 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1436 cpu
->isar
.id_isar6
= u
;
1438 u
= cpu
->isar
.mvfr0
;
1439 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1440 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1441 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1442 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1443 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1444 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1445 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1446 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1448 cpu
->isar
.mvfr0
= u
;
1450 u
= cpu
->isar
.mvfr1
;
1451 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1452 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1453 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1454 if (arm_feature(env
, ARM_FEATURE_M
)) {
1455 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1457 cpu
->isar
.mvfr1
= u
;
1459 u
= cpu
->isar
.mvfr2
;
1460 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1461 cpu
->isar
.mvfr2
= u
;
1464 if (!cpu
->has_neon
) {
1468 unset_feature(env
, ARM_FEATURE_NEON
);
1470 t
= cpu
->isar
.id_aa64isar0
;
1471 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1472 cpu
->isar
.id_aa64isar0
= t
;
1474 t
= cpu
->isar
.id_aa64isar1
;
1475 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1476 cpu
->isar
.id_aa64isar1
= t
;
1478 t
= cpu
->isar
.id_aa64pfr0
;
1479 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1480 cpu
->isar
.id_aa64pfr0
= t
;
1482 u
= cpu
->isar
.id_isar5
;
1483 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1484 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1485 cpu
->isar
.id_isar5
= u
;
1487 u
= cpu
->isar
.id_isar6
;
1488 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1489 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1490 cpu
->isar
.id_isar6
= u
;
1492 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1493 u
= cpu
->isar
.mvfr1
;
1494 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1495 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1496 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1497 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1498 cpu
->isar
.mvfr1
= u
;
1500 u
= cpu
->isar
.mvfr2
;
1501 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1502 cpu
->isar
.mvfr2
= u
;
1506 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1510 t
= cpu
->isar
.id_aa64isar0
;
1511 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1512 cpu
->isar
.id_aa64isar0
= t
;
1514 t
= cpu
->isar
.id_aa64isar1
;
1515 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1516 cpu
->isar
.id_aa64isar1
= t
;
1518 u
= cpu
->isar
.mvfr0
;
1519 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1520 cpu
->isar
.mvfr0
= u
;
1522 /* Despite the name, this field covers both VFP and Neon */
1523 u
= cpu
->isar
.mvfr1
;
1524 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1525 cpu
->isar
.mvfr1
= u
;
1528 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1531 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1533 u
= cpu
->isar
.id_isar1
;
1534 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1535 cpu
->isar
.id_isar1
= u
;
1537 u
= cpu
->isar
.id_isar2
;
1538 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1539 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1540 cpu
->isar
.id_isar2
= u
;
1542 u
= cpu
->isar
.id_isar3
;
1543 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1544 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1545 cpu
->isar
.id_isar3
= u
;
1548 /* Some features automatically imply others: */
1549 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1550 if (arm_feature(env
, ARM_FEATURE_M
)) {
1551 set_feature(env
, ARM_FEATURE_V7
);
1553 set_feature(env
, ARM_FEATURE_V7VE
);
1558 * There exist AArch64 cpus without AArch32 support. When KVM
1559 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1560 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1561 * As a general principle, we also do not make ID register
1562 * consistency checks anywhere unless using TCG, because only
1563 * for TCG would a consistency-check failure be a QEMU bug.
1565 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1566 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1569 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1570 /* v7 Virtualization Extensions. In real hardware this implies
1571 * EL2 and also the presence of the Security Extensions.
1572 * For QEMU, for backwards-compatibility we implement some
1573 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1574 * include the various other features that V7VE implies.
1575 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1576 * Security Extensions is ARM_FEATURE_EL3.
1578 assert(!tcg_enabled() || no_aa32
||
1579 cpu_isar_feature(aa32_arm_div
, cpu
));
1580 set_feature(env
, ARM_FEATURE_LPAE
);
1581 set_feature(env
, ARM_FEATURE_V7
);
1583 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1584 set_feature(env
, ARM_FEATURE_VAPA
);
1585 set_feature(env
, ARM_FEATURE_THUMB2
);
1586 set_feature(env
, ARM_FEATURE_MPIDR
);
1587 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1588 set_feature(env
, ARM_FEATURE_V6K
);
1590 set_feature(env
, ARM_FEATURE_V6
);
1593 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1594 * non-EL3 configs. This is needed by some legacy boards.
1596 set_feature(env
, ARM_FEATURE_VBAR
);
1598 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1599 set_feature(env
, ARM_FEATURE_V6
);
1600 set_feature(env
, ARM_FEATURE_MVFR
);
1602 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1603 set_feature(env
, ARM_FEATURE_V5
);
1604 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1605 assert(!tcg_enabled() || no_aa32
||
1606 cpu_isar_feature(aa32_jazelle
, cpu
));
1607 set_feature(env
, ARM_FEATURE_AUXCR
);
1610 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1611 set_feature(env
, ARM_FEATURE_V4T
);
1613 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1614 set_feature(env
, ARM_FEATURE_V7MP
);
1616 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1617 set_feature(env
, ARM_FEATURE_CBAR
);
1619 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1620 !arm_feature(env
, ARM_FEATURE_M
)) {
1621 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1625 * We rely on no XScale CPU having VFP so we can use the same bits in the
1626 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1628 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1629 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1630 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1632 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1633 !arm_feature(env
, ARM_FEATURE_M
) &&
1634 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1635 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1640 /* For CPUs which might have tiny 1K pages, or which have an
1641 * MPU and might have small region sizes, stick with 1K pages.
1645 if (!set_preferred_target_page_bits(pagebits
)) {
1646 /* This can only ever happen for hotplugging a CPU, or if
1647 * the board code incorrectly creates a CPU which it has
1648 * promised via minimum_page_size that it will not.
1650 error_setg(errp
, "This CPU requires a smaller page size than the "
1655 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1656 * We don't support setting cluster ID ([16..23]) (known as Aff2
1657 * in later ARM ARM versions), or any of the higher affinity level fields,
1658 * so these bits always RAZ.
1660 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1661 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1662 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1665 if (cpu
->reset_hivecs
) {
1666 cpu
->reset_sctlr
|= (1 << 13);
1670 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1671 cpu
->reset_sctlr
|= SCTLR_EE
;
1673 cpu
->reset_sctlr
|= SCTLR_B
;
1677 if (!cpu
->has_el3
) {
1678 /* If the has_el3 CPU property is disabled then we need to disable the
1681 unset_feature(env
, ARM_FEATURE_EL3
);
1683 /* Disable the security extension feature bits in the processor feature
1684 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1686 cpu
->isar
.id_pfr1
&= ~0xf0;
1687 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1690 if (!cpu
->has_el2
) {
1691 unset_feature(env
, ARM_FEATURE_EL2
);
1694 if (!cpu
->has_pmu
) {
1695 unset_feature(env
, ARM_FEATURE_PMU
);
1697 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1700 if (!kvm_enabled()) {
1701 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1702 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1705 #ifndef CONFIG_USER_ONLY
1706 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1710 cpu
->isar
.id_aa64dfr0
=
1711 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1712 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1717 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1718 /* Disable the hypervisor feature bits in the processor feature
1719 * registers if we don't have EL2. These are id_pfr1[15:12] and
1720 * id_aa64pfr0_el1[11:8].
1722 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1723 cpu
->isar
.id_pfr1
&= ~0xf000;
1726 #ifndef CONFIG_USER_ONLY
1727 if (cpu
->tag_memory
== NULL
&& cpu_isar_feature(aa64_mte
, cpu
)) {
1729 * Disable the MTE feature bits if we do not have tag-memory
1730 * provided by the machine.
1732 cpu
->isar
.id_aa64pfr1
=
1733 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 0);
1737 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1738 * to false or by setting pmsav7-dregion to 0.
1740 if (!cpu
->has_mpu
) {
1741 cpu
->pmsav7_dregion
= 0;
1743 if (cpu
->pmsav7_dregion
== 0) {
1744 cpu
->has_mpu
= false;
1747 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1748 arm_feature(env
, ARM_FEATURE_V7
)) {
1749 uint32_t nr
= cpu
->pmsav7_dregion
;
1752 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1757 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1759 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1760 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1761 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1762 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1763 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1766 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1767 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1768 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1773 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1774 uint32_t nr
= cpu
->sau_sregion
;
1777 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1782 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1783 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1787 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1788 set_feature(env
, ARM_FEATURE_VBAR
);
1791 register_cp_regs_for_features(cpu
);
1792 arm_cpu_register_gdb_regs_for_features(cpu
);
1794 init_cpreg_list(cpu
);
1796 #ifndef CONFIG_USER_ONLY
1797 MachineState
*ms
= MACHINE(qdev_get_machine());
1798 unsigned int smp_cpus
= ms
->smp
.cpus
;
1799 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
1802 * We must set cs->num_ases to the final value before
1803 * the first call to cpu_address_space_init.
1805 if (cpu
->tag_memory
!= NULL
) {
1806 cs
->num_ases
= 3 + has_secure
;
1808 cs
->num_ases
= 1 + has_secure
;
1812 if (!cpu
->secure_memory
) {
1813 cpu
->secure_memory
= cs
->memory
;
1815 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1816 cpu
->secure_memory
);
1819 if (cpu
->tag_memory
!= NULL
) {
1820 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
1823 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
1824 cpu
->secure_tag_memory
);
1828 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1830 /* No core_count specified, default to smp_cpus. */
1831 if (cpu
->core_count
== -1) {
1832 cpu
->core_count
= smp_cpus
;
1836 if (tcg_enabled()) {
1837 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
1840 * We only support DCZ blocklen that fits on one page.
1842 * Architectually this is always true. However TARGET_PAGE_SIZE
1843 * is variable and, for compatibility with -machine virt-2.7,
1844 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1845 * But even then, while the largest architectural DCZ blocklen
1846 * is 2KiB, no cpu actually uses such a large blocklen.
1848 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
1851 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1852 * both nibbles of each byte storing tag data may be written at once.
1853 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1855 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1856 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
1863 acc
->parent_realize(dev
, errp
);
1866 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1871 const char *cpunamestr
;
1873 cpuname
= g_strsplit(cpu_model
, ",", 1);
1874 cpunamestr
= cpuname
[0];
1875 #ifdef CONFIG_USER_ONLY
1876 /* For backwards compatibility usermode emulation allows "-cpu any",
1877 * which has the same semantics as "-cpu max".
1879 if (!strcmp(cpunamestr
, "any")) {
1883 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1884 oc
= object_class_by_name(typename
);
1885 g_strfreev(cpuname
);
1887 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1888 object_class_is_abstract(oc
)) {
1894 /* CPU models. These are not needed for the AArch64 linux-user build. */
1895 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1897 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1898 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1899 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1900 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1901 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1905 static void cortex_a8_initfn(Object
*obj
)
1907 ARMCPU
*cpu
= ARM_CPU(obj
);
1909 cpu
->dtb_compatible
= "arm,cortex-a8";
1910 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1911 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1912 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1913 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1914 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1915 cpu
->midr
= 0x410fc080;
1916 cpu
->reset_fpsid
= 0x410330c0;
1917 cpu
->isar
.mvfr0
= 0x11110222;
1918 cpu
->isar
.mvfr1
= 0x00011111;
1919 cpu
->ctr
= 0x82048004;
1920 cpu
->reset_sctlr
= 0x00c50078;
1921 cpu
->isar
.id_pfr0
= 0x1031;
1922 cpu
->isar
.id_pfr1
= 0x11;
1923 cpu
->isar
.id_dfr0
= 0x400;
1925 cpu
->isar
.id_mmfr0
= 0x31100003;
1926 cpu
->isar
.id_mmfr1
= 0x20000000;
1927 cpu
->isar
.id_mmfr2
= 0x01202000;
1928 cpu
->isar
.id_mmfr3
= 0x11;
1929 cpu
->isar
.id_isar0
= 0x00101111;
1930 cpu
->isar
.id_isar1
= 0x12112111;
1931 cpu
->isar
.id_isar2
= 0x21232031;
1932 cpu
->isar
.id_isar3
= 0x11112131;
1933 cpu
->isar
.id_isar4
= 0x00111142;
1934 cpu
->isar
.dbgdidr
= 0x15141000;
1935 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1936 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1937 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1938 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1939 cpu
->reset_auxcr
= 2;
1940 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1943 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1944 /* power_control should be set to maximum latency. Again,
1945 * default to 0 and set by private hook
1947 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1948 .access
= PL1_RW
, .resetvalue
= 0,
1949 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1950 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1951 .access
= PL1_RW
, .resetvalue
= 0,
1952 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1953 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1954 .access
= PL1_RW
, .resetvalue
= 0,
1955 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1956 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1957 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1958 /* TLB lockdown control */
1959 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1960 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1961 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1962 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1963 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1964 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1965 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1966 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1967 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1968 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1972 static void cortex_a9_initfn(Object
*obj
)
1974 ARMCPU
*cpu
= ARM_CPU(obj
);
1976 cpu
->dtb_compatible
= "arm,cortex-a9";
1977 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1978 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1979 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1980 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1981 /* Note that A9 supports the MP extensions even for
1982 * A9UP and single-core A9MP (which are both different
1983 * and valid configurations; we don't model A9UP).
1985 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1986 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1987 cpu
->midr
= 0x410fc090;
1988 cpu
->reset_fpsid
= 0x41033090;
1989 cpu
->isar
.mvfr0
= 0x11110222;
1990 cpu
->isar
.mvfr1
= 0x01111111;
1991 cpu
->ctr
= 0x80038003;
1992 cpu
->reset_sctlr
= 0x00c50078;
1993 cpu
->isar
.id_pfr0
= 0x1031;
1994 cpu
->isar
.id_pfr1
= 0x11;
1995 cpu
->isar
.id_dfr0
= 0x000;
1997 cpu
->isar
.id_mmfr0
= 0x00100103;
1998 cpu
->isar
.id_mmfr1
= 0x20000000;
1999 cpu
->isar
.id_mmfr2
= 0x01230000;
2000 cpu
->isar
.id_mmfr3
= 0x00002111;
2001 cpu
->isar
.id_isar0
= 0x00101111;
2002 cpu
->isar
.id_isar1
= 0x13112111;
2003 cpu
->isar
.id_isar2
= 0x21232041;
2004 cpu
->isar
.id_isar3
= 0x11112131;
2005 cpu
->isar
.id_isar4
= 0x00111142;
2006 cpu
->isar
.dbgdidr
= 0x35141000;
2007 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
2008 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
2009 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
2010 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
2013 #ifndef CONFIG_USER_ONLY
2014 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2016 MachineState
*ms
= MACHINE(qdev_get_machine());
2018 /* Linux wants the number of processors from here.
2019 * Might as well set the interrupt-controller bit too.
2021 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2025 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2026 #ifndef CONFIG_USER_ONLY
2027 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2028 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2029 .writefn
= arm_cp_write_ignore
, },
2031 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2032 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2036 static void cortex_a7_initfn(Object
*obj
)
2038 ARMCPU
*cpu
= ARM_CPU(obj
);
2040 cpu
->dtb_compatible
= "arm,cortex-a7";
2041 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2042 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2043 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2044 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2045 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2046 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2047 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2048 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2049 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2050 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2051 cpu
->midr
= 0x410fc075;
2052 cpu
->reset_fpsid
= 0x41023075;
2053 cpu
->isar
.mvfr0
= 0x10110222;
2054 cpu
->isar
.mvfr1
= 0x11111111;
2055 cpu
->ctr
= 0x84448003;
2056 cpu
->reset_sctlr
= 0x00c50078;
2057 cpu
->isar
.id_pfr0
= 0x00001131;
2058 cpu
->isar
.id_pfr1
= 0x00011011;
2059 cpu
->isar
.id_dfr0
= 0x02010555;
2060 cpu
->id_afr0
= 0x00000000;
2061 cpu
->isar
.id_mmfr0
= 0x10101105;
2062 cpu
->isar
.id_mmfr1
= 0x40000000;
2063 cpu
->isar
.id_mmfr2
= 0x01240000;
2064 cpu
->isar
.id_mmfr3
= 0x02102211;
2065 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2066 * table 4-41 gives 0x02101110, which includes the arm div insns.
2068 cpu
->isar
.id_isar0
= 0x02101110;
2069 cpu
->isar
.id_isar1
= 0x13112111;
2070 cpu
->isar
.id_isar2
= 0x21232041;
2071 cpu
->isar
.id_isar3
= 0x11112131;
2072 cpu
->isar
.id_isar4
= 0x10011142;
2073 cpu
->isar
.dbgdidr
= 0x3515f005;
2074 cpu
->clidr
= 0x0a200023;
2075 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2076 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2077 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2078 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2081 static void cortex_a15_initfn(Object
*obj
)
2083 ARMCPU
*cpu
= ARM_CPU(obj
);
2085 cpu
->dtb_compatible
= "arm,cortex-a15";
2086 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2087 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2088 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2089 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2090 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2091 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2092 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2093 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2094 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2095 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2096 cpu
->midr
= 0x412fc0f1;
2097 cpu
->reset_fpsid
= 0x410430f0;
2098 cpu
->isar
.mvfr0
= 0x10110222;
2099 cpu
->isar
.mvfr1
= 0x11111111;
2100 cpu
->ctr
= 0x8444c004;
2101 cpu
->reset_sctlr
= 0x00c50078;
2102 cpu
->isar
.id_pfr0
= 0x00001131;
2103 cpu
->isar
.id_pfr1
= 0x00011011;
2104 cpu
->isar
.id_dfr0
= 0x02010555;
2105 cpu
->id_afr0
= 0x00000000;
2106 cpu
->isar
.id_mmfr0
= 0x10201105;
2107 cpu
->isar
.id_mmfr1
= 0x20000000;
2108 cpu
->isar
.id_mmfr2
= 0x01240000;
2109 cpu
->isar
.id_mmfr3
= 0x02102211;
2110 cpu
->isar
.id_isar0
= 0x02101110;
2111 cpu
->isar
.id_isar1
= 0x13112111;
2112 cpu
->isar
.id_isar2
= 0x21232041;
2113 cpu
->isar
.id_isar3
= 0x11112131;
2114 cpu
->isar
.id_isar4
= 0x10011142;
2115 cpu
->isar
.dbgdidr
= 0x3515f021;
2116 cpu
->clidr
= 0x0a200023;
2117 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2118 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2119 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2120 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2123 #ifndef TARGET_AARCH64
2125 * -cpu max: a CPU with as many features enabled as our emulation supports.
2126 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2127 * this only needs to handle 32 bits, and need not care about KVM.
2129 static void arm_max_initfn(Object
*obj
)
2131 ARMCPU
*cpu
= ARM_CPU(obj
);
2133 cortex_a15_initfn(obj
);
2135 /* old-style VFP short-vector support */
2136 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2138 #ifdef CONFIG_USER_ONLY
2140 * We don't set these in system emulation mode for the moment,
2141 * since we don't correctly set (all of) the ID registers to
2144 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2148 t
= cpu
->isar
.id_isar5
;
2149 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2150 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2151 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2152 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2153 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2154 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2155 cpu
->isar
.id_isar5
= t
;
2157 t
= cpu
->isar
.id_isar6
;
2158 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2159 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2160 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2161 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2162 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2163 cpu
->isar
.id_isar6
= t
;
2165 t
= cpu
->isar
.mvfr1
;
2166 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 3); /* v8.2-FP16 */
2167 t
= FIELD_DP32(t
, MVFR1
, SIMDHP
, 2); /* v8.2-FP16 */
2168 cpu
->isar
.mvfr1
= t
;
2170 t
= cpu
->isar
.mvfr2
;
2171 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2172 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2173 cpu
->isar
.mvfr2
= t
;
2175 t
= cpu
->isar
.id_mmfr3
;
2176 t
= FIELD_DP32(t
, ID_MMFR3
, PAN
, 2); /* ATS1E1 */
2177 cpu
->isar
.id_mmfr3
= t
;
2179 t
= cpu
->isar
.id_mmfr4
;
2180 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2181 t
= FIELD_DP32(t
, ID_MMFR4
, AC2
, 1); /* ACTLR2, HACTLR2 */
2182 t
= FIELD_DP32(t
, ID_MMFR4
, CNP
, 1); /* TTCNP */
2183 t
= FIELD_DP32(t
, ID_MMFR4
, XNX
, 1); /* TTS2UXN */
2184 cpu
->isar
.id_mmfr4
= t
;
2190 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2192 static const ARMCPUInfo arm_cpus
[] = {
2193 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2194 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2195 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2196 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2197 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2198 #ifndef TARGET_AARCH64
2199 { .name
= "max", .initfn
= arm_max_initfn
},
2201 #ifdef CONFIG_USER_ONLY
2202 { .name
= "any", .initfn
= arm_max_initfn
},
2207 static Property arm_cpu_properties
[] = {
2208 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2209 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2210 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2211 mp_affinity
, ARM64_AFFINITY_INVALID
),
2212 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2213 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2214 DEFINE_PROP_END_OF_LIST()
2217 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2219 ARMCPU
*cpu
= ARM_CPU(cs
);
2220 CPUARMState
*env
= &cpu
->env
;
2222 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2223 return g_strdup("iwmmxt");
2225 return g_strdup("arm");
2228 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2230 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2231 CPUClass
*cc
= CPU_CLASS(acc
);
2232 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2234 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2235 &acc
->parent_realize
);
2237 device_class_set_props(dc
, arm_cpu_properties
);
2238 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2240 cc
->class_by_name
= arm_cpu_class_by_name
;
2241 cc
->has_work
= arm_cpu_has_work
;
2242 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2243 cc
->dump_state
= arm_cpu_dump_state
;
2244 cc
->set_pc
= arm_cpu_set_pc
;
2245 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2246 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2247 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2248 #ifndef CONFIG_USER_ONLY
2249 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2250 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2251 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2252 cc
->vmsd
= &vmstate_arm_cpu
;
2253 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2254 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2255 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2257 cc
->gdb_num_core_regs
= 26;
2258 cc
->gdb_core_xml_file
= "arm-core.xml";
2259 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2260 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2261 cc
->gdb_stop_before_watchpoint
= true;
2262 cc
->disas_set_info
= arm_disas_set_info
;
2264 cc
->tcg_initialize
= arm_translate_init
;
2265 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2266 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2267 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2268 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2269 #if !defined(CONFIG_USER_ONLY)
2270 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2271 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2272 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2277 static void arm_host_initfn(Object
*obj
)
2279 ARMCPU
*cpu
= ARM_CPU(obj
);
2281 kvm_arm_set_cpu_features_from_host(cpu
);
2282 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2283 aarch64_add_sve_properties(obj
);
2285 arm_cpu_post_init(obj
);
2288 static const TypeInfo host_arm_cpu_type_info
= {
2289 .name
= TYPE_ARM_HOST_CPU
,
2290 .parent
= TYPE_AARCH64_CPU
,
2291 .instance_init
= arm_host_initfn
,
2296 static void arm_cpu_instance_init(Object
*obj
)
2298 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2300 acc
->info
->initfn(obj
);
2301 arm_cpu_post_init(obj
);
2304 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2306 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2311 void arm_cpu_register(const ARMCPUInfo
*info
)
2313 TypeInfo type_info
= {
2314 .parent
= TYPE_ARM_CPU
,
2315 .instance_size
= sizeof(ARMCPU
),
2316 .instance_align
= __alignof__(ARMCPU
),
2317 .instance_init
= arm_cpu_instance_init
,
2318 .class_size
= sizeof(ARMCPUClass
),
2319 .class_init
= info
->class_init
?: cpu_register_class_init
,
2320 .class_data
= (void *)info
,
2323 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2324 type_register(&type_info
);
2325 g_free((void *)type_info
.name
);
2328 static const TypeInfo arm_cpu_type_info
= {
2329 .name
= TYPE_ARM_CPU
,
2331 .instance_size
= sizeof(ARMCPU
),
2332 .instance_align
= __alignof__(ARMCPU
),
2333 .instance_init
= arm_cpu_initfn
,
2334 .instance_finalize
= arm_cpu_finalizefn
,
2336 .class_size
= sizeof(ARMCPUClass
),
2337 .class_init
= arm_cpu_class_init
,
2340 static const TypeInfo idau_interface_type_info
= {
2341 .name
= TYPE_IDAU_INTERFACE
,
2342 .parent
= TYPE_INTERFACE
,
2343 .class_size
= sizeof(IDAUInterfaceClass
),
2346 static void arm_cpu_register_types(void)
2348 const size_t cpu_count
= ARRAY_SIZE(arm_cpus
);
2350 type_register_static(&arm_cpu_type_info
);
2353 type_register_static(&host_arm_cpu_type_info
);
2359 type_register_static(&idau_interface_type_info
);
2360 for (i
= 0; i
< cpu_count
; ++i
) {
2361 arm_cpu_register(&arm_cpus
[i
]);
2366 type_init(arm_cpu_register_types
)