hw/char/stm32f2xx_usart.c

   1 /*
   2  * STM32F2XX USART
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/char/stm32f2xx_usart.h"
  27 #include "qemu/log.h"
  28
  29 #ifndef STM_USART_ERR_DEBUG
  30 #define STM_USART_ERR_DEBUG 0
  31 #endif
  32
  33 #define DB_PRINT_L(lvl, fmt, args...) do { \
  34     if (STM_USART_ERR_DEBUG >= lvl) { \
  35         qemu_log("%s: " fmt, __func__, ## args); \
  36     } \
  37 } while (0);
  38
  39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  40
  41 static int stm32f2xx_usart_can_receive(void *opaque)
  42 {
  43     STM32F2XXUsartState *s = opaque;
  44
  45     if (!(s->usart_sr & USART_SR_RXNE)) {
  46         return 1;
  47     }
  48
  49     return 0;
  50 }
  51
  52 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
  53 {
  54     STM32F2XXUsartState *s = opaque;
  55
  56     s->usart_dr = *buf;
  57
  58     if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
  59         /* USART not enabled - drop the chars */
  60         DB_PRINT("Dropping the chars\n");
  61         return;
  62     }
  63
  64     s->usart_sr |= USART_SR_RXNE;
  65
  66     if (s->usart_cr1 & USART_CR1_RXNEIE) {
  67         qemu_set_irq(s->irq, 1);
  68     }
  69
  70     DB_PRINT("Receiving: %c\n", s->usart_dr);
  71 }
  72
  73 static void stm32f2xx_usart_reset(DeviceState *dev)
  74 {
  75     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
  76
  77     s->usart_sr = USART_SR_RESET;
  78     s->usart_dr = 0x00000000;
  79     s->usart_brr = 0x00000000;
  80     s->usart_cr1 = 0x00000000;
  81     s->usart_cr2 = 0x00000000;
  82     s->usart_cr3 = 0x00000000;
  83     s->usart_gtpr = 0x00000000;
  84
  85     qemu_set_irq(s->irq, 0);
  86 }
  87
  88 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
  89                                        unsigned int size)
  90 {
  91     STM32F2XXUsartState *s = opaque;
  92     uint64_t retvalue;
  93
  94     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
  95
  96     switch (addr) {
  97     case USART_SR:
  98         retvalue = s->usart_sr;
  99         s->usart_sr &= ~USART_SR_TC;
 100         if (s->chr) {
 101             qemu_chr_accept_input(s->chr);
 102         }
 103         return retvalue;
 104     case USART_DR:
 105         DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
 106         s->usart_sr |= USART_SR_TXE;
 107         s->usart_sr &= ~USART_SR_RXNE;
 108         if (s->chr) {
 109             qemu_chr_accept_input(s->chr);
 110         }
 111         qemu_set_irq(s->irq, 0);
 112         return s->usart_dr & 0x3FF;
 113     case USART_BRR:
 114         return s->usart_brr;
 115     case USART_CR1:
 116         return s->usart_cr1;
 117     case USART_CR2:
 118         return s->usart_cr2;
 119     case USART_CR3:
 120         return s->usart_cr3;
 121     case USART_GTPR:
 122         return s->usart_gtpr;
 123     default:
 124         qemu_log_mask(LOG_GUEST_ERROR,
 125                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 126         return 0;
 127     }
 128
 129     return 0;
 130 }
 131
 132 static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
 133                                   uint64_t val64, unsigned int size)
 134 {
 135     STM32F2XXUsartState *s = opaque;
 136     uint32_t value = val64;
 137     unsigned char ch;
 138
 139     DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
 140
 141     switch (addr) {
 142     case USART_SR:
 143         if (value <= 0x3FF) {
 144             s->usart_sr = value;
 145         } else {
 146             s->usart_sr &= value;
 147         }
 148         if (!(s->usart_sr & USART_SR_RXNE)) {
 149             qemu_set_irq(s->irq, 0);
 150         }
 151         return;
 152     case USART_DR:
 153         if (value < 0xF000) {
 154             ch = value;
 155             if (s->chr) {
 156                 qemu_chr_fe_write_all(s->chr, &ch, 1);
 157             }
 158             s->usart_sr |= USART_SR_TC;
 159             s->usart_sr &= ~USART_SR_TXE;
 160         }
 161         return;
 162     case USART_BRR:
 163         s->usart_brr = value;
 164         return;
 165     case USART_CR1:
 166         s->usart_cr1 = value;
 167             if (s->usart_cr1 & USART_CR1_RXNEIE &&
 168                 s->usart_sr & USART_SR_RXNE) {
 169                 qemu_set_irq(s->irq, 1);
 170             }
 171         return;
 172     case USART_CR2:
 173         s->usart_cr2 = value;
 174         return;
 175     case USART_CR3:
 176         s->usart_cr3 = value;
 177         return;
 178     case USART_GTPR:
 179         s->usart_gtpr = value;
 180         return;
 181     default:
 182         qemu_log_mask(LOG_GUEST_ERROR,
 183                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 184     }
 185 }
 186
 187 static const MemoryRegionOps stm32f2xx_usart_ops = {
 188     .read = stm32f2xx_usart_read,
 189     .write = stm32f2xx_usart_write,
 190     .endianness = DEVICE_NATIVE_ENDIAN,
 191 };
 192
 193 static Property stm32f2xx_usart_properties[] = {
 194     DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr),
 195     DEFINE_PROP_END_OF_LIST(),
 196 };
 197
 198 static void stm32f2xx_usart_init(Object *obj)
 199 {
 200     STM32F2XXUsartState *s = STM32F2XX_USART(obj);
 201
 202     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 203
 204     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
 205                           TYPE_STM32F2XX_USART, 0x2000);
 206     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 207 }
 208
 209 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
 210 {
 211     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
 212
 213     if (s->chr) {
 214         qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
 215                               stm32f2xx_usart_receive, NULL, s);
 216     }
 217 }
 218
 219 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
 220 {
 221     DeviceClass *dc = DEVICE_CLASS(klass);
 222
 223     dc->reset = stm32f2xx_usart_reset;
 224     dc->props = stm32f2xx_usart_properties;
 225     dc->realize = stm32f2xx_usart_realize;
 226 }
 227
 228 static const TypeInfo stm32f2xx_usart_info = {
 229     .name          = TYPE_STM32F2XX_USART,
 230     .parent        = TYPE_SYS_BUS_DEVICE,
 231     .instance_size = sizeof(STM32F2XXUsartState),
 232     .instance_init = stm32f2xx_usart_init,
 233     .class_init    = stm32f2xx_usart_class_init,
 234 };
 235
 236 static void stm32f2xx_usart_register_types(void)
 237 {
 238     type_register_static(&stm32f2xx_usart_info);
 239 }
 240
 241 type_init(stm32f2xx_usart_register_types)