?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target/mips: Correct helper for MSA FCLASS.<W|D> instructions
[qemu/ar7.git] / target / mips / msa_helper.c
bloba383c40eceafdaf5e0b7d1e99746275beaeb75e3
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
28
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
31
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
34
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
37
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
41
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
44
45
46
47 /*
48 * Bit Count
49 * ---------
50 *
51 * +---------------+----------------------------------------------------------+
52 * | NLOC.B | Vector Leading Ones Count (byte) |
53 * | NLOC.H | Vector Leading Ones Count (halfword) |
54 * | NLOC.W | Vector Leading Ones Count (word) |
55 * | NLOC.D | Vector Leading Ones Count (doubleword) |
56 * | NLZC.B | Vector Leading Zeros Count (byte) |
57 * | NLZC.H | Vector Leading Zeros Count (halfword) |
58 * | NLZC.W | Vector Leading Zeros Count (word) |
59 * | NLZC.D | Vector Leading Zeros Count (doubleword) |
60 * | PCNT.B | Vector Population Count (byte) |
61 * | PCNT.H | Vector Population Count (halfword) |
62 * | PCNT.W | Vector Population Count (word) |
63 * | PCNT.D | Vector Population Count (doubleword) |
64 * +---------------+----------------------------------------------------------+
65 */
66
67 /* TODO: insert Bit Count group helpers here */
68
69
70 /*
71 * Bit Move
72 * --------
73 *
74 * +---------------+----------------------------------------------------------+
75 * | BINSL.B | Vector Bit Insert Left (byte) |
76 * | BINSL.H | Vector Bit Insert Left (halfword) |
77 * | BINSL.W | Vector Bit Insert Left (word) |
78 * | BINSL.D | Vector Bit Insert Left (doubleword) |
79 * | BINSR.B | Vector Bit Insert Right (byte) |
80 * | BINSR.H | Vector Bit Insert Right (halfword) |
81 * | BINSR.W | Vector Bit Insert Right (word) |
82 * | BINSR.D | Vector Bit Insert Right (doubleword) |
83 * | BMNZ.V | Vector Bit Move If Not Zero |
84 * | BMZ.V | Vector Bit Move If Zero |
85 * | BSEL.V | Vector Bit Select |
86 * +---------------+----------------------------------------------------------+
87 */
88
89 /* TODO: insert Bit Move group helpers here */
90
91
92 /*
93 * Bit Set
94 * -------
95 *
96 * +---------------+----------------------------------------------------------+
97 * | BCLR.B | Vector Bit Clear (byte) |
98 * | BCLR.H | Vector Bit Clear (halfword) |
99 * | BCLR.W | Vector Bit Clear (word) |
100 * | BCLR.D | Vector Bit Clear (doubleword) |
101 * | BNEG.B | Vector Bit Negate (byte) |
102 * | BNEG.H | Vector Bit Negate (halfword) |
103 * | BNEG.W | Vector Bit Negate (word) |
104 * | BNEG.D | Vector Bit Negate (doubleword) |
105 * | BSET.B | Vector Bit Set (byte) |
106 * | BSET.H | Vector Bit Set (halfword) |
107 * | BSET.W | Vector Bit Set (word) |
108 * | BSET.D | Vector Bit Set (doubleword) |
109 * +---------------+----------------------------------------------------------+
110 */
111
112 /* TODO: insert Bit Set group helpers here */
113
114
115 /*
116 * Fixed Multiply
117 * --------------
118 *
119 * +---------------+----------------------------------------------------------+
120 * | MADD_Q.H | Vector Fixed-Point Multiply and Add (halfword) |
121 * | MADD_Q.W | Vector Fixed-Point Multiply and Add (word) |
122 * | MADDR_Q.H | Vector Fixed-Point Multiply and Add Rounded (halfword) |
123 * | MADDR_Q.W | Vector Fixed-Point Multiply and Add Rounded (word) |
124 * | MSUB_Q.H | Vector Fixed-Point Multiply and Subtr. (halfword) |
125 * | MSUB_Q.W | Vector Fixed-Point Multiply and Subtr. (word) |
126 * | MSUBR_Q.H | Vector Fixed-Point Multiply and Subtr. Rounded (halfword)|
127 * | MSUBR_Q.W | Vector Fixed-Point Multiply and Subtr. Rounded (word) |
128 * | MUL_Q.H | Vector Fixed-Point Multiply (halfword) |
129 * | MUL_Q.W | Vector Fixed-Point Multiply (word) |
130 * | MULR_Q.H | Vector Fixed-Point Multiply Rounded (halfword) |
131 * | MULR_Q.W | Vector Fixed-Point Multiply Rounded (word) |
132 * +---------------+----------------------------------------------------------+
133 */
134
135 /* TODO: insert Fixed Multiply group helpers here */
136
137
138 /*
139 * Float Max Min
140 * -------------
141 *
142 * +---------------+----------------------------------------------------------+
143 * | FMAX_A.W | Vector Floating-Point Maximum (Absolute) (word) |
144 * | FMAX_A.D | Vector Floating-Point Maximum (Absolute) (doubleword) |
145 * | FMAX.W | Vector Floating-Point Maximum (word) |
146 * | FMAX.D | Vector Floating-Point Maximum (doubleword) |
147 * | FMIN_A.W | Vector Floating-Point Minimum (Absolute) (word) |
148 * | FMIN_A.D | Vector Floating-Point Minimum (Absolute) (doubleword) |
149 * | FMIN.W | Vector Floating-Point Minimum (word) |
150 * | FMIN.D | Vector Floating-Point Minimum (doubleword) |
151 * +---------------+----------------------------------------------------------+
152 */
153
154 /* TODO: insert Float Max Min group helpers here */
155
156
157 /*
158 * Int Add
159 * -------
160 *
161 * +---------------+----------------------------------------------------------+
162 * | ADD_A.B | Vector Add Absolute Values (byte) |
163 * | ADD_A.H | Vector Add Absolute Values (halfword) |
164 * | ADD_A.W | Vector Add Absolute Values (word) |
165 * | ADD_A.D | Vector Add Absolute Values (doubleword) |
166 * | ADDS_A.B | Vector Signed Saturated Add (of Absolute) (byte) |
167 * | ADDS_A.H | Vector Signed Saturated Add (of Absolute) (halfword) |
168 * | ADDS_A.W | Vector Signed Saturated Add (of Absolute) (word) |
169 * | ADDS_A.D | Vector Signed Saturated Add (of Absolute) (doubleword) |
170 * | ADDS_S.B | Vector Signed Saturated Add (of Signed) (byte) |
171 * | ADDS_S.H | Vector Signed Saturated Add (of Signed) (halfword) |
172 * | ADDS_S.W | Vector Signed Saturated Add (of Signed) (word) |
173 * | ADDS_S.D | Vector Signed Saturated Add (of Signed) (doubleword) |
174 * | ADDS_U.B | Vector Unsigned Saturated Add (of Unsigned) (byte) |
175 * | ADDS_U.H | Vector Unsigned Saturated Add (of Unsigned) (halfword) |
176 * | ADDS_U.W | Vector Unsigned Saturated Add (of Unsigned) (word) |
177 * | ADDS_U.D | Vector Unsigned Saturated Add (of Unsigned) (doubleword) |
178 * | ADDV.B | Vector Add (byte) |
179 * | ADDV.H | Vector Add (halfword) |
180 * | ADDV.W | Vector Add (word) |
181 * | ADDV.D | Vector Add (doubleword) |
182 * | HADD_S.H | Vector Signed Horizontal Add (halfword) |
183 * | HADD_S.W | Vector Signed Horizontal Add (word) |
184 * | HADD_S.D | Vector Signed Horizontal Add (doubleword) |
185 * | HADD_U.H | Vector Unigned Horizontal Add (halfword) |
186 * | HADD_U.W | Vector Unigned Horizontal Add (word) |
187 * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) |
188 * +---------------+----------------------------------------------------------+
189 */
190
191 /* TODO: insert Int Add group helpers here */
192
193
194 /*
195 * Int Average
196 * -----------
197 *
198 * +---------------+----------------------------------------------------------+
199 * | AVE_S.B | Vector Signed Average (byte) |
200 * | AVE_S.H | Vector Signed Average (halfword) |
201 * | AVE_S.W | Vector Signed Average (word) |
202 * | AVE_S.D | Vector Signed Average (doubleword) |
203 * | AVE_U.B | Vector Unsigned Average (byte) |
204 * | AVE_U.H | Vector Unsigned Average (halfword) |
205 * | AVE_U.W | Vector Unsigned Average (word) |
206 * | AVE_U.D | Vector Unsigned Average (doubleword) |
207 * | AVER_S.B | Vector Signed Average Rounded (byte) |
208 * | AVER_S.H | Vector Signed Average Rounded (halfword) |
209 * | AVER_S.W | Vector Signed Average Rounded (word) |
210 * | AVER_S.D | Vector Signed Average Rounded (doubleword) |
211 * | AVER_U.B | Vector Unsigned Average Rounded (byte) |
212 * | AVER_U.H | Vector Unsigned Average Rounded (halfword) |
213 * | AVER_U.W | Vector Unsigned Average Rounded (word) |
214 * | AVER_U.D | Vector Unsigned Average Rounded (doubleword) |
215 * +---------------+----------------------------------------------------------+
216 */
217
218 /* TODO: insert Int Average group helpers here */
219
220
221 /*
222 * Int Compare
223 * -----------
224 *
225 * +---------------+----------------------------------------------------------+
226 * | CEQ.B | Vector Compare Equal (byte) |
227 * | CEQ.H | Vector Compare Equal (halfword) |
228 * | CEQ.W | Vector Compare Equal (word) |
229 * | CEQ.D | Vector Compare Equal (doubleword) |
230 * | CLE_S.B | Vector Compare Signed Less Than or Equal (byte) |
231 * | CLE_S.H | Vector Compare Signed Less Than or Equal (halfword) |
232 * | CLE_S.W | Vector Compare Signed Less Than or Equal (word) |
233 * | CLE_S.D | Vector Compare Signed Less Than or Equal (doubleword) |
234 * | CLE_U.B | Vector Compare Unsigned Less Than or Equal (byte) |
235 * | CLE_U.H | Vector Compare Unsigned Less Than or Equal (halfword) |
236 * | CLE_U.W | Vector Compare Unsigned Less Than or Equal (word) |
237 * | CLE_U.D | Vector Compare Unsigned Less Than or Equal (doubleword) |
238 * | CLT_S.B | Vector Compare Signed Less Than (byte) |
239 * | CLT_S.H | Vector Compare Signed Less Than (halfword) |
240 * | CLT_S.W | Vector Compare Signed Less Than (word) |
241 * | CLT_S.D | Vector Compare Signed Less Than (doubleword) |
242 * | CLT_U.B | Vector Compare Unsigned Less Than (byte) |
243 * | CLT_U.H | Vector Compare Unsigned Less Than (halfword) |
244 * | CLT_U.W | Vector Compare Unsigned Less Than (word) |
245 * | CLT_U.D | Vector Compare Unsigned Less Than (doubleword) |
246 * +---------------+----------------------------------------------------------+
247 */
248
249 /* TODO: insert Int Compare group helpers here */
250
251
252 /*
253 * Int Divide
254 * ----------
255 *
256 * +---------------+----------------------------------------------------------+
257 * | DIV_S.B | Vector Signed Divide (byte) |
258 * | DIV_S.H | Vector Signed Divide (halfword) |
259 * | DIV_S.W | Vector Signed Divide (word) |
260 * | DIV_S.D | Vector Signed Divide (doubleword) |
261 * | DIV_U.B | Vector Unsigned Divide (byte) |
262 * | DIV_U.H | Vector Unsigned Divide (halfword) |
263 * | DIV_U.W | Vector Unsigned Divide (word) |
264 * | DIV_U.D | Vector Unsigned Divide (doubleword) |
265 * +---------------+----------------------------------------------------------+
266 */
267
268 /* TODO: insert Int Divide group helpers here */
269
270
271 /*
272 * Int Dot Product
273 * ---------------
274 *
275 * +---------------+----------------------------------------------------------+
276 * | DOTP_S.H | Vector Signed Dot Product (halfword) |
277 * | DOTP_S.W | Vector Signed Dot Product (word) |
278 * | DOTP_S.D | Vector Signed Dot Product (doubleword) |
279 * | DOTP_U.H | Vector Unsigned Dot Product (halfword) |
280 * | DOTP_U.W | Vector Unsigned Dot Product (word) |
281 * | DOTP_U.D | Vector Unsigned Dot Product (doubleword) |
282 * | DPADD_S.H | Vector Signed Dot Product (halfword) |
283 * | DPADD_S.W | Vector Signed Dot Product (word) |
284 * | DPADD_S.D | Vector Signed Dot Product (doubleword) |
285 * | DPADD_U.H | Vector Unsigned Dot Product (halfword) |
286 * | DPADD_U.W | Vector Unsigned Dot Product (word) |
287 * | DPADD_U.D | Vector Unsigned Dot Product (doubleword) |
288 * | DPSUB_S.H | Vector Signed Dot Product (halfword) |
289 * | DPSUB_S.W | Vector Signed Dot Product (word) |
290 * | DPSUB_S.D | Vector Signed Dot Product (doubleword) |
291 * | DPSUB_U.H | Vector Unsigned Dot Product (halfword) |
292 * | DPSUB_U.W | Vector Unsigned Dot Product (word) |
293 * | DPSUB_U.D | Vector Unsigned Dot Product (doubleword) |
294 * +---------------+----------------------------------------------------------+
295 */
296
297 /* TODO: insert Int Dot Product group helpers here */
298
299
300 /*
301 * Int Max Min
302 * -----------
303 *
304 * +---------------+----------------------------------------------------------+
305 * | MAX_A.B | Vector Maximum Based on Absolute Value (byte) |
306 * | MAX_A.H | Vector Maximum Based on Absolute Value (halfword) |
307 * | MAX_A.W | Vector Maximum Based on Absolute Value (word) |
308 * | MAX_A.D | Vector Maximum Based on Absolute Value (doubleword) |
309 * | MAX_S.B | Vector Signed Maximum (byte) |
310 * | MAX_S.H | Vector Signed Maximum (halfword) |
311 * | MAX_S.W | Vector Signed Maximum (word) |
312 * | MAX_S.D | Vector Signed Maximum (doubleword) |
313 * | MAX_U.B | Vector Unsigned Maximum (byte) |
314 * | MAX_U.H | Vector Unsigned Maximum (halfword) |
315 * | MAX_U.W | Vector Unsigned Maximum (word) |
316 * | MAX_U.D | Vector Unsigned Maximum (doubleword) |
317 * | MIN_A.B | Vector Minimum Based on Absolute Value (byte) |
318 * | MIN_A.H | Vector Minimum Based on Absolute Value (halfword) |
319 * | MIN_A.W | Vector Minimum Based on Absolute Value (word) |
320 * | MIN_A.D | Vector Minimum Based on Absolute Value (doubleword) |
321 * | MIN_S.B | Vector Signed Minimum (byte) |
322 * | MIN_S.H | Vector Signed Minimum (halfword) |
323 * | MIN_S.W | Vector Signed Minimum (word) |
324 * | MIN_S.D | Vector Signed Minimum (doubleword) |
325 * | MIN_U.B | Vector Unsigned Minimum (byte) |
326 * | MIN_U.H | Vector Unsigned Minimum (halfword) |
327 * | MIN_U.W | Vector Unsigned Minimum (word) |
328 * | MIN_U.D | Vector Unsigned Minimum (doubleword) |
329 * +---------------+----------------------------------------------------------+
330 */
331
332 /* TODO: insert Int Max Min group helpers here */
333
334
335 /*
336 * Int Modulo
337 * ----------
338 *
339 * +---------------+----------------------------------------------------------+
340 * | MOD_S.B | Vector Signed Modulo (byte) |
341 * | MOD_S.H | Vector Signed Modulo (halfword) |
342 * | MOD_S.W | Vector Signed Modulo (word) |
343 * | MOD_S.D | Vector Signed Modulo (doubleword) |
344 * | MOD_U.B | Vector Unsigned Modulo (byte) |
345 * | MOD_U.H | Vector Unsigned Modulo (halfword) |
346 * | MOD_U.W | Vector Unsigned Modulo (word) |
347 * | MOD_U.D | Vector Unsigned Modulo (doubleword) |
348 * +---------------+----------------------------------------------------------+
349 */
350
351 /* TODO: insert Int Modulo group helpers here */
352
353
354 /*
355 * Int Multiply
356 * ------------
357 *
358 * +---------------+----------------------------------------------------------+
359 * | MADDV.B | Vector Multiply and Add (byte) |
360 * | MADDV.H | Vector Multiply and Add (halfword) |
361 * | MADDV.W | Vector Multiply and Add (word) |
362 * | MADDV.D | Vector Multiply and Add (doubleword) |
363 * | MSUBV.B | Vector Multiply and Subtract (byte) |
364 * | MSUBV.H | Vector Multiply and Subtract (halfword) |
365 * | MSUBV.W | Vector Multiply and Subtract (word) |
366 * | MSUBV.D | Vector Multiply and Subtract (doubleword) |
367 * | MULV.B | Vector Multiply (byte) |
368 * | MULV.H | Vector Multiply (halfword) |
369 * | MULV.W | Vector Multiply (word) |
370 * | MULV.D | Vector Multiply (doubleword) |
371 * +---------------+----------------------------------------------------------+
372 */
373
374 /* TODO: insert Int Multiply group helpers here */
375
376
377 /*
378 * Int Subtract
379 * ------------
380 *
381 * +---------------+----------------------------------------------------------+
382 * | ASUB_S.B | Vector Absolute Values of Signed Subtract (byte) |
383 * | ASUB_S.H | Vector Absolute Values of Signed Subtract (halfword) |
384 * | ASUB_S.W | Vector Absolute Values of Signed Subtract (word) |
385 * | ASUB_S.D | Vector Absolute Values of Signed Subtract (doubleword) |
386 * | ASUB_U.B | Vector Absolute Values of Unsigned Subtract (byte) |
387 * | ASUB_U.H | Vector Absolute Values of Unsigned Subtract (halfword) |
388 * | ASUB_U.W | Vector Absolute Values of Unsigned Subtract (word) |
389 * | ASUB_U.D | Vector Absolute Values of Unsigned Subtract (doubleword) |
390 * | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) |
391 * | HSUB_S.W | Vector Signed Horizontal Subtract (word) |
392 * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) |
393 * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) |
394 * | HSUB_U.W | Vector Unigned Horizontal Subtract (word) |
395 * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) |
396 * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) |
397 * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) |
398 * | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) |
399 * | SUBS_S.D | Vector Signed Saturated Subtract (of Signed) (doubleword)|
400 * | SUBS_U.B | Vector Unsigned Saturated Subtract (of Uns.) (byte) |
401 * | SUBS_U.H | Vector Unsigned Saturated Subtract (of Uns.) (halfword) |
402 * | SUBS_U.W | Vector Unsigned Saturated Subtract (of Uns.) (word) |
403 * | SUBS_U.D | Vector Unsigned Saturated Subtract (of Uns.) (doubleword)|
404 * | SUBSUS_U.B | Vector Uns. Sat. Subtract (of S. from Uns.) (byte) |
405 * | SUBSUS_U.H | Vector Uns. Sat. Subtract (of S. from Uns.) (halfword) |
406 * | SUBSUS_U.W | Vector Uns. Sat. Subtract (of S. from Uns.) (word) |
407 * | SUBSUS_U.D | Vector Uns. Sat. Subtract (of S. from Uns.) (doubleword) |
408 * | SUBSUU_S.B | Vector Signed Saturated Subtract (of Uns.) (byte) |
409 * | SUBSUU_S.H | Vector Signed Saturated Subtract (of Uns.) (halfword) |
410 * | SUBSUU_S.W | Vector Signed Saturated Subtract (of Uns.) (word) |
411 * | SUBSUU_S.D | Vector Signed Saturated Subtract (of Uns.) (doubleword) |
412 * | SUBV.B | Vector Subtract (byte) |
413 * | SUBV.H | Vector Subtract (halfword) |
414 * | SUBV.W | Vector Subtract (word) |
415 * | SUBV.D | Vector Subtract (doubleword) |
416 * +---------------+----------------------------------------------------------+
417 */
418
419 /* TODO: insert Int Subtract group helpers here */
420
421
422 /*
423 * Interleave
424 * ----------
425 *
426 * +---------------+----------------------------------------------------------+
427 * | ILVEV.B | Vector Interleave Even (byte) |
428 * | ILVEV.H | Vector Interleave Even (halfword) |
429 * | ILVEV.W | Vector Interleave Even (word) |
430 * | ILVEV.D | Vector Interleave Even (doubleword) |
431 * | ILVOD.B | Vector Interleave Odd (byte) |
432 * | ILVOD.H | Vector Interleave Odd (halfword) |
433 * | ILVOD.W | Vector Interleave Odd (word) |
434 * | ILVOD.D | Vector Interleave Odd (doubleword) |
435 * | ILVL.B | Vector Interleave Left (byte) |
436 * | ILVL.H | Vector Interleave Left (halfword) |
437 * | ILVL.W | Vector Interleave Left (word) |
438 * | ILVL.D | Vector Interleave Left (doubleword) |
439 * | ILVR.B | Vector Interleave Right (byte) |
440 * | ILVR.H | Vector Interleave Right (halfword) |
441 * | ILVR.W | Vector Interleave Right (word) |
442 * | ILVR.D | Vector Interleave Right (doubleword) |
443 * +---------------+----------------------------------------------------------+
444 */
445
446 /* TODO: insert Interleave group helpers here */
447
448
449 /*
450 * Logic
451 * -----
452 *
453 * +---------------+----------------------------------------------------------+
454 * | AND.V | Vector Logical And |
455 * | NOR.V | Vector Logical Negated Or |
456 * | OR.V | Vector Logical Or |
457 * | XOR.V | Vector Logical Exclusive Or |
458 * +---------------+----------------------------------------------------------+
459 */
460
461 /* TODO: insert Logic group helpers here */
462
463
464 /*
465 * Move
466 * ----
467 *
468 * +---------------+----------------------------------------------------------+
469 * | MOVE.V | Vector Move |
470 * +---------------+----------------------------------------------------------+
471 */
472
473 /* TODO: insert Move group helpers here */
474
475
476 /*
477 * Pack
478 * ----
479 *
480 * +---------------+----------------------------------------------------------+
481 * | PCKEV.B | Vector Pack Even (byte) |
482 * | PCKEV.H | Vector Pack Even (halfword) |
483 * | PCKEV.W | Vector Pack Even (word) |
484 * | PCKEV.D | Vector Pack Even (doubleword) |
485 * | PCKOD.B | Vector Pack Odd (byte) |
486 * | PCKOD.H | Vector Pack Odd (halfword) |
487 * | PCKOD.W | Vector Pack Odd (word) |
488 * | PCKOD.D | Vector Pack Odd (doubleword) |
489 * | VSHF.B | Vector Data Preserving Shuffle (byte) |
490 * | VSHF.H | Vector Data Preserving Shuffle (halfword) |
491 * | VSHF.W | Vector Data Preserving Shuffle (word) |
492 * | VSHF.D | Vector Data Preserving Shuffle (doubleword) |
493 * +---------------+----------------------------------------------------------+
494 */
495
496 /* TODO: insert Pack group helpers here */
497
498
499 /*
500 * Shift
501 * -----
502 *
503 * +---------------+----------------------------------------------------------+
504 * | SLL.B | Vector Shift Left (byte) |
505 * | SLL.H | Vector Shift Left (halfword) |
506 * | SLL.W | Vector Shift Left (word) |
507 * | SLL.D | Vector Shift Left (doubleword) |
508 * | SRA.B | Vector Shift Right Arithmetic (byte) |
509 * | SRA.H | Vector Shift Right Arithmetic (halfword) |
510 * | SRA.W | Vector Shift Right Arithmetic (word) |
511 * | SRA.D | Vector Shift Right Arithmetic (doubleword) |
512 * | SRAR.B | Vector Shift Right Arithmetic Rounded (byte) |
513 * | SRAR.H | Vector Shift Right Arithmetic Rounded (halfword) |
514 * | SRAR.W | Vector Shift Right Arithmetic Rounded (word) |
515 * | SRAR.D | Vector Shift Right Arithmetic Rounded (doubleword) |
516 * | SRL.B | Vector Shift Right Logical (byte) |
517 * | SRL.H | Vector Shift Right Logical (halfword) |
518 * | SRL.W | Vector Shift Right Logical (word) |
519 * | SRL.D | Vector Shift Right Logical (doubleword) |
520 * | SRLR.B | Vector Shift Right Logical Rounded (byte) |
521 * | SRLR.H | Vector Shift Right Logical Rounded (halfword) |
522 * | SRLR.W | Vector Shift Right Logical Rounded (word) |
523 * | SRLR.D | Vector Shift Right Logical Rounded (doubleword) |
524 * +---------------+----------------------------------------------------------+
525 */
526
527 /* TODO: insert Shift group helpers here */
528
529
530 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
531 {
532 uint32_t i;
533
534 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
535 pwd->d[i] = pws->d[i];
536 }
537 }
538
539 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
540 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
541 uint32_t i8) \
542 { \
543 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
544 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
545 uint32_t i; \
546 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
547 DEST = OPERATION; \
548 } \
549 }
550
551 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
552 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
553 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
554 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
555
556 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
557 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
558 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
559 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
560
561 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
562 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
563 MSA_FN_IMM8(bmzi_b, pwd->b[i],
564 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
565
566 #define BIT_SELECT(dest, arg1, arg2, df) \
567 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
568 MSA_FN_IMM8(bseli_b, pwd->b[i],
569 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
570
571 #undef MSA_FN_IMM8
572
573 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
574
575 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
576 uint32_t ws, uint32_t imm)
577 {
578 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
579 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
580 wr_t wx, *pwx = &wx;
581 uint32_t i;
582
583 switch (df) {
584 case DF_BYTE:
585 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
586 pwx->b[i] = pws->b[SHF_POS(i, imm)];
587 }
588 break;
589 case DF_HALF:
590 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
591 pwx->h[i] = pws->h[SHF_POS(i, imm)];
592 }
593 break;
594 case DF_WORD:
595 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
596 pwx->w[i] = pws->w[SHF_POS(i, imm)];
597 }
598 break;
599 default:
600 assert(0);
601 }
602 msa_move_v(pwd, pwx);
603 }
604
605 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
606 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
607 uint32_t wt) \
608 { \
609 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
610 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
611 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
612 uint32_t i; \
613 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
614 DEST = OPERATION; \
615 } \
616 }
617
618 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
619 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
620 MSA_FN_VECTOR(bmz_v, pwd->d[i],
621 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
622 MSA_FN_VECTOR(bsel_v, pwd->d[i],
623 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
624 #undef BIT_MOVE_IF_NOT_ZERO
625 #undef BIT_MOVE_IF_ZERO
626 #undef BIT_SELECT
627 #undef MSA_FN_VECTOR
628
629 void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
630 {
631 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
632 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
633 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
634
635 pwd->d[0] = pws->d[0] & pwt->d[0];
636 pwd->d[1] = pws->d[1] & pwt->d[1];
637 }
638
639 void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
640 {
641 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
642 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
643 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
644
645 pwd->d[0] = pws->d[0] | pwt->d[0];
646 pwd->d[1] = pws->d[1] | pwt->d[1];
647 }
648
649 void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
650 {
651 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
652 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
653 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
654
655 pwd->d[0] = ~(pws->d[0] | pwt->d[0]);
656 pwd->d[1] = ~(pws->d[1] | pwt->d[1]);
657 }
658
659 void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
660 {
661 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
662 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
663 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
664
665 pwd->d[0] = pws->d[0] ^ pwt->d[0];
666 pwd->d[1] = pws->d[1] ^ pwt->d[1];
667 }
668
669 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
670 {
671 return arg1 + arg2;
672 }
673
674 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
675 {
676 return arg1 - arg2;
677 }
678
679 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
680 {
681 return arg1 == arg2 ? -1 : 0;
682 }
683
684 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
685 {
686 return arg1 <= arg2 ? -1 : 0;
687 }
688
689 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
690 {
691 uint64_t u_arg1 = UNSIGNED(arg1, df);
692 uint64_t u_arg2 = UNSIGNED(arg2, df);
693 return u_arg1 <= u_arg2 ? -1 : 0;
694 }
695
696 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
697 {
698 return arg1 < arg2 ? -1 : 0;
699 }
700
701 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
702 {
703 uint64_t u_arg1 = UNSIGNED(arg1, df);
704 uint64_t u_arg2 = UNSIGNED(arg2, df);
705 return u_arg1 < u_arg2 ? -1 : 0;
706 }
707
708 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
709 {
710 return arg1 > arg2 ? arg1 : arg2;
711 }
712
713 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
714 {
715 uint64_t u_arg1 = UNSIGNED(arg1, df);
716 uint64_t u_arg2 = UNSIGNED(arg2, df);
717 return u_arg1 > u_arg2 ? arg1 : arg2;
718 }
719
720 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
721 {
722 return arg1 < arg2 ? arg1 : arg2;
723 }
724
725 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
726 {
727 uint64_t u_arg1 = UNSIGNED(arg1, df);
728 uint64_t u_arg2 = UNSIGNED(arg2, df);
729 return u_arg1 < u_arg2 ? arg1 : arg2;
730 }
731
732 #define MSA_BINOP_IMM_DF(helper, func) \
733 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
734 uint32_t wd, uint32_t ws, int32_t u5) \
735 { \
736 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
737 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
738 uint32_t i; \
739 \
740 switch (df) { \
741 case DF_BYTE: \
742 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
743 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
744 } \
745 break; \
746 case DF_HALF: \
747 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
748 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
749 } \
750 break; \
751 case DF_WORD: \
752 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
753 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
754 } \
755 break; \
756 case DF_DOUBLE: \
757 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
758 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
759 } \
760 break; \
761 default: \
762 assert(0); \
763 } \
764 }
765
766 MSA_BINOP_IMM_DF(addvi, addv)
767 MSA_BINOP_IMM_DF(subvi, subv)
768 MSA_BINOP_IMM_DF(ceqi, ceq)
769 MSA_BINOP_IMM_DF(clei_s, cle_s)
770 MSA_BINOP_IMM_DF(clei_u, cle_u)
771 MSA_BINOP_IMM_DF(clti_s, clt_s)
772 MSA_BINOP_IMM_DF(clti_u, clt_u)
773 MSA_BINOP_IMM_DF(maxi_s, max_s)
774 MSA_BINOP_IMM_DF(maxi_u, max_u)
775 MSA_BINOP_IMM_DF(mini_s, min_s)
776 MSA_BINOP_IMM_DF(mini_u, min_u)
777 #undef MSA_BINOP_IMM_DF
778
779 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
780 int32_t s10)
781 {
782 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
783 uint32_t i;
784
785 switch (df) {
786 case DF_BYTE:
787 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
788 pwd->b[i] = (int8_t)s10;
789 }
790 break;
791 case DF_HALF:
792 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
793 pwd->h[i] = (int16_t)s10;
794 }
795 break;
796 case DF_WORD:
797 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
798 pwd->w[i] = (int32_t)s10;
799 }
800 break;
801 case DF_DOUBLE:
802 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
803 pwd->d[i] = (int64_t)s10;
804 }
805 break;
806 default:
807 assert(0);
808 }
809 }
810
811 /* Data format bit position and unsigned values */
812 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
813
814 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
815 {
816 int32_t b_arg2 = BIT_POSITION(arg2, df);
817 return arg1 << b_arg2;
818 }
819
820 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
821 {
822 int32_t b_arg2 = BIT_POSITION(arg2, df);
823 return arg1 >> b_arg2;
824 }
825
826 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
827 {
828 uint64_t u_arg1 = UNSIGNED(arg1, df);
829 int32_t b_arg2 = BIT_POSITION(arg2, df);
830 return u_arg1 >> b_arg2;
831 }
832
833 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
834 {
835 int32_t b_arg2 = BIT_POSITION(arg2, df);
836 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
837 }
838
839 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
840 int64_t arg2)
841 {
842 int32_t b_arg2 = BIT_POSITION(arg2, df);
843 return UNSIGNED(arg1 | (1LL << b_arg2), df);
844 }
845
846 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
847 {
848 int32_t b_arg2 = BIT_POSITION(arg2, df);
849 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
850 }
851
852 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
853 int64_t arg2)
854 {
855 uint64_t u_arg1 = UNSIGNED(arg1, df);
856 uint64_t u_dest = UNSIGNED(dest, df);
857 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
858 int32_t sh_a = DF_BITS(df) - sh_d;
859 if (sh_d == DF_BITS(df)) {
860 return u_arg1;
861 } else {
862 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
863 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
864 }
865 }
866
867 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
868 int64_t arg2)
869 {
870 uint64_t u_arg1 = UNSIGNED(arg1, df);
871 uint64_t u_dest = UNSIGNED(dest, df);
872 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
873 int32_t sh_a = DF_BITS(df) - sh_d;
874 if (sh_d == DF_BITS(df)) {
875 return u_arg1;
876 } else {
877 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
878 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
879 }
880 }
881
882 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
883 {
884 return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
885 arg > M_MAX_INT(m + 1) ? M_MAX_INT(m + 1) :
886 arg;
887 }
888
889 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
890 {
891 uint64_t u_arg = UNSIGNED(arg, df);
892 return u_arg < M_MAX_UINT(m + 1) ? u_arg :
893 M_MAX_UINT(m + 1);
894 }
895
896 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
897 {
898 int32_t b_arg2 = BIT_POSITION(arg2, df);
899 if (b_arg2 == 0) {
900 return arg1;
901 } else {
902 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
903 return (arg1 >> b_arg2) + r_bit;
904 }
905 }
906
907 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
908 {
909 uint64_t u_arg1 = UNSIGNED(arg1, df);
910 int32_t b_arg2 = BIT_POSITION(arg2, df);
911 if (b_arg2 == 0) {
912 return u_arg1;
913 } else {
914 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
915 return (u_arg1 >> b_arg2) + r_bit;
916 }
917 }
918
919 #define MSA_BINOP_IMMU_DF(helper, func) \
920 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
921 uint32_t ws, uint32_t u5) \
922 { \
923 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
924 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
925 uint32_t i; \
926 \
927 switch (df) { \
928 case DF_BYTE: \
929 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
930 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
931 } \
932 break; \
933 case DF_HALF: \
934 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
935 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
936 } \
937 break; \
938 case DF_WORD: \
939 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
940 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
941 } \
942 break; \
943 case DF_DOUBLE: \
944 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
945 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
946 } \
947 break; \
948 default: \
949 assert(0); \
950 } \
951 }
952
953 MSA_BINOP_IMMU_DF(slli, sll)
954 MSA_BINOP_IMMU_DF(srai, sra)
955 MSA_BINOP_IMMU_DF(srli, srl)
956 MSA_BINOP_IMMU_DF(bclri, bclr)
957 MSA_BINOP_IMMU_DF(bseti, bset)
958 MSA_BINOP_IMMU_DF(bnegi, bneg)
959 MSA_BINOP_IMMU_DF(sat_s, sat_s)
960 MSA_BINOP_IMMU_DF(sat_u, sat_u)
961 MSA_BINOP_IMMU_DF(srari, srar)
962 MSA_BINOP_IMMU_DF(srlri, srlr)
963 #undef MSA_BINOP_IMMU_DF
964
965 #define MSA_TEROP_IMMU_DF(helper, func) \
966 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
967 uint32_t wd, uint32_t ws, uint32_t u5) \
968 { \
969 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
970 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
971 uint32_t i; \
972 \
973 switch (df) { \
974 case DF_BYTE: \
975 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
976 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
977 u5); \
978 } \
979 break; \
980 case DF_HALF: \
981 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
982 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
983 u5); \
984 } \
985 break; \
986 case DF_WORD: \
987 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
988 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
989 u5); \
990 } \
991 break; \
992 case DF_DOUBLE: \
993 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
994 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
995 u5); \
996 } \
997 break; \
998 default: \
999 assert(0); \
1000 } \
1001 }
1002
1003 MSA_TEROP_IMMU_DF(binsli, binsl)
1004 MSA_TEROP_IMMU_DF(binsri, binsr)
1005 #undef MSA_TEROP_IMMU_DF
1006
1007 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
1008 {
1009 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
1010 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
1011 return abs_arg1 > abs_arg2 ? arg1 : arg2;
1012 }
1013
1014 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
1015 {
1016 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
1017 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
1018 return abs_arg1 < abs_arg2 ? arg1 : arg2;
1019 }
1020
1021 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
1022 {
1023 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
1024 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
1025 return abs_arg1 + abs_arg2;
1026 }
1027
1028 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
1029 {
1030 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
1031 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
1032 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
1033 if (abs_arg1 > max_int || abs_arg2 > max_int) {
1034 return (int64_t)max_int;
1035 } else {
1036 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
1037 }
1038 }
1039
1040 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1041 {
1042 int64_t max_int = DF_MAX_INT(df);
1043 int64_t min_int = DF_MIN_INT(df);
1044 if (arg1 < 0) {
1045 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
1046 } else {
1047 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
1048 }
1049 }
1050
1051 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
1052 {
1053 uint64_t max_uint = DF_MAX_UINT(df);
1054 uint64_t u_arg1 = UNSIGNED(arg1, df);
1055 uint64_t u_arg2 = UNSIGNED(arg2, df);
1056 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
1057 }
1058
1059 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1060 {
1061 /* signed shift */
1062 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
1063 }
1064
1065 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
1066 {
1067 uint64_t u_arg1 = UNSIGNED(arg1, df);
1068 uint64_t u_arg2 = UNSIGNED(arg2, df);
1069 /* unsigned shift */
1070 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
1071 }
1072
1073 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1074 {
1075 /* signed shift */
1076 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
1077 }
1078
1079 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
1080 {
1081 uint64_t u_arg1 = UNSIGNED(arg1, df);
1082 uint64_t u_arg2 = UNSIGNED(arg2, df);
1083 /* unsigned shift */
1084 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
1085 }
1086
1087 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1088 {
1089 int64_t max_int = DF_MAX_INT(df);
1090 int64_t min_int = DF_MIN_INT(df);
1091 if (arg2 > 0) {
1092 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
1093 } else {
1094 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
1095 }
1096 }
1097
1098 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1099 {
1100 uint64_t u_arg1 = UNSIGNED(arg1, df);
1101 uint64_t u_arg2 = UNSIGNED(arg2, df);
1102 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
1103 }
1104
1105 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1106 {
1107 uint64_t u_arg1 = UNSIGNED(arg1, df);
1108 uint64_t max_uint = DF_MAX_UINT(df);
1109 if (arg2 >= 0) {
1110 uint64_t u_arg2 = (uint64_t)arg2;
1111 return (u_arg1 > u_arg2) ?
1112 (int64_t)(u_arg1 - u_arg2) :
1113 0;
1114 } else {
1115 uint64_t u_arg2 = (uint64_t)(-arg2);
1116 return (u_arg1 < max_uint - u_arg2) ?
1117 (int64_t)(u_arg1 + u_arg2) :
1118 (int64_t)max_uint;
1119 }
1120 }
1121
1122 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1123 {
1124 uint64_t u_arg1 = UNSIGNED(arg1, df);
1125 uint64_t u_arg2 = UNSIGNED(arg2, df);
1126 int64_t max_int = DF_MAX_INT(df);
1127 int64_t min_int = DF_MIN_INT(df);
1128 if (u_arg1 > u_arg2) {
1129 return u_arg1 - u_arg2 < (uint64_t)max_int ?
1130 (int64_t)(u_arg1 - u_arg2) :
1131 max_int;
1132 } else {
1133 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
1134 (int64_t)(u_arg1 - u_arg2) :
1135 min_int;
1136 }
1137 }
1138
1139 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1140 {
1141 /* signed compare */
1142 return (arg1 < arg2) ?
1143 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
1144 }
1145
1146 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
1147 {
1148 uint64_t u_arg1 = UNSIGNED(arg1, df);
1149 uint64_t u_arg2 = UNSIGNED(arg2, df);
1150 /* unsigned compare */
1151 return (u_arg1 < u_arg2) ?
1152 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
1153 }
1154
1155 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
1156 {
1157 return arg1 * arg2;
1158 }
1159
1160 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1161 {
1162 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
1163 return DF_MIN_INT(df);
1164 }
1165 return arg2 ? arg1 / arg2
1166 : arg1 >= 0 ? -1 : 1;
1167 }
1168
1169 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1170 {
1171 uint64_t u_arg1 = UNSIGNED(arg1, df);
1172 uint64_t u_arg2 = UNSIGNED(arg2, df);
1173 return arg2 ? u_arg1 / u_arg2 : -1;
1174 }
1175
1176 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1177 {
1178 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
1179 return 0;
1180 }
1181 return arg2 ? arg1 % arg2 : arg1;
1182 }
1183
1184 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1185 {
1186 uint64_t u_arg1 = UNSIGNED(arg1, df);
1187 uint64_t u_arg2 = UNSIGNED(arg2, df);
1188 return u_arg2 ? u_arg1 % u_arg2 : u_arg1;
1189 }
1190
1191 #define SIGNED_EVEN(a, df) \
1192 ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
1193
1194 #define UNSIGNED_EVEN(a, df) \
1195 ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
1196
1197 #define SIGNED_ODD(a, df) \
1198 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
1199
1200 #define UNSIGNED_ODD(a, df) \
1201 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
1202
1203 #define SIGNED_EXTRACT(e, o, a, df) \
1204 do { \
1205 e = SIGNED_EVEN(a, df); \
1206 o = SIGNED_ODD(a, df); \
1207 } while (0)
1208
1209 #define UNSIGNED_EXTRACT(e, o, a, df) \
1210 do { \
1211 e = UNSIGNED_EVEN(a, df); \
1212 o = UNSIGNED_ODD(a, df); \
1213 } while (0)
1214
1215 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1216 {
1217 int64_t even_arg1;
1218 int64_t even_arg2;
1219 int64_t odd_arg1;
1220 int64_t odd_arg2;
1221 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
1222 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
1223 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
1224 }
1225
1226 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1227 {
1228 int64_t even_arg1;
1229 int64_t even_arg2;
1230 int64_t odd_arg1;
1231 int64_t odd_arg2;
1232 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
1233 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
1234 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
1235 }
1236
1237 #define CONCATENATE_AND_SLIDE(s, k) \
1238 do { \
1239 for (i = 0; i < s; i++) { \
1240 v[i] = pws->b[s * k + i]; \
1241 v[i + s] = pwd->b[s * k + i]; \
1242 } \
1243 for (i = 0; i < s; i++) { \
1244 pwd->b[s * k + i] = v[i + n]; \
1245 } \
1246 } while (0)
1247
1248 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
1249 wr_t *pws, target_ulong rt)
1250 {
1251 uint32_t n = rt % DF_ELEMENTS(df);
1252 uint8_t v[64];
1253 uint32_t i, k;
1254
1255 switch (df) {
1256 case DF_BYTE:
1257 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
1258 break;
1259 case DF_HALF:
1260 for (k = 0; k < 2; k++) {
1261 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
1262 }
1263 break;
1264 case DF_WORD:
1265 for (k = 0; k < 4; k++) {
1266 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
1267 }
1268 break;
1269 case DF_DOUBLE:
1270 for (k = 0; k < 8; k++) {
1271 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
1272 }
1273 break;
1274 default:
1275 assert(0);
1276 }
1277 }
1278
1279 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1280 {
1281 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
1282 }
1283
1284 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1285 {
1286 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
1287 }
1288
1289 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1290 {
1291 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
1292 }
1293
1294 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1295 {
1296 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
1297 }
1298
1299 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
1300 {
1301 int64_t q_min = DF_MIN_INT(df);
1302 int64_t q_max = DF_MAX_INT(df);
1303
1304 if (arg1 == q_min && arg2 == q_min) {
1305 return q_max;
1306 }
1307 return (arg1 * arg2) >> (DF_BITS(df) - 1);
1308 }
1309
1310 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
1311 {
1312 int64_t q_min = DF_MIN_INT(df);
1313 int64_t q_max = DF_MAX_INT(df);
1314 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1315
1316 if (arg1 == q_min && arg2 == q_min) {
1317 return q_max;
1318 }
1319 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
1320 }
1321
1322 #define MSA_BINOP_DF(func) \
1323 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1324 uint32_t wd, uint32_t ws, uint32_t wt) \
1325 { \
1326 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1327 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1328 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1329 \
1330 switch (df) { \
1331 case DF_BYTE: \
1332 pwd->b[0] = msa_ ## func ## _df(df, pws->b[0], pwt->b[0]); \
1333 pwd->b[1] = msa_ ## func ## _df(df, pws->b[1], pwt->b[1]); \
1334 pwd->b[2] = msa_ ## func ## _df(df, pws->b[2], pwt->b[2]); \
1335 pwd->b[3] = msa_ ## func ## _df(df, pws->b[3], pwt->b[3]); \
1336 pwd->b[4] = msa_ ## func ## _df(df, pws->b[4], pwt->b[4]); \
1337 pwd->b[5] = msa_ ## func ## _df(df, pws->b[5], pwt->b[5]); \
1338 pwd->b[6] = msa_ ## func ## _df(df, pws->b[6], pwt->b[6]); \
1339 pwd->b[7] = msa_ ## func ## _df(df, pws->b[7], pwt->b[7]); \
1340 pwd->b[8] = msa_ ## func ## _df(df, pws->b[8], pwt->b[8]); \
1341 pwd->b[9] = msa_ ## func ## _df(df, pws->b[9], pwt->b[9]); \
1342 pwd->b[10] = msa_ ## func ## _df(df, pws->b[10], pwt->b[10]); \
1343 pwd->b[11] = msa_ ## func ## _df(df, pws->b[11], pwt->b[11]); \
1344 pwd->b[12] = msa_ ## func ## _df(df, pws->b[12], pwt->b[12]); \
1345 pwd->b[13] = msa_ ## func ## _df(df, pws->b[13], pwt->b[13]); \
1346 pwd->b[14] = msa_ ## func ## _df(df, pws->b[14], pwt->b[14]); \
1347 pwd->b[15] = msa_ ## func ## _df(df, pws->b[15], pwt->b[15]); \
1348 break; \
1349 case DF_HALF: \
1350 pwd->h[0] = msa_ ## func ## _df(df, pws->h[0], pwt->h[0]); \
1351 pwd->h[1] = msa_ ## func ## _df(df, pws->h[1], pwt->h[1]); \
1352 pwd->h[2] = msa_ ## func ## _df(df, pws->h[2], pwt->h[2]); \
1353 pwd->h[3] = msa_ ## func ## _df(df, pws->h[3], pwt->h[3]); \
1354 pwd->h[4] = msa_ ## func ## _df(df, pws->h[4], pwt->h[4]); \
1355 pwd->h[5] = msa_ ## func ## _df(df, pws->h[5], pwt->h[5]); \
1356 pwd->h[6] = msa_ ## func ## _df(df, pws->h[6], pwt->h[6]); \
1357 pwd->h[7] = msa_ ## func ## _df(df, pws->h[7], pwt->h[7]); \
1358 break; \
1359 case DF_WORD: \
1360 pwd->w[0] = msa_ ## func ## _df(df, pws->w[0], pwt->w[0]); \
1361 pwd->w[1] = msa_ ## func ## _df(df, pws->w[1], pwt->w[1]); \
1362 pwd->w[2] = msa_ ## func ## _df(df, pws->w[2], pwt->w[2]); \
1363 pwd->w[3] = msa_ ## func ## _df(df, pws->w[3], pwt->w[3]); \
1364 break; \
1365 case DF_DOUBLE: \
1366 pwd->d[0] = msa_ ## func ## _df(df, pws->d[0], pwt->d[0]); \
1367 pwd->d[1] = msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \
1368 break; \
1369 default: \
1370 assert(0); \
1371 } \
1372 }
1373
1374 MSA_BINOP_DF(sll)
1375 MSA_BINOP_DF(sra)
1376 MSA_BINOP_DF(srl)
1377 MSA_BINOP_DF(bclr)
1378 MSA_BINOP_DF(bset)
1379 MSA_BINOP_DF(bneg)
1380 MSA_BINOP_DF(addv)
1381 MSA_BINOP_DF(subv)
1382 MSA_BINOP_DF(max_s)
1383 MSA_BINOP_DF(max_u)
1384 MSA_BINOP_DF(min_s)
1385 MSA_BINOP_DF(min_u)
1386 MSA_BINOP_DF(max_a)
1387 MSA_BINOP_DF(min_a)
1388 MSA_BINOP_DF(ceq)
1389 MSA_BINOP_DF(clt_s)
1390 MSA_BINOP_DF(clt_u)
1391 MSA_BINOP_DF(cle_s)
1392 MSA_BINOP_DF(cle_u)
1393 MSA_BINOP_DF(add_a)
1394 MSA_BINOP_DF(adds_a)
1395 MSA_BINOP_DF(adds_s)
1396 MSA_BINOP_DF(adds_u)
1397 MSA_BINOP_DF(ave_s)
1398 MSA_BINOP_DF(ave_u)
1399 MSA_BINOP_DF(aver_s)
1400 MSA_BINOP_DF(aver_u)
1401 MSA_BINOP_DF(subs_s)
1402 MSA_BINOP_DF(subs_u)
1403 MSA_BINOP_DF(subsus_u)
1404 MSA_BINOP_DF(subsuu_s)
1405 MSA_BINOP_DF(asub_s)
1406 MSA_BINOP_DF(asub_u)
1407 MSA_BINOP_DF(mulv)
1408 MSA_BINOP_DF(div_s)
1409 MSA_BINOP_DF(div_u)
1410 MSA_BINOP_DF(mod_s)
1411 MSA_BINOP_DF(mod_u)
1412 MSA_BINOP_DF(dotp_s)
1413 MSA_BINOP_DF(dotp_u)
1414 MSA_BINOP_DF(srar)
1415 MSA_BINOP_DF(srlr)
1416 MSA_BINOP_DF(hadd_s)
1417 MSA_BINOP_DF(hadd_u)
1418 MSA_BINOP_DF(hsub_s)
1419 MSA_BINOP_DF(hsub_u)
1420
1421 MSA_BINOP_DF(mul_q)
1422 MSA_BINOP_DF(mulr_q)
1423 #undef MSA_BINOP_DF
1424
1425 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1426 uint32_t ws, uint32_t rt)
1427 {
1428 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1429 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1430
1431 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
1432 }
1433
1434 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
1435 int64_t arg2)
1436 {
1437 return dest + arg1 * arg2;
1438 }
1439
1440 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
1441 int64_t arg2)
1442 {
1443 return dest - arg1 * arg2;
1444 }
1445
1446 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
1447 int64_t arg2)
1448 {
1449 int64_t even_arg1;
1450 int64_t even_arg2;
1451 int64_t odd_arg1;
1452 int64_t odd_arg2;
1453 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
1454 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
1455 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
1456 }
1457
1458 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
1459 int64_t arg2)
1460 {
1461 int64_t even_arg1;
1462 int64_t even_arg2;
1463 int64_t odd_arg1;
1464 int64_t odd_arg2;
1465 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
1466 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
1467 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
1468 }
1469
1470 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
1471 int64_t arg2)
1472 {
1473 int64_t even_arg1;
1474 int64_t even_arg2;
1475 int64_t odd_arg1;
1476 int64_t odd_arg2;
1477 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
1478 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
1479 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
1480 }
1481
1482 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
1483 int64_t arg2)
1484 {
1485 int64_t even_arg1;
1486 int64_t even_arg2;
1487 int64_t odd_arg1;
1488 int64_t odd_arg2;
1489 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
1490 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
1491 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
1492 }
1493
1494 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
1495 int64_t arg2)
1496 {
1497 int64_t q_prod, q_ret;
1498
1499 int64_t q_max = DF_MAX_INT(df);
1500 int64_t q_min = DF_MIN_INT(df);
1501
1502 q_prod = arg1 * arg2;
1503 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
1504
1505 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1506 }
1507
1508 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
1509 int64_t arg2)
1510 {
1511 int64_t q_prod, q_ret;
1512
1513 int64_t q_max = DF_MAX_INT(df);
1514 int64_t q_min = DF_MIN_INT(df);
1515
1516 q_prod = arg1 * arg2;
1517 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
1518
1519 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1520 }
1521
1522 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
1523 int64_t arg2)
1524 {
1525 int64_t q_prod, q_ret;
1526
1527 int64_t q_max = DF_MAX_INT(df);
1528 int64_t q_min = DF_MIN_INT(df);
1529 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1530
1531 q_prod = arg1 * arg2;
1532 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
1533
1534 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1535 }
1536
1537 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
1538 int64_t arg2)
1539 {
1540 int64_t q_prod, q_ret;
1541
1542 int64_t q_max = DF_MAX_INT(df);
1543 int64_t q_min = DF_MIN_INT(df);
1544 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1545
1546 q_prod = arg1 * arg2;
1547 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1548
1549 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1550 }
1551
1552 #define MSA_TEROP_DF(func) \
1553 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1554 uint32_t ws, uint32_t wt) \
1555 { \
1556 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1557 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1558 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1559 \
1560 switch (df) { \
1561 case DF_BYTE: \
1562 pwd->b[0] = msa_ ## func ## _df(df, pwd->b[0], pws->b[0], \
1563 pwt->b[0]); \
1564 pwd->b[1] = msa_ ## func ## _df(df, pwd->b[1], pws->b[1], \
1565 pwt->b[1]); \
1566 pwd->b[2] = msa_ ## func ## _df(df, pwd->b[2], pws->b[2], \
1567 pwt->b[2]); \
1568 pwd->b[3] = msa_ ## func ## _df(df, pwd->b[3], pws->b[3], \
1569 pwt->b[3]); \
1570 pwd->b[4] = msa_ ## func ## _df(df, pwd->b[4], pws->b[4], \
1571 pwt->b[4]); \
1572 pwd->b[5] = msa_ ## func ## _df(df, pwd->b[5], pws->b[5], \
1573 pwt->b[5]); \
1574 pwd->b[6] = msa_ ## func ## _df(df, pwd->b[6], pws->b[6], \
1575 pwt->b[6]); \
1576 pwd->b[7] = msa_ ## func ## _df(df, pwd->b[7], pws->b[7], \
1577 pwt->b[7]); \
1578 pwd->b[8] = msa_ ## func ## _df(df, pwd->b[8], pws->b[8], \
1579 pwt->b[8]); \
1580 pwd->b[9] = msa_ ## func ## _df(df, pwd->b[9], pws->b[9], \
1581 pwt->b[9]); \
1582 pwd->b[10] = msa_ ## func ## _df(df, pwd->b[10], pws->b[10], \
1583 pwt->b[10]); \
1584 pwd->b[11] = msa_ ## func ## _df(df, pwd->b[11], pws->b[11], \
1585 pwt->b[11]); \
1586 pwd->b[12] = msa_ ## func ## _df(df, pwd->b[12], pws->b[12], \
1587 pwt->b[12]); \
1588 pwd->b[13] = msa_ ## func ## _df(df, pwd->b[13], pws->b[13], \
1589 pwt->b[13]); \
1590 pwd->b[14] = msa_ ## func ## _df(df, pwd->b[14], pws->b[14], \
1591 pwt->b[14]); \
1592 pwd->b[15] = msa_ ## func ## _df(df, pwd->b[15], pws->b[15], \
1593 pwt->b[15]); \
1594 break; \
1595 case DF_HALF: \
1596 pwd->h[0] = msa_ ## func ## _df(df, pwd->h[0], pws->h[0], pwt->h[0]); \
1597 pwd->h[1] = msa_ ## func ## _df(df, pwd->h[1], pws->h[1], pwt->h[1]); \
1598 pwd->h[2] = msa_ ## func ## _df(df, pwd->h[2], pws->h[2], pwt->h[2]); \
1599 pwd->h[3] = msa_ ## func ## _df(df, pwd->h[3], pws->h[3], pwt->h[3]); \
1600 pwd->h[4] = msa_ ## func ## _df(df, pwd->h[4], pws->h[4], pwt->h[4]); \
1601 pwd->h[5] = msa_ ## func ## _df(df, pwd->h[5], pws->h[5], pwt->h[5]); \
1602 pwd->h[6] = msa_ ## func ## _df(df, pwd->h[6], pws->h[6], pwt->h[6]); \
1603 pwd->h[7] = msa_ ## func ## _df(df, pwd->h[7], pws->h[7], pwt->h[7]); \
1604 break; \
1605 case DF_WORD: \
1606 pwd->w[0] = msa_ ## func ## _df(df, pwd->w[0], pws->w[0], pwt->w[0]); \
1607 pwd->w[1] = msa_ ## func ## _df(df, pwd->w[1], pws->w[1], pwt->w[1]); \
1608 pwd->w[2] = msa_ ## func ## _df(df, pwd->w[2], pws->w[2], pwt->w[2]); \
1609 pwd->w[3] = msa_ ## func ## _df(df, pwd->w[3], pws->w[3], pwt->w[3]); \
1610 break; \
1611 case DF_DOUBLE: \
1612 pwd->d[0] = msa_ ## func ## _df(df, pwd->d[0], pws->d[0], pwt->d[0]); \
1613 pwd->d[1] = msa_ ## func ## _df(df, pwd->d[1], pws->d[1], pwt->d[1]); \
1614 break; \
1615 default: \
1616 assert(0); \
1617 } \
1618 }
1619
1620 MSA_TEROP_DF(maddv)
1621 MSA_TEROP_DF(msubv)
1622 MSA_TEROP_DF(dpadd_s)
1623 MSA_TEROP_DF(dpadd_u)
1624 MSA_TEROP_DF(dpsub_s)
1625 MSA_TEROP_DF(dpsub_u)
1626 MSA_TEROP_DF(binsl)
1627 MSA_TEROP_DF(binsr)
1628 MSA_TEROP_DF(madd_q)
1629 MSA_TEROP_DF(msub_q)
1630 MSA_TEROP_DF(maddr_q)
1631 MSA_TEROP_DF(msubr_q)
1632 #undef MSA_TEROP_DF
1633
1634 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1635 wr_t *pws, target_ulong rt)
1636 {
1637 uint32_t n = rt % DF_ELEMENTS(df);
1638 uint32_t i;
1639
1640 switch (df) {
1641 case DF_BYTE:
1642 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1643 pwd->b[i] = pws->b[n];
1644 }
1645 break;
1646 case DF_HALF:
1647 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1648 pwd->h[i] = pws->h[n];
1649 }
1650 break;
1651 case DF_WORD:
1652 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1653 pwd->w[i] = pws->w[n];
1654 }
1655 break;
1656 case DF_DOUBLE:
1657 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1658 pwd->d[i] = pws->d[n];
1659 }
1660 break;
1661 default:
1662 assert(0);
1663 }
1664 }
1665
1666 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1667 uint32_t ws, uint32_t rt)
1668 {
1669 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1670 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1671
1672 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1673 }
1674
1675 #define MSA_DO_B MSA_DO(b)
1676 #define MSA_DO_H MSA_DO(h)
1677 #define MSA_DO_W MSA_DO(w)
1678 #define MSA_DO_D MSA_DO(d)
1679
1680 #define MSA_LOOP_B MSA_LOOP(B)
1681 #define MSA_LOOP_H MSA_LOOP(H)
1682 #define MSA_LOOP_W MSA_LOOP(W)
1683 #define MSA_LOOP_D MSA_LOOP(D)
1684
1685 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1686 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1687 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1688 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1689
1690 #define MSA_LOOP(DF) \
1691 do { \
1692 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1693 MSA_DO_ ## DF; \
1694 } \
1695 } while (0)
1696
1697 #define MSA_FN_DF(FUNC) \
1698 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1699 uint32_t ws, uint32_t wt) \
1700 { \
1701 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1702 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1703 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1704 wr_t wx, *pwx = &wx; \
1705 uint32_t i; \
1706 switch (df) { \
1707 case DF_BYTE: \
1708 MSA_LOOP_B; \
1709 break; \
1710 case DF_HALF: \
1711 MSA_LOOP_H; \
1712 break; \
1713 case DF_WORD: \
1714 MSA_LOOP_W; \
1715 break; \
1716 case DF_DOUBLE: \
1717 MSA_LOOP_D; \
1718 break; \
1719 default: \
1720 assert(0); \
1721 } \
1722 msa_move_v(pwd, pwx); \
1723 }
1724
1725 #define MSA_LOOP_COND(DF) \
1726 (DF_ELEMENTS(DF) / 2)
1727
1728 #define Rb(pwr, i) (pwr->b[i])
1729 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE) / 2])
1730 #define Rh(pwr, i) (pwr->h[i])
1731 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF) / 2])
1732 #define Rw(pwr, i) (pwr->w[i])
1733 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD) / 2])
1734 #define Rd(pwr, i) (pwr->d[i])
1735 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE) / 2])
1736
1737 #undef MSA_LOOP_COND
1738
1739 #define MSA_LOOP_COND(DF) \
1740 (DF_ELEMENTS(DF))
1741
1742 #define MSA_DO(DF) \
1743 do { \
1744 uint32_t n = DF_ELEMENTS(df); \
1745 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1746 pwx->DF[i] = \
1747 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1748 } while (0)
1749 MSA_FN_DF(vshf_df)
1750 #undef MSA_DO
1751 #undef MSA_LOOP_COND
1752 #undef MSA_FN_DF
1753
1754
1755 void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1756 uint32_t ws, uint32_t wt)
1757 {
1758 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1759 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1760 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1761
1762 switch (df) {
1763 case DF_BYTE:
1764 #if defined(HOST_WORDS_BIGENDIAN)
1765 pwd->b[8] = pws->b[9];
1766 pwd->b[9] = pwt->b[9];
1767 pwd->b[10] = pws->b[11];
1768 pwd->b[11] = pwt->b[11];
1769 pwd->b[12] = pws->b[13];
1770 pwd->b[13] = pwt->b[13];
1771 pwd->b[14] = pws->b[15];
1772 pwd->b[15] = pwt->b[15];
1773 pwd->b[0] = pws->b[1];
1774 pwd->b[1] = pwt->b[1];
1775 pwd->b[2] = pws->b[3];
1776 pwd->b[3] = pwt->b[3];
1777 pwd->b[4] = pws->b[5];
1778 pwd->b[5] = pwt->b[5];
1779 pwd->b[6] = pws->b[7];
1780 pwd->b[7] = pwt->b[7];
1781 #else
1782 pwd->b[15] = pws->b[14];
1783 pwd->b[14] = pwt->b[14];
1784 pwd->b[13] = pws->b[12];
1785 pwd->b[12] = pwt->b[12];
1786 pwd->b[11] = pws->b[10];
1787 pwd->b[10] = pwt->b[10];
1788 pwd->b[9] = pws->b[8];
1789 pwd->b[8] = pwt->b[8];
1790 pwd->b[7] = pws->b[6];
1791 pwd->b[6] = pwt->b[6];
1792 pwd->b[5] = pws->b[4];
1793 pwd->b[4] = pwt->b[4];
1794 pwd->b[3] = pws->b[2];
1795 pwd->b[2] = pwt->b[2];
1796 pwd->b[1] = pws->b[0];
1797 pwd->b[0] = pwt->b[0];
1798 #endif
1799 break;
1800 case DF_HALF:
1801 #if defined(HOST_WORDS_BIGENDIAN)
1802 pwd->h[4] = pws->h[5];
1803 pwd->h[5] = pwt->h[5];
1804 pwd->h[6] = pws->h[7];
1805 pwd->h[7] = pwt->h[7];
1806 pwd->h[0] = pws->h[1];
1807 pwd->h[1] = pwt->h[1];
1808 pwd->h[2] = pws->h[3];
1809 pwd->h[3] = pwt->h[3];
1810 #else
1811 pwd->h[7] = pws->h[6];
1812 pwd->h[6] = pwt->h[6];
1813 pwd->h[5] = pws->h[4];
1814 pwd->h[4] = pwt->h[4];
1815 pwd->h[3] = pws->h[2];
1816 pwd->h[2] = pwt->h[2];
1817 pwd->h[1] = pws->h[0];
1818 pwd->h[0] = pwt->h[0];
1819 #endif
1820 break;
1821 case DF_WORD:
1822 #if defined(HOST_WORDS_BIGENDIAN)
1823 pwd->w[2] = pws->w[3];
1824 pwd->w[3] = pwt->w[3];
1825 pwd->w[0] = pws->w[1];
1826 pwd->w[1] = pwt->w[1];
1827 #else
1828 pwd->w[3] = pws->w[2];
1829 pwd->w[2] = pwt->w[2];
1830 pwd->w[1] = pws->w[0];
1831 pwd->w[0] = pwt->w[0];
1832 #endif
1833 break;
1834 case DF_DOUBLE:
1835 pwd->d[1] = pws->d[0];
1836 pwd->d[0] = pwt->d[0];
1837 break;
1838 default:
1839 assert(0);
1840 }
1841 }
1842
1843 void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1844 uint32_t ws, uint32_t wt)
1845 {
1846 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1847 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1848 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1849
1850 switch (df) {
1851 case DF_BYTE:
1852 #if defined(HOST_WORDS_BIGENDIAN)
1853 pwd->b[7] = pwt->b[6];
1854 pwd->b[6] = pws->b[6];
1855 pwd->b[5] = pwt->b[4];
1856 pwd->b[4] = pws->b[4];
1857 pwd->b[3] = pwt->b[2];
1858 pwd->b[2] = pws->b[2];
1859 pwd->b[1] = pwt->b[0];
1860 pwd->b[0] = pws->b[0];
1861 pwd->b[15] = pwt->b[14];
1862 pwd->b[14] = pws->b[14];
1863 pwd->b[13] = pwt->b[12];
1864 pwd->b[12] = pws->b[12];
1865 pwd->b[11] = pwt->b[10];
1866 pwd->b[10] = pws->b[10];
1867 pwd->b[9] = pwt->b[8];
1868 pwd->b[8] = pws->b[8];
1869 #else
1870 pwd->b[0] = pwt->b[1];
1871 pwd->b[1] = pws->b[1];
1872 pwd->b[2] = pwt->b[3];
1873 pwd->b[3] = pws->b[3];
1874 pwd->b[4] = pwt->b[5];
1875 pwd->b[5] = pws->b[5];
1876 pwd->b[6] = pwt->b[7];
1877 pwd->b[7] = pws->b[7];
1878 pwd->b[8] = pwt->b[9];
1879 pwd->b[9] = pws->b[9];
1880 pwd->b[10] = pwt->b[11];
1881 pwd->b[11] = pws->b[11];
1882 pwd->b[12] = pwt->b[13];
1883 pwd->b[13] = pws->b[13];
1884 pwd->b[14] = pwt->b[15];
1885 pwd->b[15] = pws->b[15];
1886 #endif
1887 break;
1888 case DF_HALF:
1889 #if defined(HOST_WORDS_BIGENDIAN)
1890 pwd->h[3] = pwt->h[2];
1891 pwd->h[2] = pws->h[2];
1892 pwd->h[1] = pwt->h[0];
1893 pwd->h[0] = pws->h[0];
1894 pwd->h[7] = pwt->h[6];
1895 pwd->h[6] = pws->h[6];
1896 pwd->h[5] = pwt->h[4];
1897 pwd->h[4] = pws->h[4];
1898 #else
1899 pwd->h[0] = pwt->h[1];
1900 pwd->h[1] = pws->h[1];
1901 pwd->h[2] = pwt->h[3];
1902 pwd->h[3] = pws->h[3];
1903 pwd->h[4] = pwt->h[5];
1904 pwd->h[5] = pws->h[5];
1905 pwd->h[6] = pwt->h[7];
1906 pwd->h[7] = pws->h[7];
1907 #endif
1908 break;
1909 case DF_WORD:
1910 #if defined(HOST_WORDS_BIGENDIAN)
1911 pwd->w[1] = pwt->w[0];
1912 pwd->w[0] = pws->w[0];
1913 pwd->w[3] = pwt->w[2];
1914 pwd->w[2] = pws->w[2];
1915 #else
1916 pwd->w[0] = pwt->w[1];
1917 pwd->w[1] = pws->w[1];
1918 pwd->w[2] = pwt->w[3];
1919 pwd->w[3] = pws->w[3];
1920 #endif
1921 break;
1922 case DF_DOUBLE:
1923 pwd->d[0] = pwt->d[1];
1924 pwd->d[1] = pws->d[1];
1925 break;
1926 default:
1927 assert(0);
1928 }
1929 }
1930
1931 void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1932 uint32_t ws, uint32_t wt)
1933 {
1934 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1935 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1936 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1937
1938 switch (df) {
1939 case DF_BYTE:
1940 #if defined(HOST_WORDS_BIGENDIAN)
1941 pwd->b[7] = pwt->b[15];
1942 pwd->b[6] = pws->b[15];
1943 pwd->b[5] = pwt->b[14];
1944 pwd->b[4] = pws->b[14];
1945 pwd->b[3] = pwt->b[13];
1946 pwd->b[2] = pws->b[13];
1947 pwd->b[1] = pwt->b[12];
1948 pwd->b[0] = pws->b[12];
1949 pwd->b[15] = pwt->b[11];
1950 pwd->b[14] = pws->b[11];
1951 pwd->b[13] = pwt->b[10];
1952 pwd->b[12] = pws->b[10];
1953 pwd->b[11] = pwt->b[9];
1954 pwd->b[10] = pws->b[9];
1955 pwd->b[9] = pwt->b[8];
1956 pwd->b[8] = pws->b[8];
1957 #else
1958 pwd->b[0] = pwt->b[8];
1959 pwd->b[1] = pws->b[8];
1960 pwd->b[2] = pwt->b[9];
1961 pwd->b[3] = pws->b[9];
1962 pwd->b[4] = pwt->b[10];
1963 pwd->b[5] = pws->b[10];
1964 pwd->b[6] = pwt->b[11];
1965 pwd->b[7] = pws->b[11];
1966 pwd->b[8] = pwt->b[12];
1967 pwd->b[9] = pws->b[12];
1968 pwd->b[10] = pwt->b[13];
1969 pwd->b[11] = pws->b[13];
1970 pwd->b[12] = pwt->b[14];
1971 pwd->b[13] = pws->b[14];
1972 pwd->b[14] = pwt->b[15];
1973 pwd->b[15] = pws->b[15];
1974 #endif
1975 break;
1976 case DF_HALF:
1977 #if defined(HOST_WORDS_BIGENDIAN)
1978 pwd->h[3] = pwt->h[7];
1979 pwd->h[2] = pws->h[7];
1980 pwd->h[1] = pwt->h[6];
1981 pwd->h[0] = pws->h[6];
1982 pwd->h[7] = pwt->h[5];
1983 pwd->h[6] = pws->h[5];
1984 pwd->h[5] = pwt->h[4];
1985 pwd->h[4] = pws->h[4];
1986 #else
1987 pwd->h[0] = pwt->h[4];
1988 pwd->h[1] = pws->h[4];
1989 pwd->h[2] = pwt->h[5];
1990 pwd->h[3] = pws->h[5];
1991 pwd->h[4] = pwt->h[6];
1992 pwd->h[5] = pws->h[6];
1993 pwd->h[6] = pwt->h[7];
1994 pwd->h[7] = pws->h[7];
1995 #endif
1996 break;
1997 case DF_WORD:
1998 #if defined(HOST_WORDS_BIGENDIAN)
1999 pwd->w[1] = pwt->w[3];
2000 pwd->w[0] = pws->w[3];
2001 pwd->w[3] = pwt->w[2];
2002 pwd->w[2] = pws->w[2];
2003 #else
2004 pwd->w[0] = pwt->w[2];
2005 pwd->w[1] = pws->w[2];
2006 pwd->w[2] = pwt->w[3];
2007 pwd->w[3] = pws->w[3];
2008 #endif
2009 break;
2010 case DF_DOUBLE:
2011 pwd->d[0] = pwt->d[1];
2012 pwd->d[1] = pws->d[1];
2013 break;
2014 default:
2015 assert(0);
2016 }
2017 }
2018
2019 void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2020 uint32_t ws, uint32_t wt)
2021 {
2022 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2023 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2024 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2025
2026 switch (df) {
2027 case DF_BYTE:
2028 #if defined(HOST_WORDS_BIGENDIAN)
2029 pwd->b[8] = pws->b[0];
2030 pwd->b[9] = pwt->b[0];
2031 pwd->b[10] = pws->b[1];
2032 pwd->b[11] = pwt->b[1];
2033 pwd->b[12] = pws->b[2];
2034 pwd->b[13] = pwt->b[2];
2035 pwd->b[14] = pws->b[3];
2036 pwd->b[15] = pwt->b[3];
2037 pwd->b[0] = pws->b[4];
2038 pwd->b[1] = pwt->b[4];
2039 pwd->b[2] = pws->b[5];
2040 pwd->b[3] = pwt->b[5];
2041 pwd->b[4] = pws->b[6];
2042 pwd->b[5] = pwt->b[6];
2043 pwd->b[6] = pws->b[7];
2044 pwd->b[7] = pwt->b[7];
2045 #else
2046 pwd->b[15] = pws->b[7];
2047 pwd->b[14] = pwt->b[7];
2048 pwd->b[13] = pws->b[6];
2049 pwd->b[12] = pwt->b[6];
2050 pwd->b[11] = pws->b[5];
2051 pwd->b[10] = pwt->b[5];
2052 pwd->b[9] = pws->b[4];
2053 pwd->b[8] = pwt->b[4];
2054 pwd->b[7] = pws->b[3];
2055 pwd->b[6] = pwt->b[3];
2056 pwd->b[5] = pws->b[2];
2057 pwd->b[4] = pwt->b[2];
2058 pwd->b[3] = pws->b[1];
2059 pwd->b[2] = pwt->b[1];
2060 pwd->b[1] = pws->b[0];
2061 pwd->b[0] = pwt->b[0];
2062 #endif
2063 break;
2064 case DF_HALF:
2065 #if defined(HOST_WORDS_BIGENDIAN)
2066 pwd->h[4] = pws->h[0];
2067 pwd->h[5] = pwt->h[0];
2068 pwd->h[6] = pws->h[1];
2069 pwd->h[7] = pwt->h[1];
2070 pwd->h[0] = pws->h[2];
2071 pwd->h[1] = pwt->h[2];
2072 pwd->h[2] = pws->h[3];
2073 pwd->h[3] = pwt->h[3];
2074 #else
2075 pwd->h[7] = pws->h[3];
2076 pwd->h[6] = pwt->h[3];
2077 pwd->h[5] = pws->h[2];
2078 pwd->h[4] = pwt->h[2];
2079 pwd->h[3] = pws->h[1];
2080 pwd->h[2] = pwt->h[1];
2081 pwd->h[1] = pws->h[0];
2082 pwd->h[0] = pwt->h[0];
2083 #endif
2084 break;
2085 case DF_WORD:
2086 #if defined(HOST_WORDS_BIGENDIAN)
2087 pwd->w[2] = pws->w[0];
2088 pwd->w[3] = pwt->w[0];
2089 pwd->w[0] = pws->w[1];
2090 pwd->w[1] = pwt->w[1];
2091 #else
2092 pwd->w[3] = pws->w[1];
2093 pwd->w[2] = pwt->w[1];
2094 pwd->w[1] = pws->w[0];
2095 pwd->w[0] = pwt->w[0];
2096 #endif
2097 break;
2098 case DF_DOUBLE:
2099 pwd->d[1] = pws->d[0];
2100 pwd->d[0] = pwt->d[0];
2101 break;
2102 default:
2103 assert(0);
2104 }
2105 }
2106
2107 void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2108 uint32_t ws, uint32_t wt)
2109 {
2110 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2111 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2112 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2113
2114 switch (df) {
2115 case DF_BYTE:
2116 pwd->b[15] = pws->b[14];
2117 pwd->b[13] = pws->b[10];
2118 pwd->b[11] = pws->b[6];
2119 pwd->b[9] = pws->b[2];
2120 pwd->b[7] = pwt->b[14];
2121 pwd->b[5] = pwt->b[10];
2122 pwd->b[3] = pwt->b[6];
2123 pwd->b[1] = pwt->b[2];
2124 pwd->b[14] = pws->b[12];
2125 pwd->b[10] = pws->b[4];
2126 pwd->b[6] = pwt->b[12];
2127 pwd->b[2] = pwt->b[4];
2128 pwd->b[12] = pws->b[8];
2129 pwd->b[4] = pwt->b[8];
2130 pwd->b[8] = pws->b[0];
2131 pwd->b[0] = pwt->b[0];
2132 break;
2133 case DF_HALF:
2134 pwd->h[7] = pws->h[6];
2135 pwd->h[5] = pws->h[2];
2136 pwd->h[3] = pwt->h[6];
2137 pwd->h[1] = pwt->h[2];
2138 pwd->h[6] = pws->h[4];
2139 pwd->h[2] = pwt->h[4];
2140 pwd->h[4] = pws->h[0];
2141 pwd->h[0] = pwt->h[0];
2142 break;
2143 case DF_WORD:
2144 pwd->w[3] = pws->w[2];
2145 pwd->w[1] = pwt->w[2];
2146 pwd->w[2] = pws->w[0];
2147 pwd->w[0] = pwt->w[0];
2148 break;
2149 case DF_DOUBLE:
2150 pwd->d[1] = pws->d[0];
2151 pwd->d[0] = pwt->d[0];
2152 break;
2153 default:
2154 assert(0);
2155 }
2156 }
2157
2158 void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2159 uint32_t ws, uint32_t wt)
2160 {
2161 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2162 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2163 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2164
2165 switch (df) {
2166 case DF_BYTE:
2167 pwd->b[0] = pwt->b[1];
2168 pwd->b[2] = pwt->b[5];
2169 pwd->b[4] = pwt->b[9];
2170 pwd->b[6] = pwt->b[13];
2171 pwd->b[8] = pws->b[1];
2172 pwd->b[10] = pws->b[5];
2173 pwd->b[12] = pws->b[9];
2174 pwd->b[14] = pws->b[13];
2175 pwd->b[1] = pwt->b[3];
2176 pwd->b[5] = pwt->b[11];
2177 pwd->b[9] = pws->b[3];
2178 pwd->b[13] = pws->b[11];
2179 pwd->b[3] = pwt->b[7];
2180 pwd->b[11] = pws->b[7];
2181 pwd->b[7] = pwt->b[15];
2182 pwd->b[15] = pws->b[15];
2183 break;
2184 case DF_HALF:
2185 pwd->h[0] = pwt->h[1];
2186 pwd->h[2] = pwt->h[5];
2187 pwd->h[4] = pws->h[1];
2188 pwd->h[6] = pws->h[5];
2189 pwd->h[1] = pwt->h[3];
2190 pwd->h[5] = pws->h[3];
2191 pwd->h[3] = pwt->h[7];
2192 pwd->h[7] = pws->h[7];
2193 break;
2194 case DF_WORD:
2195 pwd->w[0] = pwt->w[1];
2196 pwd->w[2] = pws->w[1];
2197 pwd->w[1] = pwt->w[3];
2198 pwd->w[3] = pws->w[3];
2199 break;
2200 case DF_DOUBLE:
2201 pwd->d[0] = pwt->d[1];
2202 pwd->d[1] = pws->d[1];
2203 break;
2204 default:
2205 assert(0);
2206 }
2207 }
2208
2209
2210 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2211 uint32_t ws, uint32_t n)
2212 {
2213 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2214 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2215
2216 msa_sld_df(df, pwd, pws, n);
2217 }
2218
2219 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2220 uint32_t ws, uint32_t n)
2221 {
2222 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2223 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2224
2225 msa_splat_df(df, pwd, pws, n);
2226 }
2227
2228 void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
2229 uint32_t ws, uint32_t n)
2230 {
2231 n %= 16;
2232 #if defined(HOST_WORDS_BIGENDIAN)
2233 if (n < 8) {
2234 n = 8 - n - 1;
2235 } else {
2236 n = 24 - n - 1;
2237 }
2238 #endif
2239 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
2240 }
2241
2242 void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
2243 uint32_t ws, uint32_t n)
2244 {
2245 n %= 8;
2246 #if defined(HOST_WORDS_BIGENDIAN)
2247 if (n < 4) {
2248 n = 4 - n - 1;
2249 } else {
2250 n = 12 - n - 1;
2251 }
2252 #endif
2253 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
2254 }
2255
2256 void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
2257 uint32_t ws, uint32_t n)
2258 {
2259 n %= 4;
2260 #if defined(HOST_WORDS_BIGENDIAN)
2261 if (n < 2) {
2262 n = 2 - n - 1;
2263 } else {
2264 n = 6 - n - 1;
2265 }
2266 #endif
2267 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
2268 }
2269
2270 void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
2271 uint32_t ws, uint32_t n)
2272 {
2273 n %= 2;
2274 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
2275 }
2276
2277 void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
2278 uint32_t ws, uint32_t n)
2279 {
2280 n %= 16;
2281 #if defined(HOST_WORDS_BIGENDIAN)
2282 if (n < 8) {
2283 n = 8 - n - 1;
2284 } else {
2285 n = 24 - n - 1;
2286 }
2287 #endif
2288 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
2289 }
2290
2291 void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
2292 uint32_t ws, uint32_t n)
2293 {
2294 n %= 8;
2295 #if defined(HOST_WORDS_BIGENDIAN)
2296 if (n < 4) {
2297 n = 4 - n - 1;
2298 } else {
2299 n = 12 - n - 1;
2300 }
2301 #endif
2302 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
2303 }
2304
2305 void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
2306 uint32_t ws, uint32_t n)
2307 {
2308 n %= 4;
2309 #if defined(HOST_WORDS_BIGENDIAN)
2310 if (n < 2) {
2311 n = 2 - n - 1;
2312 } else {
2313 n = 6 - n - 1;
2314 }
2315 #endif
2316 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
2317 }
2318
2319 void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd,
2320 uint32_t rs_num, uint32_t n)
2321 {
2322 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2323 target_ulong rs = env->active_tc.gpr[rs_num];
2324 n %= 16;
2325 #if defined(HOST_WORDS_BIGENDIAN)
2326 if (n < 8) {
2327 n = 8 - n - 1;
2328 } else {
2329 n = 24 - n - 1;
2330 }
2331 #endif
2332 pwd->b[n] = (int8_t)rs;
2333 }
2334
2335 void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd,
2336 uint32_t rs_num, uint32_t n)
2337 {
2338 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2339 target_ulong rs = env->active_tc.gpr[rs_num];
2340 n %= 8;
2341 #if defined(HOST_WORDS_BIGENDIAN)
2342 if (n < 4) {
2343 n = 4 - n - 1;
2344 } else {
2345 n = 12 - n - 1;
2346 }
2347 #endif
2348 pwd->h[n] = (int16_t)rs;
2349 }
2350
2351 void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd,
2352 uint32_t rs_num, uint32_t n)
2353 {
2354 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2355 target_ulong rs = env->active_tc.gpr[rs_num];
2356 n %= 4;
2357 #if defined(HOST_WORDS_BIGENDIAN)
2358 if (n < 2) {
2359 n = 2 - n - 1;
2360 } else {
2361 n = 6 - n - 1;
2362 }
2363 #endif
2364 pwd->w[n] = (int32_t)rs;
2365 }
2366
2367 void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd,
2368 uint32_t rs_num, uint32_t n)
2369 {
2370 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2371 target_ulong rs = env->active_tc.gpr[rs_num];
2372 n %= 2;
2373 pwd->d[n] = (int64_t)rs;
2374 }
2375
2376 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2377 uint32_t ws, uint32_t n)
2378 {
2379 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2380 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2381
2382 switch (df) {
2383 case DF_BYTE:
2384 pwd->b[n] = (int8_t)pws->b[0];
2385 break;
2386 case DF_HALF:
2387 pwd->h[n] = (int16_t)pws->h[0];
2388 break;
2389 case DF_WORD:
2390 pwd->w[n] = (int32_t)pws->w[0];
2391 break;
2392 case DF_DOUBLE:
2393 pwd->d[n] = (int64_t)pws->d[0];
2394 break;
2395 default:
2396 assert(0);
2397 }
2398 }
2399
2400 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
2401 {
2402 switch (cd) {
2403 case 0:
2404 break;
2405 case 1:
2406 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
2407 restore_msa_fp_status(env);
2408 /* check exception */
2409 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
2410 & GET_FP_CAUSE(env->active_tc.msacsr)) {
2411 do_raise_exception(env, EXCP_MSAFPE, GETPC());
2412 }
2413 break;
2414 }
2415 }
2416
2417 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
2418 {
2419 switch (cs) {
2420 case 0:
2421 return env->msair;
2422 case 1:
2423 return env->active_tc.msacsr & MSACSR_MASK;
2424 }
2425 return 0;
2426 }
2427
2428 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
2429 {
2430 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2431 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2432
2433 msa_move_v(pwd, pws);
2434 }
2435
2436 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
2437 {
2438 uint64_t x;
2439
2440 x = UNSIGNED(arg, df);
2441
2442 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
2443 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
2444 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
2445 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
2446 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
2447 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
2448
2449 return x;
2450 }
2451
2452 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
2453 {
2454 uint64_t x, y;
2455 int n, c;
2456
2457 x = UNSIGNED(arg, df);
2458 n = DF_BITS(df);
2459 c = DF_BITS(df) / 2;
2460
2461 do {
2462 y = x >> c;
2463 if (y != 0) {
2464 n = n - c;
2465 x = y;
2466 }
2467 c = c >> 1;
2468 } while (c != 0);
2469
2470 return n - x;
2471 }
2472
2473 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
2474 {
2475 return msa_nlzc_df(df, UNSIGNED((~arg), df));
2476 }
2477
2478 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2479 uint32_t rs)
2480 {
2481 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2482 uint32_t i;
2483
2484 switch (df) {
2485 case DF_BYTE:
2486 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
2487 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
2488 }
2489 break;
2490 case DF_HALF:
2491 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
2492 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
2493 }
2494 break;
2495 case DF_WORD:
2496 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2497 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
2498 }
2499 break;
2500 case DF_DOUBLE:
2501 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2502 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
2503 }
2504 break;
2505 default:
2506 assert(0);
2507 }
2508 }
2509
2510 #define MSA_UNOP_DF(func) \
2511 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
2512 uint32_t wd, uint32_t ws) \
2513 { \
2514 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2515 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2516 \
2517 switch (df) { \
2518 case DF_BYTE: \
2519 pwd->b[0] = msa_ ## func ## _df(df, pws->b[0]); \
2520 pwd->b[1] = msa_ ## func ## _df(df, pws->b[1]); \
2521 pwd->b[2] = msa_ ## func ## _df(df, pws->b[2]); \
2522 pwd->b[3] = msa_ ## func ## _df(df, pws->b[3]); \
2523 pwd->b[4] = msa_ ## func ## _df(df, pws->b[4]); \
2524 pwd->b[5] = msa_ ## func ## _df(df, pws->b[5]); \
2525 pwd->b[6] = msa_ ## func ## _df(df, pws->b[6]); \
2526 pwd->b[7] = msa_ ## func ## _df(df, pws->b[7]); \
2527 pwd->b[8] = msa_ ## func ## _df(df, pws->b[8]); \
2528 pwd->b[9] = msa_ ## func ## _df(df, pws->b[9]); \
2529 pwd->b[10] = msa_ ## func ## _df(df, pws->b[10]); \
2530 pwd->b[11] = msa_ ## func ## _df(df, pws->b[11]); \
2531 pwd->b[12] = msa_ ## func ## _df(df, pws->b[12]); \
2532 pwd->b[13] = msa_ ## func ## _df(df, pws->b[13]); \
2533 pwd->b[14] = msa_ ## func ## _df(df, pws->b[14]); \
2534 pwd->b[15] = msa_ ## func ## _df(df, pws->b[15]); \
2535 break; \
2536 case DF_HALF: \
2537 pwd->h[0] = msa_ ## func ## _df(df, pws->h[0]); \
2538 pwd->h[1] = msa_ ## func ## _df(df, pws->h[1]); \
2539 pwd->h[2] = msa_ ## func ## _df(df, pws->h[2]); \
2540 pwd->h[3] = msa_ ## func ## _df(df, pws->h[3]); \
2541 pwd->h[4] = msa_ ## func ## _df(df, pws->h[4]); \
2542 pwd->h[5] = msa_ ## func ## _df(df, pws->h[5]); \
2543 pwd->h[6] = msa_ ## func ## _df(df, pws->h[6]); \
2544 pwd->h[7] = msa_ ## func ## _df(df, pws->h[7]); \
2545 break; \
2546 case DF_WORD: \
2547 pwd->w[0] = msa_ ## func ## _df(df, pws->w[0]); \
2548 pwd->w[1] = msa_ ## func ## _df(df, pws->w[1]); \
2549 pwd->w[2] = msa_ ## func ## _df(df, pws->w[2]); \
2550 pwd->w[3] = msa_ ## func ## _df(df, pws->w[3]); \
2551 break; \
2552 case DF_DOUBLE: \
2553 pwd->d[0] = msa_ ## func ## _df(df, pws->d[0]); \
2554 pwd->d[1] = msa_ ## func ## _df(df, pws->d[1]); \
2555 break; \
2556 default: \
2557 assert(0); \
2558 } \
2559 }
2560
2561 MSA_UNOP_DF(nlzc)
2562 MSA_UNOP_DF(nloc)
2563 MSA_UNOP_DF(pcnt)
2564 #undef MSA_UNOP_DF
2565
2566 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
2567 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
2568
2569 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
2570 /* 0x7c20 */
2571 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
2572 /* 0x7f800020 */
2573 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
2574 /* 0x7ff0000000000020 */
2575
2576 static inline void clear_msacsr_cause(CPUMIPSState *env)
2577 {
2578 SET_FP_CAUSE(env->active_tc.msacsr, 0);
2579 }
2580
2581 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
2582 {
2583 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
2584 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
2585 UPDATE_FP_FLAGS(env->active_tc.msacsr,
2586 GET_FP_CAUSE(env->active_tc.msacsr));
2587 } else {
2588 do_raise_exception(env, EXCP_MSAFPE, retaddr);
2589 }
2590 }
2591
2592 /* Flush-to-zero use cases for update_msacsr() */
2593 #define CLEAR_FS_UNDERFLOW 1
2594 #define CLEAR_IS_INEXACT 2
2595 #define RECIPROCAL_INEXACT 4
2596
2597 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
2598 {
2599 int ieee_ex;
2600
2601 int c;
2602 int cause;
2603 int enable;
2604
2605 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
2606
2607 /* QEMU softfloat does not signal all underflow cases */
2608 if (denormal) {
2609 ieee_ex |= float_flag_underflow;
2610 }
2611
2612 c = ieee_ex_to_mips(ieee_ex);
2613 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
2614
2615 /* Set Inexact (I) when flushing inputs to zero */
2616 if ((ieee_ex & float_flag_input_denormal) &&
2617 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
2618 if (action & CLEAR_IS_INEXACT) {
2619 c &= ~FP_INEXACT;
2620 } else {
2621 c |= FP_INEXACT;
2622 }
2623 }
2624
2625 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
2626 if ((ieee_ex & float_flag_output_denormal) &&
2627 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
2628 c |= FP_INEXACT;
2629 if (action & CLEAR_FS_UNDERFLOW) {
2630 c &= ~FP_UNDERFLOW;
2631 } else {
2632 c |= FP_UNDERFLOW;
2633 }
2634 }
2635
2636 /* Set Inexact (I) when Overflow (O) is not enabled */
2637 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
2638 c |= FP_INEXACT;
2639 }
2640
2641 /* Clear Exact Underflow when Underflow (U) is not enabled */
2642 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
2643 (c & FP_INEXACT) == 0) {
2644 c &= ~FP_UNDERFLOW;
2645 }
2646
2647 /*
2648 * Reciprocal operations set only Inexact when valid and not
2649 * divide by zero
2650 */
2651 if ((action & RECIPROCAL_INEXACT) &&
2652 (c & (FP_INVALID | FP_DIV0)) == 0) {
2653 c = FP_INEXACT;
2654 }
2655
2656 cause = c & enable; /* all current enabled exceptions */
2657
2658 if (cause == 0) {
2659 /*
2660 * No enabled exception, update the MSACSR Cause
2661 * with all current exceptions
2662 */
2663 SET_FP_CAUSE(env->active_tc.msacsr,
2664 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
2665 } else {
2666 /* Current exceptions are enabled */
2667 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
2668 /*
2669 * Exception(s) will trap, update MSACSR Cause
2670 * with all enabled exceptions
2671 */
2672 SET_FP_CAUSE(env->active_tc.msacsr,
2673 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
2674 }
2675 }
2676
2677 return c;
2678 }
2679
2680 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
2681 {
2682 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
2683 return c & enable;
2684 }
2685
2686 static inline float16 float16_from_float32(int32_t a, flag ieee,
2687 float_status *status)
2688 {
2689 float16 f_val;
2690
2691 f_val = float32_to_float16((float32)a, ieee, status);
2692
2693 return a < 0 ? (f_val | (1 << 15)) : f_val;
2694 }
2695
2696 static inline float32 float32_from_float64(int64_t a, float_status *status)
2697 {
2698 float32 f_val;
2699
2700 f_val = float64_to_float32((float64)a, status);
2701
2702 return a < 0 ? (f_val | (1 << 31)) : f_val;
2703 }
2704
2705 static inline float32 float32_from_float16(int16_t a, flag ieee,
2706 float_status *status)
2707 {
2708 float32 f_val;
2709
2710 f_val = float16_to_float32((float16)a, ieee, status);
2711
2712 return a < 0 ? (f_val | (1 << 31)) : f_val;
2713 }
2714
2715 static inline float64 float64_from_float32(int32_t a, float_status *status)
2716 {
2717 float64 f_val;
2718
2719 f_val = float32_to_float64((float64)a, status);
2720
2721 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
2722 }
2723
2724 static inline float32 float32_from_q16(int16_t a, float_status *status)
2725 {
2726 float32 f_val;
2727
2728 /* conversion as integer and scaling */
2729 f_val = int32_to_float32(a, status);
2730 f_val = float32_scalbn(f_val, -15, status);
2731
2732 return f_val;
2733 }
2734
2735 static inline float64 float64_from_q32(int32_t a, float_status *status)
2736 {
2737 float64 f_val;
2738
2739 /* conversion as integer and scaling */
2740 f_val = int32_to_float64(a, status);
2741 f_val = float64_scalbn(f_val, -31, status);
2742
2743 return f_val;
2744 }
2745
2746 static inline int16_t float32_to_q16(float32 a, float_status *status)
2747 {
2748 int32_t q_val;
2749 int32_t q_min = 0xffff8000;
2750 int32_t q_max = 0x00007fff;
2751
2752 int ieee_ex;
2753
2754 if (float32_is_any_nan(a)) {
2755 float_raise(float_flag_invalid, status);
2756 return 0;
2757 }
2758
2759 /* scaling */
2760 a = float32_scalbn(a, 15, status);
2761
2762 ieee_ex = get_float_exception_flags(status);
2763 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2764 , status);
2765
2766 if (ieee_ex & float_flag_overflow) {
2767 float_raise(float_flag_inexact, status);
2768 return (int32_t)a < 0 ? q_min : q_max;
2769 }
2770
2771 /* conversion to int */
2772 q_val = float32_to_int32(a, status);
2773
2774 ieee_ex = get_float_exception_flags(status);
2775 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2776 , status);
2777
2778 if (ieee_ex & float_flag_invalid) {
2779 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
2780 , status);
2781 float_raise(float_flag_overflow | float_flag_inexact, status);
2782 return (int32_t)a < 0 ? q_min : q_max;
2783 }
2784
2785 if (q_val < q_min) {
2786 float_raise(float_flag_overflow | float_flag_inexact, status);
2787 return (int16_t)q_min;
2788 }
2789
2790 if (q_max < q_val) {
2791 float_raise(float_flag_overflow | float_flag_inexact, status);
2792 return (int16_t)q_max;
2793 }
2794
2795 return (int16_t)q_val;
2796 }
2797
2798 static inline int32_t float64_to_q32(float64 a, float_status *status)
2799 {
2800 int64_t q_val;
2801 int64_t q_min = 0xffffffff80000000LL;
2802 int64_t q_max = 0x000000007fffffffLL;
2803
2804 int ieee_ex;
2805
2806 if (float64_is_any_nan(a)) {
2807 float_raise(float_flag_invalid, status);
2808 return 0;
2809 }
2810
2811 /* scaling */
2812 a = float64_scalbn(a, 31, status);
2813
2814 ieee_ex = get_float_exception_flags(status);
2815 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2816 , status);
2817
2818 if (ieee_ex & float_flag_overflow) {
2819 float_raise(float_flag_inexact, status);
2820 return (int64_t)a < 0 ? q_min : q_max;
2821 }
2822
2823 /* conversion to integer */
2824 q_val = float64_to_int64(a, status);
2825
2826 ieee_ex = get_float_exception_flags(status);
2827 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2828 , status);
2829
2830 if (ieee_ex & float_flag_invalid) {
2831 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
2832 , status);
2833 float_raise(float_flag_overflow | float_flag_inexact, status);
2834 return (int64_t)a < 0 ? q_min : q_max;
2835 }
2836
2837 if (q_val < q_min) {
2838 float_raise(float_flag_overflow | float_flag_inexact, status);
2839 return (int32_t)q_min;
2840 }
2841
2842 if (q_max < q_val) {
2843 float_raise(float_flag_overflow | float_flag_inexact, status);
2844 return (int32_t)q_max;
2845 }
2846
2847 return (int32_t)q_val;
2848 }
2849
2850 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
2851 do { \
2852 float_status *status = &env->active_tc.msa_fp_status; \
2853 int c; \
2854 int64_t cond; \
2855 set_float_exception_flags(0, status); \
2856 if (!QUIET) { \
2857 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2858 } else { \
2859 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
2860 } \
2861 DEST = cond ? M_MAX_UINT(BITS) : 0; \
2862 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
2863 \
2864 if (get_enabled_exceptions(env, c)) { \
2865 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2866 } \
2867 } while (0)
2868
2869 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
2870 do { \
2871 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
2872 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
2873 DEST = 0; \
2874 } \
2875 } while (0)
2876
2877 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
2878 do { \
2879 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2880 if (DEST == 0) { \
2881 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
2882 } \
2883 } while (0)
2884
2885 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
2886 do { \
2887 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
2888 if (DEST == 0) { \
2889 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
2890 } \
2891 } while (0)
2892
2893 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
2894 do { \
2895 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2896 if (DEST == 0) { \
2897 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
2898 if (DEST == 0) { \
2899 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
2900 } \
2901 } \
2902 } while (0)
2903
2904 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
2905 do { \
2906 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2907 if (DEST == 0) { \
2908 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
2909 } \
2910 } while (0)
2911
2912 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
2913 do { \
2914 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2915 if (DEST == 0) { \
2916 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
2917 } \
2918 } while (0)
2919
2920 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
2921 do { \
2922 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
2923 if (DEST == 0) { \
2924 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
2925 } \
2926 } while (0)
2927
2928 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2929 wr_t *pwt, uint32_t df, int quiet,
2930 uintptr_t retaddr)
2931 {
2932 wr_t wx, *pwx = &wx;
2933 uint32_t i;
2934
2935 clear_msacsr_cause(env);
2936
2937 switch (df) {
2938 case DF_WORD:
2939 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2940 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2941 }
2942 break;
2943 case DF_DOUBLE:
2944 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2945 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2946 }
2947 break;
2948 default:
2949 assert(0);
2950 }
2951
2952 check_msacsr_cause(env, retaddr);
2953
2954 msa_move_v(pwd, pwx);
2955 }
2956
2957 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2958 wr_t *pwt, uint32_t df, int quiet,
2959 uintptr_t retaddr)
2960 {
2961 wr_t wx, *pwx = &wx;
2962 uint32_t i;
2963
2964 clear_msacsr_cause(env);
2965
2966 switch (df) {
2967 case DF_WORD:
2968 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2969 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
2970 quiet);
2971 }
2972 break;
2973 case DF_DOUBLE:
2974 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2975 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
2976 quiet);
2977 }
2978 break;
2979 default:
2980 assert(0);
2981 }
2982
2983 check_msacsr_cause(env, retaddr);
2984
2985 msa_move_v(pwd, pwx);
2986 }
2987
2988 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2989 wr_t *pwt, uint32_t df, int quiet,
2990 uintptr_t retaddr)
2991 {
2992 wr_t wx, *pwx = &wx;
2993 uint32_t i;
2994
2995 clear_msacsr_cause(env);
2996
2997 switch (df) {
2998 case DF_WORD:
2999 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3000 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
3001 }
3002 break;
3003 case DF_DOUBLE:
3004 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3005 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
3006 }
3007 break;
3008 default:
3009 assert(0);
3010 }
3011
3012 check_msacsr_cause(env, retaddr);
3013
3014 msa_move_v(pwd, pwx);
3015 }
3016
3017 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3018 wr_t *pwt, uint32_t df, int quiet,
3019 uintptr_t retaddr)
3020 {
3021 wr_t wx, *pwx = &wx;
3022 uint32_t i;
3023
3024 clear_msacsr_cause(env);
3025
3026 switch (df) {
3027 case DF_WORD:
3028 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3029 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
3030 }
3031 break;
3032 case DF_DOUBLE:
3033 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3034 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
3035 }
3036 break;
3037 default:
3038 assert(0);
3039 }
3040
3041 check_msacsr_cause(env, retaddr);
3042
3043 msa_move_v(pwd, pwx);
3044 }
3045
3046 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3047 wr_t *pwt, uint32_t df, int quiet,
3048 uintptr_t retaddr)
3049 {
3050 wr_t wx, *pwx = &wx;
3051 uint32_t i;
3052
3053 clear_msacsr_cause(env);
3054
3055 switch (df) {
3056 case DF_WORD:
3057 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3058 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
3059 }
3060 break;
3061 case DF_DOUBLE:
3062 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3063 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
3064 }
3065 break;
3066 default:
3067 assert(0);
3068 }
3069
3070 check_msacsr_cause(env, retaddr);
3071
3072 msa_move_v(pwd, pwx);
3073 }
3074
3075 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3076 wr_t *pwt, uint32_t df, int quiet,
3077 uintptr_t retaddr)
3078 {
3079 wr_t wx, *pwx = &wx;
3080 uint32_t i;
3081
3082 clear_msacsr_cause(env);
3083
3084 switch (df) {
3085 case DF_WORD:
3086 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3087 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
3088 }
3089 break;
3090 case DF_DOUBLE:
3091 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3092 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
3093 }
3094 break;
3095 default:
3096 assert(0);
3097 }
3098
3099 check_msacsr_cause(env, retaddr);
3100
3101 msa_move_v(pwd, pwx);
3102 }
3103
3104 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3105 wr_t *pwt, uint32_t df, int quiet,
3106 uintptr_t retaddr)
3107 {
3108 wr_t wx, *pwx = &wx;
3109 uint32_t i;
3110
3111 clear_msacsr_cause(env);
3112
3113 switch (df) {
3114 case DF_WORD:
3115 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3116 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
3117 }
3118 break;
3119 case DF_DOUBLE:
3120 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3121 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
3122 }
3123 break;
3124 default:
3125 assert(0);
3126 }
3127
3128 check_msacsr_cause(env, retaddr);
3129
3130 msa_move_v(pwd, pwx);
3131 }
3132
3133 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3134 wr_t *pwt, uint32_t df, int quiet,
3135 uintptr_t retaddr)
3136 {
3137 wr_t wx, *pwx = &wx;
3138 uint32_t i;
3139
3140 clear_msacsr_cause(env);
3141
3142 switch (df) {
3143 case DF_WORD:
3144 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3145 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
3146 }
3147 break;
3148 case DF_DOUBLE:
3149 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3150 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
3151 }
3152 break;
3153 default:
3154 assert(0);
3155 }
3156
3157 check_msacsr_cause(env, retaddr);
3158
3159 msa_move_v(pwd, pwx);
3160 }
3161
3162 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3163 wr_t *pwt, uint32_t df, int quiet,
3164 uintptr_t retaddr)
3165 {
3166 wr_t wx, *pwx = &wx;
3167 uint32_t i;
3168
3169 clear_msacsr_cause(env);
3170
3171 switch (df) {
3172 case DF_WORD:
3173 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3174 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
3175 }
3176 break;
3177 case DF_DOUBLE:
3178 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3179 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
3180 }
3181 break;
3182 default:
3183 assert(0);
3184 }
3185
3186 check_msacsr_cause(env, retaddr);
3187
3188 msa_move_v(pwd, pwx);
3189 }
3190
3191 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3192 wr_t *pwt, uint32_t df, int quiet,
3193 uintptr_t retaddr)
3194 {
3195 wr_t wx, *pwx = &wx;
3196 uint32_t i;
3197
3198 clear_msacsr_cause(env);
3199
3200 switch (df) {
3201 case DF_WORD:
3202 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3203 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
3204 }
3205 break;
3206 case DF_DOUBLE:
3207 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3208 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
3209 }
3210 break;
3211 default:
3212 assert(0);
3213 }
3214
3215 check_msacsr_cause(env, retaddr);
3216
3217 msa_move_v(pwd, pwx);
3218 }
3219
3220 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
3221 wr_t *pwt, uint32_t df, int quiet,
3222 uintptr_t retaddr)
3223 {
3224 wr_t wx, *pwx = &wx;
3225 uint32_t i;
3226
3227 clear_msacsr_cause(env);
3228
3229 switch (df) {
3230 case DF_WORD:
3231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3232 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
3233 }
3234 break;
3235 case DF_DOUBLE:
3236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3237 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
3238 }
3239 break;
3240 default:
3241 assert(0);
3242 }
3243
3244 check_msacsr_cause(env, retaddr);
3245
3246 msa_move_v(pwd, pwx);
3247 }
3248
3249 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3250 uint32_t ws, uint32_t wt)
3251 {
3252 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3253 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3254 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3255 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
3256 }
3257
3258 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3259 uint32_t ws, uint32_t wt)
3260 {
3261 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3262 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3263 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3264 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
3265 }
3266
3267 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3268 uint32_t ws, uint32_t wt)
3269 {
3270 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3271 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3272 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3273 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
3274 }
3275
3276 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3277 uint32_t ws, uint32_t wt)
3278 {
3279 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3280 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3281 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3282 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
3283 }
3284
3285 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3286 uint32_t ws, uint32_t wt)
3287 {
3288 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3289 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3290 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3291 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
3292 }
3293
3294 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3295 uint32_t ws, uint32_t wt)
3296 {
3297 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3298 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3299 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3300 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
3301 }
3302
3303 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3304 uint32_t ws, uint32_t wt)
3305 {
3306 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3307 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3308 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3309 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
3310 }
3311
3312 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3313 uint32_t ws, uint32_t wt)
3314 {
3315 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3316 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3317 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3318 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
3319 }
3320
3321 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3322 uint32_t ws, uint32_t wt)
3323 {
3324 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3325 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3326 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3327 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
3328 }
3329
3330 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3331 uint32_t ws, uint32_t wt)
3332 {
3333 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3334 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3335 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3336 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
3337 }
3338
3339 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3340 uint32_t ws, uint32_t wt)
3341 {
3342 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3343 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3344 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3345 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
3346 }
3347
3348 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3349 uint32_t ws, uint32_t wt)
3350 {
3351 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3352 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3353 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3354 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
3355 }
3356
3357 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3358 uint32_t ws, uint32_t wt)
3359 {
3360 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3361 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3362 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3363 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
3364 }
3365
3366 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3367 uint32_t ws, uint32_t wt)
3368 {
3369 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3370 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3371 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3372 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
3373 }
3374
3375 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3376 uint32_t ws, uint32_t wt)
3377 {
3378 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3379 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3380 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3381 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
3382 }
3383
3384 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3385 uint32_t ws, uint32_t wt)
3386 {
3387 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3388 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3389 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3390 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
3391 }
3392
3393 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3394 uint32_t ws, uint32_t wt)
3395 {
3396 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3397 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3398 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3399 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
3400 }
3401
3402 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3403 uint32_t ws, uint32_t wt)
3404 {
3405 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3406 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3407 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3408 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
3409 }
3410
3411 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3412 uint32_t ws, uint32_t wt)
3413 {
3414 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3415 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3416 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3417 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
3418 }
3419
3420 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3421 uint32_t ws, uint32_t wt)
3422 {
3423 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3424 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3425 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3426 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
3427 }
3428
3429 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3430 uint32_t ws, uint32_t wt)
3431 {
3432 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3433 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3434 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3435 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
3436 }
3437
3438 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3439 uint32_t ws, uint32_t wt)
3440 {
3441 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3442 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3443 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3444 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
3445 }
3446
3447 #define float16_is_zero(ARG) 0
3448 #define float16_is_zero_or_denormal(ARG) 0
3449
3450 #define IS_DENORMAL(ARG, BITS) \
3451 (!float ## BITS ## _is_zero(ARG) \
3452 && float ## BITS ## _is_zero_or_denormal(ARG))
3453
3454 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
3455 do { \
3456 float_status *status = &env->active_tc.msa_fp_status; \
3457 int c; \
3458 \
3459 set_float_exception_flags(0, status); \
3460 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
3461 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3462 \
3463 if (get_enabled_exceptions(env, c)) { \
3464 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3465 } \
3466 } while (0)
3467
3468 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3469 uint32_t ws, uint32_t wt)
3470 {
3471 wr_t wx, *pwx = &wx;
3472 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3473 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3474 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3475 uint32_t i;
3476
3477 clear_msacsr_cause(env);
3478
3479 switch (df) {
3480 case DF_WORD:
3481 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3482 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
3483 }
3484 break;
3485 case DF_DOUBLE:
3486 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3487 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
3488 }
3489 break;
3490 default:
3491 assert(0);
3492 }
3493
3494 check_msacsr_cause(env, GETPC());
3495 msa_move_v(pwd, pwx);
3496 }
3497
3498 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3499 uint32_t ws, uint32_t wt)
3500 {
3501 wr_t wx, *pwx = &wx;
3502 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3503 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3504 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3505 uint32_t i;
3506
3507 clear_msacsr_cause(env);
3508
3509 switch (df) {
3510 case DF_WORD:
3511 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3512 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
3513 }
3514 break;
3515 case DF_DOUBLE:
3516 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3517 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
3518 }
3519 break;
3520 default:
3521 assert(0);
3522 }
3523
3524 check_msacsr_cause(env, GETPC());
3525 msa_move_v(pwd, pwx);
3526 }
3527
3528 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3529 uint32_t ws, uint32_t wt)
3530 {
3531 wr_t wx, *pwx = &wx;
3532 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3533 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3534 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3535 uint32_t i;
3536
3537 clear_msacsr_cause(env);
3538
3539 switch (df) {
3540 case DF_WORD:
3541 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3542 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
3543 }
3544 break;
3545 case DF_DOUBLE:
3546 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3547 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
3548 }
3549 break;
3550 default:
3551 assert(0);
3552 }
3553
3554 check_msacsr_cause(env, GETPC());
3555
3556 msa_move_v(pwd, pwx);
3557 }
3558
3559 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3560 uint32_t ws, uint32_t wt)
3561 {
3562 wr_t wx, *pwx = &wx;
3563 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3564 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3565 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3566 uint32_t i;
3567
3568 clear_msacsr_cause(env);
3569
3570 switch (df) {
3571 case DF_WORD:
3572 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3573 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
3574 }
3575 break;
3576 case DF_DOUBLE:
3577 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3578 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
3579 }
3580 break;
3581 default:
3582 assert(0);
3583 }
3584
3585 check_msacsr_cause(env, GETPC());
3586
3587 msa_move_v(pwd, pwx);
3588 }
3589
3590 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
3591 do { \
3592 float_status *status = &env->active_tc.msa_fp_status; \
3593 int c; \
3594 \
3595 set_float_exception_flags(0, status); \
3596 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
3597 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3598 \
3599 if (get_enabled_exceptions(env, c)) { \
3600 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3601 } \
3602 } while (0)
3603
3604 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3605 uint32_t ws, uint32_t wt)
3606 {
3607 wr_t wx, *pwx = &wx;
3608 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3609 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3610 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3611 uint32_t i;
3612
3613 clear_msacsr_cause(env);
3614
3615 switch (df) {
3616 case DF_WORD:
3617 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3618 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
3619 pws->w[i], pwt->w[i], 0, 32);
3620 }
3621 break;
3622 case DF_DOUBLE:
3623 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3624 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
3625 pws->d[i], pwt->d[i], 0, 64);
3626 }
3627 break;
3628 default:
3629 assert(0);
3630 }
3631
3632 check_msacsr_cause(env, GETPC());
3633
3634 msa_move_v(pwd, pwx);
3635 }
3636
3637 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3638 uint32_t ws, uint32_t wt)
3639 {
3640 wr_t wx, *pwx = &wx;
3641 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3642 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3643 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3644 uint32_t i;
3645
3646 clear_msacsr_cause(env);
3647
3648 switch (df) {
3649 case DF_WORD:
3650 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3651 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
3652 pws->w[i], pwt->w[i],
3653 float_muladd_negate_product, 32);
3654 }
3655 break;
3656 case DF_DOUBLE:
3657 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3658 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
3659 pws->d[i], pwt->d[i],
3660 float_muladd_negate_product, 64);
3661 }
3662 break;
3663 default:
3664 assert(0);
3665 }
3666
3667 check_msacsr_cause(env, GETPC());
3668
3669 msa_move_v(pwd, pwx);
3670 }
3671
3672 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3673 uint32_t ws, uint32_t wt)
3674 {
3675 wr_t wx, *pwx = &wx;
3676 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3677 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3678 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3679 uint32_t i;
3680
3681 clear_msacsr_cause(env);
3682
3683 switch (df) {
3684 case DF_WORD:
3685 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3686 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
3687 pwt->w[i] > 0x200 ? 0x200 :
3688 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
3689 32);
3690 }
3691 break;
3692 case DF_DOUBLE:
3693 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3694 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
3695 pwt->d[i] > 0x1000 ? 0x1000 :
3696 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
3697 64);
3698 }
3699 break;
3700 default:
3701 assert(0);
3702 }
3703
3704 check_msacsr_cause(env, GETPC());
3705
3706 msa_move_v(pwd, pwx);
3707 }
3708
3709 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
3710 do { \
3711 float_status *status = &env->active_tc.msa_fp_status; \
3712 int c; \
3713 \
3714 set_float_exception_flags(0, status); \
3715 DEST = float ## BITS ## _ ## OP(ARG, status); \
3716 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3717 \
3718 if (get_enabled_exceptions(env, c)) { \
3719 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3720 } \
3721 } while (0)
3722
3723 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3724 uint32_t ws, uint32_t wt)
3725 {
3726 wr_t wx, *pwx = &wx;
3727 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3728 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3729 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3730 uint32_t i;
3731
3732 clear_msacsr_cause(env);
3733
3734 switch (df) {
3735 case DF_WORD:
3736 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3737 /*
3738 * Half precision floats come in two formats: standard
3739 * IEEE and "ARM" format. The latter gains extra exponent
3740 * range by omitting the NaN/Inf encodings.
3741 */
3742 flag ieee = 1;
3743
3744 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
3745 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
3746 }
3747 break;
3748 case DF_DOUBLE:
3749 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3750 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
3751 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
3752 }
3753 break;
3754 default:
3755 assert(0);
3756 }
3757
3758 check_msacsr_cause(env, GETPC());
3759 msa_move_v(pwd, pwx);
3760 }
3761
3762 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
3763 do { \
3764 float_status *status = &env->active_tc.msa_fp_status; \
3765 int c; \
3766 \
3767 set_float_exception_flags(0, status); \
3768 DEST = float ## BITS ## _ ## OP(ARG, status); \
3769 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
3770 \
3771 if (get_enabled_exceptions(env, c)) { \
3772 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
3773 } \
3774 } while (0)
3775
3776 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3777 uint32_t ws, uint32_t wt)
3778 {
3779 wr_t wx, *pwx = &wx;
3780 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3781 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3782 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3783 uint32_t i;
3784
3785 clear_msacsr_cause(env);
3786
3787 switch (df) {
3788 case DF_WORD:
3789 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3790 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
3791 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
3792 }
3793 break;
3794 case DF_DOUBLE:
3795 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3796 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
3797 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
3798 }
3799 break;
3800 default:
3801 assert(0);
3802 }
3803
3804 check_msacsr_cause(env, GETPC());
3805
3806 msa_move_v(pwd, pwx);
3807 }
3808
3809 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
3810 !float ## BITS ## _is_any_nan(ARG1) \
3811 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
3812
3813 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
3814 do { \
3815 float_status *status = &env->active_tc.msa_fp_status; \
3816 int c; \
3817 \
3818 set_float_exception_flags(0, status); \
3819 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
3820 c = update_msacsr(env, 0, 0); \
3821 \
3822 if (get_enabled_exceptions(env, c)) { \
3823 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3824 } \
3825 } while (0)
3826
3827 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
3828 do { \
3829 uint## BITS ##_t S = _S, T = _T; \
3830 uint## BITS ##_t as, at, xs, xt, xd; \
3831 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
3832 T = S; \
3833 } \
3834 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
3835 S = T; \
3836 } \
3837 as = float## BITS ##_abs(S); \
3838 at = float## BITS ##_abs(T); \
3839 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
3840 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
3841 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
3842 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
3843 } while (0)
3844
3845 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3846 uint32_t ws, uint32_t wt)
3847 {
3848 float_status *status = &env->active_tc.msa_fp_status;
3849 wr_t wx, *pwx = &wx;
3850 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3851 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3852 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3853
3854 clear_msacsr_cause(env);
3855
3856 if (df == DF_WORD) {
3857
3858 if (NUMBER_QNAN_PAIR(pws->w[0], pwt->w[0], 32, status)) {
3859 MSA_FLOAT_MAXOP(pwx->w[0], min, pws->w[0], pws->w[0], 32);
3860 } else if (NUMBER_QNAN_PAIR(pwt->w[0], pws->w[0], 32, status)) {
3861 MSA_FLOAT_MAXOP(pwx->w[0], min, pwt->w[0], pwt->w[0], 32);
3862 } else {
3863 MSA_FLOAT_MAXOP(pwx->w[0], min, pws->w[0], pwt->w[0], 32);
3864 }
3865
3866 if (NUMBER_QNAN_PAIR(pws->w[1], pwt->w[1], 32, status)) {
3867 MSA_FLOAT_MAXOP(pwx->w[1], min, pws->w[1], pws->w[1], 32);
3868 } else if (NUMBER_QNAN_PAIR(pwt->w[1], pws->w[1], 32, status)) {
3869 MSA_FLOAT_MAXOP(pwx->w[1], min, pwt->w[1], pwt->w[1], 32);
3870 } else {
3871 MSA_FLOAT_MAXOP(pwx->w[1], min, pws->w[1], pwt->w[1], 32);
3872 }
3873
3874 if (NUMBER_QNAN_PAIR(pws->w[2], pwt->w[2], 32, status)) {
3875 MSA_FLOAT_MAXOP(pwx->w[2], min, pws->w[2], pws->w[2], 32);
3876 } else if (NUMBER_QNAN_PAIR(pwt->w[2], pws->w[2], 32, status)) {
3877 MSA_FLOAT_MAXOP(pwx->w[2], min, pwt->w[2], pwt->w[2], 32);
3878 } else {
3879 MSA_FLOAT_MAXOP(pwx->w[2], min, pws->w[2], pwt->w[2], 32);
3880 }
3881
3882 if (NUMBER_QNAN_PAIR(pws->w[3], pwt->w[3], 32, status)) {
3883 MSA_FLOAT_MAXOP(pwx->w[3], min, pws->w[3], pws->w[3], 32);
3884 } else if (NUMBER_QNAN_PAIR(pwt->w[3], pws->w[3], 32, status)) {
3885 MSA_FLOAT_MAXOP(pwx->w[3], min, pwt->w[3], pwt->w[3], 32);
3886 } else {
3887 MSA_FLOAT_MAXOP(pwx->w[3], min, pws->w[3], pwt->w[3], 32);
3888 }
3889
3890 } else if (df == DF_DOUBLE) {
3891
3892 if (NUMBER_QNAN_PAIR(pws->d[0], pwt->d[0], 64, status)) {
3893 MSA_FLOAT_MAXOP(pwx->d[0], min, pws->d[0], pws->d[0], 64);
3894 } else if (NUMBER_QNAN_PAIR(pwt->d[0], pws->d[0], 64, status)) {
3895 MSA_FLOAT_MAXOP(pwx->d[0], min, pwt->d[0], pwt->d[0], 64);
3896 } else {
3897 MSA_FLOAT_MAXOP(pwx->d[0], min, pws->d[0], pwt->d[0], 64);
3898 }
3899
3900 if (NUMBER_QNAN_PAIR(pws->d[1], pwt->d[1], 64, status)) {
3901 MSA_FLOAT_MAXOP(pwx->d[1], min, pws->d[1], pws->d[1], 64);
3902 } else if (NUMBER_QNAN_PAIR(pwt->d[1], pws->d[1], 64, status)) {
3903 MSA_FLOAT_MAXOP(pwx->d[1], min, pwt->d[1], pwt->d[1], 64);
3904 } else {
3905 MSA_FLOAT_MAXOP(pwx->d[1], min, pws->d[1], pwt->d[1], 64);
3906 }
3907
3908 } else {
3909
3910 assert(0);
3911
3912 }
3913
3914 check_msacsr_cause(env, GETPC());
3915
3916 msa_move_v(pwd, pwx);
3917 }
3918
3919 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3920 uint32_t ws, uint32_t wt)
3921 {
3922 float_status *status = &env->active_tc.msa_fp_status;
3923 wr_t wx, *pwx = &wx;
3924 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3925 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3926 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3927
3928 clear_msacsr_cause(env);
3929
3930 if (df == DF_WORD) {
3931 FMAXMIN_A(min, max, pwx->w[0], pws->w[0], pwt->w[0], 32, status);
3932 FMAXMIN_A(min, max, pwx->w[1], pws->w[1], pwt->w[1], 32, status);
3933 FMAXMIN_A(min, max, pwx->w[2], pws->w[2], pwt->w[2], 32, status);
3934 FMAXMIN_A(min, max, pwx->w[3], pws->w[3], pwt->w[3], 32, status);
3935 } else if (df == DF_DOUBLE) {
3936 FMAXMIN_A(min, max, pwx->d[0], pws->d[0], pwt->d[0], 64, status);
3937 FMAXMIN_A(min, max, pwx->d[1], pws->d[1], pwt->d[1], 64, status);
3938 } else {
3939 assert(0);
3940 }
3941
3942 check_msacsr_cause(env, GETPC());
3943
3944 msa_move_v(pwd, pwx);
3945 }
3946
3947 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3948 uint32_t ws, uint32_t wt)
3949 {
3950 float_status *status = &env->active_tc.msa_fp_status;
3951 wr_t wx, *pwx = &wx;
3952 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3953 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3954 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3955
3956 clear_msacsr_cause(env);
3957
3958 if (df == DF_WORD) {
3959
3960 if (NUMBER_QNAN_PAIR(pws->w[0], pwt->w[0], 32, status)) {
3961 MSA_FLOAT_MAXOP(pwx->w[0], max, pws->w[0], pws->w[0], 32);
3962 } else if (NUMBER_QNAN_PAIR(pwt->w[0], pws->w[0], 32, status)) {
3963 MSA_FLOAT_MAXOP(pwx->w[0], max, pwt->w[0], pwt->w[0], 32);
3964 } else {
3965 MSA_FLOAT_MAXOP(pwx->w[0], max, pws->w[0], pwt->w[0], 32);
3966 }
3967
3968 if (NUMBER_QNAN_PAIR(pws->w[1], pwt->w[1], 32, status)) {
3969 MSA_FLOAT_MAXOP(pwx->w[1], max, pws->w[1], pws->w[1], 32);
3970 } else if (NUMBER_QNAN_PAIR(pwt->w[1], pws->w[1], 32, status)) {
3971 MSA_FLOAT_MAXOP(pwx->w[1], max, pwt->w[1], pwt->w[1], 32);
3972 } else {
3973 MSA_FLOAT_MAXOP(pwx->w[1], max, pws->w[1], pwt->w[1], 32);
3974 }
3975
3976 if (NUMBER_QNAN_PAIR(pws->w[2], pwt->w[2], 32, status)) {
3977 MSA_FLOAT_MAXOP(pwx->w[2], max, pws->w[2], pws->w[2], 32);
3978 } else if (NUMBER_QNAN_PAIR(pwt->w[2], pws->w[2], 32, status)) {
3979 MSA_FLOAT_MAXOP(pwx->w[2], max, pwt->w[2], pwt->w[2], 32);
3980 } else {
3981 MSA_FLOAT_MAXOP(pwx->w[2], max, pws->w[2], pwt->w[2], 32);
3982 }
3983
3984 if (NUMBER_QNAN_PAIR(pws->w[3], pwt->w[3], 32, status)) {
3985 MSA_FLOAT_MAXOP(pwx->w[3], max, pws->w[3], pws->w[3], 32);
3986 } else if (NUMBER_QNAN_PAIR(pwt->w[3], pws->w[3], 32, status)) {
3987 MSA_FLOAT_MAXOP(pwx->w[3], max, pwt->w[3], pwt->w[3], 32);
3988 } else {
3989 MSA_FLOAT_MAXOP(pwx->w[3], max, pws->w[3], pwt->w[3], 32);
3990 }
3991
3992 } else if (df == DF_DOUBLE) {
3993
3994 if (NUMBER_QNAN_PAIR(pws->d[0], pwt->d[0], 64, status)) {
3995 MSA_FLOAT_MAXOP(pwx->d[0], max, pws->d[0], pws->d[0], 64);
3996 } else if (NUMBER_QNAN_PAIR(pwt->d[0], pws->d[0], 64, status)) {
3997 MSA_FLOAT_MAXOP(pwx->d[0], max, pwt->d[0], pwt->d[0], 64);
3998 } else {
3999 MSA_FLOAT_MAXOP(pwx->d[0], max, pws->d[0], pwt->d[0], 64);
4000 }
4001
4002 if (NUMBER_QNAN_PAIR(pws->d[1], pwt->d[1], 64, status)) {
4003 MSA_FLOAT_MAXOP(pwx->d[1], max, pws->d[1], pws->d[1], 64);
4004 } else if (NUMBER_QNAN_PAIR(pwt->d[1], pws->d[1], 64, status)) {
4005 MSA_FLOAT_MAXOP(pwx->d[1], max, pwt->d[1], pwt->d[1], 64);
4006 } else {
4007 MSA_FLOAT_MAXOP(pwx->d[1], max, pws->d[1], pwt->d[1], 64);
4008 }
4009
4010 } else {
4011
4012 assert(0);
4013
4014 }
4015
4016 check_msacsr_cause(env, GETPC());
4017
4018 msa_move_v(pwd, pwx);
4019 }
4020
4021 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4022 uint32_t ws, uint32_t wt)
4023 {
4024 float_status *status = &env->active_tc.msa_fp_status;
4025 wr_t wx, *pwx = &wx;
4026 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4027 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4028 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4029
4030 clear_msacsr_cause(env);
4031
4032 if (df == DF_WORD) {
4033 FMAXMIN_A(max, min, pwx->w[0], pws->w[0], pwt->w[0], 32, status);
4034 FMAXMIN_A(max, min, pwx->w[1], pws->w[1], pwt->w[1], 32, status);
4035 FMAXMIN_A(max, min, pwx->w[2], pws->w[2], pwt->w[2], 32, status);
4036 FMAXMIN_A(max, min, pwx->w[3], pws->w[3], pwt->w[3], 32, status);
4037 } else if (df == DF_DOUBLE) {
4038 FMAXMIN_A(max, min, pwx->d[0], pws->d[0], pwt->d[0], 64, status);
4039 FMAXMIN_A(max, min, pwx->d[1], pws->d[1], pwt->d[1], 64, status);
4040 } else {
4041 assert(0);
4042 }
4043
4044 check_msacsr_cause(env, GETPC());
4045
4046 msa_move_v(pwd, pwx);
4047 }
4048
4049 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
4050 uint32_t wd, uint32_t ws)
4051 {
4052 float_status *status = &env->active_tc.msa_fp_status;
4053
4054 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4055 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4056 if (df == DF_WORD) {
4057 pwd->w[0] = float_class_s(pws->w[0], status);
4058 pwd->w[1] = float_class_s(pws->w[1], status);
4059 pwd->w[2] = float_class_s(pws->w[2], status);
4060 pwd->w[3] = float_class_s(pws->w[3], status);
4061 } else if (df == DF_DOUBLE) {
4062 pwd->d[0] = float_class_d(pws->d[0], status);
4063 pwd->d[1] = float_class_d(pws->d[1], status);
4064 } else {
4065 assert(0);
4066 }
4067 }
4068
4069 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
4070 do { \
4071 float_status *status = &env->active_tc.msa_fp_status; \
4072 int c; \
4073 \
4074 set_float_exception_flags(0, status); \
4075 DEST = float ## BITS ## _ ## OP(ARG, status); \
4076 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
4077 \
4078 if (get_enabled_exceptions(env, c)) { \
4079 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
4080 } else if (float ## BITS ## _is_any_nan(ARG)) { \
4081 DEST = 0; \
4082 } \
4083 } while (0)
4084
4085 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4086 uint32_t ws)
4087 {
4088 wr_t wx, *pwx = &wx;
4089 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4090 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4091 uint32_t i;
4092
4093 clear_msacsr_cause(env);
4094
4095 switch (df) {
4096 case DF_WORD:
4097 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4098 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
4099 }
4100 break;
4101 case DF_DOUBLE:
4102 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4103 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
4104 }
4105 break;
4106 default:
4107 assert(0);
4108 }
4109
4110 check_msacsr_cause(env, GETPC());
4111
4112 msa_move_v(pwd, pwx);
4113 }
4114
4115 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4116 uint32_t ws)
4117 {
4118 wr_t wx, *pwx = &wx;
4119 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4120 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4121 uint32_t i;
4122
4123 clear_msacsr_cause(env);
4124
4125 switch (df) {
4126 case DF_WORD:
4127 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4128 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
4129 }
4130 break;
4131 case DF_DOUBLE:
4132 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4133 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
4134 }
4135 break;
4136 default:
4137 assert(0);
4138 }
4139
4140 check_msacsr_cause(env, GETPC());
4141
4142 msa_move_v(pwd, pwx);
4143 }
4144
4145 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4146 uint32_t ws)
4147 {
4148 wr_t wx, *pwx = &wx;
4149 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4150 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4151 uint32_t i;
4152
4153 clear_msacsr_cause(env);
4154
4155 switch (df) {
4156 case DF_WORD:
4157 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4158 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
4159 }
4160 break;
4161 case DF_DOUBLE:
4162 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4163 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
4164 }
4165 break;
4166 default:
4167 assert(0);
4168 }
4169
4170 check_msacsr_cause(env, GETPC());
4171
4172 msa_move_v(pwd, pwx);
4173 }
4174
4175 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
4176 do { \
4177 float_status *status = &env->active_tc.msa_fp_status; \
4178 int c; \
4179 \
4180 set_float_exception_flags(0, status); \
4181 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
4182 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
4183 float ## BITS ## _is_quiet_nan(DEST, status) ? \
4184 0 : RECIPROCAL_INEXACT, \
4185 IS_DENORMAL(DEST, BITS)); \
4186 \
4187 if (get_enabled_exceptions(env, c)) { \
4188 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
4189 } \
4190 } while (0)
4191
4192 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4193 uint32_t ws)
4194 {
4195 wr_t wx, *pwx = &wx;
4196 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4197 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4198 uint32_t i;
4199
4200 clear_msacsr_cause(env);
4201
4202 switch (df) {
4203 case DF_WORD:
4204 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4205 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
4206 &env->active_tc.msa_fp_status), 32);
4207 }
4208 break;
4209 case DF_DOUBLE:
4210 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4211 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
4212 &env->active_tc.msa_fp_status), 64);
4213 }
4214 break;
4215 default:
4216 assert(0);
4217 }
4218
4219 check_msacsr_cause(env, GETPC());
4220
4221 msa_move_v(pwd, pwx);
4222 }
4223
4224 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4225 uint32_t ws)
4226 {
4227 wr_t wx, *pwx = &wx;
4228 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4229 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4230 uint32_t i;
4231
4232 clear_msacsr_cause(env);
4233
4234 switch (df) {
4235 case DF_WORD:
4236 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4237 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
4238 }
4239 break;
4240 case DF_DOUBLE:
4241 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4242 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
4243 }
4244 break;
4245 default:
4246 assert(0);
4247 }
4248
4249 check_msacsr_cause(env, GETPC());
4250
4251 msa_move_v(pwd, pwx);
4252 }
4253
4254 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4255 uint32_t ws)
4256 {
4257 wr_t wx, *pwx = &wx;
4258 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4259 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4260 uint32_t i;
4261
4262 clear_msacsr_cause(env);
4263
4264 switch (df) {
4265 case DF_WORD:
4266 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4267 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
4268 }
4269 break;
4270 case DF_DOUBLE:
4271 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4272 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
4273 }
4274 break;
4275 default:
4276 assert(0);
4277 }
4278
4279 check_msacsr_cause(env, GETPC());
4280
4281 msa_move_v(pwd, pwx);
4282 }
4283
4284 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
4285 do { \
4286 float_status *status = &env->active_tc.msa_fp_status; \
4287 int c; \
4288 \
4289 set_float_exception_flags(0, status); \
4290 set_float_rounding_mode(float_round_down, status); \
4291 DEST = float ## BITS ## _ ## log2(ARG, status); \
4292 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
4293 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
4294 MSACSR_RM_MASK) >> MSACSR_RM], \
4295 status); \
4296 \
4297 set_float_exception_flags(get_float_exception_flags(status) & \
4298 (~float_flag_inexact), \
4299 status); \
4300 \
4301 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
4302 \
4303 if (get_enabled_exceptions(env, c)) { \
4304 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
4305 } \
4306 } while (0)
4307
4308 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4309 uint32_t ws)
4310 {
4311 wr_t wx, *pwx = &wx;
4312 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4313 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4314 uint32_t i;
4315
4316 clear_msacsr_cause(env);
4317
4318 switch (df) {
4319 case DF_WORD:
4320 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4321 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
4322 }
4323 break;
4324 case DF_DOUBLE:
4325 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4326 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
4327 }
4328 break;
4329 default:
4330 assert(0);
4331 }
4332
4333 check_msacsr_cause(env, GETPC());
4334
4335 msa_move_v(pwd, pwx);
4336 }
4337
4338 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4339 uint32_t ws)
4340 {
4341 wr_t wx, *pwx = &wx;
4342 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4343 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4344 uint32_t i;
4345
4346 clear_msacsr_cause(env);
4347
4348 switch (df) {
4349 case DF_WORD:
4350 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4351 /*
4352 * Half precision floats come in two formats: standard
4353 * IEEE and "ARM" format. The latter gains extra exponent
4354 * range by omitting the NaN/Inf encodings.
4355 */
4356 flag ieee = 1;
4357
4358 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
4359 }
4360 break;
4361 case DF_DOUBLE:
4362 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4363 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
4364 }
4365 break;
4366 default:
4367 assert(0);
4368 }
4369
4370 check_msacsr_cause(env, GETPC());
4371 msa_move_v(pwd, pwx);
4372 }
4373
4374 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4375 uint32_t ws)
4376 {
4377 wr_t wx, *pwx = &wx;
4378 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4379 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4380 uint32_t i;
4381
4382 clear_msacsr_cause(env);
4383
4384 switch (df) {
4385 case DF_WORD:
4386 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4387 /*
4388 * Half precision floats come in two formats: standard
4389 * IEEE and "ARM" format. The latter gains extra exponent
4390 * range by omitting the NaN/Inf encodings.
4391 */
4392 flag ieee = 1;
4393
4394 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
4395 }
4396 break;
4397 case DF_DOUBLE:
4398 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4399 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
4400 }
4401 break;
4402 default:
4403 assert(0);
4404 }
4405
4406 check_msacsr_cause(env, GETPC());
4407 msa_move_v(pwd, pwx);
4408 }
4409
4410 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4411 uint32_t ws)
4412 {
4413 wr_t wx, *pwx = &wx;
4414 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4415 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4416 uint32_t i;
4417
4418 switch (df) {
4419 case DF_WORD:
4420 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4421 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
4422 }
4423 break;
4424 case DF_DOUBLE:
4425 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4426 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
4427 }
4428 break;
4429 default:
4430 assert(0);
4431 }
4432
4433 msa_move_v(pwd, pwx);
4434 }
4435
4436 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4437 uint32_t ws)
4438 {
4439 wr_t wx, *pwx = &wx;
4440 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4441 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4442 uint32_t i;
4443
4444 switch (df) {
4445 case DF_WORD:
4446 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4447 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
4448 }
4449 break;
4450 case DF_DOUBLE:
4451 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4452 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
4453 }
4454 break;
4455 default:
4456 assert(0);
4457 }
4458
4459 msa_move_v(pwd, pwx);
4460 }
4461
4462 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4463 uint32_t ws)
4464 {
4465 wr_t wx, *pwx = &wx;
4466 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4467 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4468 uint32_t i;
4469
4470 clear_msacsr_cause(env);
4471
4472 switch (df) {
4473 case DF_WORD:
4474 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4475 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
4476 }
4477 break;
4478 case DF_DOUBLE:
4479 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4480 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
4481 }
4482 break;
4483 default:
4484 assert(0);
4485 }
4486
4487 check_msacsr_cause(env, GETPC());
4488
4489 msa_move_v(pwd, pwx);
4490 }
4491
4492 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4493 uint32_t ws)
4494 {
4495 wr_t wx, *pwx = &wx;
4496 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4497 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4498 uint32_t i;
4499
4500 clear_msacsr_cause(env);
4501
4502 switch (df) {
4503 case DF_WORD:
4504 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4505 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
4506 }
4507 break;
4508 case DF_DOUBLE:
4509 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4510 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
4511 }
4512 break;
4513 default:
4514 assert(0);
4515 }
4516
4517 check_msacsr_cause(env, GETPC());
4518
4519 msa_move_v(pwd, pwx);
4520 }
4521
4522 #define float32_from_int32 int32_to_float32
4523 #define float32_from_uint32 uint32_to_float32
4524
4525 #define float64_from_int64 int64_to_float64
4526 #define float64_from_uint64 uint64_to_float64
4527
4528 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4529 uint32_t ws)
4530 {
4531 wr_t wx, *pwx = &wx;
4532 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4533 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4534 uint32_t i;
4535
4536 clear_msacsr_cause(env);
4537
4538 switch (df) {
4539 case DF_WORD:
4540 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4541 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
4542 }
4543 break;
4544 case DF_DOUBLE:
4545 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4546 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
4547 }
4548 break;
4549 default:
4550 assert(0);
4551 }
4552
4553 check_msacsr_cause(env, GETPC());
4554
4555 msa_move_v(pwd, pwx);
4556 }
4557
4558 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4559 uint32_t ws)
4560 {
4561 wr_t wx, *pwx = &wx;
4562 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4563 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4564 uint32_t i;
4565
4566 clear_msacsr_cause(env);
4567
4568 switch (df) {
4569 case DF_WORD:
4570 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4571 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
4572 }
4573 break;
4574 case DF_DOUBLE:
4575 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4576 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
4577 }
4578 break;
4579 default:
4580 assert(0);
4581 }
4582
4583 check_msacsr_cause(env, GETPC());
4584
4585 msa_move_v(pwd, pwx);
4586 }
AR7 emulation for QEMU