hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "i8254.h"
  40 #include "pcspk.h"
  41 #include "msi.h"
  42 #include "sysbus.h"
  43 #include "sysemu.h"
  44 #include "kvm.h"
  45 #include "blockdev.h"
  46 #include "ui/qemu-spice.h"
  47 #include "memory.h"
  48 #include "exec-memory.h"
  49
  50 /* output Bochs bios info messages */
  51 //#define DEBUG_BIOS
  52
  53 /* debug PC/ISA interrupts */
  54 //#define DEBUG_IRQ
  55
  56 #ifdef DEBUG_IRQ
  57 #define DPRINTF(fmt, ...)                                       \
  58     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  59 #else
  60 #define DPRINTF(fmt, ...)
  61 #endif
  62
  63 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  64 #define ACPI_DATA_SIZE       0x10000
  65 #define BIOS_CFG_IOPORT 0x510
  66 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  67 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  68 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  69 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  70 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  71
  72 #define MSI_ADDR_BASE 0xfee00000
  73
  74 #define E820_NR_ENTRIES         16
  75
  76 struct e820_entry {
  77     uint64_t address;
  78     uint64_t length;
  79     uint32_t type;
  80 } QEMU_PACKED __attribute((__aligned__(4)));
  81
  82 struct e820_table {
  83     uint32_t count;
  84     struct e820_entry entry[E820_NR_ENTRIES];
  85 } QEMU_PACKED __attribute((__aligned__(4)));
  86
  87 static struct e820_table e820_table;
  88 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  89
  90 void gsi_handler(void *opaque, int n, int level)
  91 {
  92     GSIState *s = opaque;
  93
  94     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  95     if (n < ISA_NUM_IRQS) {
  96         qemu_set_irq(s->i8259_irq[n], level);
  97     }
  98     qemu_set_irq(s->ioapic_irq[n], level);
  99 }
 100
 101 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 102 {
 103 }
 104
 105 /* MSDOS compatibility mode FPU exception support */
 106 static qemu_irq ferr_irq;
 107
 108 void pc_register_ferr_irq(qemu_irq irq)
 109 {
 110     ferr_irq = irq;
 111 }
 112
 113 /* XXX: add IGNNE support */
 114 void cpu_set_ferr(CPUX86State *s)
 115 {
 116     qemu_irq_raise(ferr_irq);
 117 }
 118
 119 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 120 {
 121     qemu_irq_lower(ferr_irq);
 122 }
 123
 124 /* TSC handling */
 125 uint64_t cpu_get_tsc(CPUX86State *env)
 126 {
 127     return cpu_get_ticks();
 128 }
 129
 130 /* SMM support */
 131
 132 static cpu_set_smm_t smm_set;
 133 static void *smm_arg;
 134
 135 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 136 {
 137     assert(smm_set == NULL);
 138     assert(smm_arg == NULL);
 139     smm_set = callback;
 140     smm_arg = arg;
 141 }
 142
 143 void cpu_smm_update(CPUState *env)
 144 {
 145     if (smm_set && smm_arg && env == first_cpu)
 146         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 147 }
 148
 149
 150 /* IRQ handling */
 151 int cpu_get_pic_interrupt(CPUState *env)
 152 {
 153     int intno;
 154
 155     intno = apic_get_interrupt(env->apic_state);
 156     if (intno >= 0) {
 157         return intno;
 158     }
 159     /* read the irq from the PIC */
 160     if (!apic_accept_pic_intr(env->apic_state)) {
 161         return -1;
 162     }
 163
 164     intno = pic_read_irq(isa_pic);
 165     return intno;
 166 }
 167
 168 static void pic_irq_request(void *opaque, int irq, int level)
 169 {
 170     CPUState *env = first_cpu;
 171
 172     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 173     if (env->apic_state) {
 174         while (env) {
 175             if (apic_accept_pic_intr(env->apic_state)) {
 176                 apic_deliver_pic_intr(env->apic_state, level);
 177             }
 178             env = env->next_cpu;
 179         }
 180     } else {
 181         if (level)
 182             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 183         else
 184             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 185     }
 186 }
 187
 188 /* PC cmos mappings */
 189
 190 #define REG_EQUIPMENT_BYTE          0x14
 191
 192 static int cmos_get_fd_drive_type(FDriveType fd0)
 193 {
 194     int val;
 195
 196     switch (fd0) {
 197     case FDRIVE_DRV_144:
 198         /* 1.44 Mb 3"5 drive */
 199         val = 4;
 200         break;
 201     case FDRIVE_DRV_288:
 202         /* 2.88 Mb 3"5 drive */
 203         val = 5;
 204         break;
 205     case FDRIVE_DRV_120:
 206         /* 1.2 Mb 5"5 drive */
 207         val = 2;
 208         break;
 209     case FDRIVE_DRV_NONE:
 210     default:
 211         val = 0;
 212         break;
 213     }
 214     return val;
 215 }
 216
 217 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 218                          ISADevice *s)
 219 {
 220     int cylinders, heads, sectors;
 221     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 222     rtc_set_memory(s, type_ofs, 47);
 223     rtc_set_memory(s, info_ofs, cylinders);
 224     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 225     rtc_set_memory(s, info_ofs + 2, heads);
 226     rtc_set_memory(s, info_ofs + 3, 0xff);
 227     rtc_set_memory(s, info_ofs + 4, 0xff);
 228     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 229     rtc_set_memory(s, info_ofs + 6, cylinders);
 230     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 231     rtc_set_memory(s, info_ofs + 8, sectors);
 232 }
 233
 234 /* convert boot_device letter to something recognizable by the bios */
 235 static int boot_device2nibble(char boot_device)
 236 {
 237     switch(boot_device) {
 238     case 'a':
 239     case 'b':
 240         return 0x01; /* floppy boot */
 241     case 'c':
 242         return 0x02; /* hard drive boot */
 243     case 'd':
 244         return 0x03; /* CD-ROM boot */
 245     case 'n':
 246         return 0x04; /* Network boot */
 247     }
 248     return 0;
 249 }
 250
 251 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 252 {
 253 #define PC_MAX_BOOT_DEVICES 3
 254     int nbds, bds[3] = { 0, };
 255     int i;
 256
 257     nbds = strlen(boot_device);
 258     if (nbds > PC_MAX_BOOT_DEVICES) {
 259         error_report("Too many boot devices for PC");
 260         return(1);
 261     }
 262     for (i = 0; i < nbds; i++) {
 263         bds[i] = boot_device2nibble(boot_device[i]);
 264         if (bds[i] == 0) {
 265             error_report("Invalid boot device for PC: '%c'",
 266                          boot_device[i]);
 267             return(1);
 268         }
 269     }
 270     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 271     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 272     return(0);
 273 }
 274
 275 static int pc_boot_set(void *opaque, const char *boot_device)
 276 {
 277     return set_boot_dev(opaque, boot_device, 0);
 278 }
 279
 280 typedef struct pc_cmos_init_late_arg {
 281     ISADevice *rtc_state;
 282     BusState *idebus0, *idebus1;
 283 } pc_cmos_init_late_arg;
 284
 285 static void pc_cmos_init_late(void *opaque)
 286 {
 287     pc_cmos_init_late_arg *arg = opaque;
 288     ISADevice *s = arg->rtc_state;
 289     int val;
 290     BlockDriverState *hd_table[4];
 291     int i;
 292
 293     ide_get_bs(hd_table, arg->idebus0);
 294     ide_get_bs(hd_table + 2, arg->idebus1);
 295
 296     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 297     if (hd_table[0])
 298         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 299     if (hd_table[1])
 300         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 301
 302     val = 0;
 303     for (i = 0; i < 4; i++) {
 304         if (hd_table[i]) {
 305             int cylinders, heads, sectors, translation;
 306             /* NOTE: bdrv_get_geometry_hint() returns the physical
 307                 geometry.  It is always such that: 1 <= sects <= 63, 1
 308                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 309                 geometry can be different if a translation is done. */
 310             translation = bdrv_get_translation_hint(hd_table[i]);
 311             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 312                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 313                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 314                     /* No translation. */
 315                     translation = 0;
 316                 } else {
 317                     /* LBA translation. */
 318                     translation = 1;
 319                 }
 320             } else {
 321                 translation--;
 322             }
 323             val |= translation << (i * 2);
 324         }
 325     }
 326     rtc_set_memory(s, 0x39, val);
 327
 328     qemu_unregister_reset(pc_cmos_init_late, opaque);
 329 }
 330
 331 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 332                   const char *boot_device,
 333                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 334                   ISADevice *s)
 335 {
 336     int val, nb, nb_heads, max_track, last_sect, i;
 337     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 338     BlockDriverState *fd[MAX_FD];
 339     static pc_cmos_init_late_arg arg;
 340
 341     /* various important CMOS locations needed by PC/Bochs bios */
 342
 343     /* memory size */
 344     val = 640; /* base memory in K */
 345     rtc_set_memory(s, 0x15, val);
 346     rtc_set_memory(s, 0x16, val >> 8);
 347
 348     val = (ram_size / 1024) - 1024;
 349     if (val > 65535)
 350         val = 65535;
 351     rtc_set_memory(s, 0x17, val);
 352     rtc_set_memory(s, 0x18, val >> 8);
 353     rtc_set_memory(s, 0x30, val);
 354     rtc_set_memory(s, 0x31, val >> 8);
 355
 356     if (above_4g_mem_size) {
 357         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 358         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 359         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 360     }
 361
 362     if (ram_size > (16 * 1024 * 1024))
 363         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 364     else
 365         val = 0;
 366     if (val > 65535)
 367         val = 65535;
 368     rtc_set_memory(s, 0x34, val);
 369     rtc_set_memory(s, 0x35, val >> 8);
 370
 371     /* set the number of CPU */
 372     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 373
 374     /* set boot devices, and disable floppy signature check if requested */
 375     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 376         exit(1);
 377     }
 378
 379     /* floppy type */
 380     if (floppy) {
 381         fdc_get_bs(fd, floppy);
 382         for (i = 0; i < 2; i++) {
 383             if (fd[i] && bdrv_is_inserted(fd[i])) {
 384                 bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
 385                                               &last_sect, FDRIVE_DRV_NONE,
 386                                               &fd_type[i]);
 387             }
 388         }
 389     }
 390     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 391         cmos_get_fd_drive_type(fd_type[1]);
 392     rtc_set_memory(s, 0x10, val);
 393
 394     val = 0;
 395     nb = 0;
 396     if (fd_type[0] < FDRIVE_DRV_NONE) {
 397         nb++;
 398     }
 399     if (fd_type[1] < FDRIVE_DRV_NONE) {
 400         nb++;
 401     }
 402     switch (nb) {
 403     case 0:
 404         break;
 405     case 1:
 406         val |= 0x01; /* 1 drive, ready for boot */
 407         break;
 408     case 2:
 409         val |= 0x41; /* 2 drives, ready for boot */
 410         break;
 411     }
 412     val |= 0x02; /* FPU is there */
 413     val |= 0x04; /* PS/2 mouse installed */
 414     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 415
 416     /* hard drives */
 417     arg.rtc_state = s;
 418     arg.idebus0 = idebus0;
 419     arg.idebus1 = idebus1;
 420     qemu_register_reset(pc_cmos_init_late, &arg);
 421 }
 422
 423 /* port 92 stuff: could be split off */
 424 typedef struct Port92State {
 425     ISADevice dev;
 426     MemoryRegion io;
 427     uint8_t outport;
 428     qemu_irq *a20_out;
 429 } Port92State;
 430
 431 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 432 {
 433     Port92State *s = opaque;
 434
 435     DPRINTF("port92: write 0x%02x\n", val);
 436     s->outport = val;
 437     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 438     if (val & 1) {
 439         qemu_system_reset_request();
 440     }
 441 }
 442
 443 static uint32_t port92_read(void *opaque, uint32_t addr)
 444 {
 445     Port92State *s = opaque;
 446     uint32_t ret;
 447
 448     ret = s->outport;
 449     DPRINTF("port92: read 0x%02x\n", ret);
 450     return ret;
 451 }
 452
 453 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 454 {
 455     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 456
 457     s->a20_out = a20_out;
 458 }
 459
 460 static const VMStateDescription vmstate_port92_isa = {
 461     .name = "port92",
 462     .version_id = 1,
 463     .minimum_version_id = 1,
 464     .minimum_version_id_old = 1,
 465     .fields      = (VMStateField []) {
 466         VMSTATE_UINT8(outport, Port92State),
 467         VMSTATE_END_OF_LIST()
 468     }
 469 };
 470
 471 static void port92_reset(DeviceState *d)
 472 {
 473     Port92State *s = container_of(d, Port92State, dev.qdev);
 474
 475     s->outport &= ~1;
 476 }
 477
 478 static const MemoryRegionPortio port92_portio[] = {
 479     { 0, 1, 1, .read = port92_read, .write = port92_write },
 480     PORTIO_END_OF_LIST(),
 481 };
 482
 483 static const MemoryRegionOps port92_ops = {
 484     .old_portio = port92_portio
 485 };
 486
 487 static int port92_initfn(ISADevice *dev)
 488 {
 489     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 490
 491     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 492     isa_register_ioport(dev, &s->io, 0x92);
 493
 494     s->outport = 0;
 495     return 0;
 496 }
 497
 498 static void port92_class_initfn(ObjectClass *klass, void *data)
 499 {
 500     DeviceClass *dc = DEVICE_CLASS(klass);
 501     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 502     ic->init = port92_initfn;
 503     dc->no_user = 1;
 504     dc->reset = port92_reset;
 505     dc->vmsd = &vmstate_port92_isa;
 506 }
 507
 508 static TypeInfo port92_info = {
 509     .name          = "port92",
 510     .parent        = TYPE_ISA_DEVICE,
 511     .instance_size = sizeof(Port92State),
 512     .class_init    = port92_class_initfn,
 513 };
 514
 515 static void port92_register_types(void)
 516 {
 517     type_register_static(&port92_info);
 518 }
 519
 520 type_init(port92_register_types)
 521
 522 static void handle_a20_line_change(void *opaque, int irq, int level)
 523 {
 524     CPUState *cpu = opaque;
 525
 526     /* XXX: send to all CPUs ? */
 527     /* XXX: add logic to handle multiple A20 line sources */
 528     cpu_x86_set_a20(cpu, level);
 529 }
 530
 531 /***********************************************************/
 532 /* Bochs BIOS debug ports */
 533
 534 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 535 {
 536     static const char shutdown_str[8] = "Shutdown";
 537     static int shutdown_index = 0;
 538
 539     switch(addr) {
 540         /* Bochs BIOS messages */
 541     case 0x400:
 542     case 0x401:
 543         /* used to be panic, now unused */
 544         break;
 545     case 0x402:
 546     case 0x403:
 547 #ifdef DEBUG_BIOS
 548         fprintf(stderr, "%c", val);
 549 #endif
 550         break;
 551     case 0x8900:
 552         /* same as Bochs power off */
 553         if (val == shutdown_str[shutdown_index]) {
 554             shutdown_index++;
 555             if (shutdown_index == 8) {
 556                 shutdown_index = 0;
 557                 qemu_system_shutdown_request();
 558             }
 559         } else {
 560             shutdown_index = 0;
 561         }
 562         break;
 563
 564         /* LGPL'ed VGA BIOS messages */
 565     case 0x501:
 566     case 0x502:
 567         exit((val << 1) | 1);
 568     case 0x500:
 569     case 0x503:
 570 #ifdef DEBUG_BIOS
 571         fprintf(stderr, "%c", val);
 572 #endif
 573         break;
 574     }
 575 }
 576
 577 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 578 {
 579     int index = le32_to_cpu(e820_table.count);
 580     struct e820_entry *entry;
 581
 582     if (index >= E820_NR_ENTRIES)
 583         return -EBUSY;
 584     entry = &e820_table.entry[index++];
 585
 586     entry->address = cpu_to_le64(address);
 587     entry->length = cpu_to_le64(length);
 588     entry->type = cpu_to_le32(type);
 589
 590     e820_table.count = cpu_to_le32(index);
 591     return index;
 592 }
 593
 594 static void *bochs_bios_init(void)
 595 {
 596     void *fw_cfg;
 597     uint8_t *smbios_table;
 598     size_t smbios_len;
 599     uint64_t *numa_fw_cfg;
 600     int i, j;
 601
 602     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 603     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 604     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 605     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 606     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 607
 608     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 609     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 610     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 611     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 612     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 613
 614     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 615
 616     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 617     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 618     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 619                      acpi_tables_len);
 620     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 621
 622     smbios_table = smbios_get_table(&smbios_len);
 623     if (smbios_table)
 624         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 625                          smbios_table, smbios_len);
 626     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 627                      sizeof(struct e820_table));
 628
 629     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 630                      sizeof(struct hpet_fw_config));
 631     /* allocate memory for the NUMA channel: one (64bit) word for the number
 632      * of nodes, one word for each VCPU->node and one word for each node to
 633      * hold the amount of memory.
 634      */
 635     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 636     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 637     for (i = 0; i < max_cpus; i++) {
 638         for (j = 0; j < nb_numa_nodes; j++) {
 639             if (node_cpumask[j] & (1 << i)) {
 640                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 641                 break;
 642             }
 643         }
 644     }
 645     for (i = 0; i < nb_numa_nodes; i++) {
 646         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 647     }
 648     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 649                      (1 + max_cpus + nb_numa_nodes) * 8);
 650
 651     return fw_cfg;
 652 }
 653
 654 static long get_file_size(FILE *f)
 655 {
 656     long where, size;
 657
 658     /* XXX: on Unix systems, using fstat() probably makes more sense */
 659
 660     where = ftell(f);
 661     fseek(f, 0, SEEK_END);
 662     size = ftell(f);
 663     fseek(f, where, SEEK_SET);
 664
 665     return size;
 666 }
 667
 668 static void load_linux(void *fw_cfg,
 669                        const char *kernel_filename,
 670                        const char *initrd_filename,
 671                        const char *kernel_cmdline,
 672                        target_phys_addr_t max_ram_size)
 673 {
 674     uint16_t protocol;
 675     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 676     uint32_t initrd_max;
 677     uint8_t header[8192], *setup, *kernel, *initrd_data;
 678     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 679     FILE *f;
 680     char *vmode;
 681
 682     /* Align to 16 bytes as a paranoia measure */
 683     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 684
 685     /* load the kernel header */
 686     f = fopen(kernel_filename, "rb");
 687     if (!f || !(kernel_size = get_file_size(f)) ||
 688         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 689         MIN(ARRAY_SIZE(header), kernel_size)) {
 690         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 691                 kernel_filename, strerror(errno));
 692         exit(1);
 693     }
 694
 695     /* kernel protocol version */
 696 #if 0
 697     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 698 #endif
 699     if (ldl_p(header+0x202) == 0x53726448)
 700         protocol = lduw_p(header+0x206);
 701     else {
 702         /* This looks like a multiboot kernel. If it is, let's stop
 703            treating it like a Linux kernel. */
 704         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 705                            kernel_cmdline, kernel_size, header))
 706             return;
 707         protocol = 0;
 708     }
 709
 710     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 711         /* Low kernel */
 712         real_addr    = 0x90000;
 713         cmdline_addr = 0x9a000 - cmdline_size;
 714         prot_addr    = 0x10000;
 715     } else if (protocol < 0x202) {
 716         /* High but ancient kernel */
 717         real_addr    = 0x90000;
 718         cmdline_addr = 0x9a000 - cmdline_size;
 719         prot_addr    = 0x100000;
 720     } else {
 721         /* High and recent kernel */
 722         real_addr    = 0x10000;
 723         cmdline_addr = 0x20000;
 724         prot_addr    = 0x100000;
 725     }
 726
 727 #if 0
 728     fprintf(stderr,
 729             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 730             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 731             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 732             real_addr,
 733             cmdline_addr,
 734             prot_addr);
 735 #endif
 736
 737     /* highest address for loading the initrd */
 738     if (protocol >= 0x203)
 739         initrd_max = ldl_p(header+0x22c);
 740     else
 741         initrd_max = 0x37ffffff;
 742
 743     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 744         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 745
 746     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 747     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 748     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 749                      (uint8_t*)strdup(kernel_cmdline),
 750                      strlen(kernel_cmdline)+1);
 751
 752     if (protocol >= 0x202) {
 753         stl_p(header+0x228, cmdline_addr);
 754     } else {
 755         stw_p(header+0x20, 0xA33F);
 756         stw_p(header+0x22, cmdline_addr-real_addr);
 757     }
 758
 759     /* handle vga= parameter */
 760     vmode = strstr(kernel_cmdline, "vga=");
 761     if (vmode) {
 762         unsigned int video_mode;
 763         /* skip "vga=" */
 764         vmode += 4;
 765         if (!strncmp(vmode, "normal", 6)) {
 766             video_mode = 0xffff;
 767         } else if (!strncmp(vmode, "ext", 3)) {
 768             video_mode = 0xfffe;
 769         } else if (!strncmp(vmode, "ask", 3)) {
 770             video_mode = 0xfffd;
 771         } else {
 772             video_mode = strtol(vmode, NULL, 0);
 773         }
 774         stw_p(header+0x1fa, video_mode);
 775     }
 776
 777     /* loader type */
 778     /* High nybble = B reserved for Qemu; low nybble is revision number.
 779        If this code is substantially changed, you may want to consider
 780        incrementing the revision. */
 781     if (protocol >= 0x200)
 782         header[0x210] = 0xB0;
 783
 784     /* heap */
 785     if (protocol >= 0x201) {
 786         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 787         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 788     }
 789
 790     /* load initrd */
 791     if (initrd_filename) {
 792         if (protocol < 0x200) {
 793             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 794             exit(1);
 795         }
 796
 797         initrd_size = get_image_size(initrd_filename);
 798         if (initrd_size < 0) {
 799             fprintf(stderr, "qemu: error reading initrd %s\n",
 800                     initrd_filename);
 801             exit(1);
 802         }
 803
 804         initrd_addr = (initrd_max-initrd_size) & ~4095;
 805
 806         initrd_data = g_malloc(initrd_size);
 807         load_image(initrd_filename, initrd_data);
 808
 809         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 810         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 811         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 812
 813         stl_p(header+0x218, initrd_addr);
 814         stl_p(header+0x21c, initrd_size);
 815     }
 816
 817     /* load kernel and setup */
 818     setup_size = header[0x1f1];
 819     if (setup_size == 0)
 820         setup_size = 4;
 821     setup_size = (setup_size+1)*512;
 822     kernel_size -= setup_size;
 823
 824     setup  = g_malloc(setup_size);
 825     kernel = g_malloc(kernel_size);
 826     fseek(f, 0, SEEK_SET);
 827     if (fread(setup, 1, setup_size, f) != setup_size) {
 828         fprintf(stderr, "fread() failed\n");
 829         exit(1);
 830     }
 831     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 832         fprintf(stderr, "fread() failed\n");
 833         exit(1);
 834     }
 835     fclose(f);
 836     memcpy(setup, header, MIN(sizeof(header), setup_size));
 837
 838     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 839     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 840     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 841
 842     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 843     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 844     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 845
 846     option_rom[nb_option_roms].name = "linuxboot.bin";
 847     option_rom[nb_option_roms].bootindex = 0;
 848     nb_option_roms++;
 849 }
 850
 851 #define NE2000_NB_MAX 6
 852
 853 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 854                                               0x280, 0x380 };
 855 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 856
 857 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 858 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 859
 860 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 861 {
 862     static int nb_ne2k = 0;
 863
 864     if (nb_ne2k == NE2000_NB_MAX)
 865         return;
 866     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 867                     ne2000_irq[nb_ne2k], nd);
 868     nb_ne2k++;
 869 }
 870
 871 int cpu_is_bsp(CPUState *env)
 872 {
 873     /* We hard-wire the BSP to the first CPU. */
 874     return env->cpu_index == 0;
 875 }
 876
 877 DeviceState *cpu_get_current_apic(void)
 878 {
 879     if (cpu_single_env) {
 880         return cpu_single_env->apic_state;
 881     } else {
 882         return NULL;
 883     }
 884 }
 885
 886 static DeviceState *apic_init(void *env, uint8_t apic_id)
 887 {
 888     DeviceState *dev;
 889     static int apic_mapped;
 890
 891     if (kvm_irqchip_in_kernel()) {
 892         dev = qdev_create(NULL, "kvm-apic");
 893     } else {
 894         dev = qdev_create(NULL, "apic");
 895     }
 896     qdev_prop_set_uint8(dev, "id", apic_id);
 897     qdev_prop_set_ptr(dev, "cpu_env", env);
 898     qdev_init_nofail(dev);
 899
 900     /* XXX: mapping more APICs at the same memory location */
 901     if (apic_mapped == 0) {
 902         /* NOTE: the APIC is directly connected to the CPU - it is not
 903            on the global memory bus. */
 904         /* XXX: what if the base changes? */
 905         sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
 906         apic_mapped = 1;
 907     }
 908
 909     /* KVM does not support MSI yet. */
 910     if (!kvm_irqchip_in_kernel()) {
 911         msi_supported = true;
 912     }
 913
 914     return dev;
 915 }
 916
 917 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 918 {
 919     CPUState *s = opaque;
 920
 921     if (level) {
 922         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 923     }
 924 }
 925
 926 static void pc_cpu_reset(void *opaque)
 927 {
 928     CPUState *env = opaque;
 929
 930     cpu_reset(env);
 931     env->halted = !cpu_is_bsp(env);
 932 }
 933
 934 static CPUState *pc_new_cpu(const char *cpu_model)
 935 {
 936     CPUState *env;
 937
 938     env = cpu_init(cpu_model);
 939     if (!env) {
 940         fprintf(stderr, "Unable to find x86 CPU definition\n");
 941         exit(1);
 942     }
 943     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 944         env->apic_state = apic_init(env, env->cpuid_apic_id);
 945     }
 946     qemu_register_reset(pc_cpu_reset, env);
 947     pc_cpu_reset(env);
 948     return env;
 949 }
 950
 951 void pc_cpus_init(const char *cpu_model)
 952 {
 953     int i;
 954
 955     /* init CPUs */
 956     if (cpu_model == NULL) {
 957 #ifdef TARGET_X86_64
 958         cpu_model = "qemu64";
 959 #else
 960         cpu_model = "qemu32";
 961 #endif
 962     }
 963
 964     for(i = 0; i < smp_cpus; i++) {
 965         pc_new_cpu(cpu_model);
 966     }
 967 }
 968
 969 void pc_memory_init(MemoryRegion *system_memory,
 970                     const char *kernel_filename,
 971                     const char *kernel_cmdline,
 972                     const char *initrd_filename,
 973                     ram_addr_t below_4g_mem_size,
 974                     ram_addr_t above_4g_mem_size,
 975                     MemoryRegion *rom_memory,
 976                     MemoryRegion **ram_memory)
 977 {
 978     int linux_boot, i;
 979     MemoryRegion *ram, *option_rom_mr;
 980     MemoryRegion *ram_below_4g, *ram_above_4g;
 981     void *fw_cfg;
 982
 983     linux_boot = (kernel_filename != NULL);
 984
 985     /* Allocate RAM.  We allocate it as a single memory region and use
 986      * aliases to address portions of it, mostly for backwards compatibility
 987      * with older qemus that used qemu_ram_alloc().
 988      */
 989     ram = g_malloc(sizeof(*ram));
 990     memory_region_init_ram(ram, "pc.ram",
 991                            below_4g_mem_size + above_4g_mem_size);
 992     vmstate_register_ram_global(ram);
 993     *ram_memory = ram;
 994     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 995     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 996                              0, below_4g_mem_size);
 997     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 998     if (above_4g_mem_size > 0) {
 999         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1000         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1001                                  below_4g_mem_size, above_4g_mem_size);
1002         memory_region_add_subregion(system_memory, 0x100000000ULL,
1003                                     ram_above_4g);
1004     }
1005
1006
1007     /* Initialize PC system firmware */
1008     pc_system_firmware_init(rom_memory);
1009
1010     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1011     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
1012     vmstate_register_ram_global(option_rom_mr);
1013     memory_region_add_subregion_overlap(rom_memory,
1014                                         PC_ROM_MIN_VGA,
1015                                         option_rom_mr,
1016                                         1);
1017
1018     fw_cfg = bochs_bios_init();
1019     rom_set_fw(fw_cfg);
1020
1021     if (linux_boot) {
1022         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1023     }
1024
1025     for (i = 0; i < nb_option_roms; i++) {
1026         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1027     }
1028 }
1029
1030 qemu_irq *pc_allocate_cpu_irq(void)
1031 {
1032     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1033 }
1034
1035 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1036 {
1037     DeviceState *dev = NULL;
1038
1039     if (cirrus_vga_enabled) {
1040         if (pci_bus) {
1041             dev = pci_cirrus_vga_init(pci_bus);
1042         } else {
1043             dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
1044         }
1045     } else if (vmsvga_enabled) {
1046         if (pci_bus) {
1047             dev = pci_vmsvga_init(pci_bus);
1048         } else {
1049             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1050         }
1051 #ifdef CONFIG_SPICE
1052     } else if (qxl_enabled) {
1053         if (pci_bus) {
1054             dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
1055         } else {
1056             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1057         }
1058 #endif
1059     } else if (std_vga_enabled) {
1060         if (pci_bus) {
1061             dev = pci_vga_init(pci_bus);
1062         } else {
1063             dev = isa_vga_init(isa_bus);
1064         }
1065     }
1066
1067     return dev;
1068 }
1069
1070 static void cpu_request_exit(void *opaque, int irq, int level)
1071 {
1072     CPUState *env = cpu_single_env;
1073
1074     if (env && level) {
1075         cpu_exit(env);
1076     }
1077 }
1078
1079 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1080                           ISADevice **rtc_state,
1081                           ISADevice **floppy,
1082                           bool no_vmport)
1083 {
1084     int i;
1085     DriveInfo *fd[MAX_FD];
1086     DeviceState *hpet = NULL;
1087     int pit_isa_irq = 0;
1088     qemu_irq pit_alt_irq = NULL;
1089     qemu_irq rtc_irq = NULL;
1090     qemu_irq *a20_line;
1091     ISADevice *i8042, *port92, *vmmouse, *pit;
1092     qemu_irq *cpu_exit_irq;
1093
1094     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1095
1096     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1097
1098     if (!no_hpet) {
1099         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1100
1101         if (hpet) {
1102             for (i = 0; i < GSI_NUM_PINS; i++) {
1103                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1104             }
1105             pit_isa_irq = -1;
1106             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1107             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1108         }
1109     }
1110     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1111
1112     qemu_register_boot_set(pc_boot_set, *rtc_state);
1113
1114     pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1115     if (hpet) {
1116         /* connect PIT to output control line of the HPET */
1117         qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1118     }
1119     pcspk_init(isa_bus, pit);
1120
1121     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1122         if (serial_hds[i]) {
1123             serial_isa_init(isa_bus, i, serial_hds[i]);
1124         }
1125     }
1126
1127     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1128         if (parallel_hds[i]) {
1129             parallel_init(isa_bus, i, parallel_hds[i]);
1130         }
1131     }
1132
1133     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1134     i8042 = isa_create_simple(isa_bus, "i8042");
1135     i8042_setup_a20_line(i8042, &a20_line[0]);
1136     if (!no_vmport) {
1137         vmport_init(isa_bus);
1138         vmmouse = isa_try_create(isa_bus, "vmmouse");
1139     } else {
1140         vmmouse = NULL;
1141     }
1142     if (vmmouse) {
1143         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1144         qdev_init_nofail(&vmmouse->qdev);
1145     }
1146     port92 = isa_create_simple(isa_bus, "port92");
1147     port92_init(port92, &a20_line[1]);
1148
1149     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1150     DMA_init(0, cpu_exit_irq);
1151
1152     for(i = 0; i < MAX_FD; i++) {
1153         fd[i] = drive_get(IF_FLOPPY, 0, i);
1154     }
1155     *floppy = fdctrl_init_isa(isa_bus, fd);
1156 }
1157
1158 void pc_pci_device_init(PCIBus *pci_bus)
1159 {
1160     int max_bus;
1161     int bus;
1162
1163     max_bus = drive_get_max_bus(IF_SCSI);
1164     for (bus = 0; bus <= max_bus; bus++) {
1165         pci_create_simple(pci_bus, -1, "lsi53c895a");
1166     }
1167 }