include/hw/scsi/esp.h

   1 #ifndef QEMU_HW_ESP_H
   2 #define QEMU_HW_ESP_H
   3
   4 #include "hw/scsi/scsi.h"
   5
   6 /* esp.c */
   7 #define ESP_MAX_DEVS 7
   8 typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
   9 void esp_init(hwaddr espaddr, int it_shift,
  10               ESPDMAMemoryReadWriteFunc dma_memory_read,
  11               ESPDMAMemoryReadWriteFunc dma_memory_write,
  12               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
  13               qemu_irq *dma_enable);
  14
  15 #define ESP_REGS 16
  16 #define TI_BUFSZ 16
  17
  18 typedef struct ESPState ESPState;
  19
  20 struct ESPState {
  21     uint8_t rregs[ESP_REGS];
  22     uint8_t wregs[ESP_REGS];
  23     qemu_irq irq;
  24     uint8_t chip_id;
  25     bool tchi_written;
  26     int32_t ti_size;
  27     uint32_t ti_rptr, ti_wptr;
  28     uint32_t status;
  29     uint32_t dma;
  30     uint8_t ti_buf[TI_BUFSZ];
  31     SCSIBus bus;
  32     SCSIDevice *current_dev;
  33     SCSIRequest *current_req;
  34     uint8_t cmdbuf[TI_BUFSZ];
  35     uint32_t cmdlen;
  36     uint32_t do_cmd;
  37
  38     /* The amount of data left in the current DMA transfer.  */
  39     uint32_t dma_left;
  40     /* The size of the current DMA transfer.  Zero if no transfer is in
  41        progress.  */
  42     uint32_t dma_counter;
  43     int dma_enabled;
  44
  45     uint32_t async_len;
  46     uint8_t *async_buf;
  47
  48     ESPDMAMemoryReadWriteFunc dma_memory_read;
  49     ESPDMAMemoryReadWriteFunc dma_memory_write;
  50     void *dma_opaque;
  51     void (*dma_cb)(ESPState *s);
  52 };
  53
  54 #define ESP_TCLO   0x0
  55 #define ESP_TCMID  0x1
  56 #define ESP_FIFO   0x2
  57 #define ESP_CMD    0x3
  58 #define ESP_RSTAT  0x4
  59 #define ESP_WBUSID 0x4
  60 #define ESP_RINTR  0x5
  61 #define ESP_WSEL   0x5
  62 #define ESP_RSEQ   0x6
  63 #define ESP_WSYNTP 0x6
  64 #define ESP_RFLAGS 0x7
  65 #define ESP_WSYNO  0x7
  66 #define ESP_CFG1   0x8
  67 #define ESP_RRES1  0x9
  68 #define ESP_WCCF   0x9
  69 #define ESP_RRES2  0xa
  70 #define ESP_WTEST  0xa
  71 #define ESP_CFG2   0xb
  72 #define ESP_CFG3   0xc
  73 #define ESP_RES3   0xd
  74 #define ESP_TCHI   0xe
  75 #define ESP_RES4   0xf
  76
  77 #define CMD_DMA 0x80
  78 #define CMD_CMD 0x7f
  79
  80 #define CMD_NOP      0x00
  81 #define CMD_FLUSH    0x01
  82 #define CMD_RESET    0x02
  83 #define CMD_BUSRESET 0x03
  84 #define CMD_TI       0x10
  85 #define CMD_ICCS     0x11
  86 #define CMD_MSGACC   0x12
  87 #define CMD_PAD      0x18
  88 #define CMD_SATN     0x1a
  89 #define CMD_RSTATN   0x1b
  90 #define CMD_SEL      0x41
  91 #define CMD_SELATN   0x42
  92 #define CMD_SELATNS  0x43
  93 #define CMD_ENSEL    0x44
  94 #define CMD_DISSEL   0x45
  95
  96 #define STAT_DO 0x00
  97 #define STAT_DI 0x01
  98 #define STAT_CD 0x02
  99 #define STAT_ST 0x03
 100 #define STAT_MO 0x06
 101 #define STAT_MI 0x07
 102 #define STAT_PIO_MASK 0x06
 103
 104 #define STAT_TC 0x10
 105 #define STAT_PE 0x20
 106 #define STAT_GE 0x40
 107 #define STAT_INT 0x80
 108
 109 #define BUSID_DID 0x07
 110
 111 #define INTR_FC 0x08
 112 #define INTR_BS 0x10
 113 #define INTR_DC 0x20
 114 #define INTR_RST 0x80
 115
 116 #define SEQ_0 0x0
 117 #define SEQ_CD 0x4
 118
 119 #define CFG1_RESREPT 0x40
 120
 121 #define TCHI_FAS100A 0x4
 122 #define TCHI_AM53C974 0x12
 123
 124 void esp_dma_enable(ESPState *s, int irq, int level);
 125 void esp_request_cancelled(SCSIRequest *req);
 126 void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
 127 void esp_transfer_data(SCSIRequest *req, uint32_t len);
 128 void esp_hard_reset(ESPState *s);
 129 uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
 130 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
 131 extern const VMStateDescription vmstate_esp;
 132
 133 #endif