target/s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  * For details on the s390x architecture and used definitions (e.g.,
   5  * PSW, PER and DAT (Dynamic Address Translation)), please refer to
   6  * the "z/Architecture Principles of Operations" - a.k.a. PoP.
   7  *
   8  *  Copyright (c) 2009 Ulrich Hecht
   9  *  Copyright IBM Corp. 2012, 2018
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #ifndef S390X_CPU_H
  26 #define S390X_CPU_H
  27
  28 #include "cpu-qom.h"
  29 #include "cpu_models.h"
  30 #include "exec/cpu-defs.h"
  31 #include "qemu/cpu-float.h"
  32
  33 #define ELF_MACHINE_UNAME "S390X"
  34
  35 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */
  36 #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
  37
  38 #define TARGET_INSN_START_EXTRA_WORDS 2
  39
  40 #define MMU_USER_IDX 0
  41
  42 #define S390_MAX_CPUS 248
  43
  44 #ifndef CONFIG_KVM
  45 #define S390_ADAPTER_SUPPRESSIBLE 0x01
  46 #else
  47 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
  48 #endif
  49
  50 typedef struct PSW {
  51     uint64_t mask;
  52     uint64_t addr;
  53 } PSW;
  54
  55 struct CPUArchState {
  56     uint64_t regs[16];     /* GP registers */
  57     /*
  58      * The floating point registers are part of the vector registers.
  59      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  60      */
  61     uint64_t vregs[32][2] QEMU_ALIGNED(16);  /* vector registers */
  62     uint32_t aregs[16];    /* access registers */
  63     uint64_t gscb[4];      /* guarded storage control */
  64     uint64_t etoken;       /* etoken */
  65     uint64_t etoken_extension; /* etoken extension */
  66
  67     uint64_t diag318_info;
  68
  69     /* Fields up to this point are not cleared by initial CPU reset */
  70     struct {} start_initial_reset_fields;
  71
  72     uint32_t fpc;          /* floating-point control register */
  73     uint32_t cc_op;
  74     bool bpbc;             /* branch prediction blocking */
  75
  76     float_status fpu_status; /* passed to softfloat lib */
  77
  78     /* The low part of a 128-bit return, or remainder of a divide.  */
  79     uint64_t retxl;
  80
  81     PSW psw;
  82
  83     S390CrashReason crash_reason;
  84
  85     uint64_t cc_src;
  86     uint64_t cc_dst;
  87     uint64_t cc_vr;
  88
  89     uint64_t ex_value;
  90
  91     uint64_t __excp_addr;
  92     uint64_t psa;
  93
  94     uint32_t int_pgm_code;
  95     uint32_t int_pgm_ilen;
  96
  97     uint32_t int_svc_code;
  98     uint32_t int_svc_ilen;
  99
 100     uint64_t per_address;
 101     uint16_t per_perc_atmid;
 102
 103     uint64_t cregs[16]; /* control registers */
 104
 105     uint64_t ckc;
 106     uint64_t cputm;
 107     uint32_t todpr;
 108
 109     uint64_t pfault_token;
 110     uint64_t pfault_compare;
 111     uint64_t pfault_select;
 112
 113     uint64_t gbea;
 114     uint64_t pp;
 115
 116     /* Fields up to this point are not cleared by normal CPU reset */
 117     struct {} start_normal_reset_fields;
 118     uint8_t riccb[64];     /* runtime instrumentation control */
 119
 120     int pending_int;
 121     uint16_t external_call_addr;
 122     DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
 123
 124 #if !defined(CONFIG_USER_ONLY)
 125     uint64_t tlb_fill_tec;   /* translation exception code during tlb_fill */
 126     int tlb_fill_exc;        /* exception number seen during tlb_fill */
 127 #endif
 128
 129     /* Fields up to this point are cleared by a CPU reset */
 130     struct {} end_reset_fields;
 131
 132 #if !defined(CONFIG_USER_ONLY)
 133     uint32_t core_id; /* PoP "CPU address", same as cpu_index */
 134     uint64_t cpuid;
 135 #endif
 136
 137     QEMUTimer *tod_timer;
 138
 139     QEMUTimer *cpu_timer;
 140
 141     /*
 142      * The cpu state represents the logical state of a cpu. In contrast to other
 143      * architectures, there is a difference between a halt and a stop on s390.
 144      * If all cpus are either stopped (including check stop) or in the disabled
 145      * wait state, the vm can be shut down.
 146      * The acceptable cpu_state values are defined in the CpuInfoS390State
 147      * enum.
 148      */
 149     uint8_t cpu_state;
 150
 151     /* currently processed sigp order */
 152     uint8_t sigp_order;
 153
 154 };
 155
 156 static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
 157 {
 158     return &cs->vregs[nr][0];
 159 }
 160
 161 /**
 162  * S390CPU:
 163  * @env: #CPUS390XState.
 164  *
 165  * An S/390 CPU.
 166  */
 167 struct ArchCPU {
 168     /*< private >*/
 169     CPUState parent_obj;
 170     /*< public >*/
 171
 172     CPUNegativeOffsetState neg;
 173     CPUS390XState env;
 174     S390CPUModel *model;
 175     /* needed for live migration */
 176     void *irqstate;
 177     uint32_t irqstate_saved_size;
 178 };
 179
 180
 181 #ifndef CONFIG_USER_ONLY
 182 extern const VMStateDescription vmstate_s390_cpu;
 183 #endif
 184
 185 /* distinguish between 24 bit and 31 bit addressing */
 186 #define HIGH_ORDER_BIT 0x80000000
 187
 188 /* Interrupt Codes */
 189 /* Program Interrupts */
 190 #define PGM_OPERATION                   0x0001
 191 #define PGM_PRIVILEGED                  0x0002
 192 #define PGM_EXECUTE                     0x0003
 193 #define PGM_PROTECTION                  0x0004
 194 #define PGM_ADDRESSING                  0x0005
 195 #define PGM_SPECIFICATION               0x0006
 196 #define PGM_DATA                        0x0007
 197 #define PGM_FIXPT_OVERFLOW              0x0008
 198 #define PGM_FIXPT_DIVIDE                0x0009
 199 #define PGM_DEC_OVERFLOW                0x000a
 200 #define PGM_DEC_DIVIDE                  0x000b
 201 #define PGM_HFP_EXP_OVERFLOW            0x000c
 202 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 203 #define PGM_HFP_SIGNIFICANCE            0x000e
 204 #define PGM_HFP_DIVIDE                  0x000f
 205 #define PGM_SEGMENT_TRANS               0x0010
 206 #define PGM_PAGE_TRANS                  0x0011
 207 #define PGM_TRANS_SPEC                  0x0012
 208 #define PGM_SPECIAL_OP                  0x0013
 209 #define PGM_OPERAND                     0x0015
 210 #define PGM_TRACE_TABLE                 0x0016
 211 #define PGM_VECTOR_PROCESSING           0x001b
 212 #define PGM_SPACE_SWITCH                0x001c
 213 #define PGM_HFP_SQRT                    0x001d
 214 #define PGM_PC_TRANS_SPEC               0x001f
 215 #define PGM_AFX_TRANS                   0x0020
 216 #define PGM_ASX_TRANS                   0x0021
 217 #define PGM_LX_TRANS                    0x0022
 218 #define PGM_EX_TRANS                    0x0023
 219 #define PGM_PRIM_AUTH                   0x0024
 220 #define PGM_SEC_AUTH                    0x0025
 221 #define PGM_ALET_SPEC                   0x0028
 222 #define PGM_ALEN_SPEC                   0x0029
 223 #define PGM_ALE_SEQ                     0x002a
 224 #define PGM_ASTE_VALID                  0x002b
 225 #define PGM_ASTE_SEQ                    0x002c
 226 #define PGM_EXT_AUTH                    0x002d
 227 #define PGM_STACK_FULL                  0x0030
 228 #define PGM_STACK_EMPTY                 0x0031
 229 #define PGM_STACK_SPEC                  0x0032
 230 #define PGM_STACK_TYPE                  0x0033
 231 #define PGM_STACK_OP                    0x0034
 232 #define PGM_ASCE_TYPE                   0x0038
 233 #define PGM_REG_FIRST_TRANS             0x0039
 234 #define PGM_REG_SEC_TRANS               0x003a
 235 #define PGM_REG_THIRD_TRANS             0x003b
 236 #define PGM_MONITOR                     0x0040
 237 #define PGM_PER                         0x0080
 238 #define PGM_CRYPTO                      0x0119
 239
 240 /* External Interrupts */
 241 #define EXT_INTERRUPT_KEY               0x0040
 242 #define EXT_CLOCK_COMP                  0x1004
 243 #define EXT_CPU_TIMER                   0x1005
 244 #define EXT_MALFUNCTION                 0x1200
 245 #define EXT_EMERGENCY                   0x1201
 246 #define EXT_EXTERNAL_CALL               0x1202
 247 #define EXT_ETR                         0x1406
 248 #define EXT_SERVICE                     0x2401
 249 #define EXT_VIRTIO                      0x2603
 250
 251 /* PSW defines */
 252 #undef PSW_MASK_PER
 253 #undef PSW_MASK_UNUSED_2
 254 #undef PSW_MASK_UNUSED_3
 255 #undef PSW_MASK_DAT
 256 #undef PSW_MASK_IO
 257 #undef PSW_MASK_EXT
 258 #undef PSW_MASK_KEY
 259 #undef PSW_SHIFT_KEY
 260 #undef PSW_MASK_MCHECK
 261 #undef PSW_MASK_WAIT
 262 #undef PSW_MASK_PSTATE
 263 #undef PSW_MASK_ASC
 264 #undef PSW_SHIFT_ASC
 265 #undef PSW_MASK_CC
 266 #undef PSW_MASK_PM
 267 #undef PSW_MASK_RI
 268 #undef PSW_SHIFT_MASK_PM
 269 #undef PSW_MASK_64
 270 #undef PSW_MASK_32
 271 #undef PSW_MASK_ESA_ADDR
 272
 273 #define PSW_MASK_PER            0x4000000000000000ULL
 274 #define PSW_MASK_UNUSED_2       0x2000000000000000ULL
 275 #define PSW_MASK_UNUSED_3       0x1000000000000000ULL
 276 #define PSW_MASK_DAT            0x0400000000000000ULL
 277 #define PSW_MASK_IO             0x0200000000000000ULL
 278 #define PSW_MASK_EXT            0x0100000000000000ULL
 279 #define PSW_MASK_KEY            0x00F0000000000000ULL
 280 #define PSW_SHIFT_KEY           52
 281 #define PSW_MASK_SHORTPSW       0x0008000000000000ULL
 282 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 283 #define PSW_MASK_WAIT           0x0002000000000000ULL
 284 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 285 #define PSW_MASK_ASC            0x0000C00000000000ULL
 286 #define PSW_SHIFT_ASC           46
 287 #define PSW_MASK_CC             0x0000300000000000ULL
 288 #define PSW_MASK_PM             0x00000F0000000000ULL
 289 #define PSW_SHIFT_MASK_PM       40
 290 #define PSW_MASK_RI             0x0000008000000000ULL
 291 #define PSW_MASK_64             0x0000000100000000ULL
 292 #define PSW_MASK_32             0x0000000080000000ULL
 293 #define PSW_MASK_SHORT_ADDR     0x000000007fffffffULL
 294 #define PSW_MASK_SHORT_CTRL     0xffffffff80000000ULL
 295
 296 #undef PSW_ASC_PRIMARY
 297 #undef PSW_ASC_ACCREG
 298 #undef PSW_ASC_SECONDARY
 299 #undef PSW_ASC_HOME
 300
 301 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 302 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 303 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 304 #define PSW_ASC_HOME            0x0000C00000000000ULL
 305
 306 /* the address space values shifted */
 307 #define AS_PRIMARY              0
 308 #define AS_ACCREG               1
 309 #define AS_SECONDARY            2
 310 #define AS_HOME                 3
 311
 312 /* tb flags */
 313
 314 #define FLAG_MASK_PSW_SHIFT     31
 315 #define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 316 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> FLAG_MASK_PSW_SHIFT)
 317 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 318 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 319 #define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 320 #define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 321 #define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
 322                                 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 323
 324 /* we'll use some unused PSW positions to store CR flags in tb flags */
 325 #define FLAG_MASK_AFP           (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
 326 #define FLAG_MASK_VECTOR        (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
 327
 328 /* Control register 0 bits */
 329 #define CR0_LOWPROT             0x0000000010000000ULL
 330 #define CR0_SECONDARY           0x0000000004000000ULL
 331 #define CR0_EDAT                0x0000000000800000ULL
 332 #define CR0_AFP                 0x0000000000040000ULL
 333 #define CR0_VECTOR              0x0000000000020000ULL
 334 #define CR0_IEP                 0x0000000000100000ULL
 335 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
 336 #define CR0_EXTERNAL_CALL_SC    0x0000000000002000ULL
 337 #define CR0_CKC_SC              0x0000000000000800ULL
 338 #define CR0_CPU_TIMER_SC        0x0000000000000400ULL
 339 #define CR0_SERVICE_SC          0x0000000000000200ULL
 340
 341 /* Control register 14 bits */
 342 #define CR14_CHANNEL_REPORT_SC  0x0000000010000000ULL
 343
 344 /* MMU */
 345 #define MMU_PRIMARY_IDX         0
 346 #define MMU_SECONDARY_IDX       1
 347 #define MMU_HOME_IDX            2
 348 #define MMU_REAL_IDX            3
 349
 350 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 351 {
 352 #ifdef CONFIG_USER_ONLY
 353     return MMU_USER_IDX;
 354 #else
 355     if (!(env->psw.mask & PSW_MASK_DAT)) {
 356         return MMU_REAL_IDX;
 357     }
 358
 359     if (ifetch) {
 360         if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
 361             return MMU_HOME_IDX;
 362         }
 363         return MMU_PRIMARY_IDX;
 364     }
 365
 366     switch (env->psw.mask & PSW_MASK_ASC) {
 367     case PSW_ASC_PRIMARY:
 368         return MMU_PRIMARY_IDX;
 369     case PSW_ASC_SECONDARY:
 370         return MMU_SECONDARY_IDX;
 371     case PSW_ASC_HOME:
 372         return MMU_HOME_IDX;
 373     case PSW_ASC_ACCREG:
 374         /* Fallthrough: access register mode is not yet supported */
 375     default:
 376         abort();
 377     }
 378 #endif
 379 }
 380
 381 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 382                                         target_ulong *cs_base, uint32_t *flags)
 383 {
 384     *pc = env->psw.addr;
 385     *cs_base = env->ex_value;
 386     *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 387     if (env->cregs[0] & CR0_AFP) {
 388         *flags |= FLAG_MASK_AFP;
 389     }
 390     if (env->cregs[0] & CR0_VECTOR) {
 391         *flags |= FLAG_MASK_VECTOR;
 392     }
 393 }
 394
 395 /* PER bits from control register 9 */
 396 #define PER_CR9_EVENT_BRANCH           0x80000000
 397 #define PER_CR9_EVENT_IFETCH           0x40000000
 398 #define PER_CR9_EVENT_STORE            0x20000000
 399 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 400 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 401 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 402 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 403
 404 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 405 #define PER_CODE_EVENT_BRANCH          0x8000
 406 #define PER_CODE_EVENT_IFETCH          0x4000
 407 #define PER_CODE_EVENT_STORE           0x2000
 408 #define PER_CODE_EVENT_STORE_REAL      0x0800
 409 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 410
 411 #define EXCP_EXT 1 /* external interrupt */
 412 #define EXCP_SVC 2 /* supervisor call (syscall) */
 413 #define EXCP_PGM 3 /* program interruption */
 414 #define EXCP_RESTART 4 /* restart interrupt */
 415 #define EXCP_STOP 5 /* stop interrupt */
 416 #define EXCP_IO  7 /* I/O interrupt */
 417 #define EXCP_MCHK 8 /* machine check */
 418
 419 #define INTERRUPT_EXT_CPU_TIMER          (1 << 3)
 420 #define INTERRUPT_EXT_CLOCK_COMPARATOR   (1 << 4)
 421 #define INTERRUPT_EXTERNAL_CALL          (1 << 5)
 422 #define INTERRUPT_EMERGENCY_SIGNAL       (1 << 6)
 423 #define INTERRUPT_RESTART                (1 << 7)
 424 #define INTERRUPT_STOP                   (1 << 8)
 425
 426 /* Program Status Word.  */
 427 #define S390_PSWM_REGNUM 0
 428 #define S390_PSWA_REGNUM 1
 429 /* General Purpose Registers.  */
 430 #define S390_R0_REGNUM 2
 431 #define S390_R1_REGNUM 3
 432 #define S390_R2_REGNUM 4
 433 #define S390_R3_REGNUM 5
 434 #define S390_R4_REGNUM 6
 435 #define S390_R5_REGNUM 7
 436 #define S390_R6_REGNUM 8
 437 #define S390_R7_REGNUM 9
 438 #define S390_R8_REGNUM 10
 439 #define S390_R9_REGNUM 11
 440 #define S390_R10_REGNUM 12
 441 #define S390_R11_REGNUM 13
 442 #define S390_R12_REGNUM 14
 443 #define S390_R13_REGNUM 15
 444 #define S390_R14_REGNUM 16
 445 #define S390_R15_REGNUM 17
 446 /* Total Core Registers. */
 447 #define S390_NUM_CORE_REGS 18
 448
 449 static inline void setcc(S390CPU *cpu, uint64_t cc)
 450 {
 451     CPUS390XState *env = &cpu->env;
 452
 453     env->psw.mask &= ~(3ull << 44);
 454     env->psw.mask |= (cc & 3) << 44;
 455     env->cc_op = cc;
 456 }
 457
 458 /* STSI */
 459 #define STSI_R0_FC_MASK         0x00000000f0000000ULL
 460 #define STSI_R0_FC_CURRENT      0x0000000000000000ULL
 461 #define STSI_R0_FC_LEVEL_1      0x0000000010000000ULL
 462 #define STSI_R0_FC_LEVEL_2      0x0000000020000000ULL
 463 #define STSI_R0_FC_LEVEL_3      0x0000000030000000ULL
 464 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 465 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 466 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 467 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 468
 469 /* Basic Machine Configuration */
 470 typedef struct SysIB_111 {
 471     uint8_t  res1[32];
 472     uint8_t  manuf[16];
 473     uint8_t  type[4];
 474     uint8_t  res2[12];
 475     uint8_t  model[16];
 476     uint8_t  sequence[16];
 477     uint8_t  plant[4];
 478     uint8_t  res3[3996];
 479 } SysIB_111;
 480 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
 481
 482 /* Basic Machine CPU */
 483 typedef struct SysIB_121 {
 484     uint8_t  res1[80];
 485     uint8_t  sequence[16];
 486     uint8_t  plant[4];
 487     uint8_t  res2[2];
 488     uint16_t cpu_addr;
 489     uint8_t  res3[3992];
 490 } SysIB_121;
 491 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
 492
 493 /* Basic Machine CPUs */
 494 typedef struct SysIB_122 {
 495     uint8_t res1[32];
 496     uint32_t capability;
 497     uint16_t total_cpus;
 498     uint16_t conf_cpus;
 499     uint16_t standby_cpus;
 500     uint16_t reserved_cpus;
 501     uint16_t adjustments[2026];
 502 } SysIB_122;
 503 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
 504
 505 /* LPAR CPU */
 506 typedef struct SysIB_221 {
 507     uint8_t  res1[80];
 508     uint8_t  sequence[16];
 509     uint8_t  plant[4];
 510     uint16_t cpu_id;
 511     uint16_t cpu_addr;
 512     uint8_t  res3[3992];
 513 } SysIB_221;
 514 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
 515
 516 /* LPAR CPUs */
 517 typedef struct SysIB_222 {
 518     uint8_t  res1[32];
 519     uint16_t lpar_num;
 520     uint8_t  res2;
 521     uint8_t  lcpuc;
 522     uint16_t total_cpus;
 523     uint16_t conf_cpus;
 524     uint16_t standby_cpus;
 525     uint16_t reserved_cpus;
 526     uint8_t  name[8];
 527     uint32_t caf;
 528     uint8_t  res3[16];
 529     uint16_t dedicated_cpus;
 530     uint16_t shared_cpus;
 531     uint8_t  res4[4020];
 532 } SysIB_222;
 533 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
 534
 535 /* VM CPUs */
 536 typedef struct SysIB_322 {
 537     uint8_t  res1[31];
 538     uint8_t  count;
 539     struct {
 540         uint8_t  res2[4];
 541         uint16_t total_cpus;
 542         uint16_t conf_cpus;
 543         uint16_t standby_cpus;
 544         uint16_t reserved_cpus;
 545         uint8_t  name[8];
 546         uint32_t caf;
 547         uint8_t  cpi[16];
 548         uint8_t res5[3];
 549         uint8_t ext_name_encoding;
 550         uint32_t res3;
 551         uint8_t uuid[16];
 552     } vm[8];
 553     uint8_t res4[1504];
 554     uint8_t ext_names[8][256];
 555 } SysIB_322;
 556 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
 557
 558 typedef union SysIB {
 559     SysIB_111 sysib_111;
 560     SysIB_121 sysib_121;
 561     SysIB_122 sysib_122;
 562     SysIB_221 sysib_221;
 563     SysIB_222 sysib_222;
 564     SysIB_322 sysib_322;
 565 } SysIB;
 566 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
 567
 568 /* MMU defines */
 569 #define ASCE_ORIGIN           (~0xfffULL) /* segment table origin             */
 570 #define ASCE_SUBSPACE         0x200       /* subspace group control           */
 571 #define ASCE_PRIVATE_SPACE    0x100       /* private space control            */
 572 #define ASCE_ALT_EVENT        0x80        /* storage alteration event control */
 573 #define ASCE_SPACE_SWITCH     0x40        /* space switch event               */
 574 #define ASCE_REAL_SPACE       0x20        /* real space control               */
 575 #define ASCE_TYPE_MASK        0x0c        /* asce table type mask             */
 576 #define ASCE_TYPE_REGION1     0x0c        /* region first table type          */
 577 #define ASCE_TYPE_REGION2     0x08        /* region second table type         */
 578 #define ASCE_TYPE_REGION3     0x04        /* region third table type          */
 579 #define ASCE_TYPE_SEGMENT     0x00        /* segment table type               */
 580 #define ASCE_TABLE_LENGTH     0x03        /* region table length              */
 581
 582 #define REGION_ENTRY_ORIGIN         0xfffffffffffff000ULL
 583 #define REGION_ENTRY_P              0x0000000000000200ULL
 584 #define REGION_ENTRY_TF             0x00000000000000c0ULL
 585 #define REGION_ENTRY_I              0x0000000000000020ULL
 586 #define REGION_ENTRY_TT             0x000000000000000cULL
 587 #define REGION_ENTRY_TL             0x0000000000000003ULL
 588
 589 #define REGION_ENTRY_TT_REGION1     0x000000000000000cULL
 590 #define REGION_ENTRY_TT_REGION2     0x0000000000000008ULL
 591 #define REGION_ENTRY_TT_REGION3     0x0000000000000004ULL
 592
 593 #define REGION3_ENTRY_RFAA          0xffffffff80000000ULL
 594 #define REGION3_ENTRY_AV            0x0000000000010000ULL
 595 #define REGION3_ENTRY_ACC           0x000000000000f000ULL
 596 #define REGION3_ENTRY_F             0x0000000000000800ULL
 597 #define REGION3_ENTRY_FC            0x0000000000000400ULL
 598 #define REGION3_ENTRY_IEP           0x0000000000000100ULL
 599 #define REGION3_ENTRY_CR            0x0000000000000010ULL
 600
 601 #define SEGMENT_ENTRY_ORIGIN        0xfffffffffffff800ULL
 602 #define SEGMENT_ENTRY_SFAA          0xfffffffffff00000ULL
 603 #define SEGMENT_ENTRY_AV            0x0000000000010000ULL
 604 #define SEGMENT_ENTRY_ACC           0x000000000000f000ULL
 605 #define SEGMENT_ENTRY_F             0x0000000000000800ULL
 606 #define SEGMENT_ENTRY_FC            0x0000000000000400ULL
 607 #define SEGMENT_ENTRY_P             0x0000000000000200ULL
 608 #define SEGMENT_ENTRY_IEP           0x0000000000000100ULL
 609 #define SEGMENT_ENTRY_I             0x0000000000000020ULL
 610 #define SEGMENT_ENTRY_CS            0x0000000000000010ULL
 611 #define SEGMENT_ENTRY_TT            0x000000000000000cULL
 612
 613 #define SEGMENT_ENTRY_TT_SEGMENT    0x0000000000000000ULL
 614
 615 #define PAGE_ENTRY_0                0x0000000000000800ULL
 616 #define PAGE_ENTRY_I                0x0000000000000400ULL
 617 #define PAGE_ENTRY_P                0x0000000000000200ULL
 618 #define PAGE_ENTRY_IEP              0x0000000000000100ULL
 619
 620 #define VADDR_REGION1_TX_MASK       0xffe0000000000000ULL
 621 #define VADDR_REGION2_TX_MASK       0x001ffc0000000000ULL
 622 #define VADDR_REGION3_TX_MASK       0x000003ff80000000ULL
 623 #define VADDR_SEGMENT_TX_MASK       0x000000007ff00000ULL
 624 #define VADDR_PAGE_TX_MASK          0x00000000000ff000ULL
 625
 626 #define VADDR_REGION1_TX(vaddr)     (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
 627 #define VADDR_REGION2_TX(vaddr)     (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
 628 #define VADDR_REGION3_TX(vaddr)     (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
 629 #define VADDR_SEGMENT_TX(vaddr)     (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
 630 #define VADDR_PAGE_TX(vaddr)        (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
 631
 632 #define VADDR_REGION1_TL(vaddr)     (((vaddr) & 0xc000000000000000ULL) >> 62)
 633 #define VADDR_REGION2_TL(vaddr)     (((vaddr) & 0x0018000000000000ULL) >> 51)
 634 #define VADDR_REGION3_TL(vaddr)     (((vaddr) & 0x0000030000000000ULL) >> 40)
 635 #define VADDR_SEGMENT_TL(vaddr)     (((vaddr) & 0x0000000060000000ULL) >> 29)
 636
 637 #define SK_C                    (0x1 << 1)
 638 #define SK_R                    (0x1 << 2)
 639 #define SK_F                    (0x1 << 3)
 640 #define SK_ACC_MASK             (0xf << 4)
 641
 642 /* SIGP order codes */
 643 #define SIGP_SENSE             0x01
 644 #define SIGP_EXTERNAL_CALL     0x02
 645 #define SIGP_EMERGENCY         0x03
 646 #define SIGP_START             0x04
 647 #define SIGP_STOP              0x05
 648 #define SIGP_RESTART           0x06
 649 #define SIGP_STOP_STORE_STATUS 0x09
 650 #define SIGP_INITIAL_CPU_RESET 0x0b
 651 #define SIGP_CPU_RESET         0x0c
 652 #define SIGP_SET_PREFIX        0x0d
 653 #define SIGP_STORE_STATUS_ADDR 0x0e
 654 #define SIGP_SET_ARCH          0x12
 655 #define SIGP_COND_EMERGENCY    0x13
 656 #define SIGP_SENSE_RUNNING     0x15
 657 #define SIGP_STORE_ADTL_STATUS 0x17
 658
 659 /* SIGP condition codes */
 660 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 661 #define SIGP_CC_STATUS_STORED       1
 662 #define SIGP_CC_BUSY                2
 663 #define SIGP_CC_NOT_OPERATIONAL     3
 664
 665 /* SIGP status bits */
 666 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 667 #define SIGP_STAT_NOT_RUNNING       0x00000400UL
 668 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 669 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 670 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 671 #define SIGP_STAT_STOPPED           0x00000040UL
 672 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 673 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 674 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 675 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 676 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 677
 678 /* SIGP order code mask corresponding to bit positions 56-63 */
 679 #define SIGP_ORDER_MASK 0x000000ff
 680
 681 /* machine check interruption code */
 682
 683 /* subclasses */
 684 #define MCIC_SC_SD 0x8000000000000000ULL
 685 #define MCIC_SC_PD 0x4000000000000000ULL
 686 #define MCIC_SC_SR 0x2000000000000000ULL
 687 #define MCIC_SC_CD 0x0800000000000000ULL
 688 #define MCIC_SC_ED 0x0400000000000000ULL
 689 #define MCIC_SC_DG 0x0100000000000000ULL
 690 #define MCIC_SC_W  0x0080000000000000ULL
 691 #define MCIC_SC_CP 0x0040000000000000ULL
 692 #define MCIC_SC_SP 0x0020000000000000ULL
 693 #define MCIC_SC_CK 0x0010000000000000ULL
 694
 695 /* subclass modifiers */
 696 #define MCIC_SCM_B  0x0002000000000000ULL
 697 #define MCIC_SCM_DA 0x0000000020000000ULL
 698 #define MCIC_SCM_AP 0x0000000000080000ULL
 699
 700 /* storage errors */
 701 #define MCIC_SE_SE 0x0000800000000000ULL
 702 #define MCIC_SE_SC 0x0000400000000000ULL
 703 #define MCIC_SE_KE 0x0000200000000000ULL
 704 #define MCIC_SE_DS 0x0000100000000000ULL
 705 #define MCIC_SE_IE 0x0000000080000000ULL
 706
 707 /* validity bits */
 708 #define MCIC_VB_WP 0x0000080000000000ULL
 709 #define MCIC_VB_MS 0x0000040000000000ULL
 710 #define MCIC_VB_PM 0x0000020000000000ULL
 711 #define MCIC_VB_IA 0x0000010000000000ULL
 712 #define MCIC_VB_FA 0x0000008000000000ULL
 713 #define MCIC_VB_VR 0x0000004000000000ULL
 714 #define MCIC_VB_EC 0x0000002000000000ULL
 715 #define MCIC_VB_FP 0x0000001000000000ULL
 716 #define MCIC_VB_GR 0x0000000800000000ULL
 717 #define MCIC_VB_CR 0x0000000400000000ULL
 718 #define MCIC_VB_ST 0x0000000100000000ULL
 719 #define MCIC_VB_AR 0x0000000040000000ULL
 720 #define MCIC_VB_GS 0x0000000008000000ULL
 721 #define MCIC_VB_PR 0x0000000000200000ULL
 722 #define MCIC_VB_FC 0x0000000000100000ULL
 723 #define MCIC_VB_CT 0x0000000000020000ULL
 724 #define MCIC_VB_CC 0x0000000000010000ULL
 725
 726 static inline uint64_t s390_build_validity_mcic(void)
 727 {
 728     uint64_t mcic;
 729
 730     /*
 731      * Indicate all validity bits (no damage) only. Other bits have to be
 732      * added by the caller. (storage errors, subclasses and subclass modifiers)
 733      */
 734     mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
 735            MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
 736            MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
 737     if (s390_has_feat(S390_FEAT_VECTOR)) {
 738         mcic |= MCIC_VB_VR;
 739     }
 740     if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
 741         mcic |= MCIC_VB_GS;
 742     }
 743     return mcic;
 744 }
 745
 746 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
 747 {
 748     cpu_reset(cs);
 749 }
 750
 751 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
 752 {
 753     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 754
 755     scc->reset(cs, S390_CPU_RESET_NORMAL);
 756 }
 757
 758 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
 759 {
 760     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 761
 762     scc->reset(cs, S390_CPU_RESET_INITIAL);
 763 }
 764
 765 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
 766 {
 767     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 768
 769     scc->load_normal(cs);
 770 }
 771
 772
 773 /* cpu.c */
 774 void s390_crypto_reset(void);
 775 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
 776 void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
 777 void s390_cmma_reset(void);
 778 void s390_enable_css_support(S390CPU *cpu);
 779 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg);
 780 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
 781                                 int vq, bool assign);
 782 #ifndef CONFIG_USER_ONLY
 783 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 784 #else
 785 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 786 {
 787     return 0;
 788 }
 789 #endif /* CONFIG_USER_ONLY */
 790 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 791 {
 792     return cpu->env.cpu_state;
 793 }
 794
 795
 796 /* cpu_models.c */
 797 void s390_cpu_list(void);
 798 #define cpu_list s390_cpu_list
 799 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 800                              const S390FeatInit feat_init);
 801
 802
 803 /* helper.c */
 804 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
 805 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 806 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
 807
 808 /* interrupt.c */
 809 #define RA_IGNORED                  0
 810 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
 811 /* service interrupts are floating therefore we must not pass an cpustate */
 812 void s390_sclp_extint(uint32_t parm);
 813
 814 /* mmu_helper.c */
 815 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 816                          int len, bool is_write);
 817 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 818         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 819 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 820         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 821 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len)   \
 822         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
 823 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 824         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 825 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
 826 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
 827                        int len, bool is_write);
 828 #define s390_cpu_pv_mem_read(cpu, offset, dest, len)    \
 829         s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
 830 #define s390_cpu_pv_mem_write(cpu, offset, dest, len)       \
 831         s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
 832
 833 /* sigp.c */
 834 int s390_cpu_restart(S390CPU *cpu);
 835 void s390_init_sigp(void);
 836
 837 /* helper.c */
 838 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 839 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
 840
 841 /* outside of target/s390x/ */
 842 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 843
 844 #include "exec/cpu-all.h"
 845
 846 #endif