hw/timer/lm32_timer.c

   1 /*
   2  *  QEMU model of the LatticeMico32 timer block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32timer.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "qemu/timer.h"
  29 #include "hw/ptimer.h"
  30 #include "qemu/error-report.h"
  31 #include "qemu/main-loop.h"
  32
  33 #define DEFAULT_FREQUENCY (50*1000000)
  34
  35 enum {
  36     R_SR = 0,
  37     R_CR,
  38     R_PERIOD,
  39     R_SNAPSHOT,
  40     R_MAX
  41 };
  42
  43 enum {
  44     SR_TO    = (1 << 0),
  45     SR_RUN   = (1 << 1),
  46 };
  47
  48 enum {
  49     CR_ITO   = (1 << 0),
  50     CR_CONT  = (1 << 1),
  51     CR_START = (1 << 2),
  52     CR_STOP  = (1 << 3),
  53 };
  54
  55 #define TYPE_LM32_TIMER "lm32-timer"
  56 #define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
  57
  58 struct LM32TimerState {
  59     SysBusDevice parent_obj;
  60
  61     MemoryRegion iomem;
  62
  63     QEMUBH *bh;
  64     ptimer_state *ptimer;
  65
  66     qemu_irq irq;
  67     uint32_t freq_hz;
  68
  69     uint32_t regs[R_MAX];
  70 };
  71 typedef struct LM32TimerState LM32TimerState;
  72
  73 static void timer_update_irq(LM32TimerState *s)
  74 {
  75     int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
  76
  77     trace_lm32_timer_irq_state(state);
  78     qemu_set_irq(s->irq, state);
  79 }
  80
  81 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
  82 {
  83     LM32TimerState *s = opaque;
  84     uint32_t r = 0;
  85
  86     addr >>= 2;
  87     switch (addr) {
  88     case R_SR:
  89     case R_CR:
  90     case R_PERIOD:
  91         r = s->regs[addr];
  92         break;
  93     case R_SNAPSHOT:
  94         r = (uint32_t)ptimer_get_count(s->ptimer);
  95         break;
  96     default:
  97         error_report("lm32_timer: read access to unknown register 0x"
  98                 TARGET_FMT_plx, addr << 2);
  99         break;
 100     }
 101
 102     trace_lm32_timer_memory_read(addr << 2, r);
 103     return r;
 104 }
 105
 106 static void timer_write(void *opaque, hwaddr addr,
 107                         uint64_t value, unsigned size)
 108 {
 109     LM32TimerState *s = opaque;
 110
 111     trace_lm32_timer_memory_write(addr, value);
 112
 113     addr >>= 2;
 114     switch (addr) {
 115     case R_SR:
 116         s->regs[R_SR] &= ~SR_TO;
 117         break;
 118     case R_CR:
 119         s->regs[R_CR] = value;
 120         if (s->regs[R_CR] & CR_START) {
 121             ptimer_run(s->ptimer, 1);
 122         }
 123         if (s->regs[R_CR] & CR_STOP) {
 124             ptimer_stop(s->ptimer);
 125         }
 126         break;
 127     case R_PERIOD:
 128         s->regs[R_PERIOD] = value;
 129         ptimer_set_count(s->ptimer, value);
 130         break;
 131     case R_SNAPSHOT:
 132         error_report("lm32_timer: write access to read only register 0x"
 133                 TARGET_FMT_plx, addr << 2);
 134         break;
 135     default:
 136         error_report("lm32_timer: write access to unknown register 0x"
 137                 TARGET_FMT_plx, addr << 2);
 138         break;
 139     }
 140     timer_update_irq(s);
 141 }
 142
 143 static const MemoryRegionOps timer_ops = {
 144     .read = timer_read,
 145     .write = timer_write,
 146     .endianness = DEVICE_NATIVE_ENDIAN,
 147     .valid = {
 148         .min_access_size = 4,
 149         .max_access_size = 4,
 150     },
 151 };
 152
 153 static void timer_hit(void *opaque)
 154 {
 155     LM32TimerState *s = opaque;
 156
 157     trace_lm32_timer_hit();
 158
 159     s->regs[R_SR] |= SR_TO;
 160
 161     if (s->regs[R_CR] & CR_CONT) {
 162         ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
 163         ptimer_run(s->ptimer, 1);
 164     }
 165     timer_update_irq(s);
 166 }
 167
 168 static void timer_reset(DeviceState *d)
 169 {
 170     LM32TimerState *s = LM32_TIMER(d);
 171     int i;
 172
 173     for (i = 0; i < R_MAX; i++) {
 174         s->regs[i] = 0;
 175     }
 176     ptimer_stop(s->ptimer);
 177 }
 178
 179 static int lm32_timer_init(SysBusDevice *dev)
 180 {
 181     LM32TimerState *s = LM32_TIMER(dev);
 182
 183     sysbus_init_irq(dev, &s->irq);
 184
 185     s->bh = qemu_bh_new(timer_hit, s);
 186     s->ptimer = ptimer_init(s->bh);
 187     ptimer_set_freq(s->ptimer, s->freq_hz);
 188
 189     memory_region_init_io(&s->iomem, OBJECT(s), &timer_ops, s,
 190                           "timer", R_MAX * 4);
 191     sysbus_init_mmio(dev, &s->iomem);
 192
 193     return 0;
 194 }
 195
 196 static const VMStateDescription vmstate_lm32_timer = {
 197     .name = "lm32-timer",
 198     .version_id = 1,
 199     .minimum_version_id = 1,
 200     .fields = (VMStateField[]) {
 201         VMSTATE_PTIMER(ptimer, LM32TimerState),
 202         VMSTATE_UINT32(freq_hz, LM32TimerState),
 203         VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
 204         VMSTATE_END_OF_LIST()
 205     }
 206 };
 207
 208 static Property lm32_timer_properties[] = {
 209     DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
 210     DEFINE_PROP_END_OF_LIST(),
 211 };
 212
 213 static void lm32_timer_class_init(ObjectClass *klass, void *data)
 214 {
 215     DeviceClass *dc = DEVICE_CLASS(klass);
 216     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 217
 218     k->init = lm32_timer_init;
 219     dc->reset = timer_reset;
 220     dc->vmsd = &vmstate_lm32_timer;
 221     dc->props = lm32_timer_properties;
 222 }
 223
 224 static const TypeInfo lm32_timer_info = {
 225     .name          = TYPE_LM32_TIMER,
 226     .parent        = TYPE_SYS_BUS_DEVICE,
 227     .instance_size = sizeof(LM32TimerState),
 228     .class_init    = lm32_timer_class_init,
 229 };
 230
 231 static void lm32_timer_register_types(void)
 232 {
 233     type_register_static(&lm32_timer_info);
 234 }
 235
 236 type_init(lm32_timer_register_types)