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Merge tag 'v2.11.0-rc2'
[qemu/ar7.git] / hw / pci / pci.c
blobf11a51bf67959e74506a22f1b109ce54b6191cf2
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bridge.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "monitor/monitor.h"
31 #include "net/net.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/loader.h"
34 #include "qemu/error-report.h"
35 #include "qemu/range.h"
36 #include "qmp-commands.h"
37 #include "trace.h"
38 #include "hw/pci/msi.h"
39 #include "hw/pci/msix.h"
40 #include "exec/address-spaces.h"
41 #include "hw/hotplug.h"
42 #include "hw/boards.h"
43 #include "qemu/cutils.h"
44
45 //#define DEBUG_PCI
46 #ifdef DEBUG_PCI
47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48 #else
49 # define PCI_DPRINTF(format, ...) do { } while (0)
50 #endif
51
52 bool pci_available = true;
53
54 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
55 static char *pcibus_get_dev_path(DeviceState *dev);
56 static char *pcibus_get_fw_dev_path(DeviceState *dev);
57 static void pcibus_reset(BusState *qbus);
58
59 static Property pci_props[] = {
60 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
61 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
62 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
63 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
64 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
65 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
66 QEMU_PCI_CAP_SERR_BITNR, true),
67 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
68 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
69 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
70 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
71 DEFINE_PROP_END_OF_LIST()
72 };
73
74 static const VMStateDescription vmstate_pcibus = {
75 .name = "PCIBUS",
76 .version_id = 1,
77 .minimum_version_id = 1,
78 .fields = (VMStateField[]) {
79 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
80 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
81 nirq, 0, vmstate_info_int32,
82 int32_t),
83 VMSTATE_END_OF_LIST()
84 }
85 };
86
87 static void pci_init_bus_master(PCIDevice *pci_dev)
88 {
89 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
90
91 memory_region_init_alias(&pci_dev->bus_master_enable_region,
92 OBJECT(pci_dev), "bus master",
93 dma_as->root, 0, memory_region_size(dma_as->root));
94 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
95 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
96 &pci_dev->bus_master_enable_region);
97 }
98
99 static void pcibus_machine_done(Notifier *notifier, void *data)
100 {
101 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
102 int i;
103
104 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
105 if (bus->devices[i]) {
106 pci_init_bus_master(bus->devices[i]);
107 }
108 }
109 }
110
111 static void pci_bus_realize(BusState *qbus, Error **errp)
112 {
113 PCIBus *bus = PCI_BUS(qbus);
114
115 bus->machine_done.notify = pcibus_machine_done;
116 qemu_add_machine_init_done_notifier(&bus->machine_done);
117
118 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
119 }
120
121 static void pci_bus_unrealize(BusState *qbus, Error **errp)
122 {
123 PCIBus *bus = PCI_BUS(qbus);
124
125 qemu_remove_machine_init_done_notifier(&bus->machine_done);
126
127 vmstate_unregister(NULL, &vmstate_pcibus, bus);
128 }
129
130 static bool pcibus_is_root(PCIBus *bus)
131 {
132 return !bus->parent_dev;
133 }
134
135 static int pcibus_num(PCIBus *bus)
136 {
137 if (pcibus_is_root(bus)) {
138 return 0; /* pci host bridge */
139 }
140 return bus->parent_dev->config[PCI_SECONDARY_BUS];
141 }
142
143 static uint16_t pcibus_numa_node(PCIBus *bus)
144 {
145 return NUMA_NODE_UNASSIGNED;
146 }
147
148 static void pci_bus_class_init(ObjectClass *klass, void *data)
149 {
150 BusClass *k = BUS_CLASS(klass);
151 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
152
153 k->print_dev = pcibus_dev_print;
154 k->get_dev_path = pcibus_get_dev_path;
155 k->get_fw_dev_path = pcibus_get_fw_dev_path;
156 k->realize = pci_bus_realize;
157 k->unrealize = pci_bus_unrealize;
158 k->reset = pcibus_reset;
159
160 pbc->is_root = pcibus_is_root;
161 pbc->bus_num = pcibus_num;
162 pbc->numa_node = pcibus_numa_node;
163 }
164
165 static const TypeInfo pci_bus_info = {
166 .name = TYPE_PCI_BUS,
167 .parent = TYPE_BUS,
168 .instance_size = sizeof(PCIBus),
169 .class_size = sizeof(PCIBusClass),
170 .class_init = pci_bus_class_init,
171 };
172
173 static const TypeInfo pcie_interface_info = {
174 .name = INTERFACE_PCIE_DEVICE,
175 .parent = TYPE_INTERFACE,
176 };
177
178 static const TypeInfo conventional_pci_interface_info = {
179 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
180 .parent = TYPE_INTERFACE,
181 };
182
183 static const TypeInfo pcie_bus_info = {
184 .name = TYPE_PCIE_BUS,
185 .parent = TYPE_PCI_BUS,
186 };
187
188 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
189 static void pci_update_mappings(PCIDevice *d);
190 static void pci_irq_handler(void *opaque, int irq_num, int level);
191 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
192 static void pci_del_option_rom(PCIDevice *pdev);
193
194 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
195 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
196
197 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
198
199 int pci_bar(PCIDevice *d, int reg)
200 {
201 uint8_t type;
202
203 if (reg != PCI_ROM_SLOT)
204 return PCI_BASE_ADDRESS_0 + reg * 4;
205
206 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
207 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
208 }
209
210 static inline int pci_irq_state(PCIDevice *d, int irq_num)
211 {
212 return (d->irq_state >> irq_num) & 0x1;
213 }
214
215 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
216 {
217 d->irq_state &= ~(0x1 << irq_num);
218 d->irq_state |= level << irq_num;
219 }
220
221 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
222 {
223 PCIBus *bus;
224 for (;;) {
225 bus = pci_dev->bus;
226 irq_num = bus->map_irq(pci_dev, irq_num);
227 if (bus->set_irq)
228 break;
229 pci_dev = bus->parent_dev;
230 }
231 bus->irq_count[irq_num] += change;
232 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
233 }
234
235 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
236 {
237 assert(irq_num >= 0);
238 assert(irq_num < bus->nirq);
239 return !!bus->irq_count[irq_num];
240 }
241
242 /* Update interrupt status bit in config space on interrupt
243 * state change. */
244 static void pci_update_irq_status(PCIDevice *dev)
245 {
246 if (dev->irq_state) {
247 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
248 } else {
249 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
250 }
251 }
252
253 void pci_device_deassert_intx(PCIDevice *dev)
254 {
255 int i;
256 for (i = 0; i < PCI_NUM_PINS; ++i) {
257 pci_irq_handler(dev, i, 0);
258 }
259 }
260
261 static void pci_do_device_reset(PCIDevice *dev)
262 {
263 int r;
264
265 pci_device_deassert_intx(dev);
266 assert(dev->irq_state == 0);
267
268 /* Clear all writable bits */
269 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
270 pci_get_word(dev->wmask + PCI_COMMAND) |
271 pci_get_word(dev->w1cmask + PCI_COMMAND));
272 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
273 pci_get_word(dev->wmask + PCI_STATUS) |
274 pci_get_word(dev->w1cmask + PCI_STATUS));
275 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
276 dev->config[PCI_INTERRUPT_LINE] = 0x0;
277 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
278 PCIIORegion *region = &dev->io_regions[r];
279 if (!region->size) {
280 continue;
281 }
282
283 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
284 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
285 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
286 } else {
287 pci_set_long(dev->config + pci_bar(dev, r), region->type);
288 }
289 }
290 pci_update_mappings(dev);
291
292 msi_reset(dev);
293 msix_reset(dev);
294 }
295
296 /*
297 * This function is called on #RST and FLR.
298 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
299 */
300 void pci_device_reset(PCIDevice *dev)
301 {
302 qdev_reset_all(&dev->qdev);
303 pci_do_device_reset(dev);
304 }
305
306 /*
307 * Trigger pci bus reset under a given bus.
308 * Called via qbus_reset_all on RST# assert, after the devices
309 * have been reset qdev_reset_all-ed already.
310 */
311 static void pcibus_reset(BusState *qbus)
312 {
313 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
314 int i;
315
316 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
317 if (bus->devices[i]) {
318 pci_do_device_reset(bus->devices[i]);
319 }
320 }
321
322 for (i = 0; i < bus->nirq; i++) {
323 assert(bus->irq_count[i] == 0);
324 }
325 }
326
327 static void pci_host_bus_register(DeviceState *host)
328 {
329 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
330
331 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
332 }
333
334 PCIBus *pci_find_primary_bus(void)
335 {
336 PCIBus *primary_bus = NULL;
337 PCIHostState *host;
338
339 QLIST_FOREACH(host, &pci_host_bridges, next) {
340 if (primary_bus) {
341 /* We have multiple root buses, refuse to select a primary */
342 return NULL;
343 }
344 primary_bus = host->bus;
345 }
346
347 return primary_bus;
348 }
349
350 PCIBus *pci_device_root_bus(const PCIDevice *d)
351 {
352 PCIBus *bus = d->bus;
353
354 while (!pci_bus_is_root(bus)) {
355 d = bus->parent_dev;
356 assert(d != NULL);
357
358 bus = d->bus;
359 }
360
361 return bus;
362 }
363
364 const char *pci_root_bus_path(PCIDevice *dev)
365 {
366 PCIBus *rootbus = pci_device_root_bus(dev);
367 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
368 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
369
370 assert(host_bridge->bus == rootbus);
371
372 if (hc->root_bus_path) {
373 return (*hc->root_bus_path)(host_bridge, rootbus);
374 }
375
376 return rootbus->qbus.name;
377 }
378
379 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
380 MemoryRegion *address_space_mem,
381 MemoryRegion *address_space_io,
382 uint8_t devfn_min)
383 {
384 assert(PCI_FUNC(devfn_min) == 0);
385 bus->devfn_min = devfn_min;
386 bus->slot_reserved_mask = 0x0;
387 bus->address_space_mem = address_space_mem;
388 bus->address_space_io = address_space_io;
389
390 /* host bridge */
391 QLIST_INIT(&bus->child);
392
393 pci_host_bus_register(parent);
394 }
395
396 bool pci_bus_is_express(PCIBus *bus)
397 {
398 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
399 }
400
401 bool pci_bus_is_root(PCIBus *bus)
402 {
403 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
404 }
405
406 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
407 const char *name,
408 MemoryRegion *address_space_mem,
409 MemoryRegion *address_space_io,
410 uint8_t devfn_min, const char *typename)
411 {
412 qbus_create_inplace(bus, bus_size, typename, parent, name);
413 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
414 }
415
416 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
417 MemoryRegion *address_space_mem,
418 MemoryRegion *address_space_io,
419 uint8_t devfn_min, const char *typename)
420 {
421 PCIBus *bus;
422
423 bus = PCI_BUS(qbus_create(typename, parent, name));
424 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
425 return bus;
426 }
427
428 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
429 void *irq_opaque, int nirq)
430 {
431 bus->set_irq = set_irq;
432 bus->map_irq = map_irq;
433 bus->irq_opaque = irq_opaque;
434 bus->nirq = nirq;
435 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
436 }
437
438 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
439 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
440 void *irq_opaque,
441 MemoryRegion *address_space_mem,
442 MemoryRegion *address_space_io,
443 uint8_t devfn_min, int nirq, const char *typename)
444 {
445 PCIBus *bus;
446
447 bus = pci_bus_new(parent, name, address_space_mem,
448 address_space_io, devfn_min, typename);
449 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
450 return bus;
451 }
452
453 int pci_bus_num(PCIBus *s)
454 {
455 return PCI_BUS_GET_CLASS(s)->bus_num(s);
456 }
457
458 int pci_bus_numa_node(PCIBus *bus)
459 {
460 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
461 }
462
463 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
464 VMStateField *field)
465 {
466 PCIDevice *s = container_of(pv, PCIDevice, config);
467 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
468 uint8_t *config;
469 int i;
470
471 assert(size == pci_config_size(s));
472 config = g_malloc(size);
473
474 qemu_get_buffer(f, config, size);
475 for (i = 0; i < size; ++i) {
476 if ((config[i] ^ s->config[i]) &
477 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
478 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
479 "cmask: %x wmask: %x w1cmask:%x", __func__,
480 i, config[i], s->config[i],
481 s->cmask[i], s->wmask[i], s->w1cmask[i]);
482 g_free(config);
483 return -EINVAL;
484 }
485 }
486 memcpy(s->config, config, size);
487
488 pci_update_mappings(s);
489 if (pc->is_bridge) {
490 PCIBridge *b = PCI_BRIDGE(s);
491 pci_bridge_update_mappings(b);
492 }
493
494 memory_region_set_enabled(&s->bus_master_enable_region,
495 pci_get_word(s->config + PCI_COMMAND)
496 & PCI_COMMAND_MASTER);
497
498 g_free(config);
499 return 0;
500 }
501
502 /* just put buffer */
503 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
504 VMStateField *field, QJSON *vmdesc)
505 {
506 const uint8_t **v = pv;
507 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
508 qemu_put_buffer(f, *v, size);
509
510 return 0;
511 }
512
513 static VMStateInfo vmstate_info_pci_config = {
514 .name = "pci config",
515 .get = get_pci_config_device,
516 .put = put_pci_config_device,
517 };
518
519 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
520 VMStateField *field)
521 {
522 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
523 uint32_t irq_state[PCI_NUM_PINS];
524 int i;
525 for (i = 0; i < PCI_NUM_PINS; ++i) {
526 irq_state[i] = qemu_get_be32(f);
527 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
528 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
529 irq_state[i]);
530 return -EINVAL;
531 }
532 }
533
534 for (i = 0; i < PCI_NUM_PINS; ++i) {
535 pci_set_irq_state(s, i, irq_state[i]);
536 }
537
538 return 0;
539 }
540
541 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
542 VMStateField *field, QJSON *vmdesc)
543 {
544 int i;
545 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
546
547 for (i = 0; i < PCI_NUM_PINS; ++i) {
548 qemu_put_be32(f, pci_irq_state(s, i));
549 }
550
551 return 0;
552 }
553
554 static VMStateInfo vmstate_info_pci_irq_state = {
555 .name = "pci irq state",
556 .get = get_pci_irq_state,
557 .put = put_pci_irq_state,
558 };
559
560 static bool migrate_is_pcie(void *opaque, int version_id)
561 {
562 return pci_is_express((PCIDevice *)opaque);
563 }
564
565 static bool migrate_is_not_pcie(void *opaque, int version_id)
566 {
567 return !pci_is_express((PCIDevice *)opaque);
568 }
569
570 const VMStateDescription vmstate_pci_device = {
571 .name = "PCIDevice",
572 .version_id = 2,
573 .minimum_version_id = 1,
574 .fields = (VMStateField[]) {
575 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
576 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
577 migrate_is_not_pcie,
578 0, vmstate_info_pci_config,
579 PCI_CONFIG_SPACE_SIZE),
580 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
581 migrate_is_pcie,
582 0, vmstate_info_pci_config,
583 PCIE_CONFIG_SPACE_SIZE),
584 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
585 vmstate_info_pci_irq_state,
586 PCI_NUM_PINS * sizeof(int32_t)),
587 VMSTATE_END_OF_LIST()
588 }
589 };
590
591
592 void pci_device_save(PCIDevice *s, QEMUFile *f)
593 {
594 /* Clear interrupt status bit: it is implicit
595 * in irq_state which we are saving.
596 * This makes us compatible with old devices
597 * which never set or clear this bit. */
598 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
599 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
600 /* Restore the interrupt status bit. */
601 pci_update_irq_status(s);
602 }
603
604 int pci_device_load(PCIDevice *s, QEMUFile *f)
605 {
606 int ret;
607 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
608 /* Restore the interrupt status bit. */
609 pci_update_irq_status(s);
610 return ret;
611 }
612
613 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
614 {
615 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
616 pci_default_sub_vendor_id);
617 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
618 pci_default_sub_device_id);
619 }
620
621 /*
622 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
623 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
624 */
625 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
626 unsigned int *slotp, unsigned int *funcp)
627 {
628 const char *p;
629 char *e;
630 unsigned long val;
631 unsigned long dom = 0, bus = 0;
632 unsigned int slot = 0;
633 unsigned int func = 0;
634
635 p = addr;
636 val = strtoul(p, &e, 16);
637 if (e == p)
638 return -1;
639 if (*e == ':') {
640 bus = val;
641 p = e + 1;
642 val = strtoul(p, &e, 16);
643 if (e == p)
644 return -1;
645 if (*e == ':') {
646 dom = bus;
647 bus = val;
648 p = e + 1;
649 val = strtoul(p, &e, 16);
650 if (e == p)
651 return -1;
652 }
653 }
654
655 slot = val;
656
657 if (funcp != NULL) {
658 if (*e != '.')
659 return -1;
660
661 p = e + 1;
662 val = strtoul(p, &e, 16);
663 if (e == p)
664 return -1;
665
666 func = val;
667 }
668
669 /* if funcp == NULL func is 0 */
670 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
671 return -1;
672
673 if (*e)
674 return -1;
675
676 *domp = dom;
677 *busp = bus;
678 *slotp = slot;
679 if (funcp != NULL)
680 *funcp = func;
681 return 0;
682 }
683
684 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
685 const char *devaddr)
686 {
687 int dom, bus;
688 unsigned slot;
689
690 if (!root) {
691 fprintf(stderr, "No primary PCI bus\n");
692 return NULL;
693 }
694
695 assert(!root->parent_dev);
696
697 if (!devaddr) {
698 *devfnp = -1;
699 return pci_find_bus_nr(root, 0);
700 }
701
702 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
703 return NULL;
704 }
705
706 if (dom != 0) {
707 fprintf(stderr, "No support for non-zero PCI domains\n");
708 return NULL;
709 }
710
711 *devfnp = PCI_DEVFN(slot, 0);
712 return pci_find_bus_nr(root, bus);
713 }
714
715 static void pci_init_cmask(PCIDevice *dev)
716 {
717 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
718 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
719 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
720 dev->cmask[PCI_REVISION_ID] = 0xff;
721 dev->cmask[PCI_CLASS_PROG] = 0xff;
722 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
723 dev->cmask[PCI_HEADER_TYPE] = 0xff;
724 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
725 }
726
727 static void pci_init_wmask(PCIDevice *dev)
728 {
729 int config_size = pci_config_size(dev);
730
731 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
732 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
733 pci_set_word(dev->wmask + PCI_COMMAND,
734 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
735 PCI_COMMAND_INTX_DISABLE);
736 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
737 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
738 }
739
740 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
741 config_size - PCI_CONFIG_HEADER_SIZE);
742 }
743
744 static void pci_init_w1cmask(PCIDevice *dev)
745 {
746 /*
747 * Note: It's okay to set w1cmask even for readonly bits as
748 * long as their value is hardwired to 0.
749 */
750 pci_set_word(dev->w1cmask + PCI_STATUS,
751 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
752 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
753 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
754 }
755
756 static void pci_init_mask_bridge(PCIDevice *d)
757 {
758 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
759 PCI_SEC_LETENCY_TIMER */
760 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
761
762 /* base and limit */
763 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
764 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
765 pci_set_word(d->wmask + PCI_MEMORY_BASE,
766 PCI_MEMORY_RANGE_MASK & 0xffff);
767 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
768 PCI_MEMORY_RANGE_MASK & 0xffff);
769 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
770 PCI_PREF_RANGE_MASK & 0xffff);
771 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
772 PCI_PREF_RANGE_MASK & 0xffff);
773
774 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
775 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
776
777 /* Supported memory and i/o types */
778 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
779 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
780 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
781 PCI_PREF_RANGE_TYPE_64);
782 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
783 PCI_PREF_RANGE_TYPE_64);
784
785 /*
786 * TODO: Bridges default to 10-bit VGA decoding but we currently only
787 * implement 16-bit decoding (no alias support).
788 */
789 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
790 PCI_BRIDGE_CTL_PARITY |
791 PCI_BRIDGE_CTL_SERR |
792 PCI_BRIDGE_CTL_ISA |
793 PCI_BRIDGE_CTL_VGA |
794 PCI_BRIDGE_CTL_VGA_16BIT |
795 PCI_BRIDGE_CTL_MASTER_ABORT |
796 PCI_BRIDGE_CTL_BUS_RESET |
797 PCI_BRIDGE_CTL_FAST_BACK |
798 PCI_BRIDGE_CTL_DISCARD |
799 PCI_BRIDGE_CTL_SEC_DISCARD |
800 PCI_BRIDGE_CTL_DISCARD_SERR);
801 /* Below does not do anything as we never set this bit, put here for
802 * completeness. */
803 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
804 PCI_BRIDGE_CTL_DISCARD_STATUS);
805 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
806 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
807 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
808 PCI_PREF_RANGE_TYPE_MASK);
809 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
810 PCI_PREF_RANGE_TYPE_MASK);
811 }
812
813 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
814 {
815 uint8_t slot = PCI_SLOT(dev->devfn);
816 uint8_t func;
817
818 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
819 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
820 }
821
822 /*
823 * multifunction bit is interpreted in two ways as follows.
824 * - all functions must set the bit to 1.
825 * Example: Intel X53
826 * - function 0 must set the bit, but the rest function (> 0)
827 * is allowed to leave the bit to 0.
828 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
829 *
830 * So OS (at least Linux) checks the bit of only function 0,
831 * and doesn't see the bit of function > 0.
832 *
833 * The below check allows both interpretation.
834 */
835 if (PCI_FUNC(dev->devfn)) {
836 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
837 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
838 /* function 0 should set multifunction bit */
839 error_setg(errp, "PCI: single function device can't be populated "
840 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
841 return;
842 }
843 return;
844 }
845
846 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
847 return;
848 }
849 /* function 0 indicates single function, so function > 0 must be NULL */
850 for (func = 1; func < PCI_FUNC_MAX; ++func) {
851 if (bus->devices[PCI_DEVFN(slot, func)]) {
852 error_setg(errp, "PCI: %x.0 indicates single function, "
853 "but %x.%x is already populated.",
854 slot, slot, func);
855 return;
856 }
857 }
858 }
859
860 static void pci_config_alloc(PCIDevice *pci_dev)
861 {
862 int config_size = pci_config_size(pci_dev);
863
864 pci_dev->config = g_malloc0(config_size);
865 pci_dev->cmask = g_malloc0(config_size);
866 pci_dev->wmask = g_malloc0(config_size);
867 pci_dev->w1cmask = g_malloc0(config_size);
868 pci_dev->used = g_malloc0(config_size);
869 }
870
871 static void pci_config_free(PCIDevice *pci_dev)
872 {
873 g_free(pci_dev->config);
874 g_free(pci_dev->cmask);
875 g_free(pci_dev->wmask);
876 g_free(pci_dev->w1cmask);
877 g_free(pci_dev->used);
878 }
879
880 static void do_pci_unregister_device(PCIDevice *pci_dev)
881 {
882 pci_dev->bus->devices[pci_dev->devfn] = NULL;
883 pci_config_free(pci_dev);
884
885 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
886 memory_region_del_subregion(&pci_dev->bus_master_container_region,
887 &pci_dev->bus_master_enable_region);
888 }
889 address_space_destroy(&pci_dev->bus_master_as);
890 }
891
892 /* Extract PCIReqIDCache into BDF format */
893 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
894 {
895 uint8_t bus_n;
896 uint16_t result;
897
898 switch (cache->type) {
899 case PCI_REQ_ID_BDF:
900 result = pci_get_bdf(cache->dev);
901 break;
902 case PCI_REQ_ID_SECONDARY_BUS:
903 bus_n = pci_bus_num(cache->dev->bus);
904 result = PCI_BUILD_BDF(bus_n, 0);
905 break;
906 default:
907 error_printf("Invalid PCI requester ID cache type: %d\n",
908 cache->type);
909 exit(1);
910 break;
911 }
912
913 return result;
914 }
915
916 /* Parse bridges up to the root complex and return requester ID
917 * cache for specific device. For full PCIe topology, the cache
918 * result would be exactly the same as getting BDF of the device.
919 * However, several tricks are required when system mixed up with
920 * legacy PCI devices and PCIe-to-PCI bridges.
921 *
922 * Here we cache the proxy device (and type) not requester ID since
923 * bus number might change from time to time.
924 */
925 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
926 {
927 PCIDevice *parent;
928 PCIReqIDCache cache = {
929 .dev = dev,
930 .type = PCI_REQ_ID_BDF,
931 };
932
933 while (!pci_bus_is_root(dev->bus)) {
934 /* We are under PCI/PCIe bridges */
935 parent = dev->bus->parent_dev;
936 if (pci_is_express(parent)) {
937 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
938 /* When we pass through PCIe-to-PCI/PCIX bridges, we
939 * override the requester ID using secondary bus
940 * number of parent bridge with zeroed devfn
941 * (pcie-to-pci bridge spec chap 2.3). */
942 cache.type = PCI_REQ_ID_SECONDARY_BUS;
943 cache.dev = dev;
944 }
945 } else {
946 /* Legacy PCI, override requester ID with the bridge's
947 * BDF upstream. When the root complex connects to
948 * legacy PCI devices (including buses), it can only
949 * obtain requester ID info from directly attached
950 * devices. If devices are attached under bridges, only
951 * the requester ID of the bridge that is directly
952 * attached to the root complex can be recognized. */
953 cache.type = PCI_REQ_ID_BDF;
954 cache.dev = parent;
955 }
956 dev = parent;
957 }
958
959 return cache;
960 }
961
962 uint16_t pci_requester_id(PCIDevice *dev)
963 {
964 return pci_req_id_cache_extract(&dev->requester_id_cache);
965 }
966
967 static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
968 {
969 return !(bus->devices[devfn]);
970 }
971
972 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
973 {
974 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
975 }
976
977 /* -1 for devfn means auto assign */
978 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
979 const char *name, int devfn,
980 Error **errp)
981 {
982 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
983 PCIConfigReadFunc *config_read = pc->config_read;
984 PCIConfigWriteFunc *config_write = pc->config_write;
985 Error *local_err = NULL;
986 DeviceState *dev = DEVICE(pci_dev);
987
988 pci_dev->bus = bus;
989 /* Only pci bridges can be attached to extra PCI root buses */
990 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
991 error_setg(errp,
992 "PCI: Only PCI/PCIe bridges can be plugged into %s",
993 bus->parent_dev->name);
994 return NULL;
995 }
996
997 if (devfn < 0) {
998 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
999 devfn += PCI_FUNC_MAX) {
1000 if (pci_bus_devfn_available(bus, devfn) &&
1001 !pci_bus_devfn_reserved(bus, devfn)) {
1002 goto found;
1003 }
1004 }
1005 error_setg(errp, "PCI: no slot/function available for %s, all in use "
1006 "or reserved", name);
1007 return NULL;
1008 found: ;
1009 } else if (pci_bus_devfn_reserved(bus, devfn)) {
1010 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1011 " reserved",
1012 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1013 return NULL;
1014 } else if (!pci_bus_devfn_available(bus, devfn)) {
1015 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1016 " in use by %s",
1017 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1018 bus->devices[devfn]->name);
1019 return NULL;
1020 } else if (dev->hotplugged &&
1021 pci_get_function_0(pci_dev)) {
1022 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1023 " new func %s cannot be exposed to guest.",
1024 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1025 pci_get_function_0(pci_dev)->name,
1026 name);
1027
1028 return NULL;
1029 }
1030
1031 pci_dev->devfn = devfn;
1032 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1033 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1034
1035 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1036 "bus master container", UINT64_MAX);
1037 address_space_init(&pci_dev->bus_master_as,
1038 &pci_dev->bus_master_container_region, pci_dev->name);
1039
1040 if (qdev_hotplug) {
1041 pci_init_bus_master(pci_dev);
1042 }
1043 pci_dev->irq_state = 0;
1044 pci_config_alloc(pci_dev);
1045
1046 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1047 pci_config_set_device_id(pci_dev->config, pc->device_id);
1048 pci_config_set_revision(pci_dev->config, pc->revision);
1049 pci_config_set_class(pci_dev->config, pc->class_id);
1050
1051 if (!pc->is_bridge) {
1052 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1053 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1054 pc->subsystem_vendor_id);
1055 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1056 pc->subsystem_id);
1057 } else {
1058 pci_set_default_subsystem_id(pci_dev);
1059 }
1060 } else {
1061 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1062 assert(!pc->subsystem_vendor_id);
1063 assert(!pc->subsystem_id);
1064 }
1065 pci_init_cmask(pci_dev);
1066 pci_init_wmask(pci_dev);
1067 pci_init_w1cmask(pci_dev);
1068 if (pc->is_bridge) {
1069 pci_init_mask_bridge(pci_dev);
1070 }
1071 pci_init_multifunction(bus, pci_dev, &local_err);
1072 if (local_err) {
1073 error_propagate(errp, local_err);
1074 do_pci_unregister_device(pci_dev);
1075 return NULL;
1076 }
1077
1078 if (!config_read)
1079 config_read = pci_default_read_config;
1080 if (!config_write)
1081 config_write = pci_default_write_config;
1082 pci_dev->config_read = config_read;
1083 pci_dev->config_write = config_write;
1084 bus->devices[devfn] = pci_dev;
1085 pci_dev->version_id = 2; /* Current pci device vmstate version */
1086 return pci_dev;
1087 }
1088
1089 static void pci_unregister_io_regions(PCIDevice *pci_dev)
1090 {
1091 PCIIORegion *r;
1092 int i;
1093
1094 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1095 r = &pci_dev->io_regions[i];
1096 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1097 continue;
1098 memory_region_del_subregion(r->address_space, r->memory);
1099 }
1100
1101 pci_unregister_vga(pci_dev);
1102 }
1103
1104 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1105 {
1106 PCIDevice *pci_dev = PCI_DEVICE(dev);
1107 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1108
1109 pci_unregister_io_regions(pci_dev);
1110 pci_del_option_rom(pci_dev);
1111
1112 if (pc->exit) {
1113 pc->exit(pci_dev);
1114 }
1115
1116 pci_device_deassert_intx(pci_dev);
1117 do_pci_unregister_device(pci_dev);
1118 }
1119
1120 void pci_register_bar(PCIDevice *pci_dev, int region_num,
1121 uint8_t type, MemoryRegion *memory)
1122 {
1123 PCIIORegion *r;
1124 uint32_t addr; /* offset in pci config space */
1125 uint64_t wmask;
1126 pcibus_t size = memory_region_size(memory);
1127
1128 g_assert(region_num >= 0);
1129 g_assert(region_num < PCI_NUM_REGIONS);
1130 if (size & (size-1)) {
1131 fprintf(stderr, "ERROR: PCI region size must be pow2 "
1132 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
1133 exit(1);
1134 }
1135
1136 r = &pci_dev->io_regions[region_num];
1137 r->addr = PCI_BAR_UNMAPPED;
1138 r->size = size;
1139 r->type = type;
1140 r->memory = memory;
1141 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1142 ? pci_dev->bus->address_space_io
1143 : pci_dev->bus->address_space_mem;
1144
1145 wmask = ~(size - 1);
1146 if (region_num == PCI_ROM_SLOT) {
1147 /* ROM enable bit is writable */
1148 wmask |= PCI_ROM_ADDRESS_ENABLE;
1149 }
1150
1151 addr = pci_bar(pci_dev, region_num);
1152 pci_set_long(pci_dev->config + addr, type);
1153
1154 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1155 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1156 pci_set_quad(pci_dev->wmask + addr, wmask);
1157 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1158 } else {
1159 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1160 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1161 }
1162 }
1163
1164 static void pci_update_vga(PCIDevice *pci_dev)
1165 {
1166 uint16_t cmd;
1167
1168 if (!pci_dev->has_vga) {
1169 return;
1170 }
1171
1172 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1173
1174 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1175 cmd & PCI_COMMAND_MEMORY);
1176 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1177 cmd & PCI_COMMAND_IO);
1178 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1179 cmd & PCI_COMMAND_IO);
1180 }
1181
1182 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1183 MemoryRegion *io_lo, MemoryRegion *io_hi)
1184 {
1185 assert(!pci_dev->has_vga);
1186
1187 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1188 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1189 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
1190 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1191
1192 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1193 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1194 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1195 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1196
1197 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1198 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1199 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1200 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1201 pci_dev->has_vga = true;
1202
1203 pci_update_vga(pci_dev);
1204 }
1205
1206 void pci_unregister_vga(PCIDevice *pci_dev)
1207 {
1208 if (!pci_dev->has_vga) {
1209 return;
1210 }
1211
1212 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1213 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1214 memory_region_del_subregion(pci_dev->bus->address_space_io,
1215 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1216 memory_region_del_subregion(pci_dev->bus->address_space_io,
1217 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1218 pci_dev->has_vga = false;
1219 }
1220
1221 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1222 {
1223 return pci_dev->io_regions[region_num].addr;
1224 }
1225
1226 static pcibus_t pci_bar_address(PCIDevice *d,
1227 int reg, uint8_t type, pcibus_t size)
1228 {
1229 pcibus_t new_addr, last_addr;
1230 int bar = pci_bar(d, reg);
1231 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1232 Object *machine = qdev_get_machine();
1233 ObjectClass *oc = object_get_class(machine);
1234 MachineClass *mc = MACHINE_CLASS(oc);
1235 bool allow_0_address = mc->pci_allow_0_address;
1236
1237 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1238 if (!(cmd & PCI_COMMAND_IO)) {
1239 return PCI_BAR_UNMAPPED;
1240 }
1241 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1242 last_addr = new_addr + size - 1;
1243 /* Check if 32 bit BAR wraps around explicitly.
1244 * TODO: make priorities correct and remove this work around.
1245 */
1246 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1247 (!allow_0_address && new_addr == 0)) {
1248 return PCI_BAR_UNMAPPED;
1249 }
1250 return new_addr;
1251 }
1252
1253 if (!(cmd & PCI_COMMAND_MEMORY)) {
1254 return PCI_BAR_UNMAPPED;
1255 }
1256 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1257 new_addr = pci_get_quad(d->config + bar);
1258 } else {
1259 new_addr = pci_get_long(d->config + bar);
1260 }
1261 /* the ROM slot has a specific enable bit */
1262 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1263 return PCI_BAR_UNMAPPED;
1264 }
1265 new_addr &= ~(size - 1);
1266 last_addr = new_addr + size - 1;
1267 /* NOTE: we do not support wrapping */
1268 /* XXX: as we cannot support really dynamic
1269 mappings, we handle specific values as invalid
1270 mappings. */
1271 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1272 (!allow_0_address && new_addr == 0)) {
1273 return PCI_BAR_UNMAPPED;
1274 }
1275
1276 /* Now pcibus_t is 64bit.
1277 * Check if 32 bit BAR wraps around explicitly.
1278 * Without this, PC ide doesn't work well.
1279 * TODO: remove this work around.
1280 */
1281 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1282 return PCI_BAR_UNMAPPED;
1283 }
1284
1285 /*
1286 * OS is allowed to set BAR beyond its addressable
1287 * bits. For example, 32 bit OS can set 64bit bar
1288 * to >4G. Check it. TODO: we might need to support
1289 * it in the future for e.g. PAE.
1290 */
1291 if (last_addr >= HWADDR_MAX) {
1292 return PCI_BAR_UNMAPPED;
1293 }
1294
1295 return new_addr;
1296 }
1297
1298 static void pci_update_mappings(PCIDevice *d)
1299 {
1300 PCIIORegion *r;
1301 int i;
1302 pcibus_t new_addr;
1303
1304 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1305 r = &d->io_regions[i];
1306
1307 /* this region isn't registered */
1308 if (!r->size)
1309 continue;
1310
1311 new_addr = pci_bar_address(d, i, r->type, r->size);
1312
1313 /* This bar isn't changed */
1314 if (new_addr == r->addr)
1315 continue;
1316
1317 /* now do the real mapping */
1318 if (r->addr != PCI_BAR_UNMAPPED) {
1319 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
1320 PCI_SLOT(d->devfn),
1321 PCI_FUNC(d->devfn),
1322 i, r->addr, r->size);
1323 memory_region_del_subregion(r->address_space, r->memory);
1324 }
1325 r->addr = new_addr;
1326 if (r->addr != PCI_BAR_UNMAPPED) {
1327 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
1328 PCI_SLOT(d->devfn),
1329 PCI_FUNC(d->devfn),
1330 i, r->addr, r->size);
1331 memory_region_add_subregion_overlap(r->address_space,
1332 r->addr, r->memory, 1);
1333 }
1334 }
1335
1336 pci_update_vga(d);
1337 }
1338
1339 static inline int pci_irq_disabled(PCIDevice *d)
1340 {
1341 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1342 }
1343
1344 /* Called after interrupt disabled field update in config space,
1345 * assert/deassert interrupts if necessary.
1346 * Gets original interrupt disable bit value (before update). */
1347 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1348 {
1349 int i, disabled = pci_irq_disabled(d);
1350 if (disabled == was_irq_disabled)
1351 return;
1352 for (i = 0; i < PCI_NUM_PINS; ++i) {
1353 int state = pci_irq_state(d, i);
1354 pci_change_irq_level(d, i, disabled ? -state : state);
1355 }
1356 }
1357
1358 uint32_t pci_default_read_config(PCIDevice *d,
1359 uint32_t address, int len)
1360 {
1361 uint32_t val = 0;
1362
1363 memcpy(&val, d->config + address, len);
1364 return le32_to_cpu(val);
1365 }
1366
1367 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1368 {
1369 int i, was_irq_disabled = pci_irq_disabled(d);
1370 uint32_t val = val_in;
1371
1372 for (i = 0; i < l; val >>= 8, ++i) {
1373 uint8_t wmask = d->wmask[addr + i];
1374 uint8_t w1cmask = d->w1cmask[addr + i];
1375 assert(!(wmask & w1cmask));
1376 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1377 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1378 }
1379 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1380 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1381 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1382 range_covers_byte(addr, l, PCI_COMMAND))
1383 pci_update_mappings(d);
1384
1385 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1386 pci_update_irq_disabled(d, was_irq_disabled);
1387 memory_region_set_enabled(&d->bus_master_enable_region,
1388 pci_get_word(d->config + PCI_COMMAND)
1389 & PCI_COMMAND_MASTER);
1390 }
1391
1392 msi_write_config(d, addr, val_in, l);
1393 msix_write_config(d, addr, val_in, l);
1394 }
1395
1396 /***********************************************************/
1397 /* generic PCI irq support */
1398
1399 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1400 static void pci_irq_handler(void *opaque, int irq_num, int level)
1401 {
1402 PCIDevice *pci_dev = opaque;
1403 int change;
1404
1405 change = level - pci_irq_state(pci_dev, irq_num);
1406 if (!change)
1407 return;
1408
1409 pci_set_irq_state(pci_dev, irq_num, level);
1410 pci_update_irq_status(pci_dev);
1411 if (pci_irq_disabled(pci_dev))
1412 return;
1413 pci_change_irq_level(pci_dev, irq_num, change);
1414 }
1415
1416 static inline int pci_intx(PCIDevice *pci_dev)
1417 {
1418 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1419 }
1420
1421 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1422 {
1423 int intx = pci_intx(pci_dev);
1424
1425 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1426 }
1427
1428 void pci_set_irq(PCIDevice *pci_dev, int level)
1429 {
1430 int intx = pci_intx(pci_dev);
1431 pci_irq_handler(pci_dev, intx, level);
1432 }
1433
1434 /* Special hooks used by device assignment */
1435 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1436 {
1437 assert(pci_bus_is_root(bus));
1438 bus->route_intx_to_irq = route_intx_to_irq;
1439 }
1440
1441 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1442 {
1443 PCIBus *bus;
1444
1445 do {
1446 bus = dev->bus;
1447 pin = bus->map_irq(dev, pin);
1448 dev = bus->parent_dev;
1449 } while (dev);
1450
1451 if (!bus->route_intx_to_irq) {
1452 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1453 object_get_typename(OBJECT(bus->qbus.parent)));
1454 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1455 }
1456
1457 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1458 }
1459
1460 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1461 {
1462 return old->mode != new->mode || old->irq != new->irq;
1463 }
1464
1465 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1466 {
1467 PCIDevice *dev;
1468 PCIBus *sec;
1469 int i;
1470
1471 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1472 dev = bus->devices[i];
1473 if (dev && dev->intx_routing_notifier) {
1474 dev->intx_routing_notifier(dev);
1475 }
1476 }
1477
1478 QLIST_FOREACH(sec, &bus->child, sibling) {
1479 pci_bus_fire_intx_routing_notifier(sec);
1480 }
1481 }
1482
1483 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1484 PCIINTxRoutingNotifier notifier)
1485 {
1486 dev->intx_routing_notifier = notifier;
1487 }
1488
1489 /*
1490 * PCI-to-PCI bridge specification
1491 * 9.1: Interrupt routing. Table 9-1
1492 *
1493 * the PCI Express Base Specification, Revision 2.1
1494 * 2.2.8.1: INTx interrutp signaling - Rules
1495 * the Implementation Note
1496 * Table 2-20
1497 */
1498 /*
1499 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1500 * 0-origin unlike PCI interrupt pin register.
1501 */
1502 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1503 {
1504 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1505 }
1506
1507 /***********************************************************/
1508 /* monitor info on PCI */
1509
1510 typedef struct {
1511 uint16_t class;
1512 const char *desc;
1513 const char *fw_name;
1514 uint16_t fw_ign_bits;
1515 } pci_class_desc;
1516
1517 static const pci_class_desc pci_class_descriptions[] =
1518 {
1519 { 0x0001, "VGA controller", "display"},
1520 { 0x0100, "SCSI controller", "scsi"},
1521 { 0x0101, "IDE controller", "ide"},
1522 { 0x0102, "Floppy controller", "fdc"},
1523 { 0x0103, "IPI controller", "ipi"},
1524 { 0x0104, "RAID controller", "raid"},
1525 { 0x0106, "SATA controller"},
1526 { 0x0107, "SAS controller"},
1527 { 0x0180, "Storage controller"},
1528 { 0x0200, "Ethernet controller", "ethernet"},
1529 { 0x0201, "Token Ring controller", "token-ring"},
1530 { 0x0202, "FDDI controller", "fddi"},
1531 { 0x0203, "ATM controller", "atm"},
1532 { 0x0280, "Network controller"},
1533 { 0x0300, "VGA controller", "display", 0x00ff},
1534 { 0x0301, "XGA controller"},
1535 { 0x0302, "3D controller"},
1536 { 0x0380, "Display controller"},
1537 { 0x0400, "Video controller", "video"},
1538 { 0x0401, "Audio controller", "sound"},
1539 { 0x0402, "Phone"},
1540 { 0x0403, "Audio controller", "sound"},
1541 { 0x0480, "Multimedia controller"},
1542 { 0x0500, "RAM controller", "memory"},
1543 { 0x0501, "Flash controller", "flash"},
1544 { 0x0580, "Memory controller"},
1545 { 0x0600, "Host bridge", "host"},
1546 { 0x0601, "ISA bridge", "isa"},
1547 { 0x0602, "EISA bridge", "eisa"},
1548 { 0x0603, "MC bridge", "mca"},
1549 { 0x0604, "PCI bridge", "pci-bridge"},
1550 { 0x0605, "PCMCIA bridge", "pcmcia"},
1551 { 0x0606, "NUBUS bridge", "nubus"},
1552 { 0x0607, "CARDBUS bridge", "cardbus"},
1553 { 0x0608, "RACEWAY bridge"},
1554 { 0x0680, "Bridge"},
1555 { 0x0700, "Serial port", "serial"},
1556 { 0x0701, "Parallel port", "parallel"},
1557 { 0x0800, "Interrupt controller", "interrupt-controller"},
1558 { 0x0801, "DMA controller", "dma-controller"},
1559 { 0x0802, "Timer", "timer"},
1560 { 0x0803, "RTC", "rtc"},
1561 { 0x0900, "Keyboard", "keyboard"},
1562 { 0x0901, "Pen", "pen"},
1563 { 0x0902, "Mouse", "mouse"},
1564 { 0x0A00, "Dock station", "dock", 0x00ff},
1565 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1566 { 0x0c00, "Fireware contorller", "fireware"},
1567 { 0x0c01, "Access bus controller", "access-bus"},
1568 { 0x0c02, "SSA controller", "ssa"},
1569 { 0x0c03, "USB controller", "usb"},
1570 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1571 { 0x0c05, "SMBus"},
1572 { 0, NULL}
1573 };
1574
1575 static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1576 void (*fn)(PCIBus *b,
1577 PCIDevice *d,
1578 void *opaque),
1579 void *opaque)
1580 {
1581 PCIDevice *d;
1582 int devfn;
1583
1584 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1585 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1586 if (d) {
1587 fn(bus, d, opaque);
1588 }
1589 }
1590 }
1591
1592 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1593 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1594 void *opaque)
1595 {
1596 bus = pci_find_bus_nr(bus, bus_num);
1597
1598 if (bus) {
1599 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1600 }
1601 }
1602
1603 static void pci_for_each_device_under_bus(PCIBus *bus,
1604 void (*fn)(PCIBus *b, PCIDevice *d,
1605 void *opaque),
1606 void *opaque)
1607 {
1608 PCIDevice *d;
1609 int devfn;
1610
1611 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1612 d = bus->devices[devfn];
1613 if (d) {
1614 fn(bus, d, opaque);
1615 }
1616 }
1617 }
1618
1619 void pci_for_each_device(PCIBus *bus, int bus_num,
1620 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1621 void *opaque)
1622 {
1623 bus = pci_find_bus_nr(bus, bus_num);
1624
1625 if (bus) {
1626 pci_for_each_device_under_bus(bus, fn, opaque);
1627 }
1628 }
1629
1630 static const pci_class_desc *get_class_desc(int class)
1631 {
1632 const pci_class_desc *desc;
1633
1634 desc = pci_class_descriptions;
1635 while (desc->desc && class != desc->class) {
1636 desc++;
1637 }
1638
1639 return desc;
1640 }
1641
1642 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1643
1644 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1645 {
1646 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1647 int i;
1648
1649 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1650 const PCIIORegion *r = &dev->io_regions[i];
1651 PciMemoryRegionList *region;
1652
1653 if (!r->size) {
1654 continue;
1655 }
1656
1657 region = g_malloc0(sizeof(*region));
1658 region->value = g_malloc0(sizeof(*region->value));
1659
1660 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1661 region->value->type = g_strdup("io");
1662 } else {
1663 region->value->type = g_strdup("memory");
1664 region->value->has_prefetch = true;
1665 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1666 region->value->has_mem_type_64 = true;
1667 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1668 }
1669
1670 region->value->bar = i;
1671 region->value->address = r->addr;
1672 region->value->size = r->size;
1673
1674 /* XXX: waiting for the qapi to support GSList */
1675 if (!cur_item) {
1676 head = cur_item = region;
1677 } else {
1678 cur_item->next = region;
1679 cur_item = region;
1680 }
1681 }
1682
1683 return head;
1684 }
1685
1686 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1687 int bus_num)
1688 {
1689 PciBridgeInfo *info;
1690 PciMemoryRange *range;
1691
1692 info = g_new0(PciBridgeInfo, 1);
1693
1694 info->bus = g_new0(PciBusInfo, 1);
1695 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1696 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1697 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1698
1699 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1700 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1701 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1702
1703 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1704 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1705 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1706
1707 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1708 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1709 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1710
1711 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1712 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1713 if (child_bus) {
1714 info->has_devices = true;
1715 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1716 }
1717 }
1718
1719 return info;
1720 }
1721
1722 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1723 int bus_num)
1724 {
1725 const pci_class_desc *desc;
1726 PciDeviceInfo *info;
1727 uint8_t type;
1728 int class;
1729
1730 info = g_new0(PciDeviceInfo, 1);
1731 info->bus = bus_num;
1732 info->slot = PCI_SLOT(dev->devfn);
1733 info->function = PCI_FUNC(dev->devfn);
1734
1735 info->class_info = g_new0(PciDeviceClass, 1);
1736 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1737 info->class_info->q_class = class;
1738 desc = get_class_desc(class);
1739 if (desc->desc) {
1740 info->class_info->has_desc = true;
1741 info->class_info->desc = g_strdup(desc->desc);
1742 }
1743
1744 info->id = g_new0(PciDeviceId, 1);
1745 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1746 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1747 info->regions = qmp_query_pci_regions(dev);
1748 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1749
1750 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1751 info->has_irq = true;
1752 info->irq = dev->config[PCI_INTERRUPT_LINE];
1753 }
1754
1755 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1756 if (type == PCI_HEADER_TYPE_BRIDGE) {
1757 info->has_pci_bridge = true;
1758 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1759 }
1760
1761 return info;
1762 }
1763
1764 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1765 {
1766 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1767 PCIDevice *dev;
1768 int devfn;
1769
1770 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1771 dev = bus->devices[devfn];
1772 if (dev) {
1773 info = g_malloc0(sizeof(*info));
1774 info->value = qmp_query_pci_device(dev, bus, bus_num);
1775
1776 /* XXX: waiting for the qapi to support GSList */
1777 if (!cur_item) {
1778 head = cur_item = info;
1779 } else {
1780 cur_item->next = info;
1781 cur_item = info;
1782 }
1783 }
1784 }
1785
1786 return head;
1787 }
1788
1789 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1790 {
1791 PciInfo *info = NULL;
1792
1793 bus = pci_find_bus_nr(bus, bus_num);
1794 if (bus) {
1795 info = g_malloc0(sizeof(*info));
1796 info->bus = bus_num;
1797 info->devices = qmp_query_pci_devices(bus, bus_num);
1798 }
1799
1800 return info;
1801 }
1802
1803 PciInfoList *qmp_query_pci(Error **errp)
1804 {
1805 PciInfoList *info, *head = NULL, *cur_item = NULL;
1806 PCIHostState *host_bridge;
1807
1808 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1809 info = g_malloc0(sizeof(*info));
1810 info->value = qmp_query_pci_bus(host_bridge->bus,
1811 pci_bus_num(host_bridge->bus));
1812
1813 /* XXX: waiting for the qapi to support GSList */
1814 if (!cur_item) {
1815 head = cur_item = info;
1816 } else {
1817 cur_item->next = info;
1818 cur_item = info;
1819 }
1820 }
1821
1822 return head;
1823 }
1824
1825 static const char * const pci_nic_models[] = {
1826 #if !defined(CONFIG_WIN32)
1827 "atheros_wlan",
1828 #endif
1829 "dp83816",
1830 "e100",
1831 "ne2k_pci",
1832 "i82551",
1833 "i82557a",
1834 "i82557b",
1835 "i82557c",
1836 "i82558b",
1837 "i82559c",
1838 "i82559er",
1839 "i82801",
1840 "rtl8139",
1841 "e1000",
1842 "pcnet",
1843 "tnetw1130",
1844 "virtio",
1845 "sungem",
1846 NULL
1847 };
1848
1849 static const char * const pci_nic_names[] = {
1850 #if !defined(CONFIG_WIN32)
1851 "atheros_wlan",
1852 #endif
1853 "dp83816",
1854 "e100",
1855 "ne2k_pci",
1856 "i82551",
1857 "i82557a",
1858 "i82557b",
1859 "i82557c",
1860 "i82558b",
1861 "i82559c",
1862 "i82559er",
1863 "i82801",
1864 "rtl8139",
1865 "e1000",
1866 "pcnet",
1867 "tnetw1130",
1868 "virtio-net-pci",
1869 "sungem",
1870 NULL
1871 };
1872
1873 /* Initialize a PCI NIC. */
1874 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1875 const char *default_model,
1876 const char *default_devaddr)
1877 {
1878 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1879 PCIBus *bus;
1880 PCIDevice *pci_dev;
1881 DeviceState *dev;
1882 int devfn;
1883 int i;
1884
1885 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1886 exit(0);
1887 }
1888
1889 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1890 if (i < 0) {
1891 exit(1);
1892 }
1893
1894 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1895 if (!bus) {
1896 error_report("Invalid PCI device address %s for device %s",
1897 devaddr, pci_nic_names[i]);
1898 exit(1);
1899 }
1900
1901 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1902 dev = &pci_dev->qdev;
1903 qdev_set_nic_properties(dev, nd);
1904 qdev_init_nofail(dev);
1905
1906 return pci_dev;
1907 }
1908
1909 PCIDevice *pci_vga_init(PCIBus *bus)
1910 {
1911 switch (vga_interface_type) {
1912 case VGA_CIRRUS:
1913 return pci_create_simple(bus, -1, "cirrus-vga");
1914 case VGA_QXL:
1915 return pci_create_simple(bus, -1, "qxl-vga");
1916 case VGA_STD:
1917 return pci_create_simple(bus, -1, "VGA");
1918 case VGA_VMWARE:
1919 return pci_create_simple(bus, -1, "vmware-svga");
1920 case VGA_VIRTIO:
1921 return pci_create_simple(bus, -1, "virtio-vga");
1922 case VGA_NONE:
1923 default: /* Other non-PCI types. Checking for unsupported types is already
1924 done in vl.c. */
1925 return NULL;
1926 }
1927 }
1928
1929 /* Whether a given bus number is in range of the secondary
1930 * bus of the given bridge device. */
1931 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1932 {
1933 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1934 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1935 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1936 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1937 }
1938
1939 /* Whether a given bus number is in a range of a root bus */
1940 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1941 {
1942 int i;
1943
1944 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1945 PCIDevice *dev = bus->devices[i];
1946
1947 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1948 if (pci_secondary_bus_in_range(dev, bus_num)) {
1949 return true;
1950 }
1951 }
1952 }
1953
1954 return false;
1955 }
1956
1957 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1958 {
1959 PCIBus *sec;
1960
1961 if (!bus) {
1962 return NULL;
1963 }
1964
1965 if (pci_bus_num(bus) == bus_num) {
1966 return bus;
1967 }
1968
1969 /* Consider all bus numbers in range for the host pci bridge. */
1970 if (!pci_bus_is_root(bus) &&
1971 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1972 return NULL;
1973 }
1974
1975 /* try child bus */
1976 for (; bus; bus = sec) {
1977 QLIST_FOREACH(sec, &bus->child, sibling) {
1978 if (pci_bus_num(sec) == bus_num) {
1979 return sec;
1980 }
1981 /* PXB buses assumed to be children of bus 0 */
1982 if (pci_bus_is_root(sec)) {
1983 if (pci_root_bus_in_range(sec, bus_num)) {
1984 break;
1985 }
1986 } else {
1987 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1988 break;
1989 }
1990 }
1991 }
1992 }
1993
1994 return NULL;
1995 }
1996
1997 void pci_for_each_bus_depth_first(PCIBus *bus,
1998 void *(*begin)(PCIBus *bus, void *parent_state),
1999 void (*end)(PCIBus *bus, void *state),
2000 void *parent_state)
2001 {
2002 PCIBus *sec;
2003 void *state;
2004
2005 if (!bus) {
2006 return;
2007 }
2008
2009 if (begin) {
2010 state = begin(bus, parent_state);
2011 } else {
2012 state = parent_state;
2013 }
2014
2015 QLIST_FOREACH(sec, &bus->child, sibling) {
2016 pci_for_each_bus_depth_first(sec, begin, end, state);
2017 }
2018
2019 if (end) {
2020 end(bus, state);
2021 }
2022 }
2023
2024
2025 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
2026 {
2027 bus = pci_find_bus_nr(bus, bus_num);
2028
2029 if (!bus)
2030 return NULL;
2031
2032 return bus->devices[devfn];
2033 }
2034
2035 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2036 {
2037 PCIDevice *pci_dev = (PCIDevice *)qdev;
2038 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2039 Error *local_err = NULL;
2040 PCIBus *bus;
2041 bool is_default_rom;
2042
2043 /* initialize cap_present for pci_is_express() and pci_config_size() */
2044 if (pc->is_express) {
2045 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2046 }
2047
2048 bus = PCI_BUS(qdev_get_parent_bus(qdev));
2049 pci_dev = do_pci_register_device(pci_dev, bus,
2050 object_get_typename(OBJECT(qdev)),
2051 pci_dev->devfn, errp);
2052 if (pci_dev == NULL)
2053 return;
2054
2055 if (pc->realize) {
2056 pc->realize(pci_dev, &local_err);
2057 if (local_err) {
2058 error_propagate(errp, local_err);
2059 do_pci_unregister_device(pci_dev);
2060 return;
2061 }
2062 }
2063
2064 /* rom loading */
2065 is_default_rom = false;
2066 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2067 pci_dev->romfile = g_strdup(pc->romfile);
2068 is_default_rom = true;
2069 }
2070
2071 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2072 if (local_err) {
2073 error_propagate(errp, local_err);
2074 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2075 return;
2076 }
2077 }
2078
2079 static void pci_default_realize(PCIDevice *dev, Error **errp)
2080 {
2081 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2082
2083 if (pc->init) {
2084 if (pc->init(dev) < 0) {
2085 error_setg(errp, "Device initialization failed");
2086 return;
2087 }
2088 }
2089 }
2090
2091 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2092 const char *name)
2093 {
2094 DeviceState *dev;
2095
2096 dev = qdev_create(&bus->qbus, name);
2097 qdev_prop_set_int32(dev, "addr", devfn);
2098 qdev_prop_set_bit(dev, "multifunction", multifunction);
2099 return PCI_DEVICE(dev);
2100 }
2101
2102 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2103 bool multifunction,
2104 const char *name)
2105 {
2106 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2107 qdev_init_nofail(&dev->qdev);
2108 return dev;
2109 }
2110
2111 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2112 {
2113 return pci_create_multifunction(bus, devfn, false, name);
2114 }
2115
2116 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2117 {
2118 return pci_create_simple_multifunction(bus, devfn, false, name);
2119 }
2120
2121 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2122 {
2123 int offset = PCI_CONFIG_HEADER_SIZE;
2124 int i;
2125 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2126 if (pdev->used[i])
2127 offset = i + 1;
2128 else if (i - offset + 1 == size)
2129 return offset;
2130 }
2131 return 0;
2132 }
2133
2134 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2135 uint8_t *prev_p)
2136 {
2137 uint8_t next, prev;
2138
2139 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2140 return 0;
2141
2142 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2143 prev = next + PCI_CAP_LIST_NEXT)
2144 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2145 break;
2146
2147 if (prev_p)
2148 *prev_p = prev;
2149 return next;
2150 }
2151
2152 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2153 {
2154 uint8_t next, prev, found = 0;
2155
2156 if (!(pdev->used[offset])) {
2157 return 0;
2158 }
2159
2160 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2161
2162 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2163 prev = next + PCI_CAP_LIST_NEXT) {
2164 if (next <= offset && next > found) {
2165 found = next;
2166 }
2167 }
2168 return found;
2169 }
2170
2171 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2172 This is needed for an option rom which is used for more than one device. */
2173 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2174 {
2175 uint16_t vendor_id;
2176 uint16_t device_id;
2177 uint16_t rom_vendor_id;
2178 uint16_t rom_device_id;
2179 uint16_t rom_magic;
2180 uint16_t pcir_offset;
2181 uint8_t checksum;
2182
2183 /* Words in rom data are little endian (like in PCI configuration),
2184 so they can be read / written with pci_get_word / pci_set_word. */
2185
2186 /* Only a valid rom will be patched. */
2187 rom_magic = pci_get_word(ptr);
2188 if (rom_magic != 0xaa55) {
2189 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2190 return;
2191 }
2192 pcir_offset = pci_get_word(ptr + 0x18);
2193 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2194 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2195 return;
2196 }
2197
2198 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2199 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2200 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2201 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2202
2203 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2204 vendor_id, device_id, rom_vendor_id, rom_device_id);
2205
2206 checksum = ptr[6];
2207
2208 if (vendor_id != rom_vendor_id) {
2209 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2210 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2211 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2212 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2213 ptr[6] = checksum;
2214 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2215 }
2216
2217 if (device_id != rom_device_id) {
2218 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2219 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2220 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2221 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2222 ptr[6] = checksum;
2223 pci_set_word(ptr + pcir_offset + 6, device_id);
2224 }
2225 }
2226
2227 /* Add an option rom for the device */
2228 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2229 Error **errp)
2230 {
2231 int size;
2232 char *path;
2233 void *ptr;
2234 char name[32];
2235 const VMStateDescription *vmsd;
2236
2237 if (!pdev->romfile)
2238 return;
2239 if (strlen(pdev->romfile) == 0)
2240 return;
2241
2242 if (!pdev->rom_bar) {
2243 /*
2244 * Load rom via fw_cfg instead of creating a rom bar,
2245 * for 0.11 compatibility.
2246 */
2247 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2248
2249 /*
2250 * Hot-plugged devices can't use the option ROM
2251 * if the rom bar is disabled.
2252 */
2253 if (DEVICE(pdev)->hotplugged) {
2254 error_setg(errp, "Hot-plugged device without ROM bar"
2255 " can't have an option ROM");
2256 return;
2257 }
2258
2259 if (class == 0x0300) {
2260 rom_add_vga(pdev->romfile);
2261 } else {
2262 rom_add_option(pdev->romfile, -1);
2263 }
2264 return;
2265 }
2266
2267 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2268 if (path == NULL) {
2269 path = g_strdup(pdev->romfile);
2270 }
2271
2272 size = get_image_size(path);
2273 if (size < 0) {
2274 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2275 g_free(path);
2276 return;
2277 } else if (size == 0) {
2278 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2279 g_free(path);
2280 return;
2281 }
2282 size = pow2ceil(size);
2283
2284 vmsd = qdev_get_vmsd(DEVICE(pdev));
2285
2286 if (vmsd) {
2287 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2288 } else {
2289 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2290 }
2291 pdev->has_rom = true;
2292 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2293 ptr = memory_region_get_ram_ptr(&pdev->rom);
2294 load_image(path, ptr);
2295 g_free(path);
2296
2297 if (is_default_rom) {
2298 /* Only the default rom images will be patched (if needed). */
2299 pci_patch_ids(pdev, ptr, size);
2300 }
2301
2302 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2303 }
2304
2305 static void pci_del_option_rom(PCIDevice *pdev)
2306 {
2307 if (!pdev->has_rom)
2308 return;
2309
2310 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2311 pdev->has_rom = false;
2312 }
2313
2314 /*
2315 * On success, pci_add_capability() returns a positive value
2316 * that the offset of the pci capability.
2317 * On failure, it sets an error and returns a negative error
2318 * code.
2319 */
2320 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2321 uint8_t offset, uint8_t size,
2322 Error **errp)
2323 {
2324 uint8_t *config;
2325 int i, overlapping_cap;
2326
2327 if (!offset) {
2328 offset = pci_find_space(pdev, size);
2329 /* out of PCI config space is programming error */
2330 assert(offset);
2331 } else {
2332 /* Verify that capabilities don't overlap. Note: device assignment
2333 * depends on this check to verify that the device is not broken.
2334 * Should never trigger for emulated devices, but it's helpful
2335 * for debugging these. */
2336 for (i = offset; i < offset + size; i++) {
2337 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2338 if (overlapping_cap) {
2339 error_setg(errp, "%s:%02x:%02x.%x "
2340 "Attempt to add PCI capability %x at offset "
2341 "%x overlaps existing capability %x at offset %x",
2342 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2343 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2344 cap_id, offset, overlapping_cap, i);
2345 return -EINVAL;
2346 }
2347 }
2348 }
2349
2350 config = pdev->config + offset;
2351 config[PCI_CAP_LIST_ID] = cap_id;
2352 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2353 pdev->config[PCI_CAPABILITY_LIST] = offset;
2354 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2355 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2356 /* Make capability read-only by default */
2357 memset(pdev->wmask + offset, 0, size);
2358 /* Check capability by default */
2359 memset(pdev->cmask + offset, 0xFF, size);
2360 return offset;
2361 }
2362
2363 /* Unlink capability from the pci config space. */
2364 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2365 {
2366 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2367 if (!offset)
2368 return;
2369 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2370 /* Make capability writable again */
2371 memset(pdev->wmask + offset, 0xff, size);
2372 memset(pdev->w1cmask + offset, 0, size);
2373 /* Clear cmask as device-specific registers can't be checked */
2374 memset(pdev->cmask + offset, 0, size);
2375 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2376
2377 if (!pdev->config[PCI_CAPABILITY_LIST])
2378 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2379 }
2380
2381 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2382 {
2383 return pci_find_capability_list(pdev, cap_id, NULL);
2384 }
2385
2386 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2387 {
2388 PCIDevice *d = (PCIDevice *)dev;
2389 const pci_class_desc *desc;
2390 char ctxt[64];
2391 PCIIORegion *r;
2392 int i, class;
2393
2394 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2395 desc = pci_class_descriptions;
2396 while (desc->desc && class != desc->class)
2397 desc++;
2398 if (desc->desc) {
2399 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2400 } else {
2401 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2402 }
2403
2404 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2405 "pci id %04x:%04x (sub %04x:%04x)\n",
2406 indent, "", ctxt, pci_bus_num(d->bus),
2407 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2408 pci_get_word(d->config + PCI_VENDOR_ID),
2409 pci_get_word(d->config + PCI_DEVICE_ID),
2410 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2411 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2412 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2413 r = &d->io_regions[i];
2414 if (!r->size)
2415 continue;
2416 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2417 " [0x%"FMT_PCIBUS"]\n",
2418 indent, "",
2419 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2420 r->addr, r->addr + r->size - 1);
2421 }
2422 }
2423
2424 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2425 {
2426 PCIDevice *d = (PCIDevice *)dev;
2427 const char *name = NULL;
2428 const pci_class_desc *desc = pci_class_descriptions;
2429 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2430
2431 while (desc->desc &&
2432 (class & ~desc->fw_ign_bits) !=
2433 (desc->class & ~desc->fw_ign_bits)) {
2434 desc++;
2435 }
2436
2437 if (desc->desc) {
2438 name = desc->fw_name;
2439 }
2440
2441 if (name) {
2442 pstrcpy(buf, len, name);
2443 } else {
2444 snprintf(buf, len, "pci%04x,%04x",
2445 pci_get_word(d->config + PCI_VENDOR_ID),
2446 pci_get_word(d->config + PCI_DEVICE_ID));
2447 }
2448
2449 return buf;
2450 }
2451
2452 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2453 {
2454 PCIDevice *d = (PCIDevice *)dev;
2455 char path[50], name[33];
2456 int off;
2457
2458 off = snprintf(path, sizeof(path), "%s@%x",
2459 pci_dev_fw_name(dev, name, sizeof name),
2460 PCI_SLOT(d->devfn));
2461 if (PCI_FUNC(d->devfn))
2462 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2463 return g_strdup(path);
2464 }
2465
2466 static char *pcibus_get_dev_path(DeviceState *dev)
2467 {
2468 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2469 PCIDevice *t;
2470 int slot_depth;
2471 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2472 * 00 is added here to make this format compatible with
2473 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2474 * Slot.Function list specifies the slot and function numbers for all
2475 * devices on the path from root to the specific device. */
2476 const char *root_bus_path;
2477 int root_bus_len;
2478 char slot[] = ":SS.F";
2479 int slot_len = sizeof slot - 1 /* For '\0' */;
2480 int path_len;
2481 char *path, *p;
2482 int s;
2483
2484 root_bus_path = pci_root_bus_path(d);
2485 root_bus_len = strlen(root_bus_path);
2486
2487 /* Calculate # of slots on path between device and root. */;
2488 slot_depth = 0;
2489 for (t = d; t; t = t->bus->parent_dev) {
2490 ++slot_depth;
2491 }
2492
2493 path_len = root_bus_len + slot_len * slot_depth;
2494
2495 /* Allocate memory, fill in the terminating null byte. */
2496 path = g_malloc(path_len + 1 /* For '\0' */);
2497 path[path_len] = '\0';
2498
2499 memcpy(path, root_bus_path, root_bus_len);
2500
2501 /* Fill in slot numbers. We walk up from device to root, so need to print
2502 * them in the reverse order, last to first. */
2503 p = path + path_len;
2504 for (t = d; t; t = t->bus->parent_dev) {
2505 p -= slot_len;
2506 s = snprintf(slot, sizeof slot, ":%02x.%x",
2507 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2508 assert(s == slot_len);
2509 memcpy(p, slot, slot_len);
2510 }
2511
2512 return path;
2513 }
2514
2515 static int pci_qdev_find_recursive(PCIBus *bus,
2516 const char *id, PCIDevice **pdev)
2517 {
2518 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2519 if (!qdev) {
2520 return -ENODEV;
2521 }
2522
2523 /* roughly check if given qdev is pci device */
2524 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2525 *pdev = PCI_DEVICE(qdev);
2526 return 0;
2527 }
2528 return -EINVAL;
2529 }
2530
2531 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2532 {
2533 PCIHostState *host_bridge;
2534 int rc = -ENODEV;
2535
2536 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2537 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2538 if (!tmp) {
2539 rc = 0;
2540 break;
2541 }
2542 if (tmp != -ENODEV) {
2543 rc = tmp;
2544 }
2545 }
2546
2547 return rc;
2548 }
2549
2550 MemoryRegion *pci_address_space(PCIDevice *dev)
2551 {
2552 return dev->bus->address_space_mem;
2553 }
2554
2555 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2556 {
2557 return dev->bus->address_space_io;
2558 }
2559
2560 static void pci_device_class_init(ObjectClass *klass, void *data)
2561 {
2562 DeviceClass *k = DEVICE_CLASS(klass);
2563 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2564
2565 k->realize = pci_qdev_realize;
2566 k->unrealize = pci_qdev_unrealize;
2567 k->bus_type = TYPE_PCI_BUS;
2568 k->props = pci_props;
2569 pc->realize = pci_default_realize;
2570 }
2571
2572 static void pci_device_class_base_init(ObjectClass *klass, void *data)
2573 {
2574 if (!object_class_is_abstract(klass)) {
2575 ObjectClass *conventional =
2576 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2577 ObjectClass *pcie =
2578 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2579 assert(conventional || pcie);
2580 }
2581 }
2582
2583 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2584 {
2585 PCIBus *bus = PCI_BUS(dev->bus);
2586 PCIBus *iommu_bus = bus;
2587
2588 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2589 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus);
2590 }
2591 if (iommu_bus && iommu_bus->iommu_fn) {
2592 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2593 }
2594 return &address_space_memory;
2595 }
2596
2597 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2598 {
2599 bus->iommu_fn = fn;
2600 bus->iommu_opaque = opaque;
2601 }
2602
2603 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2604 {
2605 Range *range = opaque;
2606 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2607 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2608 int i;
2609
2610 if (!(cmd & PCI_COMMAND_MEMORY)) {
2611 return;
2612 }
2613
2614 if (pc->is_bridge) {
2615 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2616 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2617
2618 base = MAX(base, 0x1ULL << 32);
2619
2620 if (limit >= base) {
2621 Range pref_range;
2622 range_set_bounds(&pref_range, base, limit);
2623 range_extend(range, &pref_range);
2624 }
2625 }
2626 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2627 PCIIORegion *r = &dev->io_regions[i];
2628 pcibus_t lob, upb;
2629 Range region_range;
2630
2631 if (!r->size ||
2632 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2633 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2634 continue;
2635 }
2636
2637 lob = pci_bar_address(dev, i, r->type, r->size);
2638 upb = lob + r->size - 1;
2639 if (lob == PCI_BAR_UNMAPPED) {
2640 continue;
2641 }
2642
2643 lob = MAX(lob, 0x1ULL << 32);
2644
2645 if (upb >= lob) {
2646 range_set_bounds(&region_range, lob, upb);
2647 range_extend(range, &region_range);
2648 }
2649 }
2650 }
2651
2652 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2653 {
2654 range_make_empty(range);
2655 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2656 }
2657
2658 static bool pcie_has_upstream_port(PCIDevice *dev)
2659 {
2660 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus);
2661
2662 /* Device associated with an upstream port.
2663 * As there are several types of these, it's easier to check the
2664 * parent device: upstream ports are always connected to
2665 * root or downstream ports.
2666 */
2667 return parent_dev &&
2668 pci_is_express(parent_dev) &&
2669 parent_dev->exp.exp_cap &&
2670 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2671 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2672 }
2673
2674 PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2675 {
2676 if(pcie_has_upstream_port(pci_dev)) {
2677 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2678 return pci_dev->bus->devices[0];
2679 } else {
2680 /* Other bus types might support multiple devices at slots 0-31 */
2681 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2682 }
2683 }
2684
2685 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2686 {
2687 MSIMessage msg;
2688 if (msix_enabled(dev)) {
2689 msg = msix_get_message(dev, vector);
2690 } else if (msi_enabled(dev)) {
2691 msg = msi_get_message(dev, vector);
2692 } else {
2693 /* Should never happen */
2694 error_report("%s: unknown interrupt type", __func__);
2695 abort();
2696 }
2697 return msg;
2698 }
2699
2700 static const TypeInfo pci_device_type_info = {
2701 .name = TYPE_PCI_DEVICE,
2702 .parent = TYPE_DEVICE,
2703 .instance_size = sizeof(PCIDevice),
2704 .abstract = true,
2705 .class_size = sizeof(PCIDeviceClass),
2706 .class_init = pci_device_class_init,
2707 .class_base_init = pci_device_class_base_init,
2708 };
2709
2710 static void pci_register_types(void)
2711 {
2712 type_register_static(&pci_bus_info);
2713 type_register_static(&pcie_bus_info);
2714 type_register_static(&conventional_pci_interface_info);
2715 type_register_static(&pcie_interface_info);
2716 type_register_static(&pci_device_type_info);
2717 }
2718
2719 type_init(pci_register_types)
AR7 emulation for QEMU