4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 static void QEMU_NORETURN
32 raise_exception(CPUARMState
*env
, uint32_t excp
,
33 uint32_t syndrome
, uint32_t target_el
)
35 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
37 assert(!excp_is_internal(excp
));
38 cs
->exception_index
= excp
;
39 env
->exception
.syndrome
= syndrome
;
40 env
->exception
.target_el
= target_el
;
44 static int exception_target_el(CPUARMState
*env
)
46 int target_el
= MAX(1, arm_current_el(env
));
48 /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
49 * to EL3 in this case.
51 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
58 uint32_t HELPER(neon_tbl
)(CPUARMState
*env
, uint32_t ireg
, uint32_t def
,
59 uint32_t rn
, uint32_t maxindex
)
66 table
= (uint64_t *)&env
->vfp
.regs
[rn
];
68 for (shift
= 0; shift
< 32; shift
+= 8) {
69 index
= (ireg
>> shift
) & 0xff;
70 if (index
< maxindex
) {
71 tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
74 val
|= def
& (0xff << shift
);
80 #if !defined(CONFIG_USER_ONLY)
82 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
83 unsigned int target_el
,
84 bool same_el
, bool ea
,
85 bool s1ptw
, bool is_write
,
90 /* ISV is only set for data aborts routed to EL2 and
91 * never for stage-1 page table walks faulting on stage 2.
93 * Furthermore, ISV is only set for certain kinds of load/stores.
94 * If the template syndrome does not have ISV set, we should leave
97 * See ARMv8 specs, D7-1974:
98 * ISS encoding for an exception from a Data Abort, the
101 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
102 syn
= syn_data_abort_no_iss(same_el
,
103 ea
, 0, s1ptw
, is_write
, fsc
);
105 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
106 * syndrome created at translation time.
107 * Now we create the runtime syndrome with the remaining fields.
109 syn
= syn_data_abort_with_iss(same_el
,
111 ea
, 0, s1ptw
, is_write
, fsc
,
113 /* Merge the runtime syndrome with the template syndrome. */
119 static void deliver_fault(ARMCPU
*cpu
, vaddr addr
, MMUAccessType access_type
,
120 int mmu_idx
, ARMMMUFaultInfo
*fi
)
122 CPUARMState
*env
= &cpu
->env
;
125 uint32_t syn
, exc
, fsr
, fsc
;
126 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
128 target_el
= exception_target_el(env
);
131 env
->cp15
.hpfar_el2
= extract64(fi
->s2addr
, 12, 47) << 4;
133 same_el
= (arm_current_el(env
) == target_el
);
135 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
136 arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
137 /* LPAE format fault status register : bottom 6 bits are
138 * status code in the same form as needed for syndrome
140 fsr
= arm_fi_to_lfsc(fi
);
141 fsc
= extract32(fsr
, 0, 6);
143 fsr
= arm_fi_to_sfsc(fi
);
144 /* Short format FSR : this fault will never actually be reported
145 * to an EL that uses a syndrome register. Use a (currently)
146 * reserved FSR code in case the constructed syndrome does leak
147 * into the guest somehow.
152 if (access_type
== MMU_INST_FETCH
) {
153 syn
= syn_insn_abort(same_el
, fi
->ea
, fi
->s1ptw
, fsc
);
154 exc
= EXCP_PREFETCH_ABORT
;
156 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
157 same_el
, fi
->ea
, fi
->s1ptw
,
158 access_type
== MMU_DATA_STORE
,
160 if (access_type
== MMU_DATA_STORE
161 && arm_feature(env
, ARM_FEATURE_V6
)) {
164 exc
= EXCP_DATA_ABORT
;
167 env
->exception
.vaddress
= addr
;
168 env
->exception
.fsr
= fsr
;
169 raise_exception(env
, exc
, syn
, target_el
);
172 /* try to fill the TLB and return an exception if error. If retaddr is
173 * NULL, it means that the function was called in C code (i.e. not
174 * from generated code or from helper.c)
176 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
177 int mmu_idx
, uintptr_t retaddr
)
180 ARMMMUFaultInfo fi
= {};
182 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fi
);
184 ARMCPU
*cpu
= ARM_CPU(cs
);
187 /* now we have a real cpu fault */
188 cpu_restore_state(cs
, retaddr
);
191 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
195 /* Raise a data fault alignment exception for the specified virtual address */
196 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
197 MMUAccessType access_type
,
198 int mmu_idx
, uintptr_t retaddr
)
200 ARMCPU
*cpu
= ARM_CPU(cs
);
201 ARMMMUFaultInfo fi
= {};
204 /* now we have a real cpu fault */
205 cpu_restore_state(cs
, retaddr
);
208 fi
.type
= ARMFault_Alignment
;
209 deliver_fault(cpu
, vaddr
, access_type
, mmu_idx
, &fi
);
212 /* arm_cpu_do_transaction_failed: handle a memory system error response
213 * (eg "no device/memory present at address") by raising an external abort
216 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
217 vaddr addr
, unsigned size
,
218 MMUAccessType access_type
,
219 int mmu_idx
, MemTxAttrs attrs
,
220 MemTxResult response
, uintptr_t retaddr
)
222 ARMCPU
*cpu
= ARM_CPU(cs
);
223 ARMMMUFaultInfo fi
= {};
226 /* now we have a real cpu fault */
227 cpu_restore_state(cs
, retaddr
);
230 /* The EA bit in syndromes and fault status registers is an
231 * IMPDEF classification of external aborts. ARM implementations
232 * usually use this to indicate AXI bus Decode error (0) or
233 * Slave error (1); in QEMU we follow that.
235 fi
.ea
= (response
!= MEMTX_DECODE_ERROR
);
236 fi
.type
= ARMFault_SyncExternal
;
237 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
240 #endif /* !defined(CONFIG_USER_ONLY) */
242 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
244 uint32_t res
= a
+ b
;
245 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
250 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
252 uint32_t res
= a
+ b
;
253 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
255 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
260 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
262 uint32_t res
= a
- b
;
263 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
265 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
270 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
273 if (val
>= 0x40000000) {
276 } else if (val
<= (int32_t)0xc0000000) {
285 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
287 uint32_t res
= a
+ b
;
295 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
297 uint32_t res
= a
- b
;
305 /* Signed saturation. */
306 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
312 mask
= (1u << shift
) - 1;
316 } else if (top
< -1) {
323 /* Unsigned saturation. */
324 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
328 max
= (1u << shift
) - 1;
332 } else if (val
> max
) {
339 /* Signed saturate. */
340 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
342 return do_ssat(env
, x
, shift
);
345 /* Dual halfword signed saturate. */
346 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
350 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
351 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
355 /* Unsigned saturate. */
356 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
358 return do_usat(env
, x
, shift
);
361 /* Dual halfword unsigned saturate. */
362 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
366 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
367 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
371 void HELPER(setend
)(CPUARMState
*env
)
373 env
->uncached_cpsr
^= CPSR_E
;
376 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
377 * The function returns the target EL (1-3) if the instruction is to be trapped;
378 * otherwise it returns 0 indicating it is not trapped.
380 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
382 int cur_el
= arm_current_el(env
);
385 if (arm_feature(env
, ARM_FEATURE_M
)) {
386 /* M profile cores can never trap WFI/WFE. */
390 /* If we are currently in EL0 then we need to check if SCTLR is set up for
391 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
393 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
396 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
397 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
398 /* Secure EL0 and Secure PL1 is at EL3 */
404 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
409 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
410 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
411 * bits will be zero indicating no trap.
413 if (cur_el
< 2 && !arm_is_secure(env
)) {
414 mask
= (is_wfe
) ? HCR_TWE
: HCR_TWI
;
415 if (env
->cp15
.hcr_el2
& mask
) {
420 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
422 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
423 if (env
->cp15
.scr_el3
& mask
) {
431 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
433 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
434 int target_el
= check_wfx_trap(env
, false);
436 if (cpu_has_work(cs
)) {
437 /* Don't bother to go into our "low power state" if
438 * we would just wake up immediately.
445 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
449 cs
->exception_index
= EXCP_HLT
;
454 void QEMU_NORETURN
HELPER(wfe
)(CPUARMState
*env
)
456 /* This is a hint instruction that is semantically different
457 * from YIELD even though we currently implement it identically.
458 * Don't actually halt the CPU, just yield back to top
459 * level loop. This is not going into a "low power state"
460 * (ie halting until some event occurs), so we never take
461 * a configurable trap to a different exception level.
466 void QEMU_NORETURN
HELPER(yield
)(CPUARMState
*env
)
468 ARMCPU
*cpu
= arm_env_get_cpu(env
);
469 CPUState
*cs
= CPU(cpu
);
471 /* This is a non-trappable hint instruction that generally indicates
472 * that the guest is currently busy-looping. Yield control back to the
473 * top level loop so that a more deserving VCPU has a chance to run.
475 cs
->exception_index
= EXCP_YIELD
;
479 /* Raise an internal-to-QEMU exception. This is limited to only
480 * those EXCP values which are special cases for QEMU to interrupt
481 * execution and not to be used for exceptions which are passed to
482 * the guest (those must all have syndrome information and thus should
483 * use exception_with_syndrome).
485 void QEMU_NORETURN
HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
487 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
489 assert(excp_is_internal(excp
));
490 cs
->exception_index
= excp
;
494 /* Raise an exception with the specified syndrome register value */
496 HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
497 uint32_t syndrome
, uint32_t target_el
)
499 raise_exception(env
, excp
, syndrome
, target_el
);
502 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
504 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
507 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
509 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
512 /* Write the CPSR for a 32-bit exception return */
513 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
515 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
517 /* Generated code has already stored the new PC value, but
518 * without masking out its low bits, because which bits need
519 * masking depends on whether we're returning to Thumb or ARM
520 * state. Do the masking now.
522 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
524 qemu_mutex_lock_iothread();
525 arm_call_el_change_hook(arm_env_get_cpu(env
));
526 qemu_mutex_unlock_iothread();
529 /* Access to user mode registers from privileged modes. */
530 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
535 val
= env
->banked_r13
[BANK_USRSYS
];
536 } else if (regno
== 14) {
537 val
= env
->banked_r14
[BANK_USRSYS
];
538 } else if (regno
>= 8
539 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
540 val
= env
->usr_regs
[regno
- 8];
542 val
= env
->regs
[regno
];
547 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
550 env
->banked_r13
[BANK_USRSYS
] = val
;
551 } else if (regno
== 14) {
552 env
->banked_r14
[BANK_USRSYS
] = val
;
553 } else if (regno
>= 8
554 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
555 env
->usr_regs
[regno
- 8] = val
;
557 env
->regs
[regno
] = val
;
561 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
563 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
566 env
->banked_r13
[bank_number(mode
)] = val
;
570 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
572 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
573 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
574 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
576 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
577 exception_target_el(env
));
580 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
581 return env
->regs
[13];
583 return env
->banked_r13
[bank_number(mode
)];
587 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
590 /* Raise an exception if the requested access is one of the UNPREDICTABLE
591 * cases; otherwise return. This broadly corresponds to the pseudocode
592 * BankedRegisterAccessValid() and SPSRAccessValid(),
593 * except that we have already handled some cases at translate time.
595 int curmode
= env
->uncached_cpsr
& CPSR_M
;
597 if (curmode
== tgtmode
) {
601 if (tgtmode
== ARM_CPU_MODE_USR
) {
604 if (curmode
!= ARM_CPU_MODE_FIQ
) {
609 if (curmode
== ARM_CPU_MODE_SYS
) {
614 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
623 if (tgtmode
== ARM_CPU_MODE_HYP
) {
625 case 17: /* ELR_Hyp */
626 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
631 if (curmode
!= ARM_CPU_MODE_MON
) {
641 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
642 exception_target_el(env
));
645 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
648 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
652 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
654 case 17: /* ELR_Hyp */
655 env
->elr_el
[2] = value
;
658 env
->banked_r13
[bank_number(tgtmode
)] = value
;
661 env
->banked_r14
[bank_number(tgtmode
)] = value
;
665 case ARM_CPU_MODE_USR
:
666 env
->usr_regs
[regno
- 8] = value
;
668 case ARM_CPU_MODE_FIQ
:
669 env
->fiq_regs
[regno
- 8] = value
;
672 g_assert_not_reached();
676 g_assert_not_reached();
680 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
682 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
686 return env
->banked_spsr
[bank_number(tgtmode
)];
687 case 17: /* ELR_Hyp */
688 return env
->elr_el
[2];
690 return env
->banked_r13
[bank_number(tgtmode
)];
692 return env
->banked_r14
[bank_number(tgtmode
)];
695 case ARM_CPU_MODE_USR
:
696 return env
->usr_regs
[regno
- 8];
697 case ARM_CPU_MODE_FIQ
:
698 return env
->fiq_regs
[regno
- 8];
700 g_assert_not_reached();
703 g_assert_not_reached();
707 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
710 const ARMCPRegInfo
*ri
= rip
;
713 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
714 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
715 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
722 switch (ri
->accessfn(env
, ri
, isread
)) {
726 target_el
= exception_target_el(env
);
728 case CP_ACCESS_TRAP_EL2
:
729 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
730 * a bug in the access function.
732 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
735 case CP_ACCESS_TRAP_EL3
:
738 case CP_ACCESS_TRAP_UNCATEGORIZED
:
739 target_el
= exception_target_el(env
);
740 syndrome
= syn_uncategorized();
742 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
744 syndrome
= syn_uncategorized();
746 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
748 syndrome
= syn_uncategorized();
750 case CP_ACCESS_TRAP_FP_EL2
:
752 /* Since we are an implementation that takes exceptions on a trapped
753 * conditional insn only if the insn has passed its condition code
754 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
755 * (which is also the required value for AArch64 traps).
757 syndrome
= syn_fp_access_trap(1, 0xe, false);
759 case CP_ACCESS_TRAP_FP_EL3
:
761 syndrome
= syn_fp_access_trap(1, 0xe, false);
764 g_assert_not_reached();
767 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
770 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
772 const ARMCPRegInfo
*ri
= rip
;
774 if (ri
->type
& ARM_CP_IO
) {
775 qemu_mutex_lock_iothread();
776 ri
->writefn(env
, ri
, value
);
777 qemu_mutex_unlock_iothread();
779 ri
->writefn(env
, ri
, value
);
783 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
785 const ARMCPRegInfo
*ri
= rip
;
788 if (ri
->type
& ARM_CP_IO
) {
789 qemu_mutex_lock_iothread();
790 res
= ri
->readfn(env
, ri
);
791 qemu_mutex_unlock_iothread();
793 res
= ri
->readfn(env
, ri
);
799 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
801 const ARMCPRegInfo
*ri
= rip
;
803 if (ri
->type
& ARM_CP_IO
) {
804 qemu_mutex_lock_iothread();
805 ri
->writefn(env
, ri
, value
);
806 qemu_mutex_unlock_iothread();
808 ri
->writefn(env
, ri
, value
);
812 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
814 const ARMCPRegInfo
*ri
= rip
;
817 if (ri
->type
& ARM_CP_IO
) {
818 qemu_mutex_lock_iothread();
819 res
= ri
->readfn(env
, ri
);
820 qemu_mutex_unlock_iothread();
822 res
= ri
->readfn(env
, ri
);
828 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
830 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
831 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
832 * to catch that case at translate time.
834 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
835 uint32_t syndrome
= syn_aa64_sysregtrap(0, extract32(op
, 0, 3),
836 extract32(op
, 3, 3), 4,
838 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
842 case 0x05: /* SPSel */
843 update_spsel(env
, imm
);
845 case 0x1e: /* DAIFSet */
846 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
848 case 0x1f: /* DAIFClear */
849 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
852 g_assert_not_reached();
856 void HELPER(clear_pstate_ss
)(CPUARMState
*env
)
858 env
->pstate
&= ~PSTATE_SS
;
861 void HELPER(pre_hvc
)(CPUARMState
*env
)
863 ARMCPU
*cpu
= arm_env_get_cpu(env
);
864 int cur_el
= arm_current_el(env
);
865 /* FIXME: Use actual secure state. */
869 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
870 /* If PSCI is enabled and this looks like a valid PSCI call then
871 * that overrides the architecturally mandated HVC behaviour.
876 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
877 /* If EL2 doesn't exist, HVC always UNDEFs */
879 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
880 /* EL3.HCE has priority over EL2.HCD. */
881 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
883 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
886 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
887 * For ARMv8/AArch64, HVC is allowed in EL3.
888 * Note that we've already trapped HVC from EL0 at translation
891 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
896 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
897 exception_target_el(env
));
901 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
903 ARMCPU
*cpu
= arm_env_get_cpu(env
);
904 int cur_el
= arm_current_el(env
);
905 bool secure
= arm_is_secure(env
);
906 bool smd
= env
->cp15
.scr_el3
& SCR_SMD
;
907 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
908 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
909 * extensions, SMD only applies to NS state.
910 * On ARMv7 without the Virtualization extensions, the SMD bit
911 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
912 * so we need not special case this here.
914 bool undef
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd
: smd
&& !secure
;
916 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
917 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
918 /* If we have no EL3 then SMC always UNDEFs and can't be
919 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
920 * firmware within QEMU, and we want an EL2 guest to be able
921 * to forbid its EL1 from making PSCI calls into QEMU's
922 * "firmware" via HCR.TSC, so for these purposes treat
923 * PSCI-via-SMC as implying an EL3.
926 } else if (!secure
&& cur_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TSC
)) {
927 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
928 * We also want an EL2 guest to be able to forbid its EL1 from
929 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
931 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
934 /* If PSCI is enabled and this looks like a valid PSCI call then
935 * suppress the UNDEF -- we'll catch the SMC exception and
936 * implement the PSCI call behaviour there.
938 if (undef
&& !arm_is_psci_call(cpu
, EXCP_SMC
)) {
939 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
940 exception_target_el(env
));
944 static int el_from_spsr(uint32_t spsr
)
946 /* Return the exception level that this SPSR is requesting a return to,
947 * or -1 if it is invalid (an illegal return)
949 if (spsr
& PSTATE_nRW
) {
950 switch (spsr
& CPSR_M
) {
951 case ARM_CPU_MODE_USR
:
953 case ARM_CPU_MODE_HYP
:
955 case ARM_CPU_MODE_FIQ
:
956 case ARM_CPU_MODE_IRQ
:
957 case ARM_CPU_MODE_SVC
:
958 case ARM_CPU_MODE_ABT
:
959 case ARM_CPU_MODE_UND
:
960 case ARM_CPU_MODE_SYS
:
962 case ARM_CPU_MODE_MON
:
963 /* Returning to Mon from AArch64 is never possible,
964 * so this is an illegal return.
970 if (extract32(spsr
, 1, 1)) {
971 /* Return with reserved M[1] bit set */
974 if (extract32(spsr
, 0, 4) == 1) {
975 /* return to EL0 with M[0] bit set */
978 return extract32(spsr
, 2, 2);
982 void HELPER(exception_return
)(CPUARMState
*env
)
984 int cur_el
= arm_current_el(env
);
985 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
986 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
988 bool return_to_aa64
= (spsr
& PSTATE_nRW
) == 0;
990 aarch64_save_sp(env
, cur_el
);
992 arm_clear_exclusive(env
);
994 /* We must squash the PSTATE.SS bit to zero unless both of the
996 * 1. debug exceptions are currently disabled
997 * 2. singlestep will be active in the EL we return to
998 * We check 1 here and 2 after we've done the pstate/cpsr write() to
999 * transition to the EL we're going to.
1001 if (arm_generate_debug_exceptions(env
)) {
1005 new_el
= el_from_spsr(spsr
);
1007 goto illegal_return
;
1010 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
1011 /* Disallow return to an EL which is unimplemented or higher
1012 * than the current one.
1014 goto illegal_return
;
1017 if (new_el
!= 0 && arm_el_is_aa64(env
, new_el
) != return_to_aa64
) {
1018 /* Return to an EL which is configured for a different register width */
1019 goto illegal_return
;
1022 if (new_el
== 2 && arm_is_secure_below_el3(env
)) {
1023 /* Return to the non-existent secure-EL2 */
1024 goto illegal_return
;
1027 if (new_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TGE
)
1028 && !arm_is_secure_below_el3(env
)) {
1029 goto illegal_return
;
1032 if (!return_to_aa64
) {
1034 /* We do a raw CPSR write because aarch64_sync_64_to_32()
1035 * will sort the register banks out for us, and we've already
1036 * caught all the bad-mode cases in el_from_spsr().
1038 cpsr_write(env
, spsr
, ~0, CPSRWriteRaw
);
1039 if (!arm_singlestep_active(env
)) {
1040 env
->uncached_cpsr
&= ~PSTATE_SS
;
1042 aarch64_sync_64_to_32(env
);
1044 if (spsr
& CPSR_T
) {
1045 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x1;
1047 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x3;
1049 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1050 "AArch32 EL%d PC 0x%" PRIx32
"\n",
1051 cur_el
, new_el
, env
->regs
[15]);
1054 pstate_write(env
, spsr
);
1055 if (!arm_singlestep_active(env
)) {
1056 env
->pstate
&= ~PSTATE_SS
;
1058 aarch64_restore_sp(env
, new_el
);
1059 env
->pc
= env
->elr_el
[cur_el
];
1060 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1061 "AArch64 EL%d PC 0x%" PRIx64
"\n",
1062 cur_el
, new_el
, env
->pc
);
1065 qemu_mutex_lock_iothread();
1066 arm_call_el_change_hook(arm_env_get_cpu(env
));
1067 qemu_mutex_unlock_iothread();
1072 /* Illegal return events of various kinds have architecturally
1073 * mandated behaviour:
1074 * restore NZCV and DAIF from SPSR_ELx
1076 * restore PC from ELR_ELx
1077 * no change to exception level, execution state or stack pointer
1079 env
->pstate
|= PSTATE_IL
;
1080 env
->pc
= env
->elr_el
[cur_el
];
1081 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
1082 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
1083 pstate_write(env
, spsr
);
1084 if (!arm_singlestep_active(env
)) {
1085 env
->pstate
&= ~PSTATE_SS
;
1087 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal exception return at EL%d: "
1088 "resuming execution at 0x%" PRIx64
"\n", cur_el
, env
->pc
);
1091 /* Return true if the linked breakpoint entry lbn passes its checks */
1092 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
1094 CPUARMState
*env
= &cpu
->env
;
1095 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
1096 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
1097 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
1099 uint32_t contextidr
;
1101 /* Links to unimplemented or non-context aware breakpoints are
1102 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
1103 * as if linked to an UNKNOWN context-aware breakpoint (in which
1104 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
1105 * We choose the former.
1107 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1111 bcr
= env
->cp15
.dbgbcr
[lbn
];
1113 if (extract64(bcr
, 0, 1) == 0) {
1114 /* Linked breakpoint disabled : generate no events */
1118 bt
= extract64(bcr
, 20, 4);
1120 /* We match the whole register even if this is AArch32 using the
1121 * short descriptor format (in which case it holds both PROCID and ASID),
1122 * since we don't implement the optional v7 context ID masking.
1124 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1127 case 3: /* linked context ID match */
1128 if (arm_current_el(env
) > 1) {
1129 /* Context matches never fire in EL2 or (AArch64) EL3 */
1132 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1133 case 5: /* linked address mismatch (reserved in AArch64) */
1134 case 9: /* linked VMID match (reserved if no EL2) */
1135 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1137 /* Links to Unlinked context breakpoints must generate no
1138 * events; we choose to do the same for reserved values too.
1146 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1148 CPUARMState
*env
= &cpu
->env
;
1150 int pac
, hmc
, ssc
, wt
, lbn
;
1151 /* Note that for watchpoints the check is against the CPU security
1152 * state, not the S/NS attribute on the offending data access.
1154 bool is_secure
= arm_is_secure(env
);
1155 int access_el
= arm_current_el(env
);
1158 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1160 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1163 cr
= env
->cp15
.dbgwcr
[n
];
1164 if (wp
->hitattrs
.user
) {
1165 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1166 * match watchpoints as if they were accesses done at EL0, even if
1167 * the CPU is at EL1 or higher.
1172 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1174 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1177 cr
= env
->cp15
.dbgbcr
[n
];
1179 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1180 * enabled and that the address and access type match; for breakpoints
1181 * we know the address matched; check the remaining fields, including
1182 * linked breakpoints. We rely on WCR and BCR having the same layout
1183 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1184 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1185 * must act either like some valid combination or as if the watchpoint
1186 * were disabled. We choose the former, and use this together with
1187 * the fact that EL3 must always be Secure and EL2 must always be
1188 * Non-Secure to simplify the code slightly compared to the full
1189 * table in the ARM ARM.
1191 pac
= extract64(cr
, 1, 2);
1192 hmc
= extract64(cr
, 13, 1);
1193 ssc
= extract64(cr
, 14, 2);
1211 switch (access_el
) {
1219 if (extract32(pac
, 0, 1) == 0) {
1224 if (extract32(pac
, 1, 1) == 0) {
1229 g_assert_not_reached();
1232 wt
= extract64(cr
, 20, 1);
1233 lbn
= extract64(cr
, 16, 4);
1235 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1242 static bool check_watchpoints(ARMCPU
*cpu
)
1244 CPUARMState
*env
= &cpu
->env
;
1247 /* If watchpoints are disabled globally or we can't take debug
1248 * exceptions here then watchpoint firings are ignored.
1250 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1251 || !arm_generate_debug_exceptions(env
)) {
1255 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1256 if (bp_wp_matches(cpu
, n
, true)) {
1263 static bool check_breakpoints(ARMCPU
*cpu
)
1265 CPUARMState
*env
= &cpu
->env
;
1268 /* If breakpoints are disabled globally or we can't take debug
1269 * exceptions here then breakpoint firings are ignored.
1271 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1272 || !arm_generate_debug_exceptions(env
)) {
1276 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1277 if (bp_wp_matches(cpu
, n
, false)) {
1284 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1286 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1288 if (check_breakpoints(cpu
)) {
1289 HELPER(exception_internal(env
, EXCP_DEBUG
));
1293 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1295 /* Called by core code when a CPU watchpoint fires; need to check if this
1296 * is also an architectural watchpoint match.
1298 ARMCPU
*cpu
= ARM_CPU(cs
);
1300 return check_watchpoints(cpu
);
1303 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1305 ARMCPU
*cpu
= ARM_CPU(cs
);
1306 CPUARMState
*env
= &cpu
->env
;
1308 /* In BE32 system mode, target memory is stored byteswapped (on a
1309 * little-endian host system), and by the time we reach here (via an
1310 * opcode helper) the addresses of subword accesses have been adjusted
1311 * to account for that, which means that watchpoints will not match.
1312 * Undo the adjustment here.
1314 if (arm_sctlr_b(env
)) {
1317 } else if (len
== 2) {
1325 void arm_debug_excp_handler(CPUState
*cs
)
1327 /* Called by core code when a watchpoint or breakpoint fires;
1328 * need to check which one and raise the appropriate exception.
1330 ARMCPU
*cpu
= ARM_CPU(cs
);
1331 CPUARMState
*env
= &cpu
->env
;
1332 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1335 if (wp_hit
->flags
& BP_CPU
) {
1336 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1337 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1339 cs
->watchpoint_hit
= NULL
;
1341 if (extended_addresses_enabled(env
)) {
1342 env
->exception
.fsr
= (1 << 9) | 0x22;
1344 env
->exception
.fsr
= 0x2;
1346 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1347 raise_exception(env
, EXCP_DATA_ABORT
,
1348 syn_watchpoint(same_el
, 0, wnr
),
1349 arm_debug_target_el(env
));
1352 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1353 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1355 /* (1) GDB breakpoints should be handled first.
1356 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1357 * since singlestep is also done by generating a debug internal
1360 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1361 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1365 if (extended_addresses_enabled(env
)) {
1366 env
->exception
.fsr
= (1 << 9) | 0x22;
1368 env
->exception
.fsr
= 0x2;
1370 /* FAR is UNKNOWN, so doesn't need setting */
1371 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1372 syn_breakpoint(same_el
),
1373 arm_debug_target_el(env
));
1377 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1378 The only way to do that in TCG is a conditional branch, which clobbers
1379 all our temporaries. For now implement these as helper functions. */
1381 /* Similarly for variable shift instructions. */
1383 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1385 int shift
= i
& 0xff;
1392 } else if (shift
!= 0) {
1393 env
->CF
= (x
>> (32 - shift
)) & 1;
1399 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1401 int shift
= i
& 0xff;
1404 env
->CF
= (x
>> 31) & 1;
1408 } else if (shift
!= 0) {
1409 env
->CF
= (x
>> (shift
- 1)) & 1;
1415 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1417 int shift
= i
& 0xff;
1419 env
->CF
= (x
>> 31) & 1;
1420 return (int32_t)x
>> 31;
1421 } else if (shift
!= 0) {
1422 env
->CF
= (x
>> (shift
- 1)) & 1;
1423 return (int32_t)x
>> shift
;
1428 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1432 shift
= shift1
& 0x1f;
1435 env
->CF
= (x
>> 31) & 1;
1438 env
->CF
= (x
>> (shift
- 1)) & 1;
1439 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));