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hw/vfio: set interrupts using pci irq wrappers
[qemu/ar7.git] / hw / misc / vfio.c
blob9d02e49a3e8b64417d5aeed205e8769d082bbf3e
1 /*
2 * vfio based device assignment support
3 *
4 * Copyright Red Hat, Inc. 2012
5 *
6 * Authors:
7 * Alex Williamson <alex.williamson@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
19 */
20
21 #include <dirent.h>
22 #include <linux/vfio.h>
23 #include <sys/ioctl.h>
24 #include <sys/mman.h>
25 #include <sys/stat.h>
26 #include <sys/types.h>
27 #include <unistd.h>
28
29 #include "config.h"
30 #include "exec/address-spaces.h"
31 #include "exec/memory.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci.h"
35 #include "qemu-common.h"
36 #include "qemu/error-report.h"
37 #include "qemu/event_notifier.h"
38 #include "qemu/queue.h"
39 #include "qemu/range.h"
40 #include "sysemu/kvm.h"
41 #include "sysemu/sysemu.h"
42
43 /* #define DEBUG_VFIO */
44 #ifdef DEBUG_VFIO
45 #define DPRINTF(fmt, ...) \
46 do { fprintf(stderr, "vfio: " fmt, ## __VA_ARGS__); } while (0)
47 #else
48 #define DPRINTF(fmt, ...) \
49 do { } while (0)
50 #endif
51
52 /* Extra debugging, trap acceleration paths for more logging */
53 #define VFIO_ALLOW_MMAP 1
54 #define VFIO_ALLOW_KVM_INTX 1
55
56 struct VFIODevice;
57
58 typedef struct VFIOQuirk {
59 MemoryRegion mem;
60 struct VFIODevice *vdev;
61 QLIST_ENTRY(VFIOQuirk) next;
62 struct {
63 uint32_t base_offset:TARGET_PAGE_BITS;
64 uint32_t address_offset:TARGET_PAGE_BITS;
65 uint32_t address_size:3;
66 uint32_t bar:3;
67
68 uint32_t address_match;
69 uint32_t address_mask;
70
71 uint32_t address_val:TARGET_PAGE_BITS;
72 uint32_t data_offset:TARGET_PAGE_BITS;
73 uint32_t data_size:3;
74
75 uint8_t flags;
76 uint8_t read_flags;
77 uint8_t write_flags;
78 } data;
79 } VFIOQuirk;
80
81 typedef struct VFIOBAR {
82 off_t fd_offset; /* offset of BAR within device fd */
83 int fd; /* device fd, allows us to pass VFIOBAR as opaque data */
84 MemoryRegion mem; /* slow, read/write access */
85 MemoryRegion mmap_mem; /* direct mapped access */
86 void *mmap;
87 size_t size;
88 uint32_t flags; /* VFIO region flags (rd/wr/mmap) */
89 uint8_t nr; /* cache the BAR number for debug */
90 bool ioport;
91 bool mem64;
92 QLIST_HEAD(, VFIOQuirk) quirks;
93 } VFIOBAR;
94
95 typedef struct VFIOVGARegion {
96 MemoryRegion mem;
97 off_t offset;
98 int nr;
99 QLIST_HEAD(, VFIOQuirk) quirks;
100 } VFIOVGARegion;
101
102 typedef struct VFIOVGA {
103 off_t fd_offset;
104 int fd;
105 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
106 } VFIOVGA;
107
108 typedef struct VFIOINTx {
109 bool pending; /* interrupt pending */
110 bool kvm_accel; /* set when QEMU bypass through KVM enabled */
111 uint8_t pin; /* which pin to pull for qemu_set_irq */
112 EventNotifier interrupt; /* eventfd triggered on interrupt */
113 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
114 PCIINTxRoute route; /* routing info for QEMU bypass */
115 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
116 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */
117 } VFIOINTx;
118
119 typedef struct VFIOMSIVector {
120 EventNotifier interrupt; /* eventfd triggered on interrupt */
121 struct VFIODevice *vdev; /* back pointer to device */
122 int virq; /* KVM irqchip route for QEMU bypass */
123 bool use;
124 } VFIOMSIVector;
125
126 enum {
127 VFIO_INT_NONE = 0,
128 VFIO_INT_INTx = 1,
129 VFIO_INT_MSI = 2,
130 VFIO_INT_MSIX = 3,
131 };
132
133 struct VFIOGroup;
134
135 typedef struct VFIOContainer {
136 int fd; /* /dev/vfio/vfio, empowered by the attached groups */
137 struct {
138 /* enable abstraction to support various iommu backends */
139 union {
140 MemoryListener listener; /* Used by type1 iommu */
141 };
142 void (*release)(struct VFIOContainer *);
143 } iommu_data;
144 QLIST_HEAD(, VFIOGroup) group_list;
145 QLIST_ENTRY(VFIOContainer) next;
146 } VFIOContainer;
147
148 /* Cache of MSI-X setup plus extra mmap and memory region for split BAR map */
149 typedef struct VFIOMSIXInfo {
150 uint8_t table_bar;
151 uint8_t pba_bar;
152 uint16_t entries;
153 uint32_t table_offset;
154 uint32_t pba_offset;
155 MemoryRegion mmap_mem;
156 void *mmap;
157 } VFIOMSIXInfo;
158
159 typedef struct VFIODevice {
160 PCIDevice pdev;
161 int fd;
162 VFIOINTx intx;
163 unsigned int config_size;
164 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */
165 off_t config_offset; /* Offset of config space region within device fd */
166 unsigned int rom_size;
167 off_t rom_offset; /* Offset of ROM region within device fd */
168 int msi_cap_size;
169 VFIOMSIVector *msi_vectors;
170 VFIOMSIXInfo *msix;
171 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
172 int interrupt; /* Current interrupt type */
173 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
174 VFIOVGA vga; /* 0xa0000, 0x3b0, 0x3c0 */
175 PCIHostDeviceAddress host;
176 QLIST_ENTRY(VFIODevice) next;
177 struct VFIOGroup *group;
178 EventNotifier err_notifier;
179 uint32_t features;
180 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
181 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
182 int32_t bootindex;
183 uint8_t pm_cap;
184 bool reset_works;
185 bool has_vga;
186 bool pci_aer;
187 } VFIODevice;
188
189 typedef struct VFIOGroup {
190 int fd;
191 int groupid;
192 VFIOContainer *container;
193 QLIST_HEAD(, VFIODevice) device_list;
194 QLIST_ENTRY(VFIOGroup) next;
195 QLIST_ENTRY(VFIOGroup) container_next;
196 } VFIOGroup;
197
198 #define MSIX_CAP_LENGTH 12
199
200 static QLIST_HEAD(, VFIOContainer)
201 container_list = QLIST_HEAD_INITIALIZER(container_list);
202
203 static QLIST_HEAD(, VFIOGroup)
204 group_list = QLIST_HEAD_INITIALIZER(group_list);
205
206 static void vfio_disable_interrupts(VFIODevice *vdev);
207 static uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
208 static void vfio_pci_write_config(PCIDevice *pdev, uint32_t addr,
209 uint32_t val, int len);
210 static void vfio_mmap_set_enabled(VFIODevice *vdev, bool enabled);
211
212 /*
213 * Common VFIO interrupt disable
214 */
215 static void vfio_disable_irqindex(VFIODevice *vdev, int index)
216 {
217 struct vfio_irq_set irq_set = {
218 .argsz = sizeof(irq_set),
219 .flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_TRIGGER,
220 .index = index,
221 .start = 0,
222 .count = 0,
223 };
224
225 ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, &irq_set);
226 }
227
228 /*
229 * INTx
230 */
231 static void vfio_unmask_intx(VFIODevice *vdev)
232 {
233 struct vfio_irq_set irq_set = {
234 .argsz = sizeof(irq_set),
235 .flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_UNMASK,
236 .index = VFIO_PCI_INTX_IRQ_INDEX,
237 .start = 0,
238 .count = 1,
239 };
240
241 ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, &irq_set);
242 }
243
244 #ifdef CONFIG_KVM /* Unused outside of CONFIG_KVM code */
245 static void vfio_mask_intx(VFIODevice *vdev)
246 {
247 struct vfio_irq_set irq_set = {
248 .argsz = sizeof(irq_set),
249 .flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_MASK,
250 .index = VFIO_PCI_INTX_IRQ_INDEX,
251 .start = 0,
252 .count = 1,
253 };
254
255 ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, &irq_set);
256 }
257 #endif
258
259 /*
260 * Disabling BAR mmaping can be slow, but toggling it around INTx can
261 * also be a huge overhead. We try to get the best of both worlds by
262 * waiting until an interrupt to disable mmaps (subsequent transitions
263 * to the same state are effectively no overhead). If the interrupt has
264 * been serviced and the time gap is long enough, we re-enable mmaps for
265 * performance. This works well for things like graphics cards, which
266 * may not use their interrupt at all and are penalized to an unusable
267 * level by read/write BAR traps. Other devices, like NICs, have more
268 * regular interrupts and see much better latency by staying in non-mmap
269 * mode. We therefore set the default mmap_timeout such that a ping
270 * is just enough to keep the mmap disabled. Users can experiment with
271 * other options with the x-intx-mmap-timeout-ms parameter (a value of
272 * zero disables the timer).
273 */
274 static void vfio_intx_mmap_enable(void *opaque)
275 {
276 VFIODevice *vdev = opaque;
277
278 if (vdev->intx.pending) {
279 timer_mod(vdev->intx.mmap_timer,
280 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
281 return;
282 }
283
284 vfio_mmap_set_enabled(vdev, true);
285 }
286
287 static void vfio_intx_interrupt(void *opaque)
288 {
289 VFIODevice *vdev = opaque;
290
291 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) {
292 return;
293 }
294
295 DPRINTF("%s(%04x:%02x:%02x.%x) Pin %c\n", __func__, vdev->host.domain,
296 vdev->host.bus, vdev->host.slot, vdev->host.function,
297 'A' + vdev->intx.pin);
298
299 vdev->intx.pending = true;
300 pci_irq_assert(&vdev->pdev);
301 vfio_mmap_set_enabled(vdev, false);
302 if (vdev->intx.mmap_timeout) {
303 timer_mod(vdev->intx.mmap_timer,
304 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
305 }
306 }
307
308 static void vfio_eoi(VFIODevice *vdev)
309 {
310 if (!vdev->intx.pending) {
311 return;
312 }
313
314 DPRINTF("%s(%04x:%02x:%02x.%x) EOI\n", __func__, vdev->host.domain,
315 vdev->host.bus, vdev->host.slot, vdev->host.function);
316
317 vdev->intx.pending = false;
318 pci_irq_deassert(&vdev->pdev);
319 vfio_unmask_intx(vdev);
320 }
321
322 static void vfio_enable_intx_kvm(VFIODevice *vdev)
323 {
324 #ifdef CONFIG_KVM
325 struct kvm_irqfd irqfd = {
326 .fd = event_notifier_get_fd(&vdev->intx.interrupt),
327 .gsi = vdev->intx.route.irq,
328 .flags = KVM_IRQFD_FLAG_RESAMPLE,
329 };
330 struct vfio_irq_set *irq_set;
331 int ret, argsz;
332 int32_t *pfd;
333
334 if (!VFIO_ALLOW_KVM_INTX || !kvm_irqfds_enabled() ||
335 vdev->intx.route.mode != PCI_INTX_ENABLED ||
336 !kvm_check_extension(kvm_state, KVM_CAP_IRQFD_RESAMPLE)) {
337 return;
338 }
339
340 /* Get to a known interrupt state */
341 qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev);
342 vfio_mask_intx(vdev);
343 vdev->intx.pending = false;
344 pci_irq_deassert(&vdev->pdev);
345
346 /* Get an eventfd for resample/unmask */
347 if (event_notifier_init(&vdev->intx.unmask, 0)) {
348 error_report("vfio: Error: event_notifier_init failed eoi");
349 goto fail;
350 }
351
352 /* KVM triggers it, VFIO listens for it */
353 irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask);
354
355 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) {
356 error_report("vfio: Error: Failed to setup resample irqfd: %m");
357 goto fail_irqfd;
358 }
359
360 argsz = sizeof(*irq_set) + sizeof(*pfd);
361
362 irq_set = g_malloc0(argsz);
363 irq_set->argsz = argsz;
364 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK;
365 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX;
366 irq_set->start = 0;
367 irq_set->count = 1;
368 pfd = (int32_t *)&irq_set->data;
369
370 *pfd = irqfd.resamplefd;
371
372 ret = ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
373 g_free(irq_set);
374 if (ret) {
375 error_report("vfio: Error: Failed to setup INTx unmask fd: %m");
376 goto fail_vfio;
377 }
378
379 /* Let'em rip */
380 vfio_unmask_intx(vdev);
381
382 vdev->intx.kvm_accel = true;
383
384 DPRINTF("%s(%04x:%02x:%02x.%x) KVM INTx accel enabled\n",
385 __func__, vdev->host.domain, vdev->host.bus,
386 vdev->host.slot, vdev->host.function);
387
388 return;
389
390 fail_vfio:
391 irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN;
392 kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd);
393 fail_irqfd:
394 event_notifier_cleanup(&vdev->intx.unmask);
395 fail:
396 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev);
397 vfio_unmask_intx(vdev);
398 #endif
399 }
400
401 static void vfio_disable_intx_kvm(VFIODevice *vdev)
402 {
403 #ifdef CONFIG_KVM
404 struct kvm_irqfd irqfd = {
405 .fd = event_notifier_get_fd(&vdev->intx.interrupt),
406 .gsi = vdev->intx.route.irq,
407 .flags = KVM_IRQFD_FLAG_DEASSIGN,
408 };
409
410 if (!vdev->intx.kvm_accel) {
411 return;
412 }
413
414 /*
415 * Get to a known state, hardware masked, QEMU ready to accept new
416 * interrupts, QEMU IRQ de-asserted.
417 */
418 vfio_mask_intx(vdev);
419 vdev->intx.pending = false;
420 pci_irq_deassert(&vdev->pdev);
421
422 /* Tell KVM to stop listening for an INTx irqfd */
423 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) {
424 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
425 }
426
427 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
428 event_notifier_cleanup(&vdev->intx.unmask);
429
430 /* QEMU starts listening for interrupt events. */
431 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev);
432
433 vdev->intx.kvm_accel = false;
434
435 /* If we've missed an event, let it re-fire through QEMU */
436 vfio_unmask_intx(vdev);
437
438 DPRINTF("%s(%04x:%02x:%02x.%x) KVM INTx accel disabled\n",
439 __func__, vdev->host.domain, vdev->host.bus,
440 vdev->host.slot, vdev->host.function);
441 #endif
442 }
443
444 static void vfio_update_irq(PCIDevice *pdev)
445 {
446 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
447 PCIINTxRoute route;
448
449 if (vdev->interrupt != VFIO_INT_INTx) {
450 return;
451 }
452
453 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin);
454
455 if (!pci_intx_route_changed(&vdev->intx.route, &route)) {
456 return; /* Nothing changed */
457 }
458
459 DPRINTF("%s(%04x:%02x:%02x.%x) IRQ moved %d -> %d\n", __func__,
460 vdev->host.domain, vdev->host.bus, vdev->host.slot,
461 vdev->host.function, vdev->intx.route.irq, route.irq);
462
463 vfio_disable_intx_kvm(vdev);
464
465 vdev->intx.route = route;
466
467 if (route.mode != PCI_INTX_ENABLED) {
468 return;
469 }
470
471 vfio_enable_intx_kvm(vdev);
472
473 /* Re-enable the interrupt in cased we missed an EOI */
474 vfio_eoi(vdev);
475 }
476
477 static int vfio_enable_intx(VFIODevice *vdev)
478 {
479 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1);
480 int ret, argsz;
481 struct vfio_irq_set *irq_set;
482 int32_t *pfd;
483
484 if (!pin) {
485 return 0;
486 }
487
488 vfio_disable_interrupts(vdev);
489
490 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */
491 pci_config_set_interrupt_pin(vdev->pdev.config, pin);
492
493 #ifdef CONFIG_KVM
494 /*
495 * Only conditional to avoid generating error messages on platforms
496 * where we won't actually use the result anyway.
497 */
498 if (kvm_irqfds_enabled() &&
499 kvm_check_extension(kvm_state, KVM_CAP_IRQFD_RESAMPLE)) {
500 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev,
501 vdev->intx.pin);
502 }
503 #endif
504
505 ret = event_notifier_init(&vdev->intx.interrupt, 0);
506 if (ret) {
507 error_report("vfio: Error: event_notifier_init failed");
508 return ret;
509 }
510
511 argsz = sizeof(*irq_set) + sizeof(*pfd);
512
513 irq_set = g_malloc0(argsz);
514 irq_set->argsz = argsz;
515 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
516 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX;
517 irq_set->start = 0;
518 irq_set->count = 1;
519 pfd = (int32_t *)&irq_set->data;
520
521 *pfd = event_notifier_get_fd(&vdev->intx.interrupt);
522 qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev);
523
524 ret = ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
525 g_free(irq_set);
526 if (ret) {
527 error_report("vfio: Error: Failed to setup INTx fd: %m");
528 qemu_set_fd_handler(*pfd, NULL, NULL, vdev);
529 event_notifier_cleanup(&vdev->intx.interrupt);
530 return -errno;
531 }
532
533 vfio_enable_intx_kvm(vdev);
534
535 vdev->interrupt = VFIO_INT_INTx;
536
537 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
538 vdev->host.bus, vdev->host.slot, vdev->host.function);
539
540 return 0;
541 }
542
543 static void vfio_disable_intx(VFIODevice *vdev)
544 {
545 int fd;
546
547 timer_del(vdev->intx.mmap_timer);
548 vfio_disable_intx_kvm(vdev);
549 vfio_disable_irqindex(vdev, VFIO_PCI_INTX_IRQ_INDEX);
550 vdev->intx.pending = false;
551 pci_irq_deassert(&vdev->pdev);
552 vfio_mmap_set_enabled(vdev, true);
553
554 fd = event_notifier_get_fd(&vdev->intx.interrupt);
555 qemu_set_fd_handler(fd, NULL, NULL, vdev);
556 event_notifier_cleanup(&vdev->intx.interrupt);
557
558 vdev->interrupt = VFIO_INT_NONE;
559
560 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
561 vdev->host.bus, vdev->host.slot, vdev->host.function);
562 }
563
564 /*
565 * MSI/X
566 */
567 static void vfio_msi_interrupt(void *opaque)
568 {
569 VFIOMSIVector *vector = opaque;
570 VFIODevice *vdev = vector->vdev;
571 int nr = vector - vdev->msi_vectors;
572
573 if (!event_notifier_test_and_clear(&vector->interrupt)) {
574 return;
575 }
576
577 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d\n", __func__,
578 vdev->host.domain, vdev->host.bus, vdev->host.slot,
579 vdev->host.function, nr);
580
581 if (vdev->interrupt == VFIO_INT_MSIX) {
582 msix_notify(&vdev->pdev, nr);
583 } else if (vdev->interrupt == VFIO_INT_MSI) {
584 msi_notify(&vdev->pdev, nr);
585 } else {
586 error_report("vfio: MSI interrupt receieved, but not enabled?");
587 }
588 }
589
590 static int vfio_enable_vectors(VFIODevice *vdev, bool msix)
591 {
592 struct vfio_irq_set *irq_set;
593 int ret = 0, i, argsz;
594 int32_t *fds;
595
596 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds));
597
598 irq_set = g_malloc0(argsz);
599 irq_set->argsz = argsz;
600 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
601 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX;
602 irq_set->start = 0;
603 irq_set->count = vdev->nr_vectors;
604 fds = (int32_t *)&irq_set->data;
605
606 for (i = 0; i < vdev->nr_vectors; i++) {
607 if (!vdev->msi_vectors[i].use) {
608 fds[i] = -1;
609 continue;
610 }
611
612 fds[i] = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt);
613 }
614
615 ret = ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
616
617 g_free(irq_set);
618
619 return ret;
620 }
621
622 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr,
623 MSIMessage *msg, IOHandler *handler)
624 {
625 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
626 VFIOMSIVector *vector;
627 int ret;
628
629 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d used\n", __func__,
630 vdev->host.domain, vdev->host.bus, vdev->host.slot,
631 vdev->host.function, nr);
632
633 vector = &vdev->msi_vectors[nr];
634 vector->vdev = vdev;
635 vector->use = true;
636
637 msix_vector_use(pdev, nr);
638
639 if (event_notifier_init(&vector->interrupt, 0)) {
640 error_report("vfio: Error: event_notifier_init failed");
641 }
642
643 /*
644 * Attempt to enable route through KVM irqchip,
645 * default to userspace handling if unavailable.
646 */
647 vector->virq = msg ? kvm_irqchip_add_msi_route(kvm_state, *msg) : -1;
648 if (vector->virq < 0 ||
649 kvm_irqchip_add_irqfd_notifier(kvm_state, &vector->interrupt,
650 NULL, vector->virq) < 0) {
651 if (vector->virq >= 0) {
652 kvm_irqchip_release_virq(kvm_state, vector->virq);
653 vector->virq = -1;
654 }
655 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
656 handler, NULL, vector);
657 }
658
659 /*
660 * We don't want to have the host allocate all possible MSI vectors
661 * for a device if they're not in use, so we shutdown and incrementally
662 * increase them as needed.
663 */
664 if (vdev->nr_vectors < nr + 1) {
665 vfio_disable_irqindex(vdev, VFIO_PCI_MSIX_IRQ_INDEX);
666 vdev->nr_vectors = nr + 1;
667 ret = vfio_enable_vectors(vdev, true);
668 if (ret) {
669 error_report("vfio: failed to enable vectors, %d", ret);
670 }
671 } else {
672 int argsz;
673 struct vfio_irq_set *irq_set;
674 int32_t *pfd;
675
676 argsz = sizeof(*irq_set) + sizeof(*pfd);
677
678 irq_set = g_malloc0(argsz);
679 irq_set->argsz = argsz;
680 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
681 VFIO_IRQ_SET_ACTION_TRIGGER;
682 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
683 irq_set->start = nr;
684 irq_set->count = 1;
685 pfd = (int32_t *)&irq_set->data;
686
687 *pfd = event_notifier_get_fd(&vector->interrupt);
688
689 ret = ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
690 g_free(irq_set);
691 if (ret) {
692 error_report("vfio: failed to modify vector, %d", ret);
693 }
694 }
695
696 return 0;
697 }
698
699 static int vfio_msix_vector_use(PCIDevice *pdev,
700 unsigned int nr, MSIMessage msg)
701 {
702 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt);
703 }
704
705 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr)
706 {
707 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
708 VFIOMSIVector *vector = &vdev->msi_vectors[nr];
709 int argsz;
710 struct vfio_irq_set *irq_set;
711 int32_t *pfd;
712
713 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d released\n", __func__,
714 vdev->host.domain, vdev->host.bus, vdev->host.slot,
715 vdev->host.function, nr);
716
717 /*
718 * XXX What's the right thing to do here? This turns off the interrupt
719 * completely, but do we really just want to switch the interrupt to
720 * bouncing through userspace and let msix.c drop it? Not sure.
721 */
722 msix_vector_unuse(pdev, nr);
723
724 argsz = sizeof(*irq_set) + sizeof(*pfd);
725
726 irq_set = g_malloc0(argsz);
727 irq_set->argsz = argsz;
728 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
729 VFIO_IRQ_SET_ACTION_TRIGGER;
730 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
731 irq_set->start = nr;
732 irq_set->count = 1;
733 pfd = (int32_t *)&irq_set->data;
734
735 *pfd = -1;
736
737 ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
738
739 g_free(irq_set);
740
741 if (vector->virq < 0) {
742 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
743 NULL, NULL, NULL);
744 } else {
745 kvm_irqchip_remove_irqfd_notifier(kvm_state, &vector->interrupt,
746 vector->virq);
747 kvm_irqchip_release_virq(kvm_state, vector->virq);
748 vector->virq = -1;
749 }
750
751 event_notifier_cleanup(&vector->interrupt);
752 vector->use = false;
753 }
754
755 static void vfio_enable_msix(VFIODevice *vdev)
756 {
757 vfio_disable_interrupts(vdev);
758
759 vdev->msi_vectors = g_malloc0(vdev->msix->entries * sizeof(VFIOMSIVector));
760
761 vdev->interrupt = VFIO_INT_MSIX;
762
763 /*
764 * Some communication channels between VF & PF or PF & fw rely on the
765 * physical state of the device and expect that enabling MSI-X from the
766 * guest enables the same on the host. When our guest is Linux, the
767 * guest driver call to pci_enable_msix() sets the enabling bit in the
768 * MSI-X capability, but leaves the vector table masked. We therefore
769 * can't rely on a vector_use callback (from request_irq() in the guest)
770 * to switch the physical device into MSI-X mode because that may come a
771 * long time after pci_enable_msix(). This code enables vector 0 with
772 * triggering to userspace, then immediately release the vector, leaving
773 * the physical device with no vectors enabled, but MSI-X enabled, just
774 * like the guest view.
775 */
776 vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL);
777 vfio_msix_vector_release(&vdev->pdev, 0);
778
779 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use,
780 vfio_msix_vector_release, NULL)) {
781 error_report("vfio: msix_set_vector_notifiers failed");
782 }
783
784 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
785 vdev->host.bus, vdev->host.slot, vdev->host.function);
786 }
787
788 static void vfio_enable_msi(VFIODevice *vdev)
789 {
790 int ret, i;
791
792 vfio_disable_interrupts(vdev);
793
794 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev);
795 retry:
796 vdev->msi_vectors = g_malloc0(vdev->nr_vectors * sizeof(VFIOMSIVector));
797
798 for (i = 0; i < vdev->nr_vectors; i++) {
799 MSIMessage msg;
800 VFIOMSIVector *vector = &vdev->msi_vectors[i];
801
802 vector->vdev = vdev;
803 vector->use = true;
804
805 if (event_notifier_init(&vector->interrupt, 0)) {
806 error_report("vfio: Error: event_notifier_init failed");
807 }
808
809 msg = msi_get_message(&vdev->pdev, i);
810
811 /*
812 * Attempt to enable route through KVM irqchip,
813 * default to userspace handling if unavailable.
814 */
815 vector->virq = kvm_irqchip_add_msi_route(kvm_state, msg);
816 if (vector->virq < 0 ||
817 kvm_irqchip_add_irqfd_notifier(kvm_state, &vector->interrupt,
818 NULL, vector->virq) < 0) {
819 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
820 vfio_msi_interrupt, NULL, vector);
821 }
822 }
823
824 ret = vfio_enable_vectors(vdev, false);
825 if (ret) {
826 if (ret < 0) {
827 error_report("vfio: Error: Failed to setup MSI fds: %m");
828 } else if (ret != vdev->nr_vectors) {
829 error_report("vfio: Error: Failed to enable %d "
830 "MSI vectors, retry with %d", vdev->nr_vectors, ret);
831 }
832
833 for (i = 0; i < vdev->nr_vectors; i++) {
834 VFIOMSIVector *vector = &vdev->msi_vectors[i];
835 if (vector->virq >= 0) {
836 kvm_irqchip_remove_irqfd_notifier(kvm_state, &vector->interrupt,
837 vector->virq);
838 kvm_irqchip_release_virq(kvm_state, vector->virq);
839 vector->virq = -1;
840 } else {
841 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
842 NULL, NULL, NULL);
843 }
844 event_notifier_cleanup(&vector->interrupt);
845 }
846
847 g_free(vdev->msi_vectors);
848
849 if (ret > 0 && ret != vdev->nr_vectors) {
850 vdev->nr_vectors = ret;
851 goto retry;
852 }
853 vdev->nr_vectors = 0;
854
855 return;
856 }
857
858 vdev->interrupt = VFIO_INT_MSI;
859
860 DPRINTF("%s(%04x:%02x:%02x.%x) Enabled %d MSI vectors\n", __func__,
861 vdev->host.domain, vdev->host.bus, vdev->host.slot,
862 vdev->host.function, vdev->nr_vectors);
863 }
864
865 static void vfio_disable_msi_common(VFIODevice *vdev)
866 {
867 g_free(vdev->msi_vectors);
868 vdev->msi_vectors = NULL;
869 vdev->nr_vectors = 0;
870 vdev->interrupt = VFIO_INT_NONE;
871
872 vfio_enable_intx(vdev);
873 }
874
875 static void vfio_disable_msix(VFIODevice *vdev)
876 {
877 msix_unset_vector_notifiers(&vdev->pdev);
878
879 if (vdev->nr_vectors) {
880 vfio_disable_irqindex(vdev, VFIO_PCI_MSIX_IRQ_INDEX);
881 }
882
883 vfio_disable_msi_common(vdev);
884
885 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
886 vdev->host.bus, vdev->host.slot, vdev->host.function);
887 }
888
889 static void vfio_disable_msi(VFIODevice *vdev)
890 {
891 int i;
892
893 vfio_disable_irqindex(vdev, VFIO_PCI_MSI_IRQ_INDEX);
894
895 for (i = 0; i < vdev->nr_vectors; i++) {
896 VFIOMSIVector *vector = &vdev->msi_vectors[i];
897
898 if (!vector->use) {
899 continue;
900 }
901
902 if (vector->virq >= 0) {
903 kvm_irqchip_remove_irqfd_notifier(kvm_state,
904 &vector->interrupt, vector->virq);
905 kvm_irqchip_release_virq(kvm_state, vector->virq);
906 vector->virq = -1;
907 } else {
908 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
909 NULL, NULL, NULL);
910 }
911
912 event_notifier_cleanup(&vector->interrupt);
913 }
914
915 vfio_disable_msi_common(vdev);
916
917 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
918 vdev->host.bus, vdev->host.slot, vdev->host.function);
919 }
920
921 /*
922 * IO Port/MMIO - Beware of the endians, VFIO is always little endian
923 */
924 static void vfio_bar_write(void *opaque, hwaddr addr,
925 uint64_t data, unsigned size)
926 {
927 VFIOBAR *bar = opaque;
928 union {
929 uint8_t byte;
930 uint16_t word;
931 uint32_t dword;
932 uint64_t qword;
933 } buf;
934
935 switch (size) {
936 case 1:
937 buf.byte = data;
938 break;
939 case 2:
940 buf.word = cpu_to_le16(data);
941 break;
942 case 4:
943 buf.dword = cpu_to_le32(data);
944 break;
945 default:
946 hw_error("vfio: unsupported write size, %d bytes\n", size);
947 break;
948 }
949
950 if (pwrite(bar->fd, &buf, size, bar->fd_offset + addr) != size) {
951 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m",
952 __func__, addr, data, size);
953 }
954
955 #ifdef DEBUG_VFIO
956 {
957 VFIODevice *vdev = container_of(bar, VFIODevice, bars[bar->nr]);
958
959 DPRINTF("%s(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", 0x%"PRIx64
960 ", %d)\n", __func__, vdev->host.domain, vdev->host.bus,
961 vdev->host.slot, vdev->host.function, bar->nr, addr,
962 data, size);
963 }
964 #endif
965
966 /*
967 * A read or write to a BAR always signals an INTx EOI. This will
968 * do nothing if not pending (including not in INTx mode). We assume
969 * that a BAR access is in response to an interrupt and that BAR
970 * accesses will service the interrupt. Unfortunately, we don't know
971 * which access will service the interrupt, so we're potentially
972 * getting quite a few host interrupts per guest interrupt.
973 */
974 vfio_eoi(container_of(bar, VFIODevice, bars[bar->nr]));
975 }
976
977 static uint64_t vfio_bar_read(void *opaque,
978 hwaddr addr, unsigned size)
979 {
980 VFIOBAR *bar = opaque;
981 union {
982 uint8_t byte;
983 uint16_t word;
984 uint32_t dword;
985 uint64_t qword;
986 } buf;
987 uint64_t data = 0;
988
989 if (pread(bar->fd, &buf, size, bar->fd_offset + addr) != size) {
990 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m",
991 __func__, addr, size);
992 return (uint64_t)-1;
993 }
994
995 switch (size) {
996 case 1:
997 data = buf.byte;
998 break;
999 case 2:
1000 data = le16_to_cpu(buf.word);
1001 break;
1002 case 4:
1003 data = le32_to_cpu(buf.dword);
1004 break;
1005 default:
1006 hw_error("vfio: unsupported read size, %d bytes\n", size);
1007 break;
1008 }
1009
1010 #ifdef DEBUG_VFIO
1011 {
1012 VFIODevice *vdev = container_of(bar, VFIODevice, bars[bar->nr]);
1013
1014 DPRINTF("%s(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
1015 ", %d) = 0x%"PRIx64"\n", __func__, vdev->host.domain,
1016 vdev->host.bus, vdev->host.slot, vdev->host.function,
1017 bar->nr, addr, size, data);
1018 }
1019 #endif
1020
1021 /* Same as write above */
1022 vfio_eoi(container_of(bar, VFIODevice, bars[bar->nr]));
1023
1024 return data;
1025 }
1026
1027 static const MemoryRegionOps vfio_bar_ops = {
1028 .read = vfio_bar_read,
1029 .write = vfio_bar_write,
1030 .endianness = DEVICE_LITTLE_ENDIAN,
1031 };
1032
1033 static void vfio_vga_write(void *opaque, hwaddr addr,
1034 uint64_t data, unsigned size)
1035 {
1036 VFIOVGARegion *region = opaque;
1037 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1038 union {
1039 uint8_t byte;
1040 uint16_t word;
1041 uint32_t dword;
1042 uint64_t qword;
1043 } buf;
1044 off_t offset = vga->fd_offset + region->offset + addr;
1045
1046 switch (size) {
1047 case 1:
1048 buf.byte = data;
1049 break;
1050 case 2:
1051 buf.word = cpu_to_le16(data);
1052 break;
1053 case 4:
1054 buf.dword = cpu_to_le32(data);
1055 break;
1056 default:
1057 hw_error("vfio: unsupported write size, %d bytes\n", size);
1058 break;
1059 }
1060
1061 if (pwrite(vga->fd, &buf, size, offset) != size) {
1062 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m",
1063 __func__, region->offset + addr, data, size);
1064 }
1065
1066 DPRINTF("%s(0x%"HWADDR_PRIx", 0x%"PRIx64", %d)\n",
1067 __func__, region->offset + addr, data, size);
1068 }
1069
1070 static uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size)
1071 {
1072 VFIOVGARegion *region = opaque;
1073 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1074 union {
1075 uint8_t byte;
1076 uint16_t word;
1077 uint32_t dword;
1078 uint64_t qword;
1079 } buf;
1080 uint64_t data = 0;
1081 off_t offset = vga->fd_offset + region->offset + addr;
1082
1083 if (pread(vga->fd, &buf, size, offset) != size) {
1084 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m",
1085 __func__, region->offset + addr, size);
1086 return (uint64_t)-1;
1087 }
1088
1089 switch (size) {
1090 case 1:
1091 data = buf.byte;
1092 break;
1093 case 2:
1094 data = le16_to_cpu(buf.word);
1095 break;
1096 case 4:
1097 data = le32_to_cpu(buf.dword);
1098 break;
1099 default:
1100 hw_error("vfio: unsupported read size, %d bytes\n", size);
1101 break;
1102 }
1103
1104 DPRINTF("%s(0x%"HWADDR_PRIx", %d) = 0x%"PRIx64"\n",
1105 __func__, region->offset + addr, size, data);
1106
1107 return data;
1108 }
1109
1110 static const MemoryRegionOps vfio_vga_ops = {
1111 .read = vfio_vga_read,
1112 .write = vfio_vga_write,
1113 .endianness = DEVICE_LITTLE_ENDIAN,
1114 };
1115
1116 /*
1117 * Device specific quirks
1118 */
1119
1120 /* Is range1 fully contained within range2? */
1121 static bool vfio_range_contained(uint64_t first1, uint64_t len1,
1122 uint64_t first2, uint64_t len2) {
1123 return (first1 >= first2 && first1 + len1 <= first2 + len2);
1124 }
1125
1126 static bool vfio_flags_enabled(uint8_t flags, uint8_t mask)
1127 {
1128 return (mask && (flags & mask) == mask);
1129 }
1130
1131 static uint64_t vfio_generic_window_quirk_read(void *opaque,
1132 hwaddr addr, unsigned size)
1133 {
1134 VFIOQuirk *quirk = opaque;
1135 VFIODevice *vdev = quirk->vdev;
1136 uint64_t data;
1137
1138 if (vfio_flags_enabled(quirk->data.flags, quirk->data.read_flags) &&
1139 ranges_overlap(addr, size,
1140 quirk->data.data_offset, quirk->data.data_size)) {
1141 hwaddr offset = addr - quirk->data.data_offset;
1142
1143 if (!vfio_range_contained(addr, size, quirk->data.data_offset,
1144 quirk->data.data_size)) {
1145 hw_error("%s: window data read not fully contained: %s\n",
1146 __func__, memory_region_name(&quirk->mem));
1147 }
1148
1149 data = vfio_pci_read_config(&vdev->pdev,
1150 quirk->data.address_val + offset, size);
1151
1152 DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", %d) = 0x%"
1153 PRIx64"\n", memory_region_name(&quirk->mem), vdev->host.domain,
1154 vdev->host.bus, vdev->host.slot, vdev->host.function,
1155 quirk->data.bar, addr, size, data);
1156 } else {
1157 data = vfio_bar_read(&vdev->bars[quirk->data.bar],
1158 addr + quirk->data.base_offset, size);
1159 }
1160
1161 return data;
1162 }
1163
1164 static void vfio_generic_window_quirk_write(void *opaque, hwaddr addr,
1165 uint64_t data, unsigned size)
1166 {
1167 VFIOQuirk *quirk = opaque;
1168 VFIODevice *vdev = quirk->vdev;
1169
1170 if (ranges_overlap(addr, size,
1171 quirk->data.address_offset, quirk->data.address_size)) {
1172
1173 if (addr != quirk->data.address_offset) {
1174 hw_error("%s: offset write into address window: %s\n",
1175 __func__, memory_region_name(&quirk->mem));
1176 }
1177
1178 if ((data & ~quirk->data.address_mask) == quirk->data.address_match) {
1179 quirk->data.flags |= quirk->data.write_flags |
1180 quirk->data.read_flags;
1181 quirk->data.address_val = data & quirk->data.address_mask;
1182 } else {
1183 quirk->data.flags &= ~(quirk->data.write_flags |
1184 quirk->data.read_flags);
1185 }
1186 }
1187
1188 if (vfio_flags_enabled(quirk->data.flags, quirk->data.write_flags) &&
1189 ranges_overlap(addr, size,
1190 quirk->data.data_offset, quirk->data.data_size)) {
1191 hwaddr offset = addr - quirk->data.data_offset;
1192
1193 if (!vfio_range_contained(addr, size, quirk->data.data_offset,
1194 quirk->data.data_size)) {
1195 hw_error("%s: window data write not fully contained: %s\n",
1196 __func__, memory_region_name(&quirk->mem));
1197 }
1198
1199 vfio_pci_write_config(&vdev->pdev,
1200 quirk->data.address_val + offset, data, size);
1201 DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", 0x%"
1202 PRIx64", %d)\n", memory_region_name(&quirk->mem),
1203 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1204 vdev->host.function, quirk->data.bar, addr, data, size);
1205 return;
1206 }
1207
1208 vfio_bar_write(&vdev->bars[quirk->data.bar],
1209 addr + quirk->data.base_offset, data, size);
1210 }
1211
1212 static const MemoryRegionOps vfio_generic_window_quirk = {
1213 .read = vfio_generic_window_quirk_read,
1214 .write = vfio_generic_window_quirk_write,
1215 .endianness = DEVICE_LITTLE_ENDIAN,
1216 };
1217
1218 static uint64_t vfio_generic_quirk_read(void *opaque,
1219 hwaddr addr, unsigned size)
1220 {
1221 VFIOQuirk *quirk = opaque;
1222 VFIODevice *vdev = quirk->vdev;
1223 hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK;
1224 hwaddr offset = quirk->data.address_match & ~TARGET_PAGE_MASK;
1225 uint64_t data;
1226
1227 if (vfio_flags_enabled(quirk->data.flags, quirk->data.read_flags) &&
1228 ranges_overlap(addr, size, offset, quirk->data.address_mask + 1)) {
1229 if (!vfio_range_contained(addr, size, offset,
1230 quirk->data.address_mask + 1)) {
1231 hw_error("%s: read not fully contained: %s\n",
1232 __func__, memory_region_name(&quirk->mem));
1233 }
1234
1235 data = vfio_pci_read_config(&vdev->pdev, addr - offset, size);
1236
1237 DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", %d) = 0x%"
1238 PRIx64"\n", memory_region_name(&quirk->mem), vdev->host.domain,
1239 vdev->host.bus, vdev->host.slot, vdev->host.function,
1240 quirk->data.bar, addr + base, size, data);
1241 } else {
1242 data = vfio_bar_read(&vdev->bars[quirk->data.bar], addr + base, size);
1243 }
1244
1245 return data;
1246 }
1247
1248 static void vfio_generic_quirk_write(void *opaque, hwaddr addr,
1249 uint64_t data, unsigned size)
1250 {
1251 VFIOQuirk *quirk = opaque;
1252 VFIODevice *vdev = quirk->vdev;
1253 hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK;
1254 hwaddr offset = quirk->data.address_match & ~TARGET_PAGE_MASK;
1255
1256 if (vfio_flags_enabled(quirk->data.flags, quirk->data.write_flags) &&
1257 ranges_overlap(addr, size, offset, quirk->data.address_mask + 1)) {
1258 if (!vfio_range_contained(addr, size, offset,
1259 quirk->data.address_mask + 1)) {
1260 hw_error("%s: write not fully contained: %s\n",
1261 __func__, memory_region_name(&quirk->mem));
1262 }
1263
1264 vfio_pci_write_config(&vdev->pdev, addr - offset, data, size);
1265
1266 DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx", 0x%"
1267 PRIx64", %d)\n", memory_region_name(&quirk->mem),
1268 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1269 vdev->host.function, quirk->data.bar, addr + base, data, size);
1270 } else {
1271 vfio_bar_write(&vdev->bars[quirk->data.bar], addr + base, data, size);
1272 }
1273 }
1274
1275 static const MemoryRegionOps vfio_generic_quirk = {
1276 .read = vfio_generic_quirk_read,
1277 .write = vfio_generic_quirk_write,
1278 .endianness = DEVICE_LITTLE_ENDIAN,
1279 };
1280
1281 #define PCI_VENDOR_ID_ATI 0x1002
1282
1283 /*
1284 * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
1285 * through VGA register 0x3c3. On newer cards, the I/O port BAR is always
1286 * BAR4 (older cards like the X550 used BAR1, but we don't care to support
1287 * those). Note that on bare metal, a read of 0x3c3 doesn't always return the
1288 * I/O port BAR address. Originally this was coded to return the virtual BAR
1289 * address only if the physical register read returns the actual BAR address,
1290 * but users have reported greater success if we return the virtual address
1291 * unconditionally.
1292 */
1293 static uint64_t vfio_ati_3c3_quirk_read(void *opaque,
1294 hwaddr addr, unsigned size)
1295 {
1296 VFIOQuirk *quirk = opaque;
1297 VFIODevice *vdev = quirk->vdev;
1298 uint64_t data = vfio_pci_read_config(&vdev->pdev,
1299 PCI_BASE_ADDRESS_0 + (4 * 4) + 1,
1300 size);
1301 DPRINTF("%s(0x3c3, 1) = 0x%"PRIx64"\n", __func__, data);
1302
1303 return data;
1304 }
1305
1306 static const MemoryRegionOps vfio_ati_3c3_quirk = {
1307 .read = vfio_ati_3c3_quirk_read,
1308 .endianness = DEVICE_LITTLE_ENDIAN,
1309 };
1310
1311 static void vfio_vga_probe_ati_3c3_quirk(VFIODevice *vdev)
1312 {
1313 PCIDevice *pdev = &vdev->pdev;
1314 VFIOQuirk *quirk;
1315
1316 if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) {
1317 return;
1318 }
1319
1320 /*
1321 * As long as the BAR is >= 256 bytes it will be aligned such that the
1322 * lower byte is always zero. Filter out anything else, if it exists.
1323 */
1324 if (!vdev->bars[4].ioport || vdev->bars[4].size < 256) {
1325 return;
1326 }
1327
1328 quirk = g_malloc0(sizeof(*quirk));
1329 quirk->vdev = vdev;
1330
1331 memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_ati_3c3_quirk, quirk,
1332 "vfio-ati-3c3-quirk", 1);
1333 memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
1334 3 /* offset 3 bytes from 0x3c0 */, &quirk->mem);
1335
1336 QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks,
1337 quirk, next);
1338
1339 DPRINTF("Enabled ATI/AMD quirk 0x3c3 BAR4for device %04x:%02x:%02x.%x\n",
1340 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1341 vdev->host.function);
1342 }
1343
1344 /*
1345 * Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI
1346 * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
1347 * the MMIO space directly, but a window to this space is provided through
1348 * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
1349 * data register. When the address is programmed to a range of 0x4000-0x4fff
1350 * PCI configuration space is available. Experimentation seems to indicate
1351 * that only read-only access is provided, but we drop writes when the window
1352 * is enabled to config space nonetheless.
1353 */
1354 static void vfio_probe_ati_bar4_window_quirk(VFIODevice *vdev, int nr)
1355 {
1356 PCIDevice *pdev = &vdev->pdev;
1357 VFIOQuirk *quirk;
1358
1359 if (!vdev->has_vga || nr != 4 ||
1360 pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) {
1361 return;
1362 }
1363
1364 quirk = g_malloc0(sizeof(*quirk));
1365 quirk->vdev = vdev;
1366 quirk->data.address_size = 4;
1367 quirk->data.data_offset = 4;
1368 quirk->data.data_size = 4;
1369 quirk->data.address_match = 0x4000;
1370 quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1;
1371 quirk->data.bar = nr;
1372 quirk->data.read_flags = quirk->data.write_flags = 1;
1373
1374 memory_region_init_io(&quirk->mem, OBJECT(vdev),
1375 &vfio_generic_window_quirk, quirk,
1376 "vfio-ati-bar4-window-quirk", 8);
1377 memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
1378 quirk->data.base_offset, &quirk->mem, 1);
1379
1380 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
1381
1382 DPRINTF("Enabled ATI/AMD BAR4 window quirk for device %04x:%02x:%02x.%x\n",
1383 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1384 vdev->host.function);
1385 }
1386
1387 /*
1388 * Trap the BAR2 MMIO window to config space as well.
1389 */
1390 static void vfio_probe_ati_bar2_4000_quirk(VFIODevice *vdev, int nr)
1391 {
1392 PCIDevice *pdev = &vdev->pdev;
1393 VFIOQuirk *quirk;
1394
1395 /* Only enable on newer devices where BAR2 is 64bit */
1396 if (!vdev->has_vga || nr != 2 || !vdev->bars[2].mem64 ||
1397 pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) {
1398 return;
1399 }
1400
1401 quirk = g_malloc0(sizeof(*quirk));
1402 quirk->vdev = vdev;
1403 quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1;
1404 quirk->data.address_match = 0x4000;
1405 quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1;
1406 quirk->data.bar = nr;
1407
1408 memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk, quirk,
1409 "vfio-ati-bar2-4000-quirk",
1410 TARGET_PAGE_ALIGN(quirk->data.address_mask + 1));
1411 memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
1412 quirk->data.address_match & TARGET_PAGE_MASK,
1413 &quirk->mem, 1);
1414
1415 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
1416
1417 DPRINTF("Enabled ATI/AMD BAR2 0x4000 quirk for device %04x:%02x:%02x.%x\n",
1418 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1419 vdev->host.function);
1420 }
1421
1422 /*
1423 * Older ATI/AMD cards like the X550 have a similar window to that above.
1424 * I/O port BAR1 provides a window to a mirror of PCI config space located
1425 * in BAR2 at offset 0xf00. We don't care to support such older cards, but
1426 * note it for future reference.
1427 */
1428
1429 #define PCI_VENDOR_ID_NVIDIA 0x10de
1430
1431 /*
1432 * Nvidia has several different methods to get to config space, the
1433 * nouveu project has several of these documented here:
1434 * https://github.com/pathscale/envytools/tree/master/hwdocs
1435 *
1436 * The first quirk is actually not documented in envytools and is found
1437 * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an
1438 * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access
1439 * the mirror of PCI config space found at BAR0 offset 0x1800. The access
1440 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
1441 * then written to 0x3d0. Finally 0x538 is written for a read and 0x738
1442 * is written for a write to 0x3d4. The BAR0 offset is then accessible
1443 * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
1444 * that use the I/O port BAR5 window but it doesn't hurt to leave it.
1445 */
1446 enum {
1447 NV_3D0_NONE = 0,
1448 NV_3D0_SELECT,
1449 NV_3D0_WINDOW,
1450 NV_3D0_READ,
1451 NV_3D0_WRITE,
1452 };
1453
1454 static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque,
1455 hwaddr addr, unsigned size)
1456 {
1457 VFIOQuirk *quirk = opaque;
1458 VFIODevice *vdev = quirk->vdev;
1459 PCIDevice *pdev = &vdev->pdev;
1460 uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
1461 addr + quirk->data.base_offset, size);
1462
1463 if (quirk->data.flags == NV_3D0_READ && addr == quirk->data.data_offset) {
1464 data = vfio_pci_read_config(pdev, quirk->data.address_val, size);
1465 DPRINTF("%s(0x3d0, %d) = 0x%"PRIx64"\n", __func__, size, data);
1466 }
1467
1468 quirk->data.flags = NV_3D0_NONE;
1469
1470 return data;
1471 }
1472
1473 static void vfio_nvidia_3d0_quirk_write(void *opaque, hwaddr addr,
1474 uint64_t data, unsigned size)
1475 {
1476 VFIOQuirk *quirk = opaque;
1477 VFIODevice *vdev = quirk->vdev;
1478 PCIDevice *pdev = &vdev->pdev;
1479
1480 switch (quirk->data.flags) {
1481 case NV_3D0_NONE:
1482 if (addr == quirk->data.address_offset && data == 0x338) {
1483 quirk->data.flags = NV_3D0_SELECT;
1484 }
1485 break;
1486 case NV_3D0_SELECT:
1487 quirk->data.flags = NV_3D0_NONE;
1488 if (addr == quirk->data.data_offset &&
1489 (data & ~quirk->data.address_mask) == quirk->data.address_match) {
1490 quirk->data.flags = NV_3D0_WINDOW;
1491 quirk->data.address_val = data & quirk->data.address_mask;
1492 }
1493 break;
1494 case NV_3D0_WINDOW:
1495 quirk->data.flags = NV_3D0_NONE;
1496 if (addr == quirk->data.address_offset) {
1497 if (data == 0x538) {
1498 quirk->data.flags = NV_3D0_READ;
1499 } else if (data == 0x738) {
1500 quirk->data.flags = NV_3D0_WRITE;
1501 }
1502 }
1503 break;
1504 case NV_3D0_WRITE:
1505 quirk->data.flags = NV_3D0_NONE;
1506 if (addr == quirk->data.data_offset) {
1507 vfio_pci_write_config(pdev, quirk->data.address_val, data, size);
1508 DPRINTF("%s(0x3d0, 0x%"PRIx64", %d)\n", __func__, data, size);
1509 return;
1510 }
1511 break;
1512 }
1513
1514 vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
1515 addr + quirk->data.base_offset, data, size);
1516 }
1517
1518 static const MemoryRegionOps vfio_nvidia_3d0_quirk = {
1519 .read = vfio_nvidia_3d0_quirk_read,
1520 .write = vfio_nvidia_3d0_quirk_write,
1521 .endianness = DEVICE_LITTLE_ENDIAN,
1522 };
1523
1524 static void vfio_vga_probe_nvidia_3d0_quirk(VFIODevice *vdev)
1525 {
1526 PCIDevice *pdev = &vdev->pdev;
1527 VFIOQuirk *quirk;
1528
1529 if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA ||
1530 !vdev->bars[1].size) {
1531 return;
1532 }
1533
1534 quirk = g_malloc0(sizeof(*quirk));
1535 quirk->vdev = vdev;
1536 quirk->data.base_offset = 0x10;
1537 quirk->data.address_offset = 4;
1538 quirk->data.address_size = 2;
1539 quirk->data.address_match = 0x1800;
1540 quirk->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1;
1541 quirk->data.data_offset = 0;
1542 quirk->data.data_size = 4;
1543
1544 memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_3d0_quirk,
1545 quirk, "vfio-nvidia-3d0-quirk", 6);
1546 memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
1547 quirk->data.base_offset, &quirk->mem);
1548
1549 QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks,
1550 quirk, next);
1551
1552 DPRINTF("Enabled NVIDIA VGA 0x3d0 quirk for device %04x:%02x:%02x.%x\n",
1553 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1554 vdev->host.function);
1555 }
1556
1557 /*
1558 * The second quirk is documented in envytools. The I/O port BAR5 is just
1559 * a set of address/data ports to the MMIO BARs. The BAR we care about is
1560 * again BAR0. This backdoor is apparently a bit newer than the one above
1561 * so we need to not only trap 256 bytes @0x1800, but all of PCI config
1562 * space, including extended space is available at the 4k @0x88000.
1563 */
1564 enum {
1565 NV_BAR5_ADDRESS = 0x1,
1566 NV_BAR5_ENABLE = 0x2,
1567 NV_BAR5_MASTER = 0x4,
1568 NV_BAR5_VALID = 0x7,
1569 };
1570
1571 static void vfio_nvidia_bar5_window_quirk_write(void *opaque, hwaddr addr,
1572 uint64_t data, unsigned size)
1573 {
1574 VFIOQuirk *quirk = opaque;
1575
1576 switch (addr) {
1577 case 0x0:
1578 if (data & 0x1) {
1579 quirk->data.flags |= NV_BAR5_MASTER;
1580 } else {
1581 quirk->data.flags &= ~NV_BAR5_MASTER;
1582 }
1583 break;
1584 case 0x4:
1585 if (data & 0x1) {
1586 quirk->data.flags |= NV_BAR5_ENABLE;
1587 } else {
1588 quirk->data.flags &= ~NV_BAR5_ENABLE;
1589 }
1590 break;
1591 case 0x8:
1592 if (quirk->data.flags & NV_BAR5_MASTER) {
1593 if ((data & ~0xfff) == 0x88000) {
1594 quirk->data.flags |= NV_BAR5_ADDRESS;
1595 quirk->data.address_val = data & 0xfff;
1596 } else if ((data & ~0xff) == 0x1800) {
1597 quirk->data.flags |= NV_BAR5_ADDRESS;
1598 quirk->data.address_val = data & 0xff;
1599 } else {
1600 quirk->data.flags &= ~NV_BAR5_ADDRESS;
1601 }
1602 }
1603 break;
1604 }
1605
1606 vfio_generic_window_quirk_write(opaque, addr, data, size);
1607 }
1608
1609 static const MemoryRegionOps vfio_nvidia_bar5_window_quirk = {
1610 .read = vfio_generic_window_quirk_read,
1611 .write = vfio_nvidia_bar5_window_quirk_write,
1612 .valid.min_access_size = 4,
1613 .endianness = DEVICE_LITTLE_ENDIAN,
1614 };
1615
1616 static void vfio_probe_nvidia_bar5_window_quirk(VFIODevice *vdev, int nr)
1617 {
1618 PCIDevice *pdev = &vdev->pdev;
1619 VFIOQuirk *quirk;
1620
1621 if (!vdev->has_vga || nr != 5 ||
1622 pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA) {
1623 return;
1624 }
1625
1626 quirk = g_malloc0(sizeof(*quirk));
1627 quirk->vdev = vdev;
1628 quirk->data.read_flags = quirk->data.write_flags = NV_BAR5_VALID;
1629 quirk->data.address_offset = 0x8;
1630 quirk->data.address_size = 0; /* actually 4, but avoids generic code */
1631 quirk->data.data_offset = 0xc;
1632 quirk->data.data_size = 4;
1633 quirk->data.bar = nr;
1634
1635 memory_region_init_io(&quirk->mem, OBJECT(vdev),
1636 &vfio_nvidia_bar5_window_quirk, quirk,
1637 "vfio-nvidia-bar5-window-quirk", 16);
1638 memory_region_add_subregion_overlap(&vdev->bars[nr].mem, 0, &quirk->mem, 1);
1639
1640 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
1641
1642 DPRINTF("Enabled NVIDIA BAR5 window quirk for device %04x:%02x:%02x.%x\n",
1643 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1644 vdev->host.function);
1645 }
1646
1647 /*
1648 * Finally, BAR0 itself. We want to redirect any accesses to either
1649 * 0x1800 or 0x88000 through the PCI config space access functions.
1650 *
1651 * NB - quirk at a page granularity or else they don't seem to work when
1652 * BARs are mmap'd
1653 *
1654 * Here's offset 0x88000...
1655 */
1656 static void vfio_probe_nvidia_bar0_88000_quirk(VFIODevice *vdev, int nr)
1657 {
1658 PCIDevice *pdev = &vdev->pdev;
1659 VFIOQuirk *quirk;
1660
1661 if (!vdev->has_vga || nr != 0 ||
1662 pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA) {
1663 return;
1664 }
1665
1666 quirk = g_malloc0(sizeof(*quirk));
1667 quirk->vdev = vdev;
1668 quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1;
1669 quirk->data.address_match = 0x88000;
1670 quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1;
1671 quirk->data.bar = nr;
1672
1673 memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk,
1674 quirk, "vfio-nvidia-bar0-88000-quirk",
1675 TARGET_PAGE_ALIGN(quirk->data.address_mask + 1));
1676 memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
1677 quirk->data.address_match & TARGET_PAGE_MASK,
1678 &quirk->mem, 1);
1679
1680 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
1681
1682 DPRINTF("Enabled NVIDIA BAR0 0x88000 quirk for device %04x:%02x:%02x.%x\n",
1683 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1684 vdev->host.function);
1685 }
1686
1687 /*
1688 * And here's the same for BAR0 offset 0x1800...
1689 */
1690 static void vfio_probe_nvidia_bar0_1800_quirk(VFIODevice *vdev, int nr)
1691 {
1692 PCIDevice *pdev = &vdev->pdev;
1693 VFIOQuirk *quirk;
1694
1695 if (!vdev->has_vga || nr != 0 ||
1696 pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA) {
1697 return;
1698 }
1699
1700 /* Log the chipset ID */
1701 DPRINTF("Nvidia NV%02x\n",
1702 (unsigned int)(vfio_bar_read(&vdev->bars[0], 0, 4) >> 20) & 0xff);
1703
1704 quirk = g_malloc0(sizeof(*quirk));
1705 quirk->vdev = vdev;
1706 quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1;
1707 quirk->data.address_match = 0x1800;
1708 quirk->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1;
1709 quirk->data.bar = nr;
1710
1711 memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk, quirk,
1712 "vfio-nvidia-bar0-1800-quirk",
1713 TARGET_PAGE_ALIGN(quirk->data.address_mask + 1));
1714 memory_region_add_subregion_overlap(&vdev->bars[nr].mem,
1715 quirk->data.address_match & TARGET_PAGE_MASK,
1716 &quirk->mem, 1);
1717
1718 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
1719
1720 DPRINTF("Enabled NVIDIA BAR0 0x1800 quirk for device %04x:%02x:%02x.%x\n",
1721 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1722 vdev->host.function);
1723 }
1724
1725 /*
1726 * TODO - Some Nvidia devices provide config access to their companion HDA
1727 * device and even to their parent bridge via these config space mirrors.
1728 * Add quirks for those regions.
1729 */
1730
1731 /*
1732 * Common quirk probe entry points.
1733 */
1734 static void vfio_vga_quirk_setup(VFIODevice *vdev)
1735 {
1736 vfio_vga_probe_ati_3c3_quirk(vdev);
1737 vfio_vga_probe_nvidia_3d0_quirk(vdev);
1738 }
1739
1740 static void vfio_vga_quirk_teardown(VFIODevice *vdev)
1741 {
1742 int i;
1743
1744 for (i = 0; i < ARRAY_SIZE(vdev->vga.region); i++) {
1745 while (!QLIST_EMPTY(&vdev->vga.region[i].quirks)) {
1746 VFIOQuirk *quirk = QLIST_FIRST(&vdev->vga.region[i].quirks);
1747 memory_region_del_subregion(&vdev->vga.region[i].mem, &quirk->mem);
1748 QLIST_REMOVE(quirk, next);
1749 g_free(quirk);
1750 }
1751 }
1752 }
1753
1754 static void vfio_bar_quirk_setup(VFIODevice *vdev, int nr)
1755 {
1756 vfio_probe_ati_bar4_window_quirk(vdev, nr);
1757 vfio_probe_ati_bar2_4000_quirk(vdev, nr);
1758 vfio_probe_nvidia_bar5_window_quirk(vdev, nr);
1759 vfio_probe_nvidia_bar0_88000_quirk(vdev, nr);
1760 vfio_probe_nvidia_bar0_1800_quirk(vdev, nr);
1761 }
1762
1763 static void vfio_bar_quirk_teardown(VFIODevice *vdev, int nr)
1764 {
1765 VFIOBAR *bar = &vdev->bars[nr];
1766
1767 while (!QLIST_EMPTY(&bar->quirks)) {
1768 VFIOQuirk *quirk = QLIST_FIRST(&bar->quirks);
1769 memory_region_del_subregion(&bar->mem, &quirk->mem);
1770 QLIST_REMOVE(quirk, next);
1771 g_free(quirk);
1772 }
1773 }
1774
1775 /*
1776 * PCI config space
1777 */
1778 static uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len)
1779 {
1780 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
1781 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val;
1782
1783 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len);
1784 emu_bits = le32_to_cpu(emu_bits);
1785
1786 if (emu_bits) {
1787 emu_val = pci_default_read_config(pdev, addr, len);
1788 }
1789
1790 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) {
1791 ssize_t ret;
1792
1793 ret = pread(vdev->fd, &phys_val, len, vdev->config_offset + addr);
1794 if (ret != len) {
1795 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x) failed: %m",
1796 __func__, vdev->host.domain, vdev->host.bus,
1797 vdev->host.slot, vdev->host.function, addr, len);
1798 return -errno;
1799 }
1800 phys_val = le32_to_cpu(phys_val);
1801 }
1802
1803 val = (emu_val & emu_bits) | (phys_val & ~emu_bits);
1804
1805 DPRINTF("%s(%04x:%02x:%02x.%x, @0x%x, len=0x%x) %x\n", __func__,
1806 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1807 vdev->host.function, addr, len, val);
1808
1809 return val;
1810 }
1811
1812 static void vfio_pci_write_config(PCIDevice *pdev, uint32_t addr,
1813 uint32_t val, int len)
1814 {
1815 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
1816 uint32_t val_le = cpu_to_le32(val);
1817
1818 DPRINTF("%s(%04x:%02x:%02x.%x, @0x%x, 0x%x, len=0x%x)\n", __func__,
1819 vdev->host.domain, vdev->host.bus, vdev->host.slot,
1820 vdev->host.function, addr, val, len);
1821
1822 /* Write everything to VFIO, let it filter out what we can't write */
1823 if (pwrite(vdev->fd, &val_le, len, vdev->config_offset + addr) != len) {
1824 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x, 0x%x) failed: %m",
1825 __func__, vdev->host.domain, vdev->host.bus,
1826 vdev->host.slot, vdev->host.function, addr, val, len);
1827 }
1828
1829 /* MSI/MSI-X Enabling/Disabling */
1830 if (pdev->cap_present & QEMU_PCI_CAP_MSI &&
1831 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) {
1832 int is_enabled, was_enabled = msi_enabled(pdev);
1833
1834 pci_default_write_config(pdev, addr, val, len);
1835
1836 is_enabled = msi_enabled(pdev);
1837
1838 if (!was_enabled && is_enabled) {
1839 vfio_enable_msi(vdev);
1840 } else if (was_enabled && !is_enabled) {
1841 vfio_disable_msi(vdev);
1842 }
1843 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX &&
1844 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) {
1845 int is_enabled, was_enabled = msix_enabled(pdev);
1846
1847 pci_default_write_config(pdev, addr, val, len);
1848
1849 is_enabled = msix_enabled(pdev);
1850
1851 if (!was_enabled && is_enabled) {
1852 vfio_enable_msix(vdev);
1853 } else if (was_enabled && !is_enabled) {
1854 vfio_disable_msix(vdev);
1855 }
1856 } else {
1857 /* Write everything to QEMU to keep emulated bits correct */
1858 pci_default_write_config(pdev, addr, val, len);
1859 }
1860 }
1861
1862 /*
1863 * DMA - Mapping and unmapping for the "type1" IOMMU interface used on x86
1864 */
1865 static int vfio_dma_unmap(VFIOContainer *container,
1866 hwaddr iova, ram_addr_t size)
1867 {
1868 struct vfio_iommu_type1_dma_unmap unmap = {
1869 .argsz = sizeof(unmap),
1870 .flags = 0,
1871 .iova = iova,
1872 .size = size,
1873 };
1874
1875 if (ioctl(container->fd, VFIO_IOMMU_UNMAP_DMA, &unmap)) {
1876 DPRINTF("VFIO_UNMAP_DMA: %d\n", -errno);
1877 return -errno;
1878 }
1879
1880 return 0;
1881 }
1882
1883 static int vfio_dma_map(VFIOContainer *container, hwaddr iova,
1884 ram_addr_t size, void *vaddr, bool readonly)
1885 {
1886 struct vfio_iommu_type1_dma_map map = {
1887 .argsz = sizeof(map),
1888 .flags = VFIO_DMA_MAP_FLAG_READ,
1889 .vaddr = (__u64)(uintptr_t)vaddr,
1890 .iova = iova,
1891 .size = size,
1892 };
1893
1894 if (!readonly) {
1895 map.flags |= VFIO_DMA_MAP_FLAG_WRITE;
1896 }
1897
1898 /*
1899 * Try the mapping, if it fails with EBUSY, unmap the region and try
1900 * again. This shouldn't be necessary, but we sometimes see it in
1901 * the the VGA ROM space.
1902 */
1903 if (ioctl(container->fd, VFIO_IOMMU_MAP_DMA, &map) == 0 ||
1904 (errno == EBUSY && vfio_dma_unmap(container, iova, size) == 0 &&
1905 ioctl(container->fd, VFIO_IOMMU_MAP_DMA, &map) == 0)) {
1906 return 0;
1907 }
1908
1909 DPRINTF("VFIO_MAP_DMA: %d\n", -errno);
1910 return -errno;
1911 }
1912
1913 static bool vfio_listener_skipped_section(MemoryRegionSection *section)
1914 {
1915 return !memory_region_is_ram(section->mr);
1916 }
1917
1918 static void vfio_listener_region_add(MemoryListener *listener,
1919 MemoryRegionSection *section)
1920 {
1921 VFIOContainer *container = container_of(listener, VFIOContainer,
1922 iommu_data.listener);
1923 hwaddr iova, end;
1924 void *vaddr;
1925 int ret;
1926
1927 assert(!memory_region_is_iommu(section->mr));
1928
1929 if (vfio_listener_skipped_section(section)) {
1930 DPRINTF("SKIPPING region_add %"HWADDR_PRIx" - %"PRIx64"\n",
1931 section->offset_within_address_space,
1932 section->offset_within_address_space + section->size - 1);
1933 return;
1934 }
1935
1936 if (unlikely((section->offset_within_address_space & ~TARGET_PAGE_MASK) !=
1937 (section->offset_within_region & ~TARGET_PAGE_MASK))) {
1938 error_report("%s received unaligned region", __func__);
1939 return;
1940 }
1941
1942 iova = TARGET_PAGE_ALIGN(section->offset_within_address_space);
1943 end = (section->offset_within_address_space + int128_get64(section->size)) &
1944 TARGET_PAGE_MASK;
1945
1946 if (iova >= end) {
1947 return;
1948 }
1949
1950 vaddr = memory_region_get_ram_ptr(section->mr) +
1951 section->offset_within_region +
1952 (iova - section->offset_within_address_space);
1953
1954 DPRINTF("region_add %"HWADDR_PRIx" - %"HWADDR_PRIx" [%p]\n",
1955 iova, end - 1, vaddr);
1956
1957 memory_region_ref(section->mr);
1958 ret = vfio_dma_map(container, iova, end - iova, vaddr, section->readonly);
1959 if (ret) {
1960 error_report("vfio_dma_map(%p, 0x%"HWADDR_PRIx", "
1961 "0x%"HWADDR_PRIx", %p) = %d (%m)",
1962 container, iova, end - iova, vaddr, ret);
1963 }
1964 }
1965
1966 static void vfio_listener_region_del(MemoryListener *listener,
1967 MemoryRegionSection *section)
1968 {
1969 VFIOContainer *container = container_of(listener, VFIOContainer,
1970 iommu_data.listener);
1971 hwaddr iova, end;
1972 int ret;
1973
1974 if (vfio_listener_skipped_section(section)) {
1975 DPRINTF("SKIPPING region_del %"HWADDR_PRIx" - %"PRIx64"\n",
1976 section->offset_within_address_space,
1977 section->offset_within_address_space + section->size - 1);
1978 return;
1979 }
1980
1981 if (unlikely((section->offset_within_address_space & ~TARGET_PAGE_MASK) !=
1982 (section->offset_within_region & ~TARGET_PAGE_MASK))) {
1983 error_report("%s received unaligned region", __func__);
1984 return;
1985 }
1986
1987 iova = TARGET_PAGE_ALIGN(section->offset_within_address_space);
1988 end = (section->offset_within_address_space + int128_get64(section->size)) &
1989 TARGET_PAGE_MASK;
1990
1991 if (iova >= end) {
1992 return;
1993 }
1994
1995 DPRINTF("region_del %"HWADDR_PRIx" - %"HWADDR_PRIx"\n",
1996 iova, end - 1);
1997
1998 ret = vfio_dma_unmap(container, iova, end - iova);
1999 memory_region_unref(section->mr);
2000 if (ret) {
2001 error_report("vfio_dma_unmap(%p, 0x%"HWADDR_PRIx", "
2002 "0x%"HWADDR_PRIx") = %d (%m)",
2003 container, iova, end - iova, ret);
2004 }
2005 }
2006
2007 static MemoryListener vfio_memory_listener = {
2008 .region_add = vfio_listener_region_add,
2009 .region_del = vfio_listener_region_del,
2010 };
2011
2012 static void vfio_listener_release(VFIOContainer *container)
2013 {
2014 memory_listener_unregister(&container->iommu_data.listener);
2015 }
2016
2017 /*
2018 * Interrupt setup
2019 */
2020 static void vfio_disable_interrupts(VFIODevice *vdev)
2021 {
2022 switch (vdev->interrupt) {
2023 case VFIO_INT_INTx:
2024 vfio_disable_intx(vdev);
2025 break;
2026 case VFIO_INT_MSI:
2027 vfio_disable_msi(vdev);
2028 break;
2029 case VFIO_INT_MSIX:
2030 vfio_disable_msix(vdev);
2031 break;
2032 }
2033 }
2034
2035 static int vfio_setup_msi(VFIODevice *vdev, int pos)
2036 {
2037 uint16_t ctrl;
2038 bool msi_64bit, msi_maskbit;
2039 int ret, entries;
2040
2041 if (pread(vdev->fd, &ctrl, sizeof(ctrl),
2042 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) {
2043 return -errno;
2044 }
2045 ctrl = le16_to_cpu(ctrl);
2046
2047 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT);
2048 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT);
2049 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1);
2050
2051 DPRINTF("%04x:%02x:%02x.%x PCI MSI CAP @0x%x\n", vdev->host.domain,
2052 vdev->host.bus, vdev->host.slot, vdev->host.function, pos);
2053
2054 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit);
2055 if (ret < 0) {
2056 if (ret == -ENOTSUP) {
2057 return 0;
2058 }
2059 error_report("vfio: msi_init failed");
2060 return ret;
2061 }
2062 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0);
2063
2064 return 0;
2065 }
2066
2067 /*
2068 * We don't have any control over how pci_add_capability() inserts
2069 * capabilities into the chain. In order to setup MSI-X we need a
2070 * MemoryRegion for the BAR. In order to setup the BAR and not
2071 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
2072 * need to first look for where the MSI-X table lives. So we
2073 * unfortunately split MSI-X setup across two functions.
2074 */
2075 static int vfio_early_setup_msix(VFIODevice *vdev)
2076 {
2077 uint8_t pos;
2078 uint16_t ctrl;
2079 uint32_t table, pba;
2080
2081 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX);
2082 if (!pos) {
2083 return 0;
2084 }
2085
2086 if (pread(vdev->fd, &ctrl, sizeof(ctrl),
2087 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) {
2088 return -errno;
2089 }
2090
2091 if (pread(vdev->fd, &table, sizeof(table),
2092 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) {
2093 return -errno;
2094 }
2095
2096 if (pread(vdev->fd, &pba, sizeof(pba),
2097 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) {
2098 return -errno;
2099 }
2100
2101 ctrl = le16_to_cpu(ctrl);
2102 table = le32_to_cpu(table);
2103 pba = le32_to_cpu(pba);
2104
2105 vdev->msix = g_malloc0(sizeof(*(vdev->msix)));
2106 vdev->msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
2107 vdev->msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
2108 vdev->msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
2109 vdev->msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
2110 vdev->msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
2111
2112 DPRINTF("%04x:%02x:%02x.%x "
2113 "PCI MSI-X CAP @0x%x, BAR %d, offset 0x%x, entries %d\n",
2114 vdev->host.domain, vdev->host.bus, vdev->host.slot,
2115 vdev->host.function, pos, vdev->msix->table_bar,
2116 vdev->msix->table_offset, vdev->msix->entries);
2117
2118 return 0;
2119 }
2120
2121 static int vfio_setup_msix(VFIODevice *vdev, int pos)
2122 {
2123 int ret;
2124
2125 ret = msix_init(&vdev->pdev, vdev->msix->entries,
2126 &vdev->bars[vdev->msix->table_bar].mem,
2127 vdev->msix->table_bar, vdev->msix->table_offset,
2128 &vdev->bars[vdev->msix->pba_bar].mem,
2129 vdev->msix->pba_bar, vdev->msix->pba_offset, pos);
2130 if (ret < 0) {
2131 if (ret == -ENOTSUP) {
2132 return 0;
2133 }
2134 error_report("vfio: msix_init failed");
2135 return ret;
2136 }
2137
2138 return 0;
2139 }
2140
2141 static void vfio_teardown_msi(VFIODevice *vdev)
2142 {
2143 msi_uninit(&vdev->pdev);
2144
2145 if (vdev->msix) {
2146 msix_uninit(&vdev->pdev, &vdev->bars[vdev->msix->table_bar].mem,
2147 &vdev->bars[vdev->msix->pba_bar].mem);
2148 }
2149 }
2150
2151 /*
2152 * Resource setup
2153 */
2154 static void vfio_mmap_set_enabled(VFIODevice *vdev, bool enabled)
2155 {
2156 int i;
2157
2158 for (i = 0; i < PCI_ROM_SLOT; i++) {
2159 VFIOBAR *bar = &vdev->bars[i];
2160
2161 if (!bar->size) {
2162 continue;
2163 }
2164
2165 memory_region_set_enabled(&bar->mmap_mem, enabled);
2166 if (vdev->msix && vdev->msix->table_bar == i) {
2167 memory_region_set_enabled(&vdev->msix->mmap_mem, enabled);
2168 }
2169 }
2170 }
2171
2172 static void vfio_unmap_bar(VFIODevice *vdev, int nr)
2173 {
2174 VFIOBAR *bar = &vdev->bars[nr];
2175
2176 if (!bar->size) {
2177 return;
2178 }
2179
2180 vfio_bar_quirk_teardown(vdev, nr);
2181
2182 memory_region_del_subregion(&bar->mem, &bar->mmap_mem);
2183 munmap(bar->mmap, memory_region_size(&bar->mmap_mem));
2184
2185 if (vdev->msix && vdev->msix->table_bar == nr) {
2186 memory_region_del_subregion(&bar->mem, &vdev->msix->mmap_mem);
2187 munmap(vdev->msix->mmap, memory_region_size(&vdev->msix->mmap_mem));
2188 }
2189
2190 memory_region_destroy(&bar->mem);
2191 }
2192
2193 static int vfio_mmap_bar(VFIODevice *vdev, VFIOBAR *bar,
2194 MemoryRegion *mem, MemoryRegion *submem,
2195 void **map, size_t size, off_t offset,
2196 const char *name)
2197 {
2198 int ret = 0;
2199
2200 if (VFIO_ALLOW_MMAP && size && bar->flags & VFIO_REGION_INFO_FLAG_MMAP) {
2201 int prot = 0;
2202
2203 if (bar->flags & VFIO_REGION_INFO_FLAG_READ) {
2204 prot |= PROT_READ;
2205 }
2206
2207 if (bar->flags & VFIO_REGION_INFO_FLAG_WRITE) {
2208 prot |= PROT_WRITE;
2209 }
2210
2211 *map = mmap(NULL, size, prot, MAP_SHARED,
2212 bar->fd, bar->fd_offset + offset);
2213 if (*map == MAP_FAILED) {
2214 *map = NULL;
2215 ret = -errno;
2216 goto empty_region;
2217 }
2218
2219 memory_region_init_ram_ptr(submem, OBJECT(vdev), name, size, *map);
2220 } else {
2221 empty_region:
2222 /* Create a zero sized sub-region to make cleanup easy. */
2223 memory_region_init(submem, OBJECT(vdev), name, 0);
2224 }
2225
2226 memory_region_add_subregion(mem, offset, submem);
2227
2228 return ret;
2229 }
2230
2231 static void vfio_map_bar(VFIODevice *vdev, int nr)
2232 {
2233 VFIOBAR *bar = &vdev->bars[nr];
2234 unsigned size = bar->size;
2235 char name[64];
2236 uint32_t pci_bar;
2237 uint8_t type;
2238 int ret;
2239
2240 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
2241 if (!size) {
2242 return;
2243 }
2244
2245 snprintf(name, sizeof(name), "VFIO %04x:%02x:%02x.%x BAR %d",
2246 vdev->host.domain, vdev->host.bus, vdev->host.slot,
2247 vdev->host.function, nr);
2248
2249 /* Determine what type of BAR this is for registration */
2250 ret = pread(vdev->fd, &pci_bar, sizeof(pci_bar),
2251 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr));
2252 if (ret != sizeof(pci_bar)) {
2253 error_report("vfio: Failed to read BAR %d (%m)", nr);
2254 return;
2255 }
2256
2257 pci_bar = le32_to_cpu(pci_bar);
2258 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO);
2259 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64);
2260 type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK :
2261 ~PCI_BASE_ADDRESS_MEM_MASK);
2262
2263 /* A "slow" read/write mapping underlies all BARs */
2264 memory_region_init_io(&bar->mem, OBJECT(vdev), &vfio_bar_ops,
2265 bar, name, size);
2266 pci_register_bar(&vdev->pdev, nr, type, &bar->mem);
2267
2268 /*
2269 * We can't mmap areas overlapping the MSIX vector table, so we
2270 * potentially insert a direct-mapped subregion before and after it.
2271 */
2272 if (vdev->msix && vdev->msix->table_bar == nr) {
2273 size = vdev->msix->table_offset & TARGET_PAGE_MASK;
2274 }
2275
2276 strncat(name, " mmap", sizeof(name) - strlen(name) - 1);
2277 if (vfio_mmap_bar(vdev, bar, &bar->mem,
2278 &bar->mmap_mem, &bar->mmap, size, 0, name)) {
2279 error_report("%s unsupported. Performance may be slow", name);
2280 }
2281
2282 if (vdev->msix && vdev->msix->table_bar == nr) {
2283 unsigned start;
2284
2285 start = TARGET_PAGE_ALIGN(vdev->msix->table_offset +
2286 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE));
2287
2288 size = start < bar->size ? bar->size - start : 0;
2289 strncat(name, " msix-hi", sizeof(name) - strlen(name) - 1);
2290 /* VFIOMSIXInfo contains another MemoryRegion for this mapping */
2291 if (vfio_mmap_bar(vdev, bar, &bar->mem, &vdev->msix->mmap_mem,
2292 &vdev->msix->mmap, size, start, name)) {
2293 error_report("%s unsupported. Performance may be slow", name);
2294 }
2295 }
2296
2297 vfio_bar_quirk_setup(vdev, nr);
2298 }
2299
2300 static void vfio_map_bars(VFIODevice *vdev)
2301 {
2302 int i;
2303
2304 for (i = 0; i < PCI_ROM_SLOT; i++) {
2305 vfio_map_bar(vdev, i);
2306 }
2307
2308 if (vdev->has_vga) {
2309 memory_region_init_io(&vdev->vga.region[QEMU_PCI_VGA_MEM].mem,
2310 OBJECT(vdev), &vfio_vga_ops,
2311 &vdev->vga.region[QEMU_PCI_VGA_MEM],
2312 "vfio-vga-mmio@0xa0000",
2313 QEMU_PCI_VGA_MEM_SIZE);
2314 memory_region_init_io(&vdev->vga.region[QEMU_PCI_VGA_IO_LO].mem,
2315 OBJECT(vdev), &vfio_vga_ops,
2316 &vdev->vga.region[QEMU_PCI_VGA_IO_LO],
2317 "vfio-vga-io@0x3b0",
2318 QEMU_PCI_VGA_IO_LO_SIZE);
2319 memory_region_init_io(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
2320 OBJECT(vdev), &vfio_vga_ops,
2321 &vdev->vga.region[QEMU_PCI_VGA_IO_HI],
2322 "vfio-vga-io@0x3c0",
2323 QEMU_PCI_VGA_IO_HI_SIZE);
2324
2325 pci_register_vga(&vdev->pdev, &vdev->vga.region[QEMU_PCI_VGA_MEM].mem,
2326 &vdev->vga.region[QEMU_PCI_VGA_IO_LO].mem,
2327 &vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem);
2328 vfio_vga_quirk_setup(vdev);
2329 }
2330 }
2331
2332 static void vfio_unmap_bars(VFIODevice *vdev)
2333 {
2334 int i;
2335
2336 for (i = 0; i < PCI_ROM_SLOT; i++) {
2337 vfio_unmap_bar(vdev, i);
2338 }
2339
2340 if (vdev->has_vga) {
2341 vfio_vga_quirk_teardown(vdev);
2342 pci_unregister_vga(&vdev->pdev);
2343 memory_region_destroy(&vdev->vga.region[QEMU_PCI_VGA_MEM].mem);
2344 memory_region_destroy(&vdev->vga.region[QEMU_PCI_VGA_IO_LO].mem);
2345 memory_region_destroy(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem);
2346 }
2347 }
2348
2349 /*
2350 * General setup
2351 */
2352 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos)
2353 {
2354 uint8_t tmp, next = 0xff;
2355
2356 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp;
2357 tmp = pdev->config[tmp + 1]) {
2358 if (tmp > pos && tmp < next) {
2359 next = tmp;
2360 }
2361 }
2362
2363 return next - pos;
2364 }
2365
2366 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask)
2367 {
2368 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val);
2369 }
2370
2371 static void vfio_add_emulated_word(VFIODevice *vdev, int pos,
2372 uint16_t val, uint16_t mask)
2373 {
2374 vfio_set_word_bits(vdev->pdev.config + pos, val, mask);
2375 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask);
2376 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask);
2377 }
2378
2379 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask)
2380 {
2381 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val);
2382 }
2383
2384 static void vfio_add_emulated_long(VFIODevice *vdev, int pos,
2385 uint32_t val, uint32_t mask)
2386 {
2387 vfio_set_long_bits(vdev->pdev.config + pos, val, mask);
2388 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask);
2389 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask);
2390 }
2391
2392 static int vfio_setup_pcie_cap(VFIODevice *vdev, int pos, uint8_t size)
2393 {
2394 uint16_t flags;
2395 uint8_t type;
2396
2397 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS);
2398 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4;
2399
2400 if (type != PCI_EXP_TYPE_ENDPOINT &&
2401 type != PCI_EXP_TYPE_LEG_END &&
2402 type != PCI_EXP_TYPE_RC_END) {
2403
2404 error_report("vfio: Assignment of PCIe type 0x%x "
2405 "devices is not currently supported", type);
2406 return -EINVAL;
2407 }
2408
2409 if (!pci_bus_is_express(vdev->pdev.bus)) {
2410 /*
2411 * Use express capability as-is on PCI bus. It doesn't make much
2412 * sense to even expose, but some drivers (ex. tg3) depend on it
2413 * and guests don't seem to be particular about it. We'll need
2414 * to revist this or force express devices to express buses if we
2415 * ever expose an IOMMU to the guest.
2416 */
2417 } else if (pci_bus_is_root(vdev->pdev.bus)) {
2418 /*
2419 * On a Root Complex bus Endpoints become Root Complex Integrated
2420 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
2421 */
2422 if (type == PCI_EXP_TYPE_ENDPOINT) {
2423 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2424 PCI_EXP_TYPE_RC_END << 4,
2425 PCI_EXP_FLAGS_TYPE);
2426
2427 /* Link Capabilities, Status, and Control goes away */
2428 if (size > PCI_EXP_LNKCTL) {
2429 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0);
2430 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
2431 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0);
2432
2433 #ifndef PCI_EXP_LNKCAP2
2434 #define PCI_EXP_LNKCAP2 44
2435 #endif
2436 #ifndef PCI_EXP_LNKSTA2
2437 #define PCI_EXP_LNKSTA2 50
2438 #endif
2439 /* Link 2 Capabilities, Status, and Control goes away */
2440 if (size > PCI_EXP_LNKCAP2) {
2441 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0);
2442 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0);
2443 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0);
2444 }
2445 }
2446
2447 } else if (type == PCI_EXP_TYPE_LEG_END) {
2448 /*
2449 * Legacy endpoints don't belong on the root complex. Windows
2450 * seems to be happier with devices if we skip the capability.
2451 */
2452 return 0;
2453 }
2454
2455 } else {
2456 /*
2457 * Convert Root Complex Integrated Endpoints to regular endpoints.
2458 * These devices don't support LNK/LNK2 capabilities, so make them up.
2459 */
2460 if (type == PCI_EXP_TYPE_RC_END) {
2461 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2462 PCI_EXP_TYPE_ENDPOINT << 4,
2463 PCI_EXP_FLAGS_TYPE);
2464 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP,
2465 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0);
2466 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
2467 }
2468
2469 /* Mark the Link Status bits as emulated to allow virtual negotiation */
2470 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA,
2471 pci_get_word(vdev->pdev.config + pos +
2472 PCI_EXP_LNKSTA),
2473 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
2474 }
2475
2476 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size);
2477 if (pos >= 0) {
2478 vdev->pdev.exp.exp_cap = pos;
2479 }
2480
2481 return pos;
2482 }
2483
2484 static int vfio_add_std_cap(VFIODevice *vdev, uint8_t pos)
2485 {
2486 PCIDevice *pdev = &vdev->pdev;
2487 uint8_t cap_id, next, size;
2488 int ret;
2489
2490 cap_id = pdev->config[pos];
2491 next = pdev->config[pos + 1];
2492
2493 /*
2494 * If it becomes important to configure capabilities to their actual
2495 * size, use this as the default when it's something we don't recognize.
2496 * Since QEMU doesn't actually handle many of the config accesses,
2497 * exact size doesn't seem worthwhile.
2498 */
2499 size = vfio_std_cap_max_size(pdev, pos);
2500
2501 /*
2502 * pci_add_capability always inserts the new capability at the head
2503 * of the chain. Therefore to end up with a chain that matches the
2504 * physical device, we insert from the end by making this recursive.
2505 * This is also why we pre-caclulate size above as cached config space
2506 * will be changed as we unwind the stack.
2507 */
2508 if (next) {
2509 ret = vfio_add_std_cap(vdev, next);
2510 if (ret) {
2511 return ret;
2512 }
2513 } else {
2514 /* Begin the rebuild, use QEMU emulated list bits */
2515 pdev->config[PCI_CAPABILITY_LIST] = 0;
2516 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff;
2517 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2518 }
2519
2520 /* Use emulated next pointer to allow dropping caps */
2521 pci_set_byte(vdev->emulated_config_bits + pos + 1, 0xff);
2522
2523 switch (cap_id) {
2524 case PCI_CAP_ID_MSI:
2525 ret = vfio_setup_msi(vdev, pos);
2526 break;
2527 case PCI_CAP_ID_EXP:
2528 ret = vfio_setup_pcie_cap(vdev, pos, size);
2529 break;
2530 case PCI_CAP_ID_MSIX:
2531 ret = vfio_setup_msix(vdev, pos);
2532 break;
2533 case PCI_CAP_ID_PM:
2534 vdev->pm_cap = pos;
2535 default:
2536 ret = pci_add_capability(pdev, cap_id, pos, size);
2537 break;
2538 }
2539
2540 if (ret < 0) {
2541 error_report("vfio: %04x:%02x:%02x.%x Error adding PCI capability "
2542 "0x%x[0x%x]@0x%x: %d", vdev->host.domain,
2543 vdev->host.bus, vdev->host.slot, vdev->host.function,
2544 cap_id, size, pos, ret);
2545 return ret;
2546 }
2547
2548 return 0;
2549 }
2550
2551 static int vfio_add_capabilities(VFIODevice *vdev)
2552 {
2553 PCIDevice *pdev = &vdev->pdev;
2554
2555 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) ||
2556 !pdev->config[PCI_CAPABILITY_LIST]) {
2557 return 0; /* Nothing to add */
2558 }
2559
2560 return vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST]);
2561 }
2562
2563 static int vfio_load_rom(VFIODevice *vdev)
2564 {
2565 uint64_t size = vdev->rom_size;
2566 char name[32];
2567 off_t off = 0, voff = vdev->rom_offset;
2568 ssize_t bytes;
2569 void *ptr;
2570
2571 /* If loading ROM from file, pci handles it */
2572 if (vdev->pdev.romfile || !vdev->pdev.rom_bar || !size) {
2573 return 0;
2574 }
2575
2576 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
2577 vdev->host.bus, vdev->host.slot, vdev->host.function);
2578
2579 snprintf(name, sizeof(name), "vfio[%04x:%02x:%02x.%x].rom",
2580 vdev->host.domain, vdev->host.bus, vdev->host.slot,
2581 vdev->host.function);
2582 memory_region_init_ram(&vdev->pdev.rom, OBJECT(vdev), name, size);
2583 ptr = memory_region_get_ram_ptr(&vdev->pdev.rom);
2584 memset(ptr, 0xff, size);
2585
2586 while (size) {
2587 bytes = pread(vdev->fd, ptr + off, size, voff + off);
2588 if (bytes == 0) {
2589 break; /* expect that we could get back less than the ROM BAR */
2590 } else if (bytes > 0) {
2591 off += bytes;
2592 size -= bytes;
2593 } else {
2594 if (errno == EINTR || errno == EAGAIN) {
2595 continue;
2596 }
2597 error_report("vfio: Error reading device ROM: %m");
2598 memory_region_destroy(&vdev->pdev.rom);
2599 return -errno;
2600 }
2601 }
2602
2603 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, 0, &vdev->pdev.rom);
2604 vdev->pdev.has_rom = true;
2605 return 0;
2606 }
2607
2608 static int vfio_connect_container(VFIOGroup *group)
2609 {
2610 VFIOContainer *container;
2611 int ret, fd;
2612
2613 if (group->container) {
2614 return 0;
2615 }
2616
2617 QLIST_FOREACH(container, &container_list, next) {
2618 if (!ioctl(group->fd, VFIO_GROUP_SET_CONTAINER, &container->fd)) {
2619 group->container = container;
2620 QLIST_INSERT_HEAD(&container->group_list, group, container_next);
2621 return 0;
2622 }
2623 }
2624
2625 fd = qemu_open("/dev/vfio/vfio", O_RDWR);
2626 if (fd < 0) {
2627 error_report("vfio: failed to open /dev/vfio/vfio: %m");
2628 return -errno;
2629 }
2630
2631 ret = ioctl(fd, VFIO_GET_API_VERSION);
2632 if (ret != VFIO_API_VERSION) {
2633 error_report("vfio: supported vfio version: %d, "
2634 "reported version: %d", VFIO_API_VERSION, ret);
2635 close(fd);
2636 return -EINVAL;
2637 }
2638
2639 container = g_malloc0(sizeof(*container));
2640 container->fd = fd;
2641
2642 if (ioctl(fd, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU)) {
2643 ret = ioctl(group->fd, VFIO_GROUP_SET_CONTAINER, &fd);
2644 if (ret) {
2645 error_report("vfio: failed to set group container: %m");
2646 g_free(container);
2647 close(fd);
2648 return -errno;
2649 }
2650
2651 ret = ioctl(fd, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);
2652 if (ret) {
2653 error_report("vfio: failed to set iommu for container: %m");
2654 g_free(container);
2655 close(fd);
2656 return -errno;
2657 }
2658
2659 container->iommu_data.listener = vfio_memory_listener;
2660 container->iommu_data.release = vfio_listener_release;
2661
2662 memory_listener_register(&container->iommu_data.listener, &address_space_memory);
2663 } else {
2664 error_report("vfio: No available IOMMU models");
2665 g_free(container);
2666 close(fd);
2667 return -EINVAL;
2668 }
2669
2670 QLIST_INIT(&container->group_list);
2671 QLIST_INSERT_HEAD(&container_list, container, next);
2672
2673 group->container = container;
2674 QLIST_INSERT_HEAD(&container->group_list, group, container_next);
2675
2676 return 0;
2677 }
2678
2679 static void vfio_disconnect_container(VFIOGroup *group)
2680 {
2681 VFIOContainer *container = group->container;
2682
2683 if (ioctl(group->fd, VFIO_GROUP_UNSET_CONTAINER, &container->fd)) {
2684 error_report("vfio: error disconnecting group %d from container",
2685 group->groupid);
2686 }
2687
2688 QLIST_REMOVE(group, container_next);
2689 group->container = NULL;
2690
2691 if (QLIST_EMPTY(&container->group_list)) {
2692 if (container->iommu_data.release) {
2693 container->iommu_data.release(container);
2694 }
2695 QLIST_REMOVE(container, next);
2696 DPRINTF("vfio_disconnect_container: close container->fd\n");
2697 close(container->fd);
2698 g_free(container);
2699 }
2700 }
2701
2702 static VFIOGroup *vfio_get_group(int groupid)
2703 {
2704 VFIOGroup *group;
2705 char path[32];
2706 struct vfio_group_status status = { .argsz = sizeof(status) };
2707
2708 QLIST_FOREACH(group, &group_list, next) {
2709 if (group->groupid == groupid) {
2710 return group;
2711 }
2712 }
2713
2714 group = g_malloc0(sizeof(*group));
2715
2716 snprintf(path, sizeof(path), "/dev/vfio/%d", groupid);
2717 group->fd = qemu_open(path, O_RDWR);
2718 if (group->fd < 0) {
2719 error_report("vfio: error opening %s: %m", path);
2720 g_free(group);
2721 return NULL;
2722 }
2723
2724 if (ioctl(group->fd, VFIO_GROUP_GET_STATUS, &status)) {
2725 error_report("vfio: error getting group status: %m");
2726 close(group->fd);
2727 g_free(group);
2728 return NULL;
2729 }
2730
2731 if (!(status.flags & VFIO_GROUP_FLAGS_VIABLE)) {
2732 error_report("vfio: error, group %d is not viable, please ensure "
2733 "all devices within the iommu_group are bound to their "
2734 "vfio bus driver.", groupid);
2735 close(group->fd);
2736 g_free(group);
2737 return NULL;
2738 }
2739
2740 group->groupid = groupid;
2741 QLIST_INIT(&group->device_list);
2742
2743 if (vfio_connect_container(group)) {
2744 error_report("vfio: failed to setup container for group %d", groupid);
2745 close(group->fd);
2746 g_free(group);
2747 return NULL;
2748 }
2749
2750 QLIST_INSERT_HEAD(&group_list, group, next);
2751
2752 return group;
2753 }
2754
2755 static void vfio_put_group(VFIOGroup *group)
2756 {
2757 if (!QLIST_EMPTY(&group->device_list)) {
2758 return;
2759 }
2760
2761 vfio_disconnect_container(group);
2762 QLIST_REMOVE(group, next);
2763 DPRINTF("vfio_put_group: close group->fd\n");
2764 close(group->fd);
2765 g_free(group);
2766 }
2767
2768 static int vfio_get_device(VFIOGroup *group, const char *name, VFIODevice *vdev)
2769 {
2770 struct vfio_device_info dev_info = { .argsz = sizeof(dev_info) };
2771 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info) };
2772 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) };
2773 int ret, i;
2774
2775 ret = ioctl(group->fd, VFIO_GROUP_GET_DEVICE_FD, name);
2776 if (ret < 0) {
2777 error_report("vfio: error getting device %s from group %d: %m",
2778 name, group->groupid);
2779 error_printf("Verify all devices in group %d are bound to vfio-pci "
2780 "or pci-stub and not already in use\n", group->groupid);
2781 return ret;
2782 }
2783
2784 vdev->fd = ret;
2785 vdev->group = group;
2786 QLIST_INSERT_HEAD(&group->device_list, vdev, next);
2787
2788 /* Sanity check device */
2789 ret = ioctl(vdev->fd, VFIO_DEVICE_GET_INFO, &dev_info);
2790 if (ret) {
2791 error_report("vfio: error getting device info: %m");
2792 goto error;
2793 }
2794
2795 DPRINTF("Device %s flags: %u, regions: %u, irgs: %u\n", name,
2796 dev_info.flags, dev_info.num_regions, dev_info.num_irqs);
2797
2798 if (!(dev_info.flags & VFIO_DEVICE_FLAGS_PCI)) {
2799 error_report("vfio: Um, this isn't a PCI device");
2800 goto error;
2801 }
2802
2803 vdev->reset_works = !!(dev_info.flags & VFIO_DEVICE_FLAGS_RESET);
2804 if (!vdev->reset_works) {
2805 error_report("Warning, device %s does not support reset", name);
2806 }
2807
2808 if (dev_info.num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) {
2809 error_report("vfio: unexpected number of io regions %u",
2810 dev_info.num_regions);
2811 goto error;
2812 }
2813
2814 if (dev_info.num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) {
2815 error_report("vfio: unexpected number of irqs %u", dev_info.num_irqs);
2816 goto error;
2817 }
2818
2819 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) {
2820 reg_info.index = i;
2821
2822 ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info);
2823 if (ret) {
2824 error_report("vfio: Error getting region %d info: %m", i);
2825 goto error;
2826 }
2827
2828 DPRINTF("Device %s region %d:\n", name, i);
2829 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
2830 (unsigned long)reg_info.size, (unsigned long)reg_info.offset,
2831 (unsigned long)reg_info.flags);
2832
2833 vdev->bars[i].flags = reg_info.flags;
2834 vdev->bars[i].size = reg_info.size;
2835 vdev->bars[i].fd_offset = reg_info.offset;
2836 vdev->bars[i].fd = vdev->fd;
2837 vdev->bars[i].nr = i;
2838 QLIST_INIT(&vdev->bars[i].quirks);
2839 }
2840
2841 reg_info.index = VFIO_PCI_ROM_REGION_INDEX;
2842
2843 ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info);
2844 if (ret) {
2845 error_report("vfio: Error getting ROM info: %m");
2846 goto error;
2847 }
2848
2849 DPRINTF("Device %s ROM:\n", name);
2850 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
2851 (unsigned long)reg_info.size, (unsigned long)reg_info.offset,
2852 (unsigned long)reg_info.flags);
2853
2854 vdev->rom_size = reg_info.size;
2855 vdev->rom_offset = reg_info.offset;
2856
2857 reg_info.index = VFIO_PCI_CONFIG_REGION_INDEX;
2858
2859 ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info);
2860 if (ret) {
2861 error_report("vfio: Error getting config info: %m");
2862 goto error;
2863 }
2864
2865 DPRINTF("Device %s config:\n", name);
2866 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
2867 (unsigned long)reg_info.size, (unsigned long)reg_info.offset,
2868 (unsigned long)reg_info.flags);
2869
2870 vdev->config_size = reg_info.size;
2871 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) {
2872 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS;
2873 }
2874 vdev->config_offset = reg_info.offset;
2875
2876 if ((vdev->features & VFIO_FEATURE_ENABLE_VGA) &&
2877 dev_info.num_regions > VFIO_PCI_VGA_REGION_INDEX) {
2878 struct vfio_region_info vga_info = {
2879 .argsz = sizeof(vga_info),
2880 .index = VFIO_PCI_VGA_REGION_INDEX,
2881 };
2882
2883 ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, &vga_info);
2884 if (ret) {
2885 error_report(
2886 "vfio: Device does not support requested feature x-vga");
2887 goto error;
2888 }
2889
2890 if (!(vga_info.flags & VFIO_REGION_INFO_FLAG_READ) ||
2891 !(vga_info.flags & VFIO_REGION_INFO_FLAG_WRITE) ||
2892 vga_info.size < 0xbffff + 1) {
2893 error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx",
2894 (unsigned long)vga_info.flags,
2895 (unsigned long)vga_info.size);
2896 goto error;
2897 }
2898
2899 vdev->vga.fd_offset = vga_info.offset;
2900 vdev->vga.fd = vdev->fd;
2901
2902 vdev->vga.region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE;
2903 vdev->vga.region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM;
2904 QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_MEM].quirks);
2905
2906 vdev->vga.region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE;
2907 vdev->vga.region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO;
2908 QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_IO_LO].quirks);
2909
2910 vdev->vga.region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE;
2911 vdev->vga.region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI;
2912 QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks);
2913
2914 vdev->has_vga = true;
2915 }
2916 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX;
2917
2918 ret = ioctl(vdev->fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
2919 if (ret) {
2920 /* This can fail for an old kernel or legacy PCI dev */
2921 DPRINTF("VFIO_DEVICE_GET_IRQ_INFO failure ret=%d\n", ret);
2922 ret = 0;
2923 } else if (irq_info.count == 1) {
2924 vdev->pci_aer = true;
2925 } else {
2926 error_report("vfio: Warning: "
2927 "Could not enable error recovery for the device\n");
2928 }
2929
2930 error:
2931 if (ret) {
2932 QLIST_REMOVE(vdev, next);
2933 vdev->group = NULL;
2934 close(vdev->fd);
2935 }
2936 return ret;
2937 }
2938
2939 static void vfio_put_device(VFIODevice *vdev)
2940 {
2941 QLIST_REMOVE(vdev, next);
2942 vdev->group = NULL;
2943 DPRINTF("vfio_put_device: close vdev->fd\n");
2944 close(vdev->fd);
2945 if (vdev->msix) {
2946 g_free(vdev->msix);
2947 vdev->msix = NULL;
2948 }
2949 }
2950
2951 static void vfio_err_notifier_handler(void *opaque)
2952 {
2953 VFIODevice *vdev = opaque;
2954
2955 if (!event_notifier_test_and_clear(&vdev->err_notifier)) {
2956 return;
2957 }
2958
2959 /*
2960 * TBD. Retrieve the error details and decide what action
2961 * needs to be taken. One of the actions could be to pass
2962 * the error to the guest and have the guest driver recover
2963 * from the error. This requires that PCIe capabilities be
2964 * exposed to the guest. For now, we just terminate the
2965 * guest to contain the error.
2966 */
2967
2968 error_report("%s (%04x:%02x:%02x.%x)"
2969 "Unrecoverable error detected...\n"
2970 "Please collect any data possible and then kill the guest",
2971 __func__, vdev->host.domain, vdev->host.bus,
2972 vdev->host.slot, vdev->host.function);
2973
2974 vm_stop(RUN_STATE_IO_ERROR);
2975 }
2976
2977 /*
2978 * Registers error notifier for devices supporting error recovery.
2979 * If we encounter a failure in this function, we report an error
2980 * and continue after disabling error recovery support for the
2981 * device.
2982 */
2983 static void vfio_register_err_notifier(VFIODevice *vdev)
2984 {
2985 int ret;
2986 int argsz;
2987 struct vfio_irq_set *irq_set;
2988 int32_t *pfd;
2989
2990 if (!vdev->pci_aer) {
2991 return;
2992 }
2993
2994 if (event_notifier_init(&vdev->err_notifier, 0)) {
2995 error_report("vfio: Warning: "
2996 "Unable to init event notifier for error detection\n");
2997 vdev->pci_aer = false;
2998 return;
2999 }
3000
3001 argsz = sizeof(*irq_set) + sizeof(*pfd);
3002
3003 irq_set = g_malloc0(argsz);
3004 irq_set->argsz = argsz;
3005 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
3006 VFIO_IRQ_SET_ACTION_TRIGGER;
3007 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX;
3008 irq_set->start = 0;
3009 irq_set->count = 1;
3010 pfd = (int32_t *)&irq_set->data;
3011
3012 *pfd = event_notifier_get_fd(&vdev->err_notifier);
3013 qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev);
3014
3015 ret = ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
3016 if (ret) {
3017 error_report("vfio: Failed to set up error notification\n");
3018 qemu_set_fd_handler(*pfd, NULL, NULL, vdev);
3019 event_notifier_cleanup(&vdev->err_notifier);
3020 vdev->pci_aer = false;
3021 }
3022 g_free(irq_set);
3023 }
3024
3025 static void vfio_unregister_err_notifier(VFIODevice *vdev)
3026 {
3027 int argsz;
3028 struct vfio_irq_set *irq_set;
3029 int32_t *pfd;
3030 int ret;
3031
3032 if (!vdev->pci_aer) {
3033 return;
3034 }
3035
3036 argsz = sizeof(*irq_set) + sizeof(*pfd);
3037
3038 irq_set = g_malloc0(argsz);
3039 irq_set->argsz = argsz;
3040 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
3041 VFIO_IRQ_SET_ACTION_TRIGGER;
3042 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX;
3043 irq_set->start = 0;
3044 irq_set->count = 1;
3045 pfd = (int32_t *)&irq_set->data;
3046 *pfd = -1;
3047
3048 ret = ioctl(vdev->fd, VFIO_DEVICE_SET_IRQS, irq_set);
3049 if (ret) {
3050 error_report("vfio: Failed to de-assign error fd: %d\n", ret);
3051 }
3052 g_free(irq_set);
3053 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier),
3054 NULL, NULL, vdev);
3055 event_notifier_cleanup(&vdev->err_notifier);
3056 }
3057
3058 static int vfio_initfn(PCIDevice *pdev)
3059 {
3060 VFIODevice *pvdev, *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
3061 VFIOGroup *group;
3062 char path[PATH_MAX], iommu_group_path[PATH_MAX], *group_name;
3063 ssize_t len;
3064 struct stat st;
3065 int groupid;
3066 int ret;
3067
3068 /* Check that the host device exists */
3069 snprintf(path, sizeof(path),
3070 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
3071 vdev->host.domain, vdev->host.bus, vdev->host.slot,
3072 vdev->host.function);
3073 if (stat(path, &st) < 0) {
3074 error_report("vfio: error: no such host device: %s", path);
3075 return -errno;
3076 }
3077
3078 strncat(path, "iommu_group", sizeof(path) - strlen(path) - 1);
3079
3080 len = readlink(path, iommu_group_path, PATH_MAX);
3081 if (len <= 0) {
3082 error_report("vfio: error no iommu_group for device");
3083 return -errno;
3084 }
3085
3086 iommu_group_path[len] = 0;
3087 group_name = basename(iommu_group_path);
3088
3089 if (sscanf(group_name, "%d", &groupid) != 1) {
3090 error_report("vfio: error reading %s: %m", path);
3091 return -errno;
3092 }
3093
3094 DPRINTF("%s(%04x:%02x:%02x.%x) group %d\n", __func__, vdev->host.domain,
3095 vdev->host.bus, vdev->host.slot, vdev->host.function, groupid);
3096
3097 group = vfio_get_group(groupid);
3098 if (!group) {
3099 error_report("vfio: failed to get group %d", groupid);
3100 return -ENOENT;
3101 }
3102
3103 snprintf(path, sizeof(path), "%04x:%02x:%02x.%01x",
3104 vdev->host.domain, vdev->host.bus, vdev->host.slot,
3105 vdev->host.function);
3106
3107 QLIST_FOREACH(pvdev, &group->device_list, next) {
3108 if (pvdev->host.domain == vdev->host.domain &&
3109 pvdev->host.bus == vdev->host.bus &&
3110 pvdev->host.slot == vdev->host.slot &&
3111 pvdev->host.function == vdev->host.function) {
3112
3113 error_report("vfio: error: device %s is already attached", path);
3114 vfio_put_group(group);
3115 return -EBUSY;
3116 }
3117 }
3118
3119 ret = vfio_get_device(group, path, vdev);
3120 if (ret) {
3121 error_report("vfio: failed to get device %s", path);
3122 vfio_put_group(group);
3123 return ret;
3124 }
3125
3126 /* Get a copy of config space */
3127 ret = pread(vdev->fd, vdev->pdev.config,
3128 MIN(pci_config_size(&vdev->pdev), vdev->config_size),
3129 vdev->config_offset);
3130 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) {
3131 ret = ret < 0 ? -errno : -EFAULT;
3132 error_report("vfio: Failed to read device config space");
3133 goto out_put;
3134 }
3135
3136 /* vfio emulates a lot for us, but some bits need extra love */
3137 vdev->emulated_config_bits = g_malloc0(vdev->config_size);
3138
3139 /* QEMU can choose to expose the ROM or not */
3140 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4);
3141
3142 /* QEMU can change multi-function devices to single function, or reverse */
3143 vdev->emulated_config_bits[PCI_HEADER_TYPE] =
3144 PCI_HEADER_TYPE_MULTI_FUNCTION;
3145
3146 /*
3147 * Clear host resource mapping info. If we choose not to register a
3148 * BAR, such as might be the case with the option ROM, we can get
3149 * confusing, unwritable, residual addresses from the host here.
3150 */
3151 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24);
3152 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4);
3153
3154 vfio_load_rom(vdev);
3155
3156 ret = vfio_early_setup_msix(vdev);
3157 if (ret) {
3158 goto out_put;
3159 }
3160
3161 vfio_map_bars(vdev);
3162
3163 ret = vfio_add_capabilities(vdev);
3164 if (ret) {
3165 goto out_teardown;
3166 }
3167
3168 /* QEMU emulates all of MSI & MSIX */
3169 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) {
3170 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff,
3171 MSIX_CAP_LENGTH);
3172 }
3173
3174 if (pdev->cap_present & QEMU_PCI_CAP_MSI) {
3175 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff,
3176 vdev->msi_cap_size);
3177 }
3178
3179 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) {
3180 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3181 vfio_intx_mmap_enable, vdev);
3182 pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_update_irq);
3183 ret = vfio_enable_intx(vdev);
3184 if (ret) {
3185 goto out_teardown;
3186 }
3187 }
3188
3189 add_boot_device_path(vdev->bootindex, &pdev->qdev, NULL);
3190 vfio_register_err_notifier(vdev);
3191
3192 return 0;
3193
3194 out_teardown:
3195 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3196 vfio_teardown_msi(vdev);
3197 vfio_unmap_bars(vdev);
3198 out_put:
3199 g_free(vdev->emulated_config_bits);
3200 vfio_put_device(vdev);
3201 vfio_put_group(group);
3202 return ret;
3203 }
3204
3205 static void vfio_exitfn(PCIDevice *pdev)
3206 {
3207 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
3208 VFIOGroup *group = vdev->group;
3209
3210 vfio_unregister_err_notifier(vdev);
3211 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3212 vfio_disable_interrupts(vdev);
3213 if (vdev->intx.mmap_timer) {
3214 timer_free(vdev->intx.mmap_timer);
3215 }
3216 vfio_teardown_msi(vdev);
3217 vfio_unmap_bars(vdev);
3218 g_free(vdev->emulated_config_bits);
3219 vfio_put_device(vdev);
3220 vfio_put_group(group);
3221 }
3222
3223 static void vfio_pci_reset(DeviceState *dev)
3224 {
3225 PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
3226 VFIODevice *vdev = DO_UPCAST(VFIODevice, pdev, pdev);
3227 uint16_t cmd;
3228
3229 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__, vdev->host.domain,
3230 vdev->host.bus, vdev->host.slot, vdev->host.function);
3231
3232 vfio_disable_interrupts(vdev);
3233
3234 /* Make sure the device is in D0 */
3235 if (vdev->pm_cap) {
3236 uint16_t pmcsr;
3237 uint8_t state;
3238
3239 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2);
3240 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
3241 if (state) {
3242 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3243 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2);
3244 /* vfio handles the necessary delay here */
3245 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2);
3246 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
3247 if (state) {
3248 error_report("vfio: Unable to power on device, stuck in D%d\n",
3249 state);
3250 }
3251 }
3252 }
3253
3254 /*
3255 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master.
3256 * Also put INTx Disable in known state.
3257 */
3258 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2);
3259 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
3260 PCI_COMMAND_INTX_DISABLE);
3261 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2);
3262
3263 if (vdev->reset_works) {
3264 if (ioctl(vdev->fd, VFIO_DEVICE_RESET)) {
3265 error_report("vfio: Error unable to reset physical device "
3266 "(%04x:%02x:%02x.%x): %m", vdev->host.domain,
3267 vdev->host.bus, vdev->host.slot, vdev->host.function);
3268 }
3269 }
3270
3271 vfio_enable_intx(vdev);
3272 }
3273
3274 static Property vfio_pci_dev_properties[] = {
3275 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIODevice, host),
3276 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIODevice,
3277 intx.mmap_timeout, 1100),
3278 DEFINE_PROP_BIT("x-vga", VFIODevice, features,
3279 VFIO_FEATURE_ENABLE_VGA_BIT, false),
3280 DEFINE_PROP_INT32("bootindex", VFIODevice, bootindex, -1),
3281 /*
3282 * TODO - support passed fds... is this necessary?
3283 * DEFINE_PROP_STRING("vfiofd", VFIODevice, vfiofd_name),
3284 * DEFINE_PROP_STRING("vfiogroupfd, VFIODevice, vfiogroupfd_name),
3285 */
3286 DEFINE_PROP_END_OF_LIST(),
3287 };
3288
3289 static const VMStateDescription vfio_pci_vmstate = {
3290 .name = "vfio-pci",
3291 .unmigratable = 1,
3292 };
3293
3294 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data)
3295 {
3296 DeviceClass *dc = DEVICE_CLASS(klass);
3297 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass);
3298
3299 dc->reset = vfio_pci_reset;
3300 dc->props = vfio_pci_dev_properties;
3301 dc->vmsd = &vfio_pci_vmstate;
3302 dc->desc = "VFIO-based PCI device assignment";
3303 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
3304 pdc->init = vfio_initfn;
3305 pdc->exit = vfio_exitfn;
3306 pdc->config_read = vfio_pci_read_config;
3307 pdc->config_write = vfio_pci_write_config;
3308 pdc->is_express = 1; /* We might be */
3309 }
3310
3311 static const TypeInfo vfio_pci_dev_info = {
3312 .name = "vfio-pci",
3313 .parent = TYPE_PCI_DEVICE,
3314 .instance_size = sizeof(VFIODevice),
3315 .class_init = vfio_pci_dev_class_init,
3316 };
3317
3318 static void register_vfio_pci_dev_type(void)
3319 {
3320 type_register_static(&vfio_pci_dev_info);
3321 }
3322
3323 type_init(register_vfio_pci_dev_type)
AR7 emulation for QEMU