hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/isa/isa.h"
  30 #include "sysemu/block-backend.h"
  31 #include "sysemu/dma.h"
  32 #include "qemu/error-report.h"
  33 #include "hw/ide/pci.h"
  34 #include "trace.h"
  35
  36 #define BMDMA_PAGE_SIZE 4096
  37
  38 #define BM_MIGRATION_COMPAT_STATUS_BITS \
  39         (IDE_RETRY_DMA | IDE_RETRY_PIO | \
  40         IDE_RETRY_READ | IDE_RETRY_FLUSH)
  41
  42 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  43                             BlockCompletionFunc *dma_cb)
  44 {
  45     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  46
  47     bm->dma_cb = dma_cb;
  48     bm->cur_prd_last = 0;
  49     bm->cur_prd_addr = 0;
  50     bm->cur_prd_len = 0;
  51
  52     if (bm->status & BM_STATUS_DMAING) {
  53         bm->dma_cb(bmdma_active_if(bm), 0);
  54     }
  55 }
  56
  57 /**
  58  * Prepare an sglist based on available PRDs.
  59  * @limit: How many bytes to prepare total.
  60  *
  61  * Returns the number of bytes prepared, -1 on error.
  62  * IDEState.io_buffer_size will contain the number of bytes described
  63  * by the PRDs, whether or not we added them to the sglist.
  64  */
  65 static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
  66 {
  67     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  68     IDEState *s = bmdma_active_if(bm);
  69     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
  70     struct {
  71         uint32_t addr;
  72         uint32_t size;
  73     } prd;
  74     int l, len;
  75
  76     pci_dma_sglist_init(&s->sg, pci_dev,
  77                         s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  78     s->io_buffer_size = 0;
  79     for(;;) {
  80         if (bm->cur_prd_len == 0) {
  81             /* end of table (with a fail safe of one page) */
  82             if (bm->cur_prd_last ||
  83                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
  84                 return s->sg.size;
  85             }
  86             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
  87             bm->cur_addr += 8;
  88             prd.addr = le32_to_cpu(prd.addr);
  89             prd.size = le32_to_cpu(prd.size);
  90             len = prd.size & 0xfffe;
  91             if (len == 0)
  92                 len = 0x10000;
  93             bm->cur_prd_len = len;
  94             bm->cur_prd_addr = prd.addr;
  95             bm->cur_prd_last = (prd.size & 0x80000000);
  96         }
  97         l = bm->cur_prd_len;
  98         if (l > 0) {
  99             uint64_t sg_len;
 100
 101             /* Don't add extra bytes to the SGList; consume any remaining
 102              * PRDs from the guest, but ignore them. */
 103             sg_len = MIN(limit - s->sg.size, bm->cur_prd_len);
 104             if (sg_len) {
 105                 qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
 106             }
 107
 108             bm->cur_prd_addr += l;
 109             bm->cur_prd_len -= l;
 110             s->io_buffer_size += l;
 111         }
 112     }
 113
 114     qemu_sglist_destroy(&s->sg);
 115     s->io_buffer_size = 0;
 116     return -1;
 117 }
 118
 119 /* return 0 if buffer completed */
 120 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
 121 {
 122     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 123     IDEState *s = bmdma_active_if(bm);
 124     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 125     struct {
 126         uint32_t addr;
 127         uint32_t size;
 128     } prd;
 129     int l, len;
 130
 131     for(;;) {
 132         l = s->io_buffer_size - s->io_buffer_index;
 133         if (l <= 0)
 134             break;
 135         if (bm->cur_prd_len == 0) {
 136             /* end of table (with a fail safe of one page) */
 137             if (bm->cur_prd_last ||
 138                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 139                 return 0;
 140             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 141             bm->cur_addr += 8;
 142             prd.addr = le32_to_cpu(prd.addr);
 143             prd.size = le32_to_cpu(prd.size);
 144             len = prd.size & 0xfffe;
 145             if (len == 0)
 146                 len = 0x10000;
 147             bm->cur_prd_len = len;
 148             bm->cur_prd_addr = prd.addr;
 149             bm->cur_prd_last = (prd.size & 0x80000000);
 150         }
 151         if (l > bm->cur_prd_len)
 152             l = bm->cur_prd_len;
 153         if (l > 0) {
 154             if (is_write) {
 155                 pci_dma_write(pci_dev, bm->cur_prd_addr,
 156                               s->io_buffer + s->io_buffer_index, l);
 157             } else {
 158                 pci_dma_read(pci_dev, bm->cur_prd_addr,
 159                              s->io_buffer + s->io_buffer_index, l);
 160             }
 161             bm->cur_prd_addr += l;
 162             bm->cur_prd_len -= l;
 163             s->io_buffer_index += l;
 164         }
 165     }
 166     return 1;
 167 }
 168
 169 static void bmdma_set_inactive(IDEDMA *dma, bool more)
 170 {
 171     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 172
 173     bm->dma_cb = NULL;
 174     if (more) {
 175         bm->status |= BM_STATUS_DMAING;
 176     } else {
 177         bm->status &= ~BM_STATUS_DMAING;
 178     }
 179 }
 180
 181 static void bmdma_restart_dma(IDEDMA *dma)
 182 {
 183     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 184
 185     bm->cur_addr = bm->addr;
 186 }
 187
 188 static void bmdma_cancel(BMDMAState *bm)
 189 {
 190     if (bm->status & BM_STATUS_DMAING) {
 191         /* cancel DMA request */
 192         bmdma_set_inactive(&bm->dma, false);
 193     }
 194 }
 195
 196 static void bmdma_reset(IDEDMA *dma)
 197 {
 198     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 199
 200     trace_bmdma_reset();
 201     bmdma_cancel(bm);
 202     bm->cmd = 0;
 203     bm->status = 0;
 204     bm->addr = 0;
 205     bm->cur_addr = 0;
 206     bm->cur_prd_last = 0;
 207     bm->cur_prd_addr = 0;
 208     bm->cur_prd_len = 0;
 209 }
 210
 211 static void bmdma_irq(void *opaque, int n, int level)
 212 {
 213     BMDMAState *bm = opaque;
 214
 215     if (!level) {
 216         /* pass through lower */
 217         qemu_set_irq(bm->irq, level);
 218         return;
 219     }
 220
 221     bm->status |= BM_STATUS_INT;
 222
 223     /* trigger the real irq */
 224     qemu_set_irq(bm->irq, level);
 225 }
 226
 227 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 228 {
 229     trace_bmdma_cmd_writeb(val);
 230
 231     /* Ignore writes to SSBM if it keeps the old value */
 232     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 233         if (!(val & BM_CMD_START)) {
 234             ide_cancel_dma_sync(idebus_active_if(bm->bus));
 235             bm->status &= ~BM_STATUS_DMAING;
 236         } else {
 237             bm->cur_addr = bm->addr;
 238             if (!(bm->status & BM_STATUS_DMAING)) {
 239                 bm->status |= BM_STATUS_DMAING;
 240                 /* start dma transfer if possible */
 241                 if (bm->dma_cb)
 242                     bm->dma_cb(bmdma_active_if(bm), 0);
 243             }
 244         }
 245     }
 246
 247     bm->cmd = val & 0x09;
 248 }
 249
 250 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
 251                                 unsigned width)
 252 {
 253     BMDMAState *bm = opaque;
 254     uint32_t mask = (1ULL << (width * 8)) - 1;
 255     uint64_t data;
 256
 257     data = (bm->addr >> (addr * 8)) & mask;
 258     trace_bmdma_addr_read(data);
 259     return data;
 260 }
 261
 262 static void bmdma_addr_write(void *opaque, hwaddr addr,
 263                              uint64_t data, unsigned width)
 264 {
 265     BMDMAState *bm = opaque;
 266     int shift = addr * 8;
 267     uint32_t mask = (1ULL << (width * 8)) - 1;
 268
 269     trace_bmdma_addr_write(data);
 270     bm->addr &= ~(mask << shift);
 271     bm->addr |= ((data & mask) << shift) & ~3;
 272 }
 273
 274 MemoryRegionOps bmdma_addr_ioport_ops = {
 275     .read = bmdma_addr_read,
 276     .write = bmdma_addr_write,
 277     .endianness = DEVICE_LITTLE_ENDIAN,
 278 };
 279
 280 static bool ide_bmdma_current_needed(void *opaque)
 281 {
 282     BMDMAState *bm = opaque;
 283
 284     return (bm->cur_prd_len != 0);
 285 }
 286
 287 static bool ide_bmdma_status_needed(void *opaque)
 288 {
 289     BMDMAState *bm = opaque;
 290
 291     /* Older versions abused some bits in the status register for internal
 292      * error state. If any of these bits are set, we must add a subsection to
 293      * transfer the real status register */
 294     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 295
 296     return ((bm->status & abused_bits) != 0);
 297 }
 298
 299 static int ide_bmdma_pre_save(void *opaque)
 300 {
 301     BMDMAState *bm = opaque;
 302     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 303
 304     if (!(bm->status & BM_STATUS_DMAING) && bm->dma_cb) {
 305         bm->bus->error_status =
 306             ide_dma_cmd_to_retry(bmdma_active_if(bm)->dma_cmd);
 307     }
 308     bm->migration_retry_unit = bm->bus->retry_unit;
 309     bm->migration_retry_sector_num = bm->bus->retry_sector_num;
 310     bm->migration_retry_nsector = bm->bus->retry_nsector;
 311     bm->migration_compat_status =
 312         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 313
 314     return 0;
 315 }
 316
 317 /* This function accesses bm->bus->error_status which is loaded only after
 318  * BMDMA itself. This is why the function is called from ide_pci_post_load
 319  * instead of being registered with VMState where it would run too early. */
 320 static int ide_bmdma_post_load(void *opaque, int version_id)
 321 {
 322     BMDMAState *bm = opaque;
 323     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 324
 325     if (bm->status == 0) {
 326         bm->status = bm->migration_compat_status & ~abused_bits;
 327         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 328     }
 329     if (bm->bus->error_status) {
 330         bm->bus->retry_sector_num = bm->migration_retry_sector_num;
 331         bm->bus->retry_nsector = bm->migration_retry_nsector;
 332         bm->bus->retry_unit = bm->migration_retry_unit;
 333     }
 334
 335     return 0;
 336 }
 337
 338 static const VMStateDescription vmstate_bmdma_current = {
 339     .name = "ide bmdma_current",
 340     .version_id = 1,
 341     .minimum_version_id = 1,
 342     .needed = ide_bmdma_current_needed,
 343     .fields = (VMStateField[]) {
 344         VMSTATE_UINT32(cur_addr, BMDMAState),
 345         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 346         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 347         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 348         VMSTATE_END_OF_LIST()
 349     }
 350 };
 351
 352 static const VMStateDescription vmstate_bmdma_status = {
 353     .name ="ide bmdma/status",
 354     .version_id = 1,
 355     .minimum_version_id = 1,
 356     .needed = ide_bmdma_status_needed,
 357     .fields = (VMStateField[]) {
 358         VMSTATE_UINT8(status, BMDMAState),
 359         VMSTATE_END_OF_LIST()
 360     }
 361 };
 362
 363 static const VMStateDescription vmstate_bmdma = {
 364     .name = "ide bmdma",
 365     .version_id = 3,
 366     .minimum_version_id = 0,
 367     .pre_save  = ide_bmdma_pre_save,
 368     .fields = (VMStateField[]) {
 369         VMSTATE_UINT8(cmd, BMDMAState),
 370         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 371         VMSTATE_UINT32(addr, BMDMAState),
 372         VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
 373         VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
 374         VMSTATE_UINT8(migration_retry_unit, BMDMAState),
 375         VMSTATE_END_OF_LIST()
 376     },
 377     .subsections = (const VMStateDescription*[]) {
 378         &vmstate_bmdma_current,
 379         &vmstate_bmdma_status,
 380         NULL
 381     }
 382 };
 383
 384 static int ide_pci_post_load(void *opaque, int version_id)
 385 {
 386     PCIIDEState *d = opaque;
 387     int i;
 388
 389     for(i = 0; i < 2; i++) {
 390         /* current versions always store 0/1, but older version
 391            stored bigger values. We only need last bit */
 392         d->bmdma[i].migration_retry_unit &= 1;
 393         ide_bmdma_post_load(&d->bmdma[i], -1);
 394     }
 395
 396     return 0;
 397 }
 398
 399 const VMStateDescription vmstate_ide_pci = {
 400     .name = "ide",
 401     .version_id = 3,
 402     .minimum_version_id = 0,
 403     .post_load = ide_pci_post_load,
 404     .fields = (VMStateField[]) {
 405         VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
 406         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 407                              vmstate_bmdma, BMDMAState),
 408         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 409         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 410         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 411         VMSTATE_END_OF_LIST()
 412     }
 413 };
 414
 415 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 416 {
 417     PCIIDEState *d = PCI_IDE(dev);
 418     static const int bus[4]  = { 0, 0, 1, 1 };
 419     static const int unit[4] = { 0, 1, 0, 1 };
 420     int i;
 421
 422     for (i = 0; i < 4; i++) {
 423         if (hd_table[i] == NULL)
 424             continue;
 425         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 426     }
 427 }
 428
 429 static const struct IDEDMAOps bmdma_ops = {
 430     .start_dma = bmdma_start_dma,
 431     .prepare_buf = bmdma_prepare_buf,
 432     .rw_buf = bmdma_rw_buf,
 433     .restart_dma = bmdma_restart_dma,
 434     .set_inactive = bmdma_set_inactive,
 435     .reset = bmdma_reset,
 436 };
 437
 438 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 439 {
 440     if (bus->dma == &bm->dma) {
 441         return;
 442     }
 443
 444     bm->dma.ops = &bmdma_ops;
 445     bus->dma = &bm->dma;
 446     bm->irq = bus->irq;
 447     bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
 448     bm->pci_dev = d;
 449 }
 450
 451 static const TypeInfo pci_ide_type_info = {
 452     .name = TYPE_PCI_IDE,
 453     .parent = TYPE_PCI_DEVICE,
 454     .instance_size = sizeof(PCIIDEState),
 455     .abstract = true,
 456 };
 457
 458 static void pci_ide_register_types(void)
 459 {
 460     type_register_static(&pci_ide_type_info);
 461 }
 462
 463 type_init(pci_ide_register_types)