target/microblaze/cpu.h

   1 /*
   2  *  MicroBlaze virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef MICROBLAZE_CPU_H
  21 #define MICROBLAZE_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "fpu/softfloat-types.h"
  26
  27 typedef struct CPUMBState CPUMBState;
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "mmu.h"
  30 #endif
  31
  32 #define EXCP_MMU        1
  33 #define EXCP_IRQ        2
  34 #define EXCP_BREAK      3
  35 #define EXCP_HW_BREAK   4
  36 #define EXCP_HW_EXCP    5
  37
  38 /* MicroBlaze-specific interrupt pending bits.  */
  39 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  40
  41 /* Meanings of the MBCPU object's two inbound GPIO lines */
  42 #define MB_CPU_IRQ 0
  43 #define MB_CPU_FIR 1
  44
  45 /* Register aliases. R0 - R15 */
  46 #define R_SP     1
  47 #define SR_PC    0
  48 #define SR_MSR   1
  49 #define SR_EAR   3
  50 #define SR_ESR   5
  51 #define SR_FSR   7
  52 #define SR_BTR   0xb
  53 #define SR_EDR   0xd
  54
  55 /* MSR flags.  */
  56 #define MSR_BE  (1<<0) /* 0x001 */
  57 #define MSR_IE  (1<<1) /* 0x002 */
  58 #define MSR_C   (1<<2) /* 0x004 */
  59 #define MSR_BIP (1<<3) /* 0x008 */
  60 #define MSR_FSL (1<<4) /* 0x010 */
  61 #define MSR_ICE (1<<5) /* 0x020 */
  62 #define MSR_DZ  (1<<6) /* 0x040 */
  63 #define MSR_DCE (1<<7) /* 0x080 */
  64 #define MSR_EE  (1<<8) /* 0x100 */
  65 #define MSR_EIP (1<<9) /* 0x200 */
  66 #define MSR_PVR (1<<10) /* 0x400 */
  67 #define MSR_CC  (1<<31)
  68
  69 /* Machine State Register (MSR) Fields */
  70 #define MSR_UM (1<<11) /* User Mode */
  71 #define MSR_UMS        (1<<12) /* User Mode Save */
  72 #define MSR_VM (1<<13) /* Virtual Mode */
  73 #define MSR_VMS        (1<<14) /* Virtual Mode Save */
  74
  75 #define MSR_KERNEL      MSR_EE|MSR_VM
  76 //#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  77 #define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  78 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  79
  80 /* Exception State Register (ESR) Fields */
  81 #define          ESR_DIZ       (1<<11) /* Zone Protection */
  82 #define          ESR_S         (1<<10) /* Store instruction */
  83
  84 #define          ESR_ESS_FSL_OFFSET     5
  85
  86 #define          ESR_EC_FSL             0
  87 #define          ESR_EC_UNALIGNED_DATA  1
  88 #define          ESR_EC_ILLEGAL_OP      2
  89 #define          ESR_EC_INSN_BUS        3
  90 #define          ESR_EC_DATA_BUS        4
  91 #define          ESR_EC_DIVZERO         5
  92 #define          ESR_EC_FPU             6
  93 #define          ESR_EC_PRIVINSN        7
  94 #define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
  95 #define          ESR_EC_DATA_STORAGE    8
  96 #define          ESR_EC_INSN_STORAGE    9
  97 #define          ESR_EC_DATA_TLB        10
  98 #define          ESR_EC_INSN_TLB        11
  99 #define          ESR_EC_MASK            31
 100
 101 /* Floating Point Status Register (FSR) Bits */
 102 #define FSR_IO          (1<<4) /* Invalid operation */
 103 #define FSR_DZ          (1<<3) /* Divide-by-zero */
 104 #define FSR_OF          (1<<2) /* Overflow */
 105 #define FSR_UF          (1<<1) /* Underflow */
 106 #define FSR_DO          (1<<0) /* Denormalized operand error */
 107
 108 /* Version reg.  */
 109 /* Basic PVR mask */
 110 #define PVR0_PVR_FULL_MASK              0x80000000
 111 #define PVR0_USE_BARREL_MASK            0x40000000
 112 #define PVR0_USE_DIV_MASK               0x20000000
 113 #define PVR0_USE_HW_MUL_MASK            0x10000000
 114 #define PVR0_USE_FPU_MASK               0x08000000
 115 #define PVR0_USE_EXC_MASK               0x04000000
 116 #define PVR0_USE_ICACHE_MASK            0x02000000
 117 #define PVR0_USE_DCACHE_MASK            0x01000000
 118 #define PVR0_USE_MMU_MASK               0x00800000
 119 #define PVR0_USE_BTC                    0x00400000
 120 #define PVR0_ENDI_MASK                  0x00200000
 121 #define PVR0_FAULT                      0x00100000
 122 #define PVR0_VERSION_MASK               0x0000FF00
 123 #define PVR0_USER1_MASK                 0x000000FF
 124 #define PVR0_SPROT_MASK                 0x00000001
 125
 126 #define PVR0_VERSION_SHIFT              8
 127
 128 /* User 2 PVR mask */
 129 #define PVR1_USER2_MASK                 0xFFFFFFFF
 130
 131 /* Configuration PVR masks */
 132 #define PVR2_D_OPB_MASK                 0x80000000
 133 #define PVR2_D_LMB_MASK                 0x40000000
 134 #define PVR2_I_OPB_MASK                 0x20000000
 135 #define PVR2_I_LMB_MASK                 0x10000000
 136 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 137 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 138 #define PVR2_D_PLB_MASK                 0x02000000      /* new */
 139 #define PVR2_I_PLB_MASK                 0x01000000      /* new */
 140 #define PVR2_INTERCONNECT               0x00800000      /* new */
 141 #define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 142 #define PVR2_USE_FSL_EXC                0x00040000      /* new */
 143 #define PVR2_USE_MSR_INSTR              0x00020000
 144 #define PVR2_USE_PCMP_INSTR             0x00010000
 145 #define PVR2_AREA_OPTIMISED             0x00008000
 146 #define PVR2_USE_BARREL_MASK            0x00004000
 147 #define PVR2_USE_DIV_MASK               0x00002000
 148 #define PVR2_USE_HW_MUL_MASK            0x00001000
 149 #define PVR2_USE_FPU_MASK               0x00000800
 150 #define PVR2_USE_MUL64_MASK             0x00000400
 151 #define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 152 #define PVR2_USE_IPLBEXC                0x00000100
 153 #define PVR2_USE_DPLBEXC                0x00000080
 154 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 155 #define PVR2_UNALIGNED_EXC_MASK         0x00000020
 156 #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 157 #define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 158 #define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 159 #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 160 #define PVR2_FPU_EXC_MASK               0x00000001
 161
 162 /* Debug and exception PVR masks */
 163 #define PVR3_DEBUG_ENABLED_MASK         0x80000000
 164 #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 165 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 166 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 167 #define PVR3_FSL_LINKS_MASK             0x00000380
 168
 169 /* ICache config PVR masks */
 170 #define PVR4_USE_ICACHE_MASK            0x80000000
 171 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 172 #define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 173 #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 174 #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 175 #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 176
 177 /* DCache config PVR masks */
 178 #define PVR5_USE_DCACHE_MASK            0x80000000
 179 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 180 #define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 181 #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 182 #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 183 #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 184 #define PVR5_DCACHE_WRITEBACK_MASK      0x00004000
 185
 186 /* ICache base address PVR mask */
 187 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 188
 189 /* ICache high address PVR mask */
 190 #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 191
 192 /* DCache base address PVR mask */
 193 #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 194
 195 /* DCache high address PVR mask */
 196 #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 197
 198 /* Target family PVR mask */
 199 #define PVR10_TARGET_FAMILY_MASK        0xFF000000
 200 #define PVR10_ASIZE_SHIFT               18
 201
 202 /* MMU descrtiption */
 203 #define PVR11_USE_MMU                   0xC0000000
 204 #define PVR11_MMU_ITLB_SIZE             0x38000000
 205 #define PVR11_MMU_DTLB_SIZE             0x07000000
 206 #define PVR11_MMU_TLB_ACCESS            0x00C00000
 207 #define PVR11_MMU_ZONES                 0x003E0000
 208 /* MSR Reset value PVR mask */
 209 #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 210
 211 #define C_PVR_NONE                      0
 212 #define C_PVR_BASIC                     1
 213 #define C_PVR_FULL                      2
 214
 215 /* CPU flags.  */
 216
 217 /* Condition codes.  */
 218 #define CC_GE  5
 219 #define CC_GT  4
 220 #define CC_LE  3
 221 #define CC_LT  2
 222 #define CC_NE  1
 223 #define CC_EQ  0
 224
 225 #define STREAM_EXCEPTION (1 << 0)
 226 #define STREAM_ATOMIC    (1 << 1)
 227 #define STREAM_TEST      (1 << 2)
 228 #define STREAM_CONTROL   (1 << 3)
 229 #define STREAM_NONBLOCK  (1 << 4)
 230
 231 #define TARGET_INSN_START_EXTRA_WORDS 1
 232
 233 struct CPUMBState {
 234     uint32_t btaken;
 235     uint32_t btarget;
 236
 237     uint32_t imm;
 238     uint32_t regs[32];
 239     uint32_t pc;
 240     uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
 241     uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
 242     uint64_t ear;
 243     uint32_t esr;
 244     uint32_t fsr;
 245     uint32_t btr;
 246     uint32_t edr;
 247     float_status fp_status;
 248     /* Stack protectors. Yes, it's a hw feature.  */
 249     uint32_t slr, shr;
 250
 251     /* lwx/swx reserved address */
 252 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
 253     target_ulong res_addr;
 254     uint32_t res_val;
 255
 256     /* Internal flags.  */
 257 #define IMM_FLAG        (1 << 0)
 258 #define BIMM_FLAG       (1 << 1)
 259 /* MSR_EE               (1 << 8)  */
 260 /* MSR_UM               (1 << 11) */
 261 /* MSR_VM               (1 << 13) */
 262 #define DRTI_FLAG       (1 << 16)
 263 #define DRTE_FLAG       (1 << 17)
 264 #define DRTB_FLAG       (1 << 18)
 265 #define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 266
 267 /* TB dependent CPUMBState.  */
 268 #define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 269 #define MSR_TB_MASK     (MSR_UM | MSR_VM | MSR_EE)
 270
 271     uint32_t iflags;
 272
 273 #if !defined(CONFIG_USER_ONLY)
 274     /* Unified MMU.  */
 275     struct microblaze_mmu mmu;
 276 #endif
 277
 278     /* Fields up to this point are cleared by a CPU reset */
 279     struct {} end_reset_fields;
 280
 281     /* These fields are preserved on reset.  */
 282
 283     struct {
 284         uint32_t regs[13];
 285     } pvr;
 286 };
 287
 288 /**
 289  * MicroBlazeCPU:
 290  * @env: #CPUMBState
 291  *
 292  * A MicroBlaze CPU.
 293  */
 294 struct MicroBlazeCPU {
 295     /*< private >*/
 296     CPUState parent_obj;
 297
 298     /*< public >*/
 299
 300     CPUNegativeOffsetState neg;
 301     CPUMBState env;
 302
 303     /* Microblaze Configuration Settings */
 304     struct {
 305         bool stackprot;
 306         uint32_t base_vectors;
 307         uint8_t addr_size;
 308         uint8_t use_fpu;
 309         uint8_t use_hw_mul;
 310         bool use_barrel;
 311         bool use_div;
 312         bool use_msr_instr;
 313         bool use_pcmp_instr;
 314         bool use_mmu;
 315         bool dcache_writeback;
 316         bool endi;
 317         bool dopb_bus_exception;
 318         bool iopb_bus_exception;
 319         bool illegal_opcode_exception;
 320         bool opcode_0_illegal;
 321         bool div_zero_exception;
 322         bool unaligned_exceptions;
 323         uint8_t pvr_user1;
 324         uint32_t pvr_user2;
 325         char *version;
 326         uint8_t pvr;
 327     } cfg;
 328 };
 329
 330
 331 void mb_cpu_do_interrupt(CPUState *cs);
 332 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
 333 void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 334 hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 335 int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 336 int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 337
 338 static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
 339 {
 340     /* Replicate MSR[C] to MSR[CC]. */
 341     return env->msr | (env->msr_c * (MSR_C | MSR_CC));
 342 }
 343
 344 static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
 345 {
 346     env->msr_c = (val >> 2) & 1;
 347     /*
 348      * Clear both MSR[C] and MSR[CC] from the saved copy.
 349      * MSR_PVR is not writable and is always clear.
 350      */
 351     env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR);
 352 }
 353
 354 void mb_tcg_init(void);
 355 /* you can call this signal handler from your SIGBUS and SIGSEGV
 356    signal handlers to inform the virtual CPU of exceptions. non zero
 357    is returned if the signal was handled by the virtual CPU.  */
 358 int cpu_mb_signal_handler(int host_signum, void *pinfo,
 359                           void *puc);
 360
 361 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
 362
 363 #define cpu_signal_handler cpu_mb_signal_handler
 364
 365 /* MMU modes definitions */
 366 #define MMU_NOMMU_IDX   0
 367 #define MMU_KERNEL_IDX  1
 368 #define MMU_USER_IDX    2
 369 /* See NB_MMU_MODES further up the file.  */
 370
 371 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 372                      MMUAccessType access_type, int mmu_idx,
 373                      bool probe, uintptr_t retaddr);
 374
 375 typedef CPUMBState CPUArchState;
 376 typedef MicroBlazeCPU ArchCPU;
 377
 378 #include "exec/cpu-all.h"
 379
 380 /* Ensure there is no overlap between the two masks. */
 381 QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
 382
 383 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
 384                                         target_ulong *cs_base, uint32_t *flags)
 385 {
 386     *pc = env->pc;
 387     *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
 388     *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
 389 }
 390
 391 #if !defined(CONFIG_USER_ONLY)
 392 void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 393                                unsigned size, MMUAccessType access_type,
 394                                int mmu_idx, MemTxAttrs attrs,
 395                                MemTxResult response, uintptr_t retaddr);
 396 #endif
 397
 398 static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
 399 {
 400     MicroBlazeCPU *cpu = env_archcpu(env);
 401
 402     /* Are we in nommu mode?.  */
 403     if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
 404         return MMU_NOMMU_IDX;
 405     }
 406
 407     if (env->msr & MSR_UM) {
 408         return MMU_USER_IDX;
 409     }
 410     return MMU_KERNEL_IDX;
 411 }
 412
 413 #endif