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target/arm: Implement MVE WLSTP insn
[qemu/ar7.git] / hw / ppc / spapr_pci.c
blob7a725855f91fa9ce4a9d12fcfc2720f183179219
1 /*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "hw/irq.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/ram_addr.h"
38 #include <libfdt.h>
39 #include "trace.h"
40 #include "qemu/error-report.h"
41 #include "qemu/module.h"
42 #include "qapi/qmp/qerror.h"
43 #include "hw/ppc/fdt.h"
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/pci/pci_ids.h"
47 #include "hw/ppc/spapr_drc.h"
48 #include "hw/qdev-properties.h"
49 #include "sysemu/device_tree.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hostmem.h"
52 #include "sysemu/numa.h"
53 #include "hw/ppc/spapr_numa.h"
54 #include "qemu/log.h"
55
56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
57 #define RTAS_QUERY_FN 0
58 #define RTAS_CHANGE_FN 1
59 #define RTAS_RESET_FN 2
60 #define RTAS_CHANGE_MSI_FN 3
61 #define RTAS_CHANGE_MSIX_FN 4
62
63 /* Interrupt types to return on RTAS_CHANGE_* */
64 #define RTAS_TYPE_MSI 1
65 #define RTAS_TYPE_MSIX 2
66
67 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid)
68 {
69 SpaprPhbState *sphb;
70
71 QLIST_FOREACH(sphb, &spapr->phbs, list) {
72 if (sphb->buid != buid) {
73 continue;
74 }
75 return sphb;
76 }
77
78 return NULL;
79 }
80
81 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
82 uint32_t config_addr)
83 {
84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid);
85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
86 int bus_num = (config_addr >> 16) & 0xFF;
87 int devfn = (config_addr >> 8) & 0xFF;
88
89 if (!phb) {
90 return NULL;
91 }
92
93 return pci_find_device(phb->bus, bus_num, devfn);
94 }
95
96 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
97 {
98 /* This handles the encoding of extended config space addresses */
99 return ((arg >> 20) & 0xf00) | (arg & 0xff);
100 }
101
102 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid,
103 uint32_t addr, uint32_t size,
104 target_ulong rets)
105 {
106 PCIDevice *pci_dev;
107 uint32_t val;
108
109 if ((size != 1) && (size != 2) && (size != 4)) {
110 /* access must be 1, 2 or 4 bytes */
111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
112 return;
113 }
114
115 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
116 addr = rtas_pci_cfgaddr(addr);
117
118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
119 /* Access must be to a valid device, within bounds and
120 * naturally aligned */
121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
122 return;
123 }
124
125 val = pci_host_config_read_common(pci_dev, addr,
126 pci_config_size(pci_dev), size);
127
128 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
129 rtas_st(rets, 1, val);
130 }
131
132 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
133 uint32_t token, uint32_t nargs,
134 target_ulong args,
135 uint32_t nret, target_ulong rets)
136 {
137 uint64_t buid;
138 uint32_t size, addr;
139
140 if ((nargs != 4) || (nret != 2)) {
141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
142 return;
143 }
144
145 buid = rtas_ldq(args, 1);
146 size = rtas_ld(args, 3);
147 addr = rtas_ld(args, 0);
148
149 finish_read_pci_config(spapr, buid, addr, size, rets);
150 }
151
152 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
153 uint32_t token, uint32_t nargs,
154 target_ulong args,
155 uint32_t nret, target_ulong rets)
156 {
157 uint32_t size, addr;
158
159 if ((nargs != 2) || (nret != 2)) {
160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
161 return;
162 }
163
164 size = rtas_ld(args, 1);
165 addr = rtas_ld(args, 0);
166
167 finish_read_pci_config(spapr, 0, addr, size, rets);
168 }
169
170 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid,
171 uint32_t addr, uint32_t size,
172 uint32_t val, target_ulong rets)
173 {
174 PCIDevice *pci_dev;
175
176 if ((size != 1) && (size != 2) && (size != 4)) {
177 /* access must be 1, 2 or 4 bytes */
178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
179 return;
180 }
181
182 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
183 addr = rtas_pci_cfgaddr(addr);
184
185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
186 /* Access must be to a valid device, within bounds and
187 * naturally aligned */
188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
189 return;
190 }
191
192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
193 val, size);
194
195 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
196 }
197
198 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
199 uint32_t token, uint32_t nargs,
200 target_ulong args,
201 uint32_t nret, target_ulong rets)
202 {
203 uint64_t buid;
204 uint32_t val, size, addr;
205
206 if ((nargs != 5) || (nret != 1)) {
207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
208 return;
209 }
210
211 buid = rtas_ldq(args, 1);
212 val = rtas_ld(args, 4);
213 size = rtas_ld(args, 3);
214 addr = rtas_ld(args, 0);
215
216 finish_write_pci_config(spapr, buid, addr, size, val, rets);
217 }
218
219 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
220 uint32_t token, uint32_t nargs,
221 target_ulong args,
222 uint32_t nret, target_ulong rets)
223 {
224 uint32_t val, size, addr;
225
226 if ((nargs != 3) || (nret != 1)) {
227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
228 return;
229 }
230
231
232 val = rtas_ld(args, 2);
233 size = rtas_ld(args, 1);
234 addr = rtas_ld(args, 0);
235
236 finish_write_pci_config(spapr, 0, addr, size, val, rets);
237 }
238
239 /*
240 * Set MSI/MSIX message data.
241 * This is required for msi_notify()/msix_notify() which
242 * will write at the addresses via spapr_msi_write().
243 *
244 * If hwaddr == 0, all entries will have .data == first_irq i.e.
245 * table will be reset.
246 */
247 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
248 unsigned first_irq, unsigned req_num)
249 {
250 unsigned i;
251 MSIMessage msg = { .address = addr, .data = first_irq };
252
253 if (!msix) {
254 msi_set_message(pdev, msg);
255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
256 return;
257 }
258
259 for (i = 0; i < req_num; ++i) {
260 msix_set_message(pdev, i, msg);
261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
262 if (addr) {
263 ++msg.data;
264 }
265 }
266 }
267
268 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
269 uint32_t token, uint32_t nargs,
270 target_ulong args, uint32_t nret,
271 target_ulong rets)
272 {
273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
274 uint32_t config_addr = rtas_ld(args, 0);
275 uint64_t buid = rtas_ldq(args, 1);
276 unsigned int func = rtas_ld(args, 3);
277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
278 unsigned int seq_num = rtas_ld(args, 5);
279 unsigned int ret_intr_type;
280 unsigned int irq, max_irqs = 0;
281 SpaprPhbState *phb = NULL;
282 PCIDevice *pdev = NULL;
283 SpaprPciMsi *msi;
284 int *config_addr_key;
285 Error *err = NULL;
286 int i;
287
288 /* Fins SpaprPhbState */
289 phb = spapr_pci_find_phb(spapr, buid);
290 if (phb) {
291 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
292 }
293 if (!phb || !pdev) {
294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
295 return;
296 }
297
298 switch (func) {
299 case RTAS_CHANGE_FN:
300 if (msi_present(pdev)) {
301 ret_intr_type = RTAS_TYPE_MSI;
302 } else if (msix_present(pdev)) {
303 ret_intr_type = RTAS_TYPE_MSIX;
304 } else {
305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
306 return;
307 }
308 break;
309 case RTAS_CHANGE_MSI_FN:
310 if (msi_present(pdev)) {
311 ret_intr_type = RTAS_TYPE_MSI;
312 } else {
313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
314 return;
315 }
316 break;
317 case RTAS_CHANGE_MSIX_FN:
318 if (msix_present(pdev)) {
319 ret_intr_type = RTAS_TYPE_MSIX;
320 } else {
321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
322 return;
323 }
324 break;
325 default:
326 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
328 return;
329 }
330
331 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
332
333 /* Releasing MSIs */
334 if (!req_num) {
335 if (!msi) {
336 trace_spapr_pci_msi("Releasing wrong config", config_addr);
337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
338 return;
339 }
340
341 if (msi_present(pdev)) {
342 spapr_msi_setmsg(pdev, 0, false, 0, 0);
343 }
344 if (msix_present(pdev)) {
345 spapr_msi_setmsg(pdev, 0, true, 0, 0);
346 }
347 g_hash_table_remove(phb->msi, &config_addr);
348
349 trace_spapr_pci_msi("Released MSIs", config_addr);
350 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
351 rtas_st(rets, 1, 0);
352 return;
353 }
354
355 /* Enabling MSI */
356
357 /* Check if the device supports as many IRQs as requested */
358 if (ret_intr_type == RTAS_TYPE_MSI) {
359 max_irqs = msi_nr_vectors_allocated(pdev);
360 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
361 max_irqs = pdev->msix_entries_nr;
362 }
363 if (!max_irqs) {
364 error_report("Requested interrupt type %d is not enabled for device %x",
365 ret_intr_type, config_addr);
366 rtas_st(rets, 0, -1); /* Hardware error */
367 return;
368 }
369 /* Correct the number if the guest asked for too many */
370 if (req_num > max_irqs) {
371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
372 req_num = max_irqs;
373 irq = 0; /* to avoid misleading trace */
374 goto out;
375 }
376
377 /* Allocate MSIs */
378 if (smc->legacy_irq_allocation) {
379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
380 &err);
381 } else {
382 irq = spapr_irq_msi_alloc(spapr, req_num,
383 ret_intr_type == RTAS_TYPE_MSI, &err);
384 }
385 if (err) {
386 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
387 config_addr);
388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
389 return;
390 }
391
392 for (i = 0; i < req_num; i++) {
393 spapr_irq_claim(spapr, irq + i, false, &err);
394 if (err) {
395 if (i) {
396 spapr_irq_free(spapr, irq, i);
397 }
398 if (!smc->legacy_irq_allocation) {
399 spapr_irq_msi_free(spapr, irq, req_num);
400 }
401 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
402 config_addr);
403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
404 return;
405 }
406 }
407
408 /* Release previous MSIs */
409 if (msi) {
410 g_hash_table_remove(phb->msi, &config_addr);
411 }
412
413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
415 irq, req_num);
416
417 /* Add MSI device to cache */
418 msi = g_new(SpaprPciMsi, 1);
419 msi->first_irq = irq;
420 msi->num = req_num;
421 config_addr_key = g_new(int, 1);
422 *config_addr_key = config_addr;
423 g_hash_table_insert(phb->msi, config_addr_key, msi);
424
425 out:
426 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
427 rtas_st(rets, 1, req_num);
428 rtas_st(rets, 2, ++seq_num);
429 if (nret > 3) {
430 rtas_st(rets, 3, ret_intr_type);
431 }
432
433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
434 }
435
436 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
437 SpaprMachineState *spapr,
438 uint32_t token,
439 uint32_t nargs,
440 target_ulong args,
441 uint32_t nret,
442 target_ulong rets)
443 {
444 uint32_t config_addr = rtas_ld(args, 0);
445 uint64_t buid = rtas_ldq(args, 1);
446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
447 SpaprPhbState *phb = NULL;
448 PCIDevice *pdev = NULL;
449 SpaprPciMsi *msi;
450
451 /* Find SpaprPhbState */
452 phb = spapr_pci_find_phb(spapr, buid);
453 if (phb) {
454 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
455 }
456 if (!phb || !pdev) {
457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
458 return;
459 }
460
461 /* Find device descriptor and start IRQ */
462 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
464 trace_spapr_pci_msi("Failed to return vector", config_addr);
465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
466 return;
467 }
468 intr_src_num = msi->first_irq + ioa_intr_num;
469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
470 intr_src_num);
471
472 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
473 rtas_st(rets, 1, intr_src_num);
474 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
475 }
476
477 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
478 SpaprMachineState *spapr,
479 uint32_t token, uint32_t nargs,
480 target_ulong args, uint32_t nret,
481 target_ulong rets)
482 {
483 SpaprPhbState *sphb;
484 uint32_t addr, option;
485 uint64_t buid;
486 int ret;
487
488 if ((nargs != 4) || (nret != 1)) {
489 goto param_error_exit;
490 }
491
492 buid = rtas_ldq(args, 1);
493 addr = rtas_ld(args, 0);
494 option = rtas_ld(args, 3);
495
496 sphb = spapr_pci_find_phb(spapr, buid);
497 if (!sphb) {
498 goto param_error_exit;
499 }
500
501 if (!spapr_phb_eeh_available(sphb)) {
502 goto param_error_exit;
503 }
504
505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
506 rtas_st(rets, 0, ret);
507 return;
508
509 param_error_exit:
510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
511 }
512
513 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
514 SpaprMachineState *spapr,
515 uint32_t token, uint32_t nargs,
516 target_ulong args, uint32_t nret,
517 target_ulong rets)
518 {
519 SpaprPhbState *sphb;
520 PCIDevice *pdev;
521 uint32_t addr, option;
522 uint64_t buid;
523
524 if ((nargs != 4) || (nret != 2)) {
525 goto param_error_exit;
526 }
527
528 buid = rtas_ldq(args, 1);
529 sphb = spapr_pci_find_phb(spapr, buid);
530 if (!sphb) {
531 goto param_error_exit;
532 }
533
534 if (!spapr_phb_eeh_available(sphb)) {
535 goto param_error_exit;
536 }
537
538 /*
539 * We always have PE address of form "00BB0001". "BB"
540 * represents the bus number of PE's primary bus.
541 */
542 option = rtas_ld(args, 3);
543 switch (option) {
544 case RTAS_GET_PE_ADDR:
545 addr = rtas_ld(args, 0);
546 pdev = spapr_pci_find_dev(spapr, buid, addr);
547 if (!pdev) {
548 goto param_error_exit;
549 }
550
551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
552 break;
553 case RTAS_GET_PE_MODE:
554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
555 break;
556 default:
557 goto param_error_exit;
558 }
559
560 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
561 return;
562
563 param_error_exit:
564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
565 }
566
567 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
568 SpaprMachineState *spapr,
569 uint32_t token, uint32_t nargs,
570 target_ulong args, uint32_t nret,
571 target_ulong rets)
572 {
573 SpaprPhbState *sphb;
574 uint64_t buid;
575 int state, ret;
576
577 if ((nargs != 3) || (nret != 4 && nret != 5)) {
578 goto param_error_exit;
579 }
580
581 buid = rtas_ldq(args, 1);
582 sphb = spapr_pci_find_phb(spapr, buid);
583 if (!sphb) {
584 goto param_error_exit;
585 }
586
587 if (!spapr_phb_eeh_available(sphb)) {
588 goto param_error_exit;
589 }
590
591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
592 rtas_st(rets, 0, ret);
593 if (ret != RTAS_OUT_SUCCESS) {
594 return;
595 }
596
597 rtas_st(rets, 1, state);
598 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
600 if (nret >= 5) {
601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
602 }
603 return;
604
605 param_error_exit:
606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
607 }
608
609 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
610 SpaprMachineState *spapr,
611 uint32_t token, uint32_t nargs,
612 target_ulong args, uint32_t nret,
613 target_ulong rets)
614 {
615 SpaprPhbState *sphb;
616 uint32_t option;
617 uint64_t buid;
618 int ret;
619
620 if ((nargs != 4) || (nret != 1)) {
621 goto param_error_exit;
622 }
623
624 buid = rtas_ldq(args, 1);
625 option = rtas_ld(args, 3);
626 sphb = spapr_pci_find_phb(spapr, buid);
627 if (!sphb) {
628 goto param_error_exit;
629 }
630
631 if (!spapr_phb_eeh_available(sphb)) {
632 goto param_error_exit;
633 }
634
635 ret = spapr_phb_vfio_eeh_reset(sphb, option);
636 rtas_st(rets, 0, ret);
637 return;
638
639 param_error_exit:
640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
641 }
642
643 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
644 SpaprMachineState *spapr,
645 uint32_t token, uint32_t nargs,
646 target_ulong args, uint32_t nret,
647 target_ulong rets)
648 {
649 SpaprPhbState *sphb;
650 uint64_t buid;
651 int ret;
652
653 if ((nargs != 3) || (nret != 1)) {
654 goto param_error_exit;
655 }
656
657 buid = rtas_ldq(args, 1);
658 sphb = spapr_pci_find_phb(spapr, buid);
659 if (!sphb) {
660 goto param_error_exit;
661 }
662
663 if (!spapr_phb_eeh_available(sphb)) {
664 goto param_error_exit;
665 }
666
667 ret = spapr_phb_vfio_eeh_configure(sphb);
668 rtas_st(rets, 0, ret);
669 return;
670
671 param_error_exit:
672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
673 }
674
675 /* To support it later */
676 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
677 SpaprMachineState *spapr,
678 uint32_t token, uint32_t nargs,
679 target_ulong args, uint32_t nret,
680 target_ulong rets)
681 {
682 SpaprPhbState *sphb;
683 int option;
684 uint64_t buid;
685
686 if ((nargs != 8) || (nret != 1)) {
687 goto param_error_exit;
688 }
689
690 buid = rtas_ldq(args, 1);
691 sphb = spapr_pci_find_phb(spapr, buid);
692 if (!sphb) {
693 goto param_error_exit;
694 }
695
696 if (!spapr_phb_eeh_available(sphb)) {
697 goto param_error_exit;
698 }
699
700 option = rtas_ld(args, 7);
701 switch (option) {
702 case RTAS_SLOT_TEMP_ERR_LOG:
703 case RTAS_SLOT_PERM_ERR_LOG:
704 break;
705 default:
706 goto param_error_exit;
707 }
708
709 /* We don't have error log yet */
710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
711 return;
712
713 param_error_exit:
714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
715 }
716
717 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
718 {
719 /*
720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
721 * corresponding qemu_irq.
722 */
723 SpaprPhbState *phb = opaque;
724 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
725
726 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
727 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level);
728 }
729
730 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
731 {
732 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
733 PCIINTxRoute route;
734
735 route.mode = PCI_INTX_ENABLED;
736 route.irq = sphb->lsi_table[pin].irq;
737
738 return route;
739 }
740
741 static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size)
742 {
743 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__);
744 return 0;
745 }
746
747 /*
748 * MSI/MSIX memory region implementation.
749 * The handler handles both MSI and MSIX.
750 * The vector number is encoded in least bits in data.
751 */
752 static void spapr_msi_write(void *opaque, hwaddr addr,
753 uint64_t data, unsigned size)
754 {
755 SpaprMachineState *spapr = opaque;
756 uint32_t irq = data;
757
758 trace_spapr_pci_msi_write(addr, data, irq);
759
760 qemu_irq_pulse(spapr_qirq(spapr, irq));
761 }
762
763 static const MemoryRegionOps spapr_msi_ops = {
764 /*
765 * .read result is undefined by PCI spec.
766 * define .read method to avoid assert failure in memory_region_init_io
767 */
768 .read = spapr_msi_read,
769 .write = spapr_msi_write,
770 .endianness = DEVICE_LITTLE_ENDIAN
771 };
772
773 /*
774 * PHB PCI device
775 */
776 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
777 {
778 SpaprPhbState *phb = opaque;
779
780 return &phb->iommu_as;
781 }
782
783 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
784 {
785 char *path = NULL, *buf = NULL, *host = NULL;
786
787 /* Get the PCI VFIO host id */
788 host = object_property_get_str(OBJECT(pdev), "host", NULL);
789 if (!host) {
790 goto err_out;
791 }
792
793 /* Construct the path of the file that will give us the DT location */
794 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
795 g_free(host);
796 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
797 goto err_out;
798 }
799 g_free(path);
800
801 /* Construct and read from host device tree the loc-code */
802 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
803 g_free(buf);
804 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
805 goto err_out;
806 }
807 return buf;
808
809 err_out:
810 g_free(path);
811 return NULL;
812 }
813
814 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
815 {
816 char *buf;
817 const char *devtype = "qemu";
818 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
819
820 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
821 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
822 if (buf) {
823 return buf;
824 }
825 devtype = "vfio";
826 }
827 /*
828 * For emulated devices and VFIO-failure case, make up
829 * the loc-code.
830 */
831 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
832 devtype, pdev->name, sphb->index, busnr,
833 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
834 return buf;
835 }
836
837 /* Macros to operate with address in OF binding to PCI */
838 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
839 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
840 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
841 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
842 #define b_ss(x) b_x((x), 24, 2) /* the space code */
843 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
844 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
845 #define b_fff(x) b_x((x), 8, 3) /* function number */
846 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
847
848 /* for 'reg' OF properties */
849 #define RESOURCE_CELLS_SIZE 2
850 #define RESOURCE_CELLS_ADDRESS 3
851
852 typedef struct ResourceFields {
853 uint32_t phys_hi;
854 uint32_t phys_mid;
855 uint32_t phys_lo;
856 uint32_t size_hi;
857 uint32_t size_lo;
858 } QEMU_PACKED ResourceFields;
859
860 typedef struct ResourceProps {
861 ResourceFields reg[8];
862 uint32_t reg_len;
863 } ResourceProps;
864
865 /* fill in the 'reg' OF properties for
866 * a PCI device. 'reg' describes resource requirements for a
867 * device's IO/MEM regions.
868 *
869 * the property is an array of ('phys-addr', 'size') pairs describing
870 * the addressable regions of the PCI device, where 'phys-addr' is a
871 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
872 * (phys.hi, phys.mid, phys.lo), and 'size' is a
873 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
874 *
875 * phys.hi = 0xYYXXXXZZ, where:
876 * 0xYY = npt000ss
877 * ||| |
878 * ||| +-- space code
879 * ||| |
880 * ||| + 00 if configuration space
881 * ||| + 01 if IO region,
882 * ||| + 10 if 32-bit MEM region
883 * ||| + 11 if 64-bit MEM region
884 * |||
885 * ||+------ for non-relocatable IO: 1 if aliased
886 * || for relocatable IO: 1 if below 64KB
887 * || for MEM: 1 if below 1MB
888 * |+------- 1 if region is prefetchable
889 * +-------- 1 if region is non-relocatable
890 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
891 * bits respectively
892 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
893 * to the region
894 *
895 * phys.mid and phys.lo correspond respectively to the hi/lo portions
896 * of the actual address of the region.
897 *
898 * note also that addresses defined in this property are, at least
899 * for PAPR guests, relative to the PHBs IO/MEM windows, and
900 * correspond directly to the addresses in the BARs.
901 *
902 * in accordance with PCI Bus Binding to Open Firmware,
903 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
904 * Appendix C.
905 */
906 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
907 {
908 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
909 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
910 b_ddddd(PCI_SLOT(d->devfn)) |
911 b_fff(PCI_FUNC(d->devfn)));
912 ResourceFields *reg;
913 int i, reg_idx = 0;
914
915 /* config space region */
916 reg = &rp->reg[reg_idx++];
917 reg->phys_hi = cpu_to_be32(dev_id);
918 reg->phys_mid = 0;
919 reg->phys_lo = 0;
920 reg->size_hi = 0;
921 reg->size_lo = 0;
922
923 for (i = 0; i < PCI_NUM_REGIONS; i++) {
924 if (!d->io_regions[i].size) {
925 continue;
926 }
927
928 reg = &rp->reg[reg_idx++];
929
930 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
931 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
932 reg->phys_hi |= cpu_to_be32(b_ss(1));
933 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
934 reg->phys_hi |= cpu_to_be32(b_ss(3));
935 } else {
936 reg->phys_hi |= cpu_to_be32(b_ss(2));
937 }
938 reg->phys_mid = 0;
939 reg->phys_lo = 0;
940 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
941 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
942 }
943
944 rp->reg_len = reg_idx * sizeof(ResourceFields);
945 }
946
947 typedef struct PCIClass PCIClass;
948 typedef struct PCISubClass PCISubClass;
949 typedef struct PCIIFace PCIIFace;
950
951 struct PCIIFace {
952 int iface;
953 const char *name;
954 };
955
956 struct PCISubClass {
957 int subclass;
958 const char *name;
959 const PCIIFace *iface;
960 };
961
962 struct PCIClass {
963 const char *name;
964 const PCISubClass *subc;
965 };
966
967 static const PCISubClass undef_subclass[] = {
968 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
969 { 0xFF, NULL, NULL },
970 };
971
972 static const PCISubClass mass_subclass[] = {
973 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
974 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
975 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
976 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
977 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
978 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
979 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
980 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
981 { 0xFF, NULL, NULL },
982 };
983
984 static const PCISubClass net_subclass[] = {
985 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
986 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
987 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
988 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
989 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
990 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
991 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
992 { 0xFF, NULL, NULL },
993 };
994
995 static const PCISubClass displ_subclass[] = {
996 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
997 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
998 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
999 { 0xFF, NULL, NULL },
1000 };
1001
1002 static const PCISubClass media_subclass[] = {
1003 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1004 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1005 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1006 { 0xFF, NULL, NULL },
1007 };
1008
1009 static const PCISubClass mem_subclass[] = {
1010 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1011 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1012 { 0xFF, NULL, NULL },
1013 };
1014
1015 static const PCISubClass bridg_subclass[] = {
1016 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1017 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1018 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1019 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1020 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1021 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1022 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1023 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1024 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1025 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1026 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1027 { 0xFF, NULL, NULL },
1028 };
1029
1030 static const PCISubClass comm_subclass[] = {
1031 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1032 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1033 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1034 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1035 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1036 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1037 { 0xFF, NULL, NULL, },
1038 };
1039
1040 static const PCIIFace pic_iface[] = {
1041 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1042 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1043 { 0xFF, NULL },
1044 };
1045
1046 static const PCISubClass sys_subclass[] = {
1047 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1048 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1049 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1050 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1051 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1052 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1053 { 0xFF, NULL, NULL },
1054 };
1055
1056 static const PCISubClass inp_subclass[] = {
1057 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1058 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1059 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1060 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1061 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1062 { 0xFF, NULL, NULL },
1063 };
1064
1065 static const PCISubClass dock_subclass[] = {
1066 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1067 { 0xFF, NULL, NULL },
1068 };
1069
1070 static const PCISubClass cpu_subclass[] = {
1071 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1072 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1073 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1074 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1075 { 0xFF, NULL, NULL },
1076 };
1077
1078 static const PCIIFace usb_iface[] = {
1079 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1080 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1081 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1082 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1083 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1084 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1085 { 0xFF, NULL },
1086 };
1087
1088 static const PCISubClass ser_subclass[] = {
1089 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1090 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1091 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1092 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1093 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1094 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1095 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1096 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1097 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1098 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1099 { 0xFF, NULL, NULL },
1100 };
1101
1102 static const PCISubClass wrl_subclass[] = {
1103 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1104 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1105 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1106 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1107 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1108 { 0xFF, NULL, NULL },
1109 };
1110
1111 static const PCISubClass sat_subclass[] = {
1112 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1113 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1114 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1115 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1116 { 0xFF, NULL, NULL },
1117 };
1118
1119 static const PCISubClass crypt_subclass[] = {
1120 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1121 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1122 "entertainment-encryption", NULL },
1123 { 0xFF, NULL, NULL },
1124 };
1125
1126 static const PCISubClass spc_subclass[] = {
1127 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1128 { PCI_CLASS_SP_PERF, "counter", NULL },
1129 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1130 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1131 { 0xFF, NULL, NULL },
1132 };
1133
1134 static const PCIClass pci_classes[] = {
1135 { "legacy-device", undef_subclass },
1136 { "mass-storage", mass_subclass },
1137 { "network", net_subclass },
1138 { "display", displ_subclass, },
1139 { "multimedia-device", media_subclass },
1140 { "memory-controller", mem_subclass },
1141 { "unknown-bridge", bridg_subclass },
1142 { "communication-controller", comm_subclass},
1143 { "system-peripheral", sys_subclass },
1144 { "input-controller", inp_subclass },
1145 { "docking-station", dock_subclass },
1146 { "cpu", cpu_subclass },
1147 { "serial-bus", ser_subclass },
1148 { "wireless-controller", wrl_subclass },
1149 { "intelligent-io", NULL },
1150 { "satellite-device", sat_subclass },
1151 { "encryption", crypt_subclass },
1152 { "data-processing-controller", spc_subclass },
1153 };
1154
1155 static const char *dt_name_from_class(uint8_t class, uint8_t subclass,
1156 uint8_t iface)
1157 {
1158 const PCIClass *pclass;
1159 const PCISubClass *psubclass;
1160 const PCIIFace *piface;
1161 const char *name;
1162
1163 if (class >= ARRAY_SIZE(pci_classes)) {
1164 return "pci";
1165 }
1166
1167 pclass = pci_classes + class;
1168 name = pclass->name;
1169
1170 if (pclass->subc == NULL) {
1171 return name;
1172 }
1173
1174 psubclass = pclass->subc;
1175 while ((psubclass->subclass & 0xff) != 0xff) {
1176 if ((psubclass->subclass & 0xff) == subclass) {
1177 name = psubclass->name;
1178 break;
1179 }
1180 psubclass++;
1181 }
1182
1183 piface = psubclass->iface;
1184 if (piface == NULL) {
1185 return name;
1186 }
1187 while ((piface->iface & 0xff) != 0xff) {
1188 if ((piface->iface & 0xff) == iface) {
1189 name = piface->name;
1190 break;
1191 }
1192 piface++;
1193 }
1194
1195 return name;
1196 }
1197
1198 /*
1199 * DRC helper functions
1200 */
1201
1202 static uint32_t drc_id_from_devfn(SpaprPhbState *phb,
1203 uint8_t chassis, int32_t devfn)
1204 {
1205 return (phb->index << 16) | (chassis << 8) | devfn;
1206 }
1207
1208 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb,
1209 uint8_t chassis, int32_t devfn)
1210 {
1211 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1212 drc_id_from_devfn(phb, chassis, devfn));
1213 }
1214
1215 static uint8_t chassis_from_bus(PCIBus *bus)
1216 {
1217 if (pci_bus_is_root(bus)) {
1218 return 0;
1219 } else {
1220 PCIDevice *bridge = pci_bridge_get_device(bus);
1221
1222 return object_property_get_uint(OBJECT(bridge), "chassis_nr",
1223 &error_abort);
1224 }
1225 }
1226
1227 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev)
1228 {
1229 uint8_t chassis = chassis_from_bus(pci_get_bus(dev));
1230
1231 return drc_from_devfn(phb, chassis, dev->devfn);
1232 }
1233
1234 static void add_drcs(SpaprPhbState *phb, PCIBus *bus)
1235 {
1236 Object *owner;
1237 int i;
1238 uint8_t chassis;
1239
1240 if (!phb->dr_enabled) {
1241 return;
1242 }
1243
1244 chassis = chassis_from_bus(bus);
1245
1246 if (pci_bus_is_root(bus)) {
1247 owner = OBJECT(phb);
1248 } else {
1249 owner = OBJECT(pci_bridge_get_device(bus));
1250 }
1251
1252 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) {
1253 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI,
1254 drc_id_from_devfn(phb, chassis, i));
1255 }
1256 }
1257
1258 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus)
1259 {
1260 int i;
1261 uint8_t chassis;
1262
1263 if (!phb->dr_enabled) {
1264 return;
1265 }
1266
1267 chassis = chassis_from_bus(bus);
1268
1269 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) {
1270 SpaprDrc *drc = drc_from_devfn(phb, chassis, i);
1271
1272 if (drc) {
1273 object_unparent(OBJECT(drc));
1274 }
1275 }
1276 }
1277
1278 typedef struct PciWalkFdt {
1279 void *fdt;
1280 int offset;
1281 SpaprPhbState *sphb;
1282 int err;
1283 } PciWalkFdt;
1284
1285 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1286 void *fdt, int parent_offset);
1287
1288 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev,
1289 void *opaque)
1290 {
1291 PciWalkFdt *p = opaque;
1292 int err;
1293
1294 if (p->err) {
1295 /* Something's already broken, don't keep going */
1296 return;
1297 }
1298
1299 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset);
1300 if (err < 0) {
1301 p->err = err;
1302 }
1303 }
1304
1305 /* Augment PCI device node with bridge specific information */
1306 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus,
1307 void *fdt, int offset)
1308 {
1309 Object *owner;
1310 PciWalkFdt cbinfo = {
1311 .fdt = fdt,
1312 .offset = offset,
1313 .sphb = sphb,
1314 .err = 0,
1315 };
1316 int ret;
1317
1318 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1319 RESOURCE_CELLS_ADDRESS));
1320 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1321 RESOURCE_CELLS_SIZE));
1322
1323 assert(bus);
1324 pci_for_each_device_reverse(bus, pci_bus_num(bus),
1325 spapr_dt_pci_device_cb, &cbinfo);
1326 if (cbinfo.err) {
1327 return cbinfo.err;
1328 }
1329
1330 if (pci_bus_is_root(bus)) {
1331 owner = OBJECT(sphb);
1332 } else {
1333 owner = OBJECT(pci_bridge_get_device(bus));
1334 }
1335
1336 ret = spapr_dt_drc(fdt, offset, owner,
1337 SPAPR_DR_CONNECTOR_TYPE_PCI);
1338 if (ret) {
1339 return ret;
1340 }
1341
1342 return offset;
1343 }
1344
1345 char *spapr_pci_fw_dev_name(PCIDevice *dev)
1346 {
1347 const gchar *basename;
1348 int slot = PCI_SLOT(dev->devfn);
1349 int func = PCI_FUNC(dev->devfn);
1350 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1351
1352 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1353 ccode & 0xff);
1354
1355 if (func != 0) {
1356 return g_strdup_printf("%s@%x,%x", basename, slot, func);
1357 } else {
1358 return g_strdup_printf("%s@%x", basename, slot);
1359 }
1360 }
1361
1362 /* create OF node for pci device and required OF DT properties */
1363 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1364 void *fdt, int parent_offset)
1365 {
1366 int offset;
1367 g_autofree gchar *nodename = spapr_pci_fw_dev_name(dev);
1368 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1369 ResourceProps rp;
1370 SpaprDrc *drc = drc_from_dev(sphb, dev);
1371 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2);
1372 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2);
1373 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1);
1374 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1375 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1);
1376 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2);
1377 uint32_t subsystem_vendor_id =
1378 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1379 uint32_t cache_line_size =
1380 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1);
1381 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1382 gchar *loc_code;
1383
1384 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename));
1385
1386 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1387 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id));
1388 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id));
1389 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id));
1390
1391 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1392 if (irq_pin) {
1393 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin));
1394 }
1395
1396 if (subsystem_id) {
1397 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id));
1398 }
1399
1400 if (subsystem_vendor_id) {
1401 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1402 subsystem_vendor_id));
1403 }
1404
1405 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size));
1406
1407
1408 /* the following fdt cells are masked off the pci status register */
1409 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1410 PCI_STATUS_DEVSEL_MASK & pci_status));
1411
1412 if (pci_status & PCI_STATUS_FAST_BACK) {
1413 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1414 }
1415 if (pci_status & PCI_STATUS_66MHZ) {
1416 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1417 }
1418 if (pci_status & PCI_STATUS_UDF) {
1419 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1420 }
1421
1422 loc_code = spapr_phb_get_loc_code(sphb, dev);
1423 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code));
1424 g_free(loc_code);
1425
1426 if (drc) {
1427 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index",
1428 spapr_drc_index(drc)));
1429 }
1430
1431 if (msi_present(dev)) {
1432 uint32_t max_msi = msi_nr_vectors_allocated(dev);
1433 if (max_msi) {
1434 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1435 }
1436 }
1437 if (msix_present(dev)) {
1438 uint32_t max_msix = dev->msix_entries_nr;
1439 if (max_msix) {
1440 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1441 }
1442 }
1443
1444 populate_resource_props(dev, &rp);
1445 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1446
1447 if (sphb->pcie_ecs && pci_is_express(dev)) {
1448 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1449 }
1450
1451 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb);
1452
1453 if (!pc->is_bridge) {
1454 /* Properties only for non-bridges */
1455 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1);
1456 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1);
1457 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant));
1458 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency));
1459 return offset;
1460 } else {
1461 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1462
1463 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset);
1464 }
1465 }
1466
1467 /* Callback to be called during DRC release. */
1468 void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1469 {
1470 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
1471
1472 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
1473 object_unparent(OBJECT(dev));
1474 }
1475
1476 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
1477 void *fdt, int *fdt_start_offset, Error **errp)
1478 {
1479 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev);
1480 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler);
1481 PCIDevice *pdev = PCI_DEVICE(drc->dev);
1482
1483 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0);
1484 return 0;
1485 }
1486
1487 static void spapr_pci_bridge_plug(SpaprPhbState *phb,
1488 PCIBridge *bridge)
1489 {
1490 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1491
1492 add_drcs(phb, bus);
1493 }
1494
1495 /* Returns non-zero if the value of "chassis_nr" is already in use */
1496 static int check_chassis_nr(Object *obj, void *opaque)
1497 {
1498 int new_chassis_nr =
1499 object_property_get_uint(opaque, "chassis_nr", &error_abort);
1500 int chassis_nr =
1501 object_property_get_uint(obj, "chassis_nr", NULL);
1502
1503 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) {
1504 return 0;
1505 }
1506
1507 /* Skip unsupported bridge types */
1508 if (!chassis_nr) {
1509 return 0;
1510 }
1511
1512 /* Skip self */
1513 if (obj == opaque) {
1514 return 0;
1515 }
1516
1517 return chassis_nr == new_chassis_nr;
1518 }
1519
1520 static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp)
1521 {
1522 int chassis_nr =
1523 object_property_get_uint(bridge, "chassis_nr", NULL);
1524
1525 /*
1526 * slotid_cap_init() already ensures that "chassis_nr" isn't null for
1527 * standard PCI bridges, so this really tells if "chassis_nr" is present
1528 * or not.
1529 */
1530 if (!chassis_nr) {
1531 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property");
1532 error_append_hint(errp, "Try -device pci-bridge instead.\n");
1533 return false;
1534 }
1535
1536 /* We want unique values for "chassis_nr" */
1537 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr,
1538 bridge)) {
1539 error_setg(errp, "Bridge chassis %d already in use", chassis_nr);
1540 return false;
1541 }
1542
1543 return true;
1544 }
1545
1546 static void spapr_pci_pre_plug(HotplugHandler *plug_handler,
1547 DeviceState *plugged_dev, Error **errp)
1548 {
1549 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1550 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1551 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1552 SpaprDrc *drc = drc_from_dev(phb, pdev);
1553 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1554 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1555
1556 if (!phb->dr_enabled) {
1557 /* if this is a hotplug operation initiated by the user
1558 * we need to let them know it's not enabled
1559 */
1560 if (plugged_dev->hotplugged) {
1561 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1562 object_get_typename(OBJECT(phb)));
1563 return;
1564 }
1565 }
1566
1567 if (pc->is_bridge) {
1568 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) {
1569 return;
1570 }
1571 }
1572
1573 /* Following the QEMU convention used for PCIe multifunction
1574 * hotplug, we do not allow functions to be hotplugged to a
1575 * slot that already has function 0 present
1576 */
1577 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1578 PCI_FUNC(pdev->devfn) != 0) {
1579 error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
1580 " additional functions can no longer be exposed to guest.",
1581 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1582 }
1583
1584 if (drc && drc->dev) {
1585 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr,
1586 pci_get_function_0(PCI_DEVICE(drc->dev))->name);
1587 return;
1588 }
1589 }
1590
1591 static void spapr_pci_plug(HotplugHandler *plug_handler,
1592 DeviceState *plugged_dev, Error **errp)
1593 {
1594 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1595 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1596 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1597 SpaprDrc *drc = drc_from_dev(phb, pdev);
1598 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1599
1600 /*
1601 * If DR is disabled we don't need to do anything in the case of
1602 * hotplug or coldplug callbacks.
1603 */
1604 if (!phb->dr_enabled) {
1605 return;
1606 }
1607
1608 g_assert(drc);
1609
1610 if (pc->is_bridge) {
1611 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev));
1612 }
1613
1614 /* spapr_pci_pre_plug() already checked the DRC is attachable */
1615 spapr_drc_attach(drc, DEVICE(pdev));
1616
1617 /* If this is function 0, signal hotplug for all the device functions.
1618 * Otherwise defer sending the hotplug event.
1619 */
1620 if (!spapr_drc_hotplugged(plugged_dev)) {
1621 spapr_drc_reset(drc);
1622 } else if (PCI_FUNC(pdev->devfn) == 0) {
1623 int i;
1624 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1625
1626 for (i = 0; i < 8; i++) {
1627 SpaprDrc *func_drc;
1628 SpaprDrcClass *func_drck;
1629 SpaprDREntitySense state;
1630
1631 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1632 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1633 state = func_drck->dr_entity_sense(func_drc);
1634
1635 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1636 spapr_hotplug_req_add_by_index(func_drc);
1637 }
1638 }
1639 }
1640 }
1641
1642 static void spapr_pci_bridge_unplug(SpaprPhbState *phb,
1643 PCIBridge *bridge)
1644 {
1645 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1646
1647 remove_drcs(phb, bus);
1648 }
1649
1650 static void spapr_pci_unplug(HotplugHandler *plug_handler,
1651 DeviceState *plugged_dev, Error **errp)
1652 {
1653 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1654 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1655
1656 /* some version guests do not wait for completion of a device
1657 * cleanup (generally done asynchronously by the kernel) before
1658 * signaling to QEMU that the device is safe, but instead sleep
1659 * for some 'safe' period of time. unfortunately on a busy host
1660 * this sleep isn't guaranteed to be long enough, resulting in
1661 * bad things like IRQ lines being left asserted during final
1662 * device removal. to deal with this we call reset just prior
1663 * to finalizing the device, which will put the device back into
1664 * an 'idle' state, as the device cleanup code expects.
1665 */
1666 pci_device_reset(PCI_DEVICE(plugged_dev));
1667
1668 if (pc->is_bridge) {
1669 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev));
1670 return;
1671 }
1672
1673 qdev_unrealize(plugged_dev);
1674 }
1675
1676 static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1677 DeviceState *plugged_dev, Error **errp)
1678 {
1679 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1680 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1681 SpaprDrc *drc = drc_from_dev(phb, pdev);
1682
1683 if (!phb->dr_enabled) {
1684 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1685 object_get_typename(OBJECT(phb)));
1686 return;
1687 }
1688
1689 g_assert(drc);
1690 g_assert(drc->dev == plugged_dev);
1691
1692 if (!spapr_drc_unplug_requested(drc)) {
1693 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1694 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1695 SpaprDrc *func_drc;
1696 SpaprDrcClass *func_drck;
1697 SpaprDREntitySense state;
1698 int i;
1699 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1700
1701 if (pc->is_bridge) {
1702 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");
1703 return;
1704 }
1705 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) {
1706 error_setg(errp, "PCI: Cannot unplug NVLink2 devices");
1707 return;
1708 }
1709
1710 /* ensure any other present functions are pending unplug */
1711 if (PCI_FUNC(pdev->devfn) == 0) {
1712 for (i = 1; i < 8; i++) {
1713 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1714 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1715 state = func_drck->dr_entity_sense(func_drc);
1716 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1717 && !spapr_drc_unplug_requested(func_drc)) {
1718 /*
1719 * Attempting to remove function 0 of a multifunction
1720 * device will will cascade into removing all child
1721 * functions, even if their unplug weren't requested
1722 * beforehand.
1723 */
1724 spapr_drc_unplug_request(func_drc);
1725 }
1726 }
1727 }
1728
1729 spapr_drc_unplug_request(drc);
1730
1731 /* if this isn't func 0, defer unplug event. otherwise signal removal
1732 * for all present functions
1733 */
1734 if (PCI_FUNC(pdev->devfn) == 0) {
1735 for (i = 7; i >= 0; i--) {
1736 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1737 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1738 state = func_drck->dr_entity_sense(func_drc);
1739 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1740 spapr_hotplug_req_remove_by_index(func_drc);
1741 }
1742 }
1743 }
1744 } else {
1745 error_setg(errp,
1746 "PCI device unplug already in progress for device %s",
1747 drc->dev->id);
1748 }
1749 }
1750
1751 static void spapr_phb_finalizefn(Object *obj)
1752 {
1753 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj);
1754
1755 g_free(sphb->dtbusname);
1756 sphb->dtbusname = NULL;
1757 }
1758
1759 static void spapr_phb_unrealize(DeviceState *dev)
1760 {
1761 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1762 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1763 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1764 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb);
1765 SpaprTceTable *tcet;
1766 int i;
1767 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1768
1769 spapr_phb_nvgpu_free(sphb);
1770
1771 if (sphb->msi) {
1772 g_hash_table_unref(sphb->msi);
1773 sphb->msi = NULL;
1774 }
1775
1776 /*
1777 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1778 * via PHB's unrealize->object_finalize
1779 */
1780 for (i = windows_supported - 1; i >= 0; i--) {
1781 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1782 if (tcet) {
1783 memory_region_del_subregion(&sphb->iommu_root,
1784 spapr_tce_get_iommu(tcet));
1785 }
1786 }
1787
1788 remove_drcs(sphb, phb->bus);
1789
1790 for (i = PCI_NUM_PINS - 1; i >= 0; i--) {
1791 if (sphb->lsi_table[i].irq) {
1792 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1);
1793 sphb->lsi_table[i].irq = 0;
1794 }
1795 }
1796
1797 QLIST_REMOVE(sphb, list);
1798
1799 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow);
1800
1801 /*
1802 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have
1803 * unmapped all sections. Remove the listeners now, before destroying the
1804 * address space.
1805 */
1806 address_space_remove_listeners(&sphb->iommu_as);
1807 address_space_destroy(&sphb->iommu_as);
1808
1809 qbus_set_hotplug_handler(BUS(phb->bus), NULL);
1810 pci_unregister_root_bus(phb->bus);
1811
1812 memory_region_del_subregion(get_system_memory(), &sphb->iowindow);
1813 if (sphb->mem64_win_pciaddr != (hwaddr)-1) {
1814 memory_region_del_subregion(get_system_memory(), &sphb->mem64window);
1815 }
1816 memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
1817 }
1818
1819 static void spapr_phb_destroy_msi(gpointer opaque)
1820 {
1821 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1822 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1823 SpaprPciMsi *msi = opaque;
1824
1825 if (!smc->legacy_irq_allocation) {
1826 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
1827 }
1828 spapr_irq_free(spapr, msi->first_irq, msi->num);
1829 g_free(msi);
1830 }
1831
1832 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1833 {
1834 ERRP_GUARD();
1835 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1836 * tries to add a sPAPR PHB to a non-pseries machine.
1837 */
1838 SpaprMachineState *spapr =
1839 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
1840 TYPE_SPAPR_MACHINE);
1841 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL;
1842 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1843 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1844 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1845 MachineState *ms = MACHINE(spapr);
1846 char *namebuf;
1847 int i;
1848 PCIBus *bus;
1849 uint64_t msi_window_size = 4096;
1850 SpaprTceTable *tcet;
1851 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1852
1853 if (!spapr) {
1854 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1855 return;
1856 }
1857
1858 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1859
1860 if (sphb->mem64_win_size != 0) {
1861 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1862 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1863 " (max 2 GiB)", sphb->mem_win_size);
1864 return;
1865 }
1866
1867 /* 64-bit window defaults to identity mapping */
1868 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1869 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1870 /*
1871 * For compatibility with old configuration, if no 64-bit MMIO
1872 * window is specified, but the ordinary (32-bit) memory
1873 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1874 * window, with a 64-bit MMIO window following on immediately
1875 * afterwards
1876 */
1877 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1878 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1879 sphb->mem64_win_pciaddr =
1880 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1881 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1882 }
1883
1884 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1885 SpaprPhbState *s;
1886
1887 error_setg(errp, "PCI host bridges must have unique indexes");
1888 error_append_hint(errp, "The following indexes are already in use:");
1889 QLIST_FOREACH(s, &spapr->phbs, list) {
1890 error_append_hint(errp, " %d", s->index);
1891 }
1892 error_append_hint(errp, "\nTry another value for the index property\n");
1893 return;
1894 }
1895
1896 if (sphb->numa_node != -1 &&
1897 (sphb->numa_node >= MAX_NODES ||
1898 !ms->numa_state->nodes[sphb->numa_node].present)) {
1899 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1900 return;
1901 }
1902
1903 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1904
1905 /* Initialize memory regions */
1906 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1907 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1908 g_free(namebuf);
1909
1910 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1911 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1912 namebuf, &sphb->memspace,
1913 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1914 g_free(namebuf);
1915 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1916 &sphb->mem32window);
1917
1918 if (sphb->mem64_win_size != 0) {
1919 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1920 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1921 namebuf, &sphb->memspace,
1922 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1923 g_free(namebuf);
1924
1925 memory_region_add_subregion(get_system_memory(),
1926 sphb->mem64_win_addr,
1927 &sphb->mem64window);
1928 }
1929
1930 /* Initialize IO regions */
1931 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1932 memory_region_init(&sphb->iospace, OBJECT(sphb),
1933 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1934 g_free(namebuf);
1935
1936 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1937 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1938 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1939 g_free(namebuf);
1940 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1941 &sphb->iowindow);
1942
1943 bus = pci_register_root_bus(dev, NULL,
1944 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
1945 &sphb->memspace, &sphb->iospace,
1946 PCI_DEVFN(0, 0), PCI_NUM_PINS,
1947 TYPE_PCI_BUS);
1948
1949 /*
1950 * Despite resembling a vanilla PCI bus in most ways, the PAPR
1951 * para-virtualized PCI bus *does* permit PCI-E extended config
1952 * space access
1953 */
1954 if (sphb->pcie_ecs) {
1955 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1956 }
1957 phb->bus = bus;
1958 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb));
1959
1960 /*
1961 * Initialize PHB address space.
1962 * By default there will be at least one subregion for default
1963 * 32bit DMA window.
1964 * Later the guest might want to create another DMA window
1965 * which will become another memory subregion.
1966 */
1967 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1968 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1969 namebuf, UINT64_MAX);
1970 g_free(namebuf);
1971 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1972 sphb->dtbusname);
1973
1974 /*
1975 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1976 * we need to allocate some memory to catch those writes coming
1977 * from msi_notify()/msix_notify().
1978 * As MSIMessage:addr is going to be the same and MSIMessage:data
1979 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1980 * be used.
1981 *
1982 * For KVM we want to ensure that this memory is a full page so that
1983 * our memory slot is of page size granularity.
1984 */
1985 if (kvm_enabled()) {
1986 msi_window_size = qemu_real_host_page_size;
1987 }
1988
1989 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1990 "msi", msi_window_size);
1991 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1992 &sphb->msiwindow);
1993
1994 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1995
1996 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1997
1998 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1999
2000 /* Initialize the LSI table */
2001 for (i = 0; i < PCI_NUM_PINS; i++) {
2002 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
2003
2004 if (smc->legacy_irq_allocation) {
2005 irq = spapr_irq_findone(spapr, errp);
2006 if (irq < 0) {
2007 error_prepend(errp, "can't allocate LSIs: ");
2008 /*
2009 * Older machines will never support PHB hotplug, ie, this is an
2010 * init only path and QEMU will terminate. No need to rollback.
2011 */
2012 return;
2013 }
2014 }
2015
2016 if (spapr_irq_claim(spapr, irq, true, errp) < 0) {
2017 error_prepend(errp, "can't allocate LSIs: ");
2018 goto unrealize;
2019 }
2020
2021 sphb->lsi_table[i].irq = irq;
2022 }
2023
2024 /* allocate connectors for child PCI devices */
2025 add_drcs(sphb, phb->bus);
2026
2027 /* DMA setup */
2028 for (i = 0; i < windows_supported; ++i) {
2029 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
2030 if (!tcet) {
2031 error_setg(errp, "Creating window#%d failed for %s",
2032 i, sphb->dtbusname);
2033 goto unrealize;
2034 }
2035 memory_region_add_subregion(&sphb->iommu_root, 0,
2036 spapr_tce_get_iommu(tcet));
2037 }
2038
2039 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free,
2040 spapr_phb_destroy_msi);
2041 return;
2042
2043 unrealize:
2044 spapr_phb_unrealize(dev);
2045 }
2046
2047 static int spapr_phb_children_reset(Object *child, void *opaque)
2048 {
2049 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
2050
2051 if (dev) {
2052 device_legacy_reset(dev);
2053 }
2054
2055 return 0;
2056 }
2057
2058 void spapr_phb_dma_reset(SpaprPhbState *sphb)
2059 {
2060 int i;
2061 SpaprTceTable *tcet;
2062
2063 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
2064 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
2065
2066 if (tcet && tcet->nb_table) {
2067 spapr_tce_table_disable(tcet);
2068 }
2069 }
2070
2071 /* Register default 32bit DMA window */
2072 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
2073 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
2074 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
2075 }
2076
2077 static void spapr_phb_reset(DeviceState *qdev)
2078 {
2079 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
2080 Error *err = NULL;
2081
2082 spapr_phb_dma_reset(sphb);
2083 spapr_phb_nvgpu_free(sphb);
2084 spapr_phb_nvgpu_setup(sphb, &err);
2085 if (err) {
2086 error_report_err(err);
2087 }
2088
2089 /* Reset the IOMMU state */
2090 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
2091
2092 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
2093 spapr_phb_vfio_reset(qdev);
2094 }
2095
2096 g_hash_table_remove_all(sphb->msi);
2097 }
2098
2099 static Property spapr_phb_properties[] = {
2100 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1),
2101 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size,
2102 SPAPR_PCI_MEM32_WIN_SIZE),
2103 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size,
2104 SPAPR_PCI_MEM64_WIN_SIZE),
2105 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size,
2106 SPAPR_PCI_IO_WIN_SIZE),
2107 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled,
2108 true),
2109 /* Default DMA window is 0..1GB */
2110 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0),
2111 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000),
2112 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr,
2113 0x800000000000000ULL),
2114 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true),
2115 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask,
2116 (1ULL << 12) | (1ULL << 16)
2117 | (1ULL << 21) | (1ULL << 24)),
2118 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
2119 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState,
2120 pre_2_8_migration, false),
2121 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
2122 pcie_ecs, true),
2123 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0),
2124 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0),
2125 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,
2126 pre_5_1_assoc, false),
2127 DEFINE_PROP_END_OF_LIST(),
2128 };
2129
2130 static const VMStateDescription vmstate_spapr_pci_lsi = {
2131 .name = "spapr_pci/lsi",
2132 .version_id = 1,
2133 .minimum_version_id = 1,
2134 .fields = (VMStateField[]) {
2135 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL),
2136
2137 VMSTATE_END_OF_LIST()
2138 },
2139 };
2140
2141 static const VMStateDescription vmstate_spapr_pci_msi = {
2142 .name = "spapr_pci/msi",
2143 .version_id = 1,
2144 .minimum_version_id = 1,
2145 .fields = (VMStateField []) {
2146 VMSTATE_UINT32(key, SpaprPciMsiMig),
2147 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig),
2148 VMSTATE_UINT32(value.num, SpaprPciMsiMig),
2149 VMSTATE_END_OF_LIST()
2150 },
2151 };
2152
2153 static int spapr_pci_pre_save(void *opaque)
2154 {
2155 SpaprPhbState *sphb = opaque;
2156 GHashTableIter iter;
2157 gpointer key, value;
2158 int i;
2159
2160 if (sphb->pre_2_8_migration) {
2161 sphb->mig_liobn = sphb->dma_liobn[0];
2162 sphb->mig_mem_win_addr = sphb->mem_win_addr;
2163 sphb->mig_mem_win_size = sphb->mem_win_size;
2164 sphb->mig_io_win_addr = sphb->io_win_addr;
2165 sphb->mig_io_win_size = sphb->io_win_size;
2166
2167 if ((sphb->mem64_win_size != 0)
2168 && (sphb->mem64_win_addr
2169 == (sphb->mem_win_addr + sphb->mem_win_size))) {
2170 sphb->mig_mem_win_size += sphb->mem64_win_size;
2171 }
2172 }
2173
2174 g_free(sphb->msi_devs);
2175 sphb->msi_devs = NULL;
2176 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
2177 if (!sphb->msi_devs_num) {
2178 return 0;
2179 }
2180 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num);
2181
2182 g_hash_table_iter_init(&iter, sphb->msi);
2183 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
2184 sphb->msi_devs[i].key = *(uint32_t *) key;
2185 sphb->msi_devs[i].value = *(SpaprPciMsi *) value;
2186 }
2187
2188 return 0;
2189 }
2190
2191 static int spapr_pci_post_save(void *opaque)
2192 {
2193 SpaprPhbState *sphb = opaque;
2194
2195 g_free(sphb->msi_devs);
2196 sphb->msi_devs = NULL;
2197 sphb->msi_devs_num = 0;
2198 return 0;
2199 }
2200
2201 static int spapr_pci_post_load(void *opaque, int version_id)
2202 {
2203 SpaprPhbState *sphb = opaque;
2204 gpointer key, value;
2205 int i;
2206
2207 for (i = 0; i < sphb->msi_devs_num; ++i) {
2208 key = g_memdup(&sphb->msi_devs[i].key,
2209 sizeof(sphb->msi_devs[i].key));
2210 value = g_memdup(&sphb->msi_devs[i].value,
2211 sizeof(sphb->msi_devs[i].value));
2212 g_hash_table_insert(sphb->msi, key, value);
2213 }
2214 g_free(sphb->msi_devs);
2215 sphb->msi_devs = NULL;
2216 sphb->msi_devs_num = 0;
2217
2218 return 0;
2219 }
2220
2221 static bool pre_2_8_migration(void *opaque, int version_id)
2222 {
2223 SpaprPhbState *sphb = opaque;
2224
2225 return sphb->pre_2_8_migration;
2226 }
2227
2228 static const VMStateDescription vmstate_spapr_pci = {
2229 .name = "spapr_pci",
2230 .version_id = 2,
2231 .minimum_version_id = 2,
2232 .pre_save = spapr_pci_pre_save,
2233 .post_save = spapr_pci_post_save,
2234 .post_load = spapr_pci_post_load,
2235 .fields = (VMStateField[]) {
2236 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL),
2237 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration),
2238 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration),
2239 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration),
2240 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration),
2241 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration),
2242 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
2243 vmstate_spapr_pci_lsi, SpaprPciLsi),
2244 VMSTATE_INT32(msi_devs_num, SpaprPhbState),
2245 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
2246 vmstate_spapr_pci_msi, SpaprPciMsiMig),
2247 VMSTATE_END_OF_LIST()
2248 },
2249 };
2250
2251 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
2252 PCIBus *rootbus)
2253 {
2254 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
2255
2256 return sphb->dtbusname;
2257 }
2258
2259 static void spapr_phb_class_init(ObjectClass *klass, void *data)
2260 {
2261 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
2262 DeviceClass *dc = DEVICE_CLASS(klass);
2263 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
2264
2265 hc->root_bus_path = spapr_phb_root_bus_path;
2266 dc->realize = spapr_phb_realize;
2267 dc->unrealize = spapr_phb_unrealize;
2268 device_class_set_props(dc, spapr_phb_properties);
2269 dc->reset = spapr_phb_reset;
2270 dc->vmsd = &vmstate_spapr_pci;
2271 /* Supported by TYPE_SPAPR_MACHINE */
2272 dc->user_creatable = true;
2273 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
2274 hp->pre_plug = spapr_pci_pre_plug;
2275 hp->plug = spapr_pci_plug;
2276 hp->unplug = spapr_pci_unplug;
2277 hp->unplug_request = spapr_pci_unplug_request;
2278 }
2279
2280 static const TypeInfo spapr_phb_info = {
2281 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
2282 .parent = TYPE_PCI_HOST_BRIDGE,
2283 .instance_size = sizeof(SpaprPhbState),
2284 .instance_finalize = spapr_phb_finalizefn,
2285 .class_init = spapr_phb_class_init,
2286 .interfaces = (InterfaceInfo[]) {
2287 { TYPE_HOTPLUG_HANDLER },
2288 { }
2289 }
2290 };
2291
2292 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2293 void *opaque)
2294 {
2295 unsigned int *bus_no = opaque;
2296 PCIBus *sec_bus = NULL;
2297
2298 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2299 PCI_HEADER_TYPE_BRIDGE)) {
2300 return;
2301 }
2302
2303 (*bus_no)++;
2304 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
2305 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2306 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2307
2308 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2309 if (!sec_bus) {
2310 return;
2311 }
2312
2313 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2314 spapr_phb_pci_enumerate_bridge, bus_no);
2315 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2316 }
2317
2318 static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
2319 {
2320 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2321 unsigned int bus_no = 0;
2322
2323 pci_for_each_device(bus, pci_bus_num(bus),
2324 spapr_phb_pci_enumerate_bridge,
2325 &bus_no);
2326
2327 }
2328
2329 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
2330 uint32_t intc_phandle, void *fdt, int *node_offset)
2331 {
2332 int bus_off, i, j, ret;
2333 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2334 struct {
2335 uint32_t hi;
2336 uint64_t child;
2337 uint64_t parent;
2338 uint64_t size;
2339 } QEMU_PACKED ranges[] = {
2340 {
2341 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2342 cpu_to_be64(phb->io_win_addr),
2343 cpu_to_be64(memory_region_size(&phb->iospace)),
2344 },
2345 {
2346 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2347 cpu_to_be64(phb->mem_win_addr),
2348 cpu_to_be64(phb->mem_win_size),
2349 },
2350 {
2351 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2352 cpu_to_be64(phb->mem64_win_addr),
2353 cpu_to_be64(phb->mem64_win_size),
2354 },
2355 };
2356 const unsigned sizeof_ranges =
2357 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2358 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2359 uint32_t interrupt_map_mask[] = {
2360 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2361 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2362 uint32_t ddw_applicable[] = {
2363 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2364 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2365 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2366 };
2367 uint32_t ddw_extensions[] = {
2368 cpu_to_be32(1),
2369 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2370 };
2371 SpaprTceTable *tcet;
2372 SpaprDrc *drc;
2373 Error *err = NULL;
2374
2375 /* Start populating the FDT */
2376 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname));
2377 if (node_offset) {
2378 *node_offset = bus_off;
2379 }
2380
2381 /* Write PHB properties */
2382 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2383 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2384 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2385 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2386 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2387 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2388 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2389 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2390 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi",
2391 spapr_irq_nr_msis(spapr)));
2392
2393 /* Dynamic DMA window */
2394 if (phb->ddw_enabled) {
2395 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2396 sizeof(ddw_applicable)));
2397 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2398 &ddw_extensions, sizeof(ddw_extensions)));
2399 }
2400
2401 /* Advertise NUMA via ibm,associativity */
2402 if (phb->numa_node != -1) {
2403 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node);
2404 }
2405
2406 /* Build the interrupt-map, this must matches what is done
2407 * in pci_swizzle_map_irq_fn
2408 */
2409 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2410 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2411 for (i = 0; i < PCI_SLOT_MAX; i++) {
2412 for (j = 0; j < PCI_NUM_PINS; j++) {
2413 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2414 int lsi_num = pci_swizzle(i, j);
2415
2416 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2417 irqmap[1] = 0;
2418 irqmap[2] = 0;
2419 irqmap[3] = cpu_to_be32(j+1);
2420 irqmap[4] = cpu_to_be32(intc_phandle);
2421 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
2422 }
2423 }
2424 /* Write interrupt map */
2425 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2426 sizeof(interrupt_map)));
2427
2428 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2429 if (!tcet) {
2430 return -1;
2431 }
2432 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2433 tcet->liobn, tcet->bus_offset,
2434 tcet->nb_table << tcet->page_shift);
2435
2436 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index);
2437 if (drc) {
2438 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc));
2439
2440 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index,
2441 sizeof(drc_index)));
2442 }
2443
2444 /* Walk the bridges and program the bus numbers*/
2445 spapr_phb_pci_enumerate(phb);
2446 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2447
2448 /* Walk the bridge and subordinate buses */
2449 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off);
2450 if (ret < 0) {
2451 return ret;
2452 }
2453
2454 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &err);
2455 if (err) {
2456 error_report_err(err);
2457 }
2458 spapr_phb_nvgpu_ram_populate_dt(phb, fdt);
2459
2460 return 0;
2461 }
2462
2463 void spapr_pci_rtas_init(void)
2464 {
2465 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2466 rtas_read_pci_config);
2467 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2468 rtas_write_pci_config);
2469 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2470 rtas_ibm_read_pci_config);
2471 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2472 rtas_ibm_write_pci_config);
2473 if (msi_nonbroken) {
2474 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2475 "ibm,query-interrupt-source-number",
2476 rtas_ibm_query_interrupt_source_number);
2477 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2478 rtas_ibm_change_msi);
2479 }
2480
2481 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2482 "ibm,set-eeh-option",
2483 rtas_ibm_set_eeh_option);
2484 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2485 "ibm,get-config-addr-info2",
2486 rtas_ibm_get_config_addr_info2);
2487 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2488 "ibm,read-slot-reset-state2",
2489 rtas_ibm_read_slot_reset_state2);
2490 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2491 "ibm,set-slot-reset",
2492 rtas_ibm_set_slot_reset);
2493 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2494 "ibm,configure-pe",
2495 rtas_ibm_configure_pe);
2496 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2497 "ibm,slot-error-detail",
2498 rtas_ibm_slot_error_detail);
2499 }
2500
2501 static void spapr_pci_register_types(void)
2502 {
2503 type_register_static(&spapr_phb_info);
2504 }
2505
2506 type_init(spapr_pci_register_types)
2507
2508 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2509 {
2510 bool be = *(bool *)opaque;
2511
2512 if (object_dynamic_cast(OBJECT(dev), "VGA")
2513 || object_dynamic_cast(OBJECT(dev), "secondary-vga")
2514 || object_dynamic_cast(OBJECT(dev), "bochs-display")
2515 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) {
2516 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be,
2517 &error_abort);
2518 }
2519 return 0;
2520 }
2521
2522 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian)
2523 {
2524 SpaprPhbState *sphb;
2525
2526 /*
2527 * For backward compatibility with existing guests, we switch
2528 * the endianness of the VGA controller when changing the guest
2529 * interrupt mode
2530 */
2531 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2532 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2533 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2534 &big_endian);
2535 }
2536 }
AR7 emulation for QEMU