target/arm: Implement MVE WLSTP insn
[qemu/ar7.git] / hw / pci-host / sh_pci.c
blob08c1562e2281daf0f37d7268876bfb248470b6c4
1 /*
2 * SuperH on-chip PCIC emulation.
4 * Copyright (c) 2008 Takashi YOSHII
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "hw/sh4/sh.h"
28 #include "hw/irq.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_host.h"
31 #include "qemu/bswap.h"
32 #include "qemu/module.h"
33 #include "qom/object.h"
35 #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
37 OBJECT_DECLARE_SIMPLE_TYPE(SHPCIState, SH_PCI_HOST_BRIDGE)
39 struct SHPCIState {
40 PCIHostState parent_obj;
42 PCIDevice *dev;
43 qemu_irq irq[4];
44 MemoryRegion memconfig_p4;
45 MemoryRegion memconfig_a7;
46 MemoryRegion isa;
47 uint32_t par;
48 uint32_t mbr;
49 uint32_t iobr;
52 static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
53 unsigned size)
55 SHPCIState *pcic = p;
56 PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
58 switch(addr) {
59 case 0 ... 0xfc:
60 stl_le_p(pcic->dev->config + addr, val);
61 break;
62 case 0x1c0:
63 pcic->par = val;
64 break;
65 case 0x1c4:
66 pcic->mbr = val & 0xff000001;
67 break;
68 case 0x1c8:
69 pcic->iobr = val & 0xfffc0001;
70 memory_region_set_alias_offset(&pcic->isa, val & 0xfffc0000);
71 break;
72 case 0x220:
73 pci_data_write(phb->bus, pcic->par, val, 4);
74 break;
78 static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
79 unsigned size)
81 SHPCIState *pcic = p;
82 PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
84 switch(addr) {
85 case 0 ... 0xfc:
86 return ldl_le_p(pcic->dev->config + addr);
87 case 0x1c0:
88 return pcic->par;
89 case 0x1c4:
90 return pcic->mbr;
91 case 0x1c8:
92 return pcic->iobr;
93 case 0x220:
94 return pci_data_read(phb->bus, pcic->par, 4);
96 return 0;
99 static const MemoryRegionOps sh_pci_reg_ops = {
100 .read = sh_pci_reg_read,
101 .write = sh_pci_reg_write,
102 .endianness = DEVICE_NATIVE_ENDIAN,
103 .valid = {
104 .min_access_size = 4,
105 .max_access_size = 4,
109 static int sh_pci_map_irq(PCIDevice *d, int irq_num)
111 return PCI_SLOT(d->devfn);
114 static void sh_pci_set_irq(void *opaque, int irq_num, int level)
116 qemu_irq *pic = opaque;
118 qemu_set_irq(pic[irq_num], level);
121 static void sh_pci_device_realize(DeviceState *dev, Error **errp)
123 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
124 SHPCIState *s = SH_PCI_HOST_BRIDGE(dev);
125 PCIHostState *phb = PCI_HOST_BRIDGE(s);
126 int i;
128 for (i = 0; i < 4; i++) {
129 sysbus_init_irq(sbd, &s->irq[i]);
131 phb->bus = pci_register_root_bus(dev, "pci",
132 sh_pci_set_irq, sh_pci_map_irq,
133 s->irq,
134 get_system_memory(),
135 get_system_io(),
136 PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
137 memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
138 "sh_pci", 0x224);
139 memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
140 &s->memconfig_p4, 0, 0x224);
141 memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa",
142 get_system_io(), 0, 0x40000);
143 sysbus_init_mmio(sbd, &s->memconfig_p4);
144 sysbus_init_mmio(sbd, &s->memconfig_a7);
145 memory_region_add_subregion(get_system_memory(), 0xfe240000, &s->isa);
147 s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
150 static void sh_pci_host_realize(PCIDevice *d, Error **errp)
152 pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
153 pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
154 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
157 static void sh_pci_host_class_init(ObjectClass *klass, void *data)
159 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
160 DeviceClass *dc = DEVICE_CLASS(klass);
162 k->realize = sh_pci_host_realize;
163 k->vendor_id = PCI_VENDOR_ID_HITACHI;
164 k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R;
166 * PCI-facing part of the host bridge, not usable without the
167 * host-facing part, which can't be device_add'ed, yet.
169 dc->user_creatable = false;
172 static const TypeInfo sh_pci_host_info = {
173 .name = "sh_pci_host",
174 .parent = TYPE_PCI_DEVICE,
175 .instance_size = sizeof(PCIDevice),
176 .class_init = sh_pci_host_class_init,
177 .interfaces = (InterfaceInfo[]) {
178 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
179 { },
183 static void sh_pci_device_class_init(ObjectClass *klass, void *data)
185 DeviceClass *dc = DEVICE_CLASS(klass);
187 dc->realize = sh_pci_device_realize;
190 static const TypeInfo sh_pci_device_info = {
191 .name = TYPE_SH_PCI_HOST_BRIDGE,
192 .parent = TYPE_PCI_HOST_BRIDGE,
193 .instance_size = sizeof(SHPCIState),
194 .class_init = sh_pci_device_class_init,
197 static void sh_pci_register_types(void)
199 type_register_static(&sh_pci_device_info);
200 type_register_static(&sh_pci_host_info);
203 type_init(sh_pci_register_types)