1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
57 #include "hw/acpi/aml-build.h"
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
62 #include "hw/acpi/ipmi.h"
64 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
65 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
66 * a little bit, there should be plenty of free space since the DSDT
67 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
69 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
70 #define ACPI_BUILD_ALIGN_SIZE 0x1000
72 #define ACPI_BUILD_TABLE_SIZE 0x20000
74 /* #define DEBUG_ACPI_BUILD */
75 #ifdef DEBUG_ACPI_BUILD
76 #define ACPI_BUILD_DPRINTF(fmt, ...) \
77 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
79 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 typedef struct AcpiMcfgInfo
{
87 typedef struct AcpiPmInfo
{
93 uint8_t acpi_enable_cmd
;
94 uint8_t acpi_disable_cmd
;
96 uint32_t gpe0_blk_len
;
98 uint16_t cpu_hp_io_base
;
99 uint16_t mem_hp_io_base
;
100 uint16_t mem_hp_io_len
;
101 uint16_t pcihp_io_base
;
102 uint16_t pcihp_io_len
;
105 typedef struct AcpiMiscInfo
{
108 TPMVersion tpm_version
;
109 const unsigned char *dsdt_code
;
111 uint16_t pvpanic_port
;
112 uint16_t applesmc_io_base
;
115 typedef struct AcpiBuildPciBusHotplugState
{
116 GArray
*device_table
;
117 GArray
*notify_table
;
118 struct AcpiBuildPciBusHotplugState
*parent
;
119 bool pcihp_bridge_en
;
120 } AcpiBuildPciBusHotplugState
;
122 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
124 Object
*piix
= piix4_pm_find();
125 Object
*lpc
= ich9_lpc_find();
129 pm
->cpu_hp_io_base
= 0;
130 pm
->pcihp_io_base
= 0;
131 pm
->pcihp_io_len
= 0;
134 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
136 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
138 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
142 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
146 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
147 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
149 /* Fill in optional s3/s4 related properties */
150 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
152 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
154 pm
->s3_disabled
= false;
157 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
159 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
161 pm
->s4_disabled
= false;
164 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
166 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
172 /* Fill in mandatory properties */
173 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
175 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
176 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
178 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
179 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
181 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
183 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
185 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
187 pm
->pcihp_bridge_en
=
188 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
192 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
194 Object
*piix
= piix4_pm_find();
195 Object
*lpc
= ich9_lpc_find();
196 assert(!!piix
!= !!lpc
);
199 info
->is_piix4
= true;
202 info
->is_piix4
= false;
205 info
->has_hpet
= hpet_find();
206 info
->tpm_version
= tpm_get_version();
207 info
->pvpanic_port
= pvpanic_port();
208 info
->applesmc_io_base
= applesmc_port();
212 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
213 * On i386 arch we only have two pci hosts, so we can look only for them.
215 static Object
*acpi_get_i386_pci_host(void)
219 host
= OBJECT_CHECK(PCIHostState
,
220 object_resolve_path("/machine/i440fx", NULL
),
221 TYPE_PCI_HOST_BRIDGE
);
223 host
= OBJECT_CHECK(PCIHostState
,
224 object_resolve_path("/machine/q35", NULL
),
225 TYPE_PCI_HOST_BRIDGE
);
231 static void acpi_get_pci_info(PcPciInfo
*info
)
236 pci_host
= acpi_get_i386_pci_host();
239 info
->w32
.begin
= object_property_get_int(pci_host
,
240 PCI_HOST_PROP_PCI_HOLE_START
,
242 info
->w32
.end
= object_property_get_int(pci_host
,
243 PCI_HOST_PROP_PCI_HOLE_END
,
245 info
->w64
.begin
= object_property_get_int(pci_host
,
246 PCI_HOST_PROP_PCI_HOLE64_START
,
248 info
->w64
.end
= object_property_get_int(pci_host
,
249 PCI_HOST_PROP_PCI_HOLE64_END
,
253 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
255 static void acpi_align_size(GArray
*blob
, unsigned align
)
257 /* Align size to multiple of given size. This reduces the chance
258 * we need to change size in the future (breaking cross version migration).
260 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
265 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
267 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
268 memcpy(&facs
->signature
, "FACS", 4);
269 facs
->length
= cpu_to_le32(sizeof(*facs
));
272 /* Load chipset information in FADT */
273 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
277 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
278 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
279 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
280 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
281 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
282 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
283 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
284 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
285 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
286 /* EVT, CNT, TMR length matches hw/acpi/core.c */
287 fadt
->pm1_evt_len
= 4;
288 fadt
->pm1_cnt_len
= 2;
289 fadt
->pm_tmr_len
= 4;
290 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
291 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
292 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
293 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
294 (1 << ACPI_FADT_F_PROC_C1
) |
295 (1 << ACPI_FADT_F_SLP_BUTTON
) |
296 (1 << ACPI_FADT_F_RTC_S4
));
297 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
298 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
299 * For more than 8 CPUs, "Clustered Logical" mode has to be used
302 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
304 fadt
->century
= RTC_CENTURY
;
310 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
311 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
312 const char *oem_id
, const char *oem_table_id
)
314 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
315 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
316 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
318 /* FACS address to be filled by Guest linker */
319 bios_linker_loader_add_pointer(linker
,
320 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
321 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
323 /* DSDT address to be filled by Guest linker */
324 fadt_setup(fadt
, pm
);
325 bios_linker_loader_add_pointer(linker
,
326 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
327 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
329 build_header(linker
, table_data
,
330 (void *)fadt
, "FACP", sizeof(*fadt
), 1, oem_id
, oem_table_id
);
333 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
334 CPUArchIdList
*apic_ids
, GArray
*entry
)
337 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
339 apic_id
= apic_ids
->cpus
[uid
].arch_id
;
340 apic
->type
= ACPI_APIC_PROCESSOR
;
341 apic
->length
= sizeof(*apic
);
342 apic
->processor_id
= uid
;
343 apic
->local_apic_id
= apic_id
;
344 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
345 apic
->flags
= cpu_to_le32(1);
347 /* ACPI spec says that LAPIC entry for non present
348 * CPU may be omitted from MADT or it must be marked
349 * as disabled. However omitting non present CPU from
350 * MADT breaks hotplug on linux. So possible CPUs
351 * should be put in MADT but kept disabled.
353 apic
->flags
= cpu_to_le32(0);
358 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
360 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
361 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
362 int madt_start
= table_data
->len
;
363 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
364 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
366 AcpiMultipleApicTable
*madt
;
367 AcpiMadtIoApic
*io_apic
;
368 AcpiMadtIntsrcovr
*intsrcovr
;
369 AcpiMadtLocalNmi
*local_nmi
;
372 madt
= acpi_data_push(table_data
, sizeof *madt
);
373 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
374 madt
->flags
= cpu_to_le32(1);
376 for (i
= 0; i
< apic_ids
->len
; i
++) {
377 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
381 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
382 io_apic
->type
= ACPI_APIC_IO
;
383 io_apic
->length
= sizeof(*io_apic
);
384 #define ACPI_BUILD_IOAPIC_ID 0x0
385 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
386 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
387 io_apic
->interrupt
= cpu_to_le32(0);
389 if (pcms
->apic_xrupt_override
) {
390 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
391 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
392 intsrcovr
->length
= sizeof(*intsrcovr
);
393 intsrcovr
->source
= 0;
394 intsrcovr
->gsi
= cpu_to_le32(2);
395 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
397 for (i
= 1; i
< 16; i
++) {
398 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
399 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
400 /* No need for a INT source override structure. */
403 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
404 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
405 intsrcovr
->length
= sizeof(*intsrcovr
);
406 intsrcovr
->source
= i
;
407 intsrcovr
->gsi
= cpu_to_le32(i
);
408 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
411 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
412 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
413 local_nmi
->length
= sizeof(*local_nmi
);
414 local_nmi
->processor_id
= 0xff; /* all processors */
415 local_nmi
->flags
= cpu_to_le16(0);
416 local_nmi
->lint
= 1; /* ACPI_LINT1 */
418 build_header(linker
, table_data
,
419 (void *)(table_data
->data
+ madt_start
), "APIC",
420 table_data
->len
- madt_start
, 1, NULL
, NULL
);
423 /* Assign BSEL property to all buses. In the future, this can be changed
424 * to only assign to buses that support hotplug.
426 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
428 unsigned *bsel_alloc
= opaque
;
431 if (qbus_is_hotpluggable(BUS(bus
))) {
432 bus_bsel
= g_malloc(sizeof *bus_bsel
);
434 *bus_bsel
= (*bsel_alloc
)++;
435 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
442 static void acpi_set_pci_info(void)
444 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
445 unsigned bsel_alloc
= 0;
448 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
449 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
453 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
456 int32_t devfn
= PCI_DEVFN(slot
, 0);
458 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
459 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
460 aml_append(method
, if_ctx
);
463 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
464 bool pcihp_bridge_en
)
466 Aml
*dev
, *notify_method
, *method
;
471 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
473 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
475 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
476 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
479 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
482 PCIDevice
*pdev
= bus
->devices
[i
];
483 int slot
= PCI_SLOT(i
);
484 bool hotplug_enabled_dev
;
488 if (bsel
) { /* add hotplug slots for non present devices */
489 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
490 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
491 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
492 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
494 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
496 aml_append(dev
, method
);
497 aml_append(parent_scope
, dev
);
499 build_append_pcihp_notify_entry(notify_method
, slot
);
504 pc
= PCI_DEVICE_GET_CLASS(pdev
);
505 dc
= DEVICE_GET_CLASS(pdev
);
507 /* When hotplug for bridges is enabled, bridges are
508 * described in ACPI separately (see build_pci_bus_end).
509 * In this case they aren't themselves hot-pluggable.
510 * Hotplugged bridges *are* hot-pluggable.
512 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
513 !DEVICE(pdev
)->hotplugged
;
515 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
517 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
521 /* start to compose PCI slot descriptor */
522 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
523 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
525 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
526 /* add VGA specific AML methods */
529 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
535 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
536 aml_append(method
, aml_return(aml_int(0)));
537 aml_append(dev
, method
);
539 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
540 aml_append(method
, aml_return(aml_int(0)));
541 aml_append(dev
, method
);
543 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
544 aml_append(method
, aml_return(aml_int(s3d
)));
545 aml_append(dev
, method
);
546 } else if (hotplug_enabled_dev
) {
547 /* add _SUN/_EJ0 to make slot hotpluggable */
548 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
550 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
552 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
554 aml_append(dev
, method
);
557 build_append_pcihp_notify_entry(notify_method
, slot
);
559 } else if (bridge_in_acpi
) {
561 * device is coldplugged bridge,
562 * add child device descriptions into its scope
564 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
566 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
568 /* slot descriptor has been composed, add it into parent context */
569 aml_append(parent_scope
, dev
);
573 aml_append(parent_scope
, notify_method
);
576 /* Append PCNT method to notify about events on local and child buses.
577 * Add unconditionally for root since DSDT expects it.
579 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
581 /* If bus supports hotplug select it and notify about local events */
583 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
584 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
586 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
589 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
593 /* Notify about child bus events in any case */
594 if (pcihp_bridge_en
) {
595 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
596 int32_t devfn
= sec
->parent_dev
->devfn
;
598 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
601 aml_append(parent_scope
, method
);
602 qobject_decref(bsel
);
607 * @link_name: link name for PCI route entry
609 * build AML package containing a PCI route entry for @link_name
611 static Aml
*build_prt_entry(const char *link_name
)
613 Aml
*a_zero
= aml_int(0);
614 Aml
*pkg
= aml_package(4);
615 aml_append(pkg
, a_zero
);
616 aml_append(pkg
, a_zero
);
617 aml_append(pkg
, aml_name("%s", link_name
));
618 aml_append(pkg
, a_zero
);
623 * initialize_route - Initialize the interrupt routing rule
624 * through a specific LINK:
625 * if (lnk_idx == idx)
626 * route using link 'link_name'
628 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
629 Aml
*lnk_idx
, int idx
)
631 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
632 Aml
*pkg
= build_prt_entry(link_name
);
634 aml_append(if_ctx
, aml_store(pkg
, route
));
640 * build_prt - Define interrupt rounting rules
642 * Returns an array of 128 routes, one for each device,
643 * based on device location.
644 * The main goal is to equaly distribute the interrupts
645 * over the 4 existing ACPI links (works only for i440fx).
646 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
649 static Aml
*build_prt(bool is_pci0_prt
)
651 Aml
*method
, *while_ctx
, *pin
, *res
;
653 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
656 aml_append(method
, aml_store(aml_package(128), res
));
657 aml_append(method
, aml_store(aml_int(0), pin
));
659 /* while (pin < 128) */
660 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
662 Aml
*slot
= aml_local(2);
663 Aml
*lnk_idx
= aml_local(3);
664 Aml
*route
= aml_local(4);
666 /* slot = pin >> 2 */
667 aml_append(while_ctx
,
668 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
669 /* lnk_idx = (slot + pin) & 3 */
670 aml_append(while_ctx
,
671 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
674 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
675 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
677 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
679 /* device 1 is the power-management device, needs SCI */
680 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
682 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
685 aml_store(build_prt_entry("LNKS"), route
));
687 aml_append(if_device_1
, if_pin_4
);
688 else_pin_4
= aml_else();
690 aml_append(else_pin_4
,
691 aml_store(build_prt_entry("LNKA"), route
));
693 aml_append(if_device_1
, else_pin_4
);
695 aml_append(while_ctx
, if_device_1
);
697 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
699 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
700 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
702 /* route[0] = 0x[slot]FFFF */
703 aml_append(while_ctx
,
704 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
706 aml_index(route
, aml_int(0))));
707 /* route[1] = pin & 3 */
708 aml_append(while_ctx
,
709 aml_store(aml_and(pin
, aml_int(3), NULL
),
710 aml_index(route
, aml_int(1))));
711 /* res[pin] = route */
712 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
714 aml_append(while_ctx
, aml_increment(pin
));
716 aml_append(method
, while_ctx
);
718 aml_append(method
, aml_return(res
));
723 typedef struct CrsRangeEntry
{
728 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
730 CrsRangeEntry
*entry
;
732 entry
= g_malloc(sizeof(*entry
));
734 entry
->limit
= limit
;
736 g_ptr_array_add(ranges
, entry
);
739 static void crs_range_free(gpointer data
)
741 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
745 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
747 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
748 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
750 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
754 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
755 * interval, computes the 'free' ranges from the same interval.
756 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
757 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
759 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
760 uint64_t start
, uint64_t end
)
762 GPtrArray
*free_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
763 uint64_t free_base
= start
;
766 g_ptr_array_sort(ranges
, crs_range_compare
);
767 for (i
= 0; i
< ranges
->len
; i
++) {
768 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
770 if (free_base
< used
->base
) {
771 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
774 free_base
= used
->limit
+ 1;
777 if (free_base
< end
) {
778 crs_range_insert(free_ranges
, free_base
, end
);
781 g_ptr_array_set_size(ranges
, 0);
782 for (i
= 0; i
< free_ranges
->len
; i
++) {
783 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
786 g_ptr_array_free(free_ranges
, false);
790 * crs_range_merge - merges adjacent ranges in the given array.
791 * Array elements are deleted and replaced with the merged ranges.
793 static void crs_range_merge(GPtrArray
*range
)
795 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
796 CrsRangeEntry
*entry
;
797 uint64_t range_base
, range_limit
;
804 g_ptr_array_sort(range
, crs_range_compare
);
806 entry
= g_ptr_array_index(range
, 0);
807 range_base
= entry
->base
;
808 range_limit
= entry
->limit
;
809 for (i
= 1; i
< range
->len
; i
++) {
810 entry
= g_ptr_array_index(range
, i
);
811 if (entry
->base
- 1 == range_limit
) {
812 range_limit
= entry
->limit
;
814 crs_range_insert(tmp
, range_base
, range_limit
);
815 range_base
= entry
->base
;
816 range_limit
= entry
->limit
;
819 crs_range_insert(tmp
, range_base
, range_limit
);
821 g_ptr_array_set_size(range
, 0);
822 for (i
= 0; i
< tmp
->len
; i
++) {
823 entry
= g_ptr_array_index(tmp
, i
);
824 crs_range_insert(range
, entry
->base
, entry
->limit
);
826 g_ptr_array_free(tmp
, true);
829 static Aml
*build_crs(PCIHostState
*host
,
830 GPtrArray
*io_ranges
, GPtrArray
*mem_ranges
)
832 Aml
*crs
= aml_resource_template();
833 GPtrArray
*host_io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
834 GPtrArray
*host_mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
835 CrsRangeEntry
*entry
;
836 uint8_t max_bus
= pci_bus_num(host
->bus
);
841 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
842 uint64_t range_base
, range_limit
;
843 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
849 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
850 PCIIORegion
*r
= &dev
->io_regions
[i
];
852 range_base
= r
->addr
;
853 range_limit
= r
->addr
+ r
->size
- 1;
856 * Work-around for old bioses
857 * that do not support multiple root buses
859 if (!range_base
|| range_base
> range_limit
) {
863 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
864 crs_range_insert(host_io_ranges
, range_base
, range_limit
);
865 } else { /* "memory" */
866 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
870 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
871 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
872 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
873 if (subordinate
> max_bus
) {
874 max_bus
= subordinate
;
877 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
878 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
881 * Work-around for old bioses
882 * that do not support multiple root buses
884 if (range_base
&& range_base
<= range_limit
) {
885 crs_range_insert(host_io_ranges
, range_base
, range_limit
);
889 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
891 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
894 * Work-around for old bioses
895 * that do not support multiple root buses
897 if (range_base
&& range_base
<= range_limit
) {
898 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
902 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
904 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
907 * Work-around for old bioses
908 * that do not support multiple root buses
910 if (range_base
&& range_base
<= range_limit
) {
911 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
916 crs_range_merge(host_io_ranges
);
917 for (i
= 0; i
< host_io_ranges
->len
; i
++) {
918 entry
= g_ptr_array_index(host_io_ranges
, i
);
920 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
921 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
922 0, entry
->base
, entry
->limit
, 0,
923 entry
->limit
- entry
->base
+ 1));
924 crs_range_insert(io_ranges
, entry
->base
, entry
->limit
);
926 g_ptr_array_free(host_io_ranges
, true);
928 crs_range_merge(host_mem_ranges
);
929 for (i
= 0; i
< host_mem_ranges
->len
; i
++) {
930 entry
= g_ptr_array_index(host_mem_ranges
, i
);
932 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
933 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
935 0, entry
->base
, entry
->limit
, 0,
936 entry
->limit
- entry
->base
+ 1));
937 crs_range_insert(mem_ranges
, entry
->base
, entry
->limit
);
939 g_ptr_array_free(host_mem_ranges
, true);
942 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
944 pci_bus_num(host
->bus
),
947 max_bus
- pci_bus_num(host
->bus
) + 1));
952 static void build_memory_devices(Aml
*sb_scope
, int nr_mem
,
953 uint16_t io_base
, uint16_t io_len
)
963 /* build memory devices */
964 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
965 scope
= aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE
);
967 aml_name_decl(MEMORY_SLOTS_NUMBER
, aml_int(nr_mem
))
970 crs
= aml_resource_template();
972 aml_io(AML_DECODE16
, io_base
, io_base
, 0, io_len
)
974 aml_append(scope
, aml_name_decl("_CRS", crs
));
976 aml_append(scope
, aml_operation_region(
977 MEMORY_HOTPLUG_IO_REGION
, AML_SYSTEM_IO
,
978 aml_int(io_base
), io_len
)
981 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
982 AML_NOLOCK
, AML_PRESERVE
);
983 aml_append(field
, /* read only */
984 aml_named_field(MEMORY_SLOT_ADDR_LOW
, 32));
985 aml_append(field
, /* read only */
986 aml_named_field(MEMORY_SLOT_ADDR_HIGH
, 32));
987 aml_append(field
, /* read only */
988 aml_named_field(MEMORY_SLOT_SIZE_LOW
, 32));
989 aml_append(field
, /* read only */
990 aml_named_field(MEMORY_SLOT_SIZE_HIGH
, 32));
991 aml_append(field
, /* read only */
992 aml_named_field(MEMORY_SLOT_PROXIMITY
, 32));
993 aml_append(scope
, field
);
995 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_BYTE_ACC
,
996 AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
997 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
998 aml_append(field
, /* 1 if enabled, read only */
999 aml_named_field(MEMORY_SLOT_ENABLED
, 1));
1001 /*(read) 1 if has a insert event. (write) 1 to clear event */
1002 aml_named_field(MEMORY_SLOT_INSERT_EVENT
, 1));
1004 /* (read) 1 if has a remove event. (write) 1 to clear event */
1005 aml_named_field(MEMORY_SLOT_REMOVE_EVENT
, 1));
1007 /* initiates device eject, write only */
1008 aml_named_field(MEMORY_SLOT_EJECT
, 1));
1009 aml_append(scope
, field
);
1011 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1012 AML_NOLOCK
, AML_PRESERVE
);
1013 aml_append(field
, /* DIMM selector, write only */
1014 aml_named_field(MEMORY_SLOT_SLECTOR
, 32));
1015 aml_append(field
, /* _OST event code, write only */
1016 aml_named_field(MEMORY_SLOT_OST_EVENT
, 32));
1017 aml_append(field
, /* _OST status code, write only */
1018 aml_named_field(MEMORY_SLOT_OST_STATUS
, 32));
1019 aml_append(scope
, field
);
1020 aml_append(sb_scope
, scope
);
1022 for (i
= 0; i
< nr_mem
; i
++) {
1023 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1026 dev
= aml_device("MP%02X", i
);
1027 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1028 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1030 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1031 s
= BASEPATH MEMORY_SLOT_CRS_METHOD
;
1032 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1033 aml_append(dev
, method
);
1035 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1036 s
= BASEPATH MEMORY_SLOT_STATUS_METHOD
;
1037 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1038 aml_append(dev
, method
);
1040 method
= aml_method("_PXM", 0, AML_NOTSERIALIZED
);
1041 s
= BASEPATH MEMORY_SLOT_PROXIMITY_METHOD
;
1042 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1043 aml_append(dev
, method
);
1045 method
= aml_method("_OST", 3, AML_NOTSERIALIZED
);
1046 s
= BASEPATH MEMORY_SLOT_OST_METHOD
;
1048 aml_append(method
, aml_return(aml_call4(
1049 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1051 aml_append(dev
, method
);
1053 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
1054 s
= BASEPATH MEMORY_SLOT_EJECT_METHOD
;
1055 aml_append(method
, aml_return(aml_call2(
1056 s
, aml_name("_UID"), aml_arg(0))));
1057 aml_append(dev
, method
);
1059 aml_append(sb_scope
, dev
);
1062 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1063 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1065 method
= aml_method(MEMORY_SLOT_NOTIFY_METHOD
, 2, AML_NOTSERIALIZED
);
1066 for (i
= 0; i
< nr_mem
; i
++) {
1067 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1069 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1071 aml_append(method
, ifctx
);
1073 aml_append(sb_scope
, method
);
1076 static void build_hpet_aml(Aml
*table
)
1082 Aml
*scope
= aml_scope("_SB");
1083 Aml
*dev
= aml_device("HPET");
1084 Aml
*zero
= aml_int(0);
1085 Aml
*id
= aml_local(0);
1086 Aml
*period
= aml_local(1);
1088 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1089 aml_append(dev
, aml_name_decl("_UID", zero
));
1092 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1094 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1095 aml_append(field
, aml_named_field("VEND", 32));
1096 aml_append(field
, aml_named_field("PRD", 32));
1097 aml_append(dev
, field
);
1099 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1100 aml_append(method
, aml_store(aml_name("VEND"), id
));
1101 aml_append(method
, aml_store(aml_name("PRD"), period
));
1102 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1103 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1104 aml_equal(id
, aml_int(0xffff))));
1106 aml_append(if_ctx
, aml_return(zero
));
1108 aml_append(method
, if_ctx
);
1110 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1111 aml_lgreater(period
, aml_int(100000000))));
1113 aml_append(if_ctx
, aml_return(zero
));
1115 aml_append(method
, if_ctx
);
1117 aml_append(method
, aml_return(aml_int(0x0F)));
1118 aml_append(dev
, method
);
1120 crs
= aml_resource_template();
1121 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1122 aml_append(dev
, aml_name_decl("_CRS", crs
));
1124 aml_append(scope
, dev
);
1125 aml_append(table
, scope
);
1128 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1131 uint8_t maxc
, maxh
, maxs
;
1133 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1135 dev
= aml_device("FLP%c", 'A' + idx
);
1137 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1139 fdi
= aml_package(16);
1140 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1142 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1144 * the values below are the limits of the drive, and are thus independent
1145 * of the inserted media
1147 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1148 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1149 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1151 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1152 * the drive type, so shall we
1154 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1155 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1156 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1157 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1158 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1159 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1160 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1161 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1162 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1163 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1164 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1166 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1170 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1176 #define ACPI_FDE_MAX_FD 4
1177 uint32_t fde_buf
[5] = {
1178 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1179 cpu_to_le32(2) /* tape presence (2 == never present) */
1182 dev
= aml_device("FDC0");
1183 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1185 crs
= aml_resource_template();
1186 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1187 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1188 aml_append(crs
, aml_irq_no_flags(6));
1190 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1191 aml_append(dev
, aml_name_decl("_CRS", crs
));
1193 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1194 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1196 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1197 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1198 aml_append(dev
, build_fdinfo_aml(i
, type
));
1201 aml_append(dev
, aml_name_decl("_FDE",
1202 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1207 static Aml
*build_rtc_device_aml(void)
1212 dev
= aml_device("RTC");
1213 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1214 crs
= aml_resource_template();
1215 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1216 aml_append(crs
, aml_irq_no_flags(8));
1217 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1218 aml_append(dev
, aml_name_decl("_CRS", crs
));
1223 static Aml
*build_kbd_device_aml(void)
1229 dev
= aml_device("KBD");
1230 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1232 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1233 aml_append(method
, aml_return(aml_int(0x0f)));
1234 aml_append(dev
, method
);
1236 crs
= aml_resource_template();
1237 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1238 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1239 aml_append(crs
, aml_irq_no_flags(1));
1240 aml_append(dev
, aml_name_decl("_CRS", crs
));
1245 static Aml
*build_mouse_device_aml(void)
1251 dev
= aml_device("MOU");
1252 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1254 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1255 aml_append(method
, aml_return(aml_int(0x0f)));
1256 aml_append(dev
, method
);
1258 crs
= aml_resource_template();
1259 aml_append(crs
, aml_irq_no_flags(12));
1260 aml_append(dev
, aml_name_decl("_CRS", crs
));
1265 static Aml
*build_lpt_device_aml(void)
1272 Aml
*zero
= aml_int(0);
1273 Aml
*is_present
= aml_local(0);
1275 dev
= aml_device("LPT");
1276 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1278 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1279 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1280 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1282 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1284 aml_append(method
, if_ctx
);
1285 else_ctx
= aml_else();
1287 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1289 aml_append(method
, else_ctx
);
1290 aml_append(dev
, method
);
1292 crs
= aml_resource_template();
1293 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1294 aml_append(crs
, aml_irq_no_flags(7));
1295 aml_append(dev
, aml_name_decl("_CRS", crs
));
1300 static Aml
*build_com_device_aml(uint8_t uid
)
1307 Aml
*zero
= aml_int(0);
1308 Aml
*is_present
= aml_local(0);
1309 const char *enabled_field
= "CAEN";
1311 uint16_t io_port
= 0x03F8;
1313 assert(uid
== 1 || uid
== 2);
1315 enabled_field
= "CBEN";
1320 dev
= aml_device("COM%d", uid
);
1321 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1322 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1324 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1325 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1326 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1328 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1330 aml_append(method
, if_ctx
);
1331 else_ctx
= aml_else();
1333 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1335 aml_append(method
, else_ctx
);
1336 aml_append(dev
, method
);
1338 crs
= aml_resource_template();
1339 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1340 aml_append(crs
, aml_irq_no_flags(irq
));
1341 aml_append(dev
, aml_name_decl("_CRS", crs
));
1346 static void build_isa_devices_aml(Aml
*table
)
1348 ISADevice
*fdc
= pc_find_fdc0();
1351 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1352 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1354 aml_append(scope
, build_rtc_device_aml());
1355 aml_append(scope
, build_kbd_device_aml());
1356 aml_append(scope
, build_mouse_device_aml());
1358 aml_append(scope
, build_fdc_device_aml(fdc
));
1360 aml_append(scope
, build_lpt_device_aml());
1361 aml_append(scope
, build_com_device_aml(1));
1362 aml_append(scope
, build_com_device_aml(2));
1365 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1367 error_report("No ISA bus, unable to define IPMI ACPI data");
1369 build_acpi_ipmi_devices(scope
, BUS(obj
));
1372 aml_append(table
, scope
);
1375 static void build_dbg_aml(Aml
*table
)
1380 Aml
*scope
= aml_scope("\\");
1381 Aml
*buf
= aml_local(0);
1382 Aml
*len
= aml_local(1);
1383 Aml
*idx
= aml_local(2);
1386 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1387 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1388 aml_append(field
, aml_named_field("DBGB", 8));
1389 aml_append(scope
, field
);
1391 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1393 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1394 aml_append(method
, aml_to_buffer(buf
, buf
));
1395 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1396 aml_append(method
, aml_store(aml_int(0), idx
));
1398 while_ctx
= aml_while(aml_lless(idx
, len
));
1399 aml_append(while_ctx
,
1400 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1401 aml_append(while_ctx
, aml_increment(idx
));
1402 aml_append(method
, while_ctx
);
1404 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1405 aml_append(scope
, method
);
1407 aml_append(table
, scope
);
1410 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1415 uint32_t irqs
[] = {5, 10, 11};
1417 dev
= aml_device("%s", name
);
1418 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1419 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1421 crs
= aml_resource_template();
1422 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1423 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1424 aml_append(dev
, aml_name_decl("_PRS", crs
));
1426 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1427 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1428 aml_append(dev
, method
);
1430 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1431 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1432 aml_append(dev
, method
);
1434 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1435 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1436 aml_append(dev
, method
);
1438 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1439 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1440 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1441 aml_append(dev
, method
);
1446 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1453 dev
= aml_device("%s", name
);
1454 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1455 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1457 crs
= aml_resource_template();
1459 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1460 AML_SHARED
, &irqs
, 1));
1461 aml_append(dev
, aml_name_decl("_PRS", crs
));
1463 aml_append(dev
, aml_name_decl("_CRS", crs
));
1466 * _DIS can be no-op because the interrupt cannot be disabled.
1468 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1469 aml_append(dev
, method
);
1471 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1472 aml_append(dev
, method
);
1477 /* _CRS method - get current settings */
1478 static Aml
*build_iqcr_method(bool is_piix4
)
1482 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1483 Aml
*crs
= aml_resource_template();
1486 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1487 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1488 aml_append(method
, aml_name_decl("PRR0", crs
));
1491 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1494 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1495 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1496 aml_append(method
, if_ctx
);
1499 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1503 aml_append(method
, aml_return(aml_name("PRR0")));
1507 /* _STA method - get status */
1508 static Aml
*build_irq_status_method(void)
1511 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1513 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1514 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1515 aml_append(method
, if_ctx
);
1516 aml_append(method
, aml_return(aml_int(0x0B)));
1520 static void build_piix4_pci0_int(Aml
*table
)
1527 Aml
*sb_scope
= aml_scope("_SB");
1528 Aml
*pci0_scope
= aml_scope("PCI0");
1530 aml_append(pci0_scope
, build_prt(true));
1531 aml_append(sb_scope
, pci0_scope
);
1533 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1534 aml_append(field
, aml_named_field("PRQ0", 8));
1535 aml_append(field
, aml_named_field("PRQ1", 8));
1536 aml_append(field
, aml_named_field("PRQ2", 8));
1537 aml_append(field
, aml_named_field("PRQ3", 8));
1538 aml_append(sb_scope
, field
);
1540 aml_append(sb_scope
, build_irq_status_method());
1541 aml_append(sb_scope
, build_iqcr_method(true));
1543 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1544 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1545 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1546 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1548 dev
= aml_device("LNKS");
1550 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1551 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1553 crs
= aml_resource_template();
1555 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1556 AML_ACTIVE_HIGH
, AML_SHARED
,
1558 aml_append(dev
, aml_name_decl("_PRS", crs
));
1560 /* The SCI cannot be disabled and is always attached to GSI 9,
1561 * so these are no-ops. We only need this link to override the
1562 * polarity to active high and match the content of the MADT.
1564 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1565 aml_append(method
, aml_return(aml_int(0x0b)));
1566 aml_append(dev
, method
);
1568 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1569 aml_append(dev
, method
);
1571 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1572 aml_append(method
, aml_return(aml_name("_PRS")));
1573 aml_append(dev
, method
);
1575 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1576 aml_append(dev
, method
);
1578 aml_append(sb_scope
, dev
);
1580 aml_append(table
, sb_scope
);
1583 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1588 char base
= name
[3] < 'E' ? 'A' : 'E';
1589 char *s
= g_strdup(name
);
1590 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1592 assert(strlen(s
) == 4);
1594 head
= name
[3] - base
;
1595 for (i
= 0; i
< 4; i
++) {
1599 s
[3] = base
+ head
+ i
;
1600 pkg
= aml_package(4);
1601 aml_append(pkg
, a_nr
);
1602 aml_append(pkg
, aml_int(i
));
1603 aml_append(pkg
, aml_name("%s", s
));
1604 aml_append(pkg
, aml_int(0));
1605 aml_append(ctx
, pkg
);
1610 static Aml
*build_q35_routing_table(const char *str
)
1614 char *name
= g_strdup_printf("%s ", str
);
1616 pkg
= aml_package(128);
1617 for (i
= 0; i
< 0x18; i
++) {
1618 name
[3] = 'E' + (i
& 0x3);
1619 append_q35_prt_entry(pkg
, i
, name
);
1623 append_q35_prt_entry(pkg
, 0x18, name
);
1625 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1626 for (i
= 0x0019; i
< 0x1e; i
++) {
1628 append_q35_prt_entry(pkg
, i
, name
);
1631 /* PCIe->PCI bridge. use PIRQ[E-H] */
1633 append_q35_prt_entry(pkg
, 0x1e, name
);
1635 append_q35_prt_entry(pkg
, 0x1f, name
);
1641 static void build_q35_pci0_int(Aml
*table
)
1645 Aml
*sb_scope
= aml_scope("_SB");
1646 Aml
*pci0_scope
= aml_scope("PCI0");
1648 /* Zero => PIC mode, One => APIC Mode */
1649 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1650 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1652 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1654 aml_append(table
, method
);
1656 aml_append(pci0_scope
,
1657 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1658 aml_append(pci0_scope
,
1659 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1661 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1666 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1668 /* Note: we provide the same info as the PCI routing
1669 table of the Bochs BIOS */
1670 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1671 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1672 aml_append(method
, if_ctx
);
1673 else_ctx
= aml_else();
1674 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1675 aml_append(method
, else_ctx
);
1677 aml_append(pci0_scope
, method
);
1678 aml_append(sb_scope
, pci0_scope
);
1680 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1681 aml_append(field
, aml_named_field("PRQA", 8));
1682 aml_append(field
, aml_named_field("PRQB", 8));
1683 aml_append(field
, aml_named_field("PRQC", 8));
1684 aml_append(field
, aml_named_field("PRQD", 8));
1685 aml_append(field
, aml_reserved_field(0x20));
1686 aml_append(field
, aml_named_field("PRQE", 8));
1687 aml_append(field
, aml_named_field("PRQF", 8));
1688 aml_append(field
, aml_named_field("PRQG", 8));
1689 aml_append(field
, aml_named_field("PRQH", 8));
1690 aml_append(sb_scope
, field
);
1692 aml_append(sb_scope
, build_irq_status_method());
1693 aml_append(sb_scope
, build_iqcr_method(false));
1695 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1696 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1697 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1698 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1699 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1700 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1701 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1702 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1704 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1705 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1706 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1707 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1708 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1709 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1710 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1711 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1713 aml_append(table
, sb_scope
);
1716 static void build_q35_isa_bridge(Aml
*table
)
1722 scope
= aml_scope("_SB.PCI0");
1723 dev
= aml_device("ISA");
1724 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1726 /* ICH9 PCI to ISA irq remapping */
1727 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1728 aml_int(0x60), 0x0C));
1730 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1731 aml_int(0x80), 0x02));
1732 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1733 aml_append(field
, aml_named_field("COMA", 3));
1734 aml_append(field
, aml_reserved_field(1));
1735 aml_append(field
, aml_named_field("COMB", 3));
1736 aml_append(field
, aml_reserved_field(1));
1737 aml_append(field
, aml_named_field("LPTD", 2));
1738 aml_append(dev
, field
);
1740 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1741 aml_int(0x82), 0x02));
1743 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1744 aml_append(field
, aml_named_field("CAEN", 1));
1745 aml_append(field
, aml_named_field("CBEN", 1));
1746 aml_append(field
, aml_named_field("LPEN", 1));
1747 aml_append(dev
, field
);
1749 aml_append(scope
, dev
);
1750 aml_append(table
, scope
);
1753 static void build_piix4_pm(Aml
*table
)
1758 scope
= aml_scope("_SB.PCI0");
1759 dev
= aml_device("PX13");
1760 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1762 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1763 aml_int(0x00), 0xff));
1764 aml_append(scope
, dev
);
1765 aml_append(table
, scope
);
1768 static void build_piix4_isa_bridge(Aml
*table
)
1774 scope
= aml_scope("_SB.PCI0");
1775 dev
= aml_device("ISA");
1776 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1778 /* PIIX PCI to ISA irq remapping */
1779 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1780 aml_int(0x60), 0x04));
1782 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1783 /* Offset(0x5f),, 7, */
1784 aml_append(field
, aml_reserved_field(0x2f8));
1785 aml_append(field
, aml_reserved_field(7));
1786 aml_append(field
, aml_named_field("LPEN", 1));
1787 /* Offset(0x67),, 3, */
1788 aml_append(field
, aml_reserved_field(0x38));
1789 aml_append(field
, aml_reserved_field(3));
1790 aml_append(field
, aml_named_field("CAEN", 1));
1791 aml_append(field
, aml_reserved_field(3));
1792 aml_append(field
, aml_named_field("CBEN", 1));
1793 aml_append(dev
, field
);
1795 aml_append(scope
, dev
);
1796 aml_append(table
, scope
);
1799 static void build_piix4_pci_hotplug(Aml
*table
)
1805 scope
= aml_scope("_SB.PCI0");
1808 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1809 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1810 aml_append(field
, aml_named_field("PCIU", 32));
1811 aml_append(field
, aml_named_field("PCID", 32));
1812 aml_append(scope
, field
);
1815 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1816 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1817 aml_append(field
, aml_named_field("B0EJ", 32));
1818 aml_append(scope
, field
);
1821 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1822 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1823 aml_append(field
, aml_named_field("BNUM", 32));
1824 aml_append(scope
, field
);
1826 aml_append(scope
, aml_mutex("BLCK", 0));
1828 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1829 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1830 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1832 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1833 aml_append(method
, aml_release(aml_name("BLCK")));
1834 aml_append(method
, aml_return(aml_int(0)));
1835 aml_append(scope
, method
);
1837 aml_append(table
, scope
);
1840 static Aml
*build_q35_osc_method(void)
1846 Aml
*a_cwd1
= aml_name("CDW1");
1847 Aml
*a_ctrl
= aml_name("CTRL");
1849 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1850 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1852 if_ctx
= aml_if(aml_equal(
1853 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1854 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1855 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1857 aml_append(if_ctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1858 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1861 * Always allow native PME, AER (no dependencies)
1862 * Never allow SHPC (no SHPC controller in this system)
1864 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1866 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1867 /* Unknown revision */
1868 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1869 aml_append(if_ctx
, if_ctx2
);
1871 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1872 /* Capabilities bits were masked */
1873 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1874 aml_append(if_ctx
, if_ctx2
);
1876 /* Update DWORD3 in the buffer */
1877 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1878 aml_append(method
, if_ctx
);
1880 else_ctx
= aml_else();
1881 /* Unrecognized UUID */
1882 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1883 aml_append(method
, else_ctx
);
1885 aml_append(method
, aml_return(aml_arg(3)));
1890 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1891 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1892 PcPciInfo
*pci
, MachineState
*machine
)
1894 CrsRangeEntry
*entry
;
1895 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1896 GPtrArray
*mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
1897 GPtrArray
*io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
1898 PCMachineState
*pcms
= PC_MACHINE(machine
);
1899 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1900 uint32_t nr_mem
= machine
->ram_slots
;
1901 int root_bus_limit
= 0xFF;
1905 dsdt
= init_aml_allocator();
1907 /* Reserve space for header */
1908 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1910 build_dbg_aml(dsdt
);
1911 if (misc
->is_piix4
) {
1912 sb_scope
= aml_scope("_SB");
1913 dev
= aml_device("PCI0");
1914 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1915 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1916 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1917 aml_append(sb_scope
, dev
);
1918 aml_append(dsdt
, sb_scope
);
1920 build_hpet_aml(dsdt
);
1921 build_piix4_pm(dsdt
);
1922 build_piix4_isa_bridge(dsdt
);
1923 build_isa_devices_aml(dsdt
);
1924 build_piix4_pci_hotplug(dsdt
);
1925 build_piix4_pci0_int(dsdt
);
1927 sb_scope
= aml_scope("_SB");
1928 aml_append(sb_scope
,
1929 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
1930 aml_append(sb_scope
,
1931 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
1932 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1933 aml_append(field
, aml_named_field("PCIB", 8));
1934 aml_append(sb_scope
, field
);
1935 aml_append(dsdt
, sb_scope
);
1937 sb_scope
= aml_scope("_SB");
1938 dev
= aml_device("PCI0");
1939 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1940 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1941 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1942 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1943 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
1944 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
1945 aml_append(dev
, build_q35_osc_method());
1946 aml_append(sb_scope
, dev
);
1947 aml_append(dsdt
, sb_scope
);
1949 build_hpet_aml(dsdt
);
1950 build_q35_isa_bridge(dsdt
);
1951 build_isa_devices_aml(dsdt
);
1952 build_q35_pci0_int(dsdt
);
1955 if (pcmc
->legacy_cpu_hotplug
) {
1956 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1958 CPUHotplugFeatures opts
= {
1959 .apci_1_compatible
= true, .has_legacy_cphp
= true
1961 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1962 "\\_SB.PCI0", "\\_GPE._E02");
1964 build_memory_hotplug_aml(dsdt
, nr_mem
, pm
->mem_hp_io_base
,
1967 scope
= aml_scope("_GPE");
1969 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1971 if (misc
->is_piix4
) {
1972 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1974 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1975 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1976 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1977 aml_append(scope
, method
);
1980 method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
1981 aml_append(method
, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH
));
1982 aml_append(scope
, method
);
1984 aml_append(dsdt
, scope
);
1986 bus
= PC_MACHINE(machine
)->bus
;
1988 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1989 uint8_t bus_num
= pci_bus_num(bus
);
1990 uint8_t numa_node
= pci_bus_numa_node(bus
);
1992 /* look only for expander root buses */
1993 if (!pci_bus_is_root(bus
)) {
1997 if (bus_num
< root_bus_limit
) {
1998 root_bus_limit
= bus_num
- 1;
2001 scope
= aml_scope("\\_SB");
2002 dev
= aml_device("PC%.02X", bus_num
);
2003 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
2004 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2005 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
2007 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
2008 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
2011 aml_append(dev
, build_prt(false));
2012 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
),
2013 io_ranges
, mem_ranges
);
2014 aml_append(dev
, aml_name_decl("_CRS", crs
));
2015 aml_append(scope
, dev
);
2016 aml_append(dsdt
, scope
);
2020 scope
= aml_scope("\\_SB.PCI0");
2021 /* build PCI0._CRS */
2022 crs
= aml_resource_template();
2024 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
2025 0x0000, 0x0, root_bus_limit
,
2026 0x0000, root_bus_limit
+ 1));
2027 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
2030 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2031 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2032 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2034 crs_replace_with_free_ranges(io_ranges
, 0x0D00, 0xFFFF);
2035 for (i
= 0; i
< io_ranges
->len
; i
++) {
2036 entry
= g_ptr_array_index(io_ranges
, i
);
2038 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2039 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2040 0x0000, entry
->base
, entry
->limit
,
2041 0x0000, entry
->limit
- entry
->base
+ 1));
2045 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2046 AML_CACHEABLE
, AML_READ_WRITE
,
2047 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2049 crs_replace_with_free_ranges(mem_ranges
, pci
->w32
.begin
, pci
->w32
.end
- 1);
2050 for (i
= 0; i
< mem_ranges
->len
; i
++) {
2051 entry
= g_ptr_array_index(mem_ranges
, i
);
2053 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2054 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2055 0, entry
->base
, entry
->limit
,
2056 0, entry
->limit
- entry
->base
+ 1));
2059 if (pci
->w64
.begin
) {
2061 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2062 AML_CACHEABLE
, AML_READ_WRITE
,
2063 0, pci
->w64
.begin
, pci
->w64
.end
- 1, 0,
2064 pci
->w64
.end
- pci
->w64
.begin
));
2067 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2068 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2069 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2071 aml_append(scope
, aml_name_decl("_CRS", crs
));
2073 /* reserve GPE0 block resources */
2074 dev
= aml_device("GPE0");
2075 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2076 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2077 /* device present, functioning, decoding, not shown in UI */
2078 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2079 crs
= aml_resource_template();
2081 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2083 aml_append(dev
, aml_name_decl("_CRS", crs
));
2084 aml_append(scope
, dev
);
2086 g_ptr_array_free(io_ranges
, true);
2087 g_ptr_array_free(mem_ranges
, true);
2089 /* reserve PCIHP resources */
2090 if (pm
->pcihp_io_len
) {
2091 dev
= aml_device("PHPR");
2092 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2094 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2095 /* device present, functioning, decoding, not shown in UI */
2096 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2097 crs
= aml_resource_template();
2099 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2102 aml_append(dev
, aml_name_decl("_CRS", crs
));
2103 aml_append(scope
, dev
);
2105 aml_append(dsdt
, scope
);
2107 /* create S3_ / S4_ / S5_ packages if necessary */
2108 scope
= aml_scope("\\");
2109 if (!pm
->s3_disabled
) {
2110 pkg
= aml_package(4);
2111 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2112 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2113 aml_append(pkg
, aml_int(0)); /* reserved */
2114 aml_append(pkg
, aml_int(0)); /* reserved */
2115 aml_append(scope
, aml_name_decl("_S3", pkg
));
2118 if (!pm
->s4_disabled
) {
2119 pkg
= aml_package(4);
2120 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2121 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2122 aml_append(pkg
, aml_int(pm
->s4_val
));
2123 aml_append(pkg
, aml_int(0)); /* reserved */
2124 aml_append(pkg
, aml_int(0)); /* reserved */
2125 aml_append(scope
, aml_name_decl("_S4", pkg
));
2128 pkg
= aml_package(4);
2129 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2130 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2131 aml_append(pkg
, aml_int(0)); /* reserved */
2132 aml_append(pkg
, aml_int(0)); /* reserved */
2133 aml_append(scope
, aml_name_decl("_S5", pkg
));
2134 aml_append(dsdt
, scope
);
2136 /* create fw_cfg node, unconditionally */
2138 /* when using port i/o, the 8-bit data register *always* overlaps
2139 * with half of the 16-bit control register. Hence, the total size
2140 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2141 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2142 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2143 "dma_enabled", NULL
) ?
2144 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2147 scope
= aml_scope("\\_SB.PCI0");
2148 dev
= aml_device("FWCF");
2150 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2152 /* device present, functioning, decoding, not shown in UI */
2153 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2155 crs
= aml_resource_template();
2157 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2159 aml_append(dev
, aml_name_decl("_CRS", crs
));
2161 aml_append(scope
, dev
);
2162 aml_append(dsdt
, scope
);
2165 if (misc
->applesmc_io_base
) {
2166 scope
= aml_scope("\\_SB.PCI0.ISA");
2167 dev
= aml_device("SMC");
2169 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2170 /* device present, functioning, decoding, not shown in UI */
2171 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2173 crs
= aml_resource_template();
2175 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2176 0x01, APPLESMC_MAX_DATA_LENGTH
)
2178 aml_append(crs
, aml_irq_no_flags(6));
2179 aml_append(dev
, aml_name_decl("_CRS", crs
));
2181 aml_append(scope
, dev
);
2182 aml_append(dsdt
, scope
);
2185 if (misc
->pvpanic_port
) {
2186 scope
= aml_scope("\\_SB.PCI0.ISA");
2188 dev
= aml_device("PEVT");
2189 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2191 crs
= aml_resource_template();
2193 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2195 aml_append(dev
, aml_name_decl("_CRS", crs
));
2197 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2198 aml_int(misc
->pvpanic_port
), 1));
2199 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2200 aml_append(field
, aml_named_field("PEPT", 8));
2201 aml_append(dev
, field
);
2203 /* device present, functioning, decoding, shown in UI */
2204 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2206 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2207 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2208 aml_append(method
, aml_return(aml_local(0)));
2209 aml_append(dev
, method
);
2211 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2212 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2213 aml_append(dev
, method
);
2215 aml_append(scope
, dev
);
2216 aml_append(dsdt
, scope
);
2219 sb_scope
= aml_scope("\\_SB");
2221 build_memory_devices(sb_scope
, nr_mem
, pm
->mem_hp_io_base
,
2228 pci_host
= acpi_get_i386_pci_host();
2230 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2234 Aml
*scope
= aml_scope("PCI0");
2235 /* Scan all PCI buses. Generate tables to support hotplug. */
2236 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2238 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2239 dev
= aml_device("ISA.TPM");
2240 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2241 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2242 crs
= aml_resource_template();
2243 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2244 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2246 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2247 Rewrite to take IRQ from TPM device model and
2248 fix default IRQ value there to use some unused IRQ
2250 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2251 aml_append(dev
, aml_name_decl("_CRS", crs
));
2252 aml_append(scope
, dev
);
2255 aml_append(sb_scope
, scope
);
2258 aml_append(dsdt
, sb_scope
);
2261 /* copy AML table into ACPI tables blob and patch header there */
2262 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2263 build_header(linker
, table_data
,
2264 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2265 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2266 free_aml_allocator();
2270 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2274 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2275 /* Note timer_block_id value must be kept in sync with value advertised by
2278 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2279 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2280 build_header(linker
, table_data
,
2281 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2285 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2287 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2288 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2289 unsigned log_addr_offset
=
2290 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2292 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2293 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2294 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2296 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2297 false /* high memory */);
2299 /* log area start address to be filled by Guest linker */
2300 bios_linker_loader_add_pointer(linker
,
2301 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2302 ACPI_BUILD_TPMLOG_FILE
, 0);
2304 build_header(linker
, table_data
,
2305 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2309 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
)
2311 Acpi20TPM2
*tpm2_ptr
;
2313 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2315 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2316 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2317 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2319 build_header(linker
, table_data
,
2320 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2324 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2326 AcpiSystemResourceAffinityTable
*srat
;
2327 AcpiSratProcessorAffinity
*core
;
2328 AcpiSratMemoryAffinity
*numamem
;
2332 int srat_start
, numa_start
, slots
;
2333 uint64_t mem_len
, mem_base
, next_base
;
2334 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2335 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2336 PCMachineState
*pcms
= PC_MACHINE(machine
);
2337 ram_addr_t hotplugabble_address_space_size
=
2338 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2341 srat_start
= table_data
->len
;
2343 srat
= acpi_data_push(table_data
, sizeof *srat
);
2344 srat
->reserved1
= cpu_to_le32(1);
2346 for (i
= 0; i
< apic_ids
->len
; i
++) {
2347 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
2349 core
= acpi_data_push(table_data
, sizeof *core
);
2350 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2351 core
->length
= sizeof(*core
);
2352 core
->local_apic_id
= apic_id
;
2353 curnode
= pcms
->node_cpu
[apic_id
];
2354 core
->proximity_lo
= curnode
;
2355 memset(core
->proximity_hi
, 0, 3);
2356 core
->local_sapic_eid
= 0;
2357 core
->flags
= cpu_to_le32(1);
2361 /* the memory map is a bit tricky, it contains at least one hole
2362 * from 640k-1M and possibly another one from 3.5G-4G.
2365 numa_start
= table_data
->len
;
2367 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2368 build_srat_memory(numamem
, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED
);
2369 next_base
= 1024 * 1024;
2370 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2371 mem_base
= next_base
;
2372 mem_len
= pcms
->node_mem
[i
- 1];
2374 mem_len
-= 1024 * 1024;
2376 next_base
= mem_base
+ mem_len
;
2378 /* Cut out the ACPI_PCI hole */
2379 if (mem_base
<= pcms
->below_4g_mem_size
&&
2380 next_base
> pcms
->below_4g_mem_size
) {
2381 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2383 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2384 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2385 MEM_AFFINITY_ENABLED
);
2387 mem_base
= 1ULL << 32;
2388 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2389 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2391 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2392 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2393 MEM_AFFINITY_ENABLED
);
2395 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2396 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2397 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2398 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2402 * Entry is required for Windows to enable memory hotplug in OS.
2403 * Memory devices may override proximity set by this entry,
2404 * providing _PXM method if necessary.
2406 if (hotplugabble_address_space_size
) {
2407 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2408 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2409 hotplugabble_address_space_size
, 0,
2410 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2413 build_header(linker
, table_data
,
2414 (void *)(table_data
->data
+ srat_start
),
2416 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2421 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2423 AcpiTableMcfg
*mcfg
;
2425 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2427 mcfg
= acpi_data_push(table_data
, len
);
2428 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2429 /* Only a single allocation so no need to play with segments */
2430 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2431 mcfg
->allocation
[0].start_bus_number
= 0;
2432 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2434 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2435 * To avoid table size changes (which create migration issues),
2436 * always create the table even if there are no allocations,
2437 * but set the signature to a reserved value in this case.
2438 * ACPI spec requires OSPMs to ignore such tables.
2440 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2441 /* Reserved signature: ignored by OSPM */
2446 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2450 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2452 int dmar_start
= table_data
->len
;
2454 AcpiTableDmar
*dmar
;
2455 AcpiDmarHardwareUnit
*drhd
;
2457 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2458 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2459 dmar
->flags
= 0; /* No intr_remap for now */
2461 /* DMAR Remapping Hardware Unit Definition structure */
2462 drhd
= acpi_data_push(table_data
, sizeof(*drhd
));
2463 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2464 drhd
->length
= cpu_to_le16(sizeof(*drhd
)); /* No device scope now */
2465 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2466 drhd
->pci_segment
= cpu_to_le16(0);
2467 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2469 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2470 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2474 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2476 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2477 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2478 unsigned rsdt_pa_offset
=
2479 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2481 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2482 true /* fseg memory */);
2484 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2485 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2486 /* Address to be filled by Guest linker */
2487 bios_linker_loader_add_pointer(linker
,
2488 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2489 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2491 /* Checksum to be filled by Guest linker */
2492 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2493 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2494 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2500 struct AcpiBuildState
{
2501 /* Copy of table in RAM (for patching). */
2502 MemoryRegion
*table_mr
;
2503 /* Is table patched? */
2506 MemoryRegion
*rsdp_mr
;
2507 MemoryRegion
*linker_mr
;
2510 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2515 pci_host
= acpi_get_i386_pci_host();
2518 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2522 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2525 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2527 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2532 static bool acpi_has_iommu(void)
2535 Object
*intel_iommu
;
2537 intel_iommu
= object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE
,
2539 return intel_iommu
&& !ambiguous
;
2543 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2545 PCMachineState
*pcms
= PC_MACHINE(machine
);
2546 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2547 GArray
*table_offsets
;
2548 unsigned facs
, dsdt
, rsdt
, fadt
;
2555 GArray
*tables_blob
= tables
->table_data
;
2556 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2558 acpi_get_pm_info(&pm
);
2559 acpi_get_misc_info(&misc
);
2560 acpi_get_pci_info(&pci
);
2561 acpi_get_slic_oem(&slic_oem
);
2563 table_offsets
= g_array_new(false, true /* clear */,
2565 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2567 bios_linker_loader_alloc(tables
->linker
,
2568 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2569 64 /* Ensure FACS is aligned */,
2570 false /* high memory */);
2573 * FACS is pointed to by FADT.
2574 * We place it first since it's the only table that has alignment
2577 facs
= tables_blob
->len
;
2578 build_facs(tables_blob
, tables
->linker
);
2580 /* DSDT is pointed to by FADT */
2581 dsdt
= tables_blob
->len
;
2582 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
, &pci
, machine
);
2584 /* Count the size of the DSDT and SSDT, we will need it for legacy
2585 * sizing of ACPI tables.
2587 aml_len
+= tables_blob
->len
- dsdt
;
2589 /* ACPI tables pointed to by RSDT */
2590 fadt
= tables_blob
->len
;
2591 acpi_add_table(table_offsets
, tables_blob
);
2592 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2593 slic_oem
.id
, slic_oem
.table_id
);
2594 aml_len
+= tables_blob
->len
- fadt
;
2596 acpi_add_table(table_offsets
, tables_blob
);
2597 build_madt(tables_blob
, tables
->linker
, pcms
);
2599 if (misc
.has_hpet
) {
2600 acpi_add_table(table_offsets
, tables_blob
);
2601 build_hpet(tables_blob
, tables
->linker
);
2603 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2604 acpi_add_table(table_offsets
, tables_blob
);
2605 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2607 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2608 acpi_add_table(table_offsets
, tables_blob
);
2609 build_tpm2(tables_blob
, tables
->linker
);
2612 if (pcms
->numa_nodes
) {
2613 acpi_add_table(table_offsets
, tables_blob
);
2614 build_srat(tables_blob
, tables
->linker
, machine
);
2616 if (acpi_get_mcfg(&mcfg
)) {
2617 acpi_add_table(table_offsets
, tables_blob
);
2618 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2620 if (acpi_has_iommu()) {
2621 acpi_add_table(table_offsets
, tables_blob
);
2622 build_dmar_q35(tables_blob
, tables
->linker
);
2624 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2625 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2626 pcms
->acpi_nvdimm_state
.dsm_mem
);
2629 /* Add tables supplied by user (if any) */
2630 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2631 unsigned len
= acpi_table_len(u
);
2633 acpi_add_table(table_offsets
, tables_blob
);
2634 g_array_append_vals(tables_blob
, u
, len
);
2637 /* RSDT is pointed to by RSDP */
2638 rsdt
= tables_blob
->len
;
2639 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2640 slic_oem
.id
, slic_oem
.table_id
);
2642 /* RSDP is in FSEG memory, so allocate it separately */
2643 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2645 /* We'll expose it all to Guest so we want to reduce
2646 * chance of size changes.
2648 * We used to align the tables to 4k, but of course this would
2649 * too simple to be enough. 4k turned out to be too small an
2650 * alignment very soon, and in fact it is almost impossible to
2651 * keep the table size stable for all (max_cpus, max_memory_slots)
2652 * combinations. So the table size is always 64k for pc-i440fx-2.1
2653 * and we give an error if the table grows beyond that limit.
2655 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2656 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2657 * than 2.0 and we can always pad the smaller tables with zeros. We can
2658 * then use the exact size of the 2.0 tables.
2660 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2662 if (pcmc
->legacy_acpi_table_size
) {
2663 /* Subtracting aml_len gives the size of fixed tables. Then add the
2664 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2666 int legacy_aml_len
=
2667 pcmc
->legacy_acpi_table_size
+
2668 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
2669 int legacy_table_size
=
2670 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2671 ACPI_BUILD_ALIGN_SIZE
);
2672 if (tables_blob
->len
> legacy_table_size
) {
2673 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2674 error_report("Warning: migration may not work.");
2676 g_array_set_size(tables_blob
, legacy_table_size
);
2678 /* Make sure we have a buffer in case we need to resize the tables. */
2679 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2680 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2681 error_report("Warning: ACPI tables are larger than 64k.");
2682 error_report("Warning: migration may not work.");
2683 error_report("Warning: please remove CPUs, NUMA nodes, "
2684 "memory slots or PCI bridges.");
2686 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2689 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2691 /* Cleanup memory that's no longer used. */
2692 g_array_free(table_offsets
, true);
2695 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2697 uint32_t size
= acpi_data_len(data
);
2699 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2700 memory_region_ram_resize(mr
, size
, &error_abort
);
2702 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2703 memory_region_set_dirty(mr
, 0, size
);
2706 static void acpi_build_update(void *build_opaque
)
2708 AcpiBuildState
*build_state
= build_opaque
;
2709 AcpiBuildTables tables
;
2711 /* No state to update or already patched? Nothing to do. */
2712 if (!build_state
|| build_state
->patched
) {
2715 build_state
->patched
= 1;
2717 acpi_build_tables_init(&tables
);
2719 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2721 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2723 if (build_state
->rsdp
) {
2724 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2726 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2729 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2730 acpi_build_tables_cleanup(&tables
, true);
2733 static void acpi_build_reset(void *build_opaque
)
2735 AcpiBuildState
*build_state
= build_opaque
;
2736 build_state
->patched
= 0;
2739 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2740 GArray
*blob
, const char *name
,
2743 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2744 name
, acpi_build_update
, build_state
);
2747 static const VMStateDescription vmstate_acpi_build
= {
2748 .name
= "acpi_build",
2750 .minimum_version_id
= 1,
2751 .fields
= (VMStateField
[]) {
2752 VMSTATE_UINT8(patched
, AcpiBuildState
),
2753 VMSTATE_END_OF_LIST()
2757 void acpi_setup(void)
2759 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2760 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2761 AcpiBuildTables tables
;
2762 AcpiBuildState
*build_state
;
2764 if (!pcms
->fw_cfg
) {
2765 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2769 if (!pcmc
->has_acpi_build
) {
2770 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2774 if (!acpi_enabled
) {
2775 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2779 build_state
= g_malloc0(sizeof *build_state
);
2781 acpi_set_pci_info();
2783 acpi_build_tables_init(&tables
);
2784 acpi_build(&tables
, MACHINE(pcms
));
2786 /* Now expose it all to Guest */
2787 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2788 ACPI_BUILD_TABLE_FILE
,
2789 ACPI_BUILD_TABLE_MAX_SIZE
);
2790 assert(build_state
->table_mr
!= NULL
);
2792 build_state
->linker_mr
=
2793 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2794 "etc/table-loader", 0);
2796 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2797 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2799 if (!pcmc
->rsdp_in_ram
) {
2801 * Keep for compatibility with old machine types.
2802 * Though RSDP is small, its contents isn't immutable, so
2803 * we'll update it along with the rest of tables on guest access.
2805 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2807 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2808 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2809 acpi_build_update
, build_state
,
2810 build_state
->rsdp
, rsdp_size
);
2811 build_state
->rsdp_mr
= NULL
;
2813 build_state
->rsdp
= NULL
;
2814 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2815 ACPI_BUILD_RSDP_FILE
, 0);
2818 qemu_register_reset(acpi_build_reset
, build_state
);
2819 acpi_build_reset(build_state
);
2820 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2822 /* Cleanup tables but don't free the memory: we track it
2825 acpi_build_tables_cleanup(&tables
, false);