hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/ssi.h"
  12 #include "hw/arm/arm.h"
  13 #include "hw/devices.h"
  14 #include "qemu/timer.h"
  15 #include "hw/i2c/i2c.h"
  16 #include "net/net.h"
  17 #include "hw/boards.h"
  18 #include "exec/address-spaces.h"
  19 #include "sysemu/sysemu.h"
  20
  21 #define GPIO_A 0
  22 #define GPIO_B 1
  23 #define GPIO_C 2
  24 #define GPIO_D 3
  25 #define GPIO_E 4
  26 #define GPIO_F 5
  27 #define GPIO_G 6
  28
  29 #define BP_OLED_I2C  0x01
  30 #define BP_OLED_SSI  0x02
  31 #define BP_GAMEPAD   0x04
  32
  33 #define NUM_IRQ_LINES 64
  34
  35 typedef const struct {
  36     const char *name;
  37     uint32_t did0;
  38     uint32_t did1;
  39     uint32_t dc0;
  40     uint32_t dc1;
  41     uint32_t dc2;
  42     uint32_t dc3;
  43     uint32_t dc4;
  44     uint32_t peripherals;
  45 } stellaris_board_info;
  46
  47 /* General purpose timer module.  */
  48
  49 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  50 #define STELLARIS_GPTM(obj) \
  51     OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
  52
  53 typedef struct gptm_state {
  54     SysBusDevice parent_obj;
  55
  56     MemoryRegion iomem;
  57     uint32_t config;
  58     uint32_t mode[2];
  59     uint32_t control;
  60     uint32_t state;
  61     uint32_t mask;
  62     uint32_t load[2];
  63     uint32_t match[2];
  64     uint32_t prescale[2];
  65     uint32_t match_prescale[2];
  66     uint32_t rtc;
  67     int64_t tick[2];
  68     struct gptm_state *opaque[2];
  69     QEMUTimer *timer[2];
  70     /* The timers have an alternate output used to trigger the ADC.  */
  71     qemu_irq trigger;
  72     qemu_irq irq;
  73 } gptm_state;
  74
  75 static void gptm_update_irq(gptm_state *s)
  76 {
  77     int level;
  78     level = (s->state & s->mask) != 0;
  79     qemu_set_irq(s->irq, level);
  80 }
  81
  82 static void gptm_stop(gptm_state *s, int n)
  83 {
  84     timer_del(s->timer[n]);
  85 }
  86
  87 static void gptm_reload(gptm_state *s, int n, int reset)
  88 {
  89     int64_t tick;
  90     if (reset)
  91         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  92     else
  93         tick = s->tick[n];
  94
  95     if (s->config == 0) {
  96         /* 32-bit CountDown.  */
  97         uint32_t count;
  98         count = s->load[0] | (s->load[1] << 16);
  99         tick += (int64_t)count * system_clock_scale;
 100     } else if (s->config == 1) {
 101         /* 32-bit RTC.  1Hz tick.  */
 102         tick += get_ticks_per_sec();
 103     } else if (s->mode[n] == 0xa) {
 104         /* PWM mode.  Not implemented.  */
 105     } else {
 106         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 107     }
 108     s->tick[n] = tick;
 109     timer_mod(s->timer[n], tick);
 110 }
 111
 112 static void gptm_tick(void *opaque)
 113 {
 114     gptm_state **p = (gptm_state **)opaque;
 115     gptm_state *s;
 116     int n;
 117
 118     s = *p;
 119     n = p - s->opaque;
 120     if (s->config == 0) {
 121         s->state |= 1;
 122         if ((s->control & 0x20)) {
 123             /* Output trigger.  */
 124             qemu_irq_pulse(s->trigger);
 125         }
 126         if (s->mode[0] & 1) {
 127             /* One-shot.  */
 128             s->control &= ~1;
 129         } else {
 130             /* Periodic.  */
 131             gptm_reload(s, 0, 0);
 132         }
 133     } else if (s->config == 1) {
 134         /* RTC.  */
 135         uint32_t match;
 136         s->rtc++;
 137         match = s->match[0] | (s->match[1] << 16);
 138         if (s->rtc > match)
 139             s->rtc = 0;
 140         if (s->rtc == 0) {
 141             s->state |= 8;
 142         }
 143         gptm_reload(s, 0, 0);
 144     } else if (s->mode[n] == 0xa) {
 145         /* PWM mode.  Not implemented.  */
 146     } else {
 147         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 148     }
 149     gptm_update_irq(s);
 150 }
 151
 152 static uint64_t gptm_read(void *opaque, hwaddr offset,
 153                           unsigned size)
 154 {
 155     gptm_state *s = (gptm_state *)opaque;
 156
 157     switch (offset) {
 158     case 0x00: /* CFG */
 159         return s->config;
 160     case 0x04: /* TAMR */
 161         return s->mode[0];
 162     case 0x08: /* TBMR */
 163         return s->mode[1];
 164     case 0x0c: /* CTL */
 165         return s->control;
 166     case 0x18: /* IMR */
 167         return s->mask;
 168     case 0x1c: /* RIS */
 169         return s->state;
 170     case 0x20: /* MIS */
 171         return s->state & s->mask;
 172     case 0x24: /* CR */
 173         return 0;
 174     case 0x28: /* TAILR */
 175         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 176     case 0x2c: /* TBILR */
 177         return s->load[1];
 178     case 0x30: /* TAMARCHR */
 179         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 180     case 0x34: /* TBMATCHR */
 181         return s->match[1];
 182     case 0x38: /* TAPR */
 183         return s->prescale[0];
 184     case 0x3c: /* TBPR */
 185         return s->prescale[1];
 186     case 0x40: /* TAPMR */
 187         return s->match_prescale[0];
 188     case 0x44: /* TBPMR */
 189         return s->match_prescale[1];
 190     case 0x48: /* TAR */
 191         if (s->config == 1) {
 192             return s->rtc;
 193         }
 194         qemu_log_mask(LOG_UNIMP,
 195                       "GPTM: read of TAR but timer read not supported");
 196         return 0;
 197     case 0x4c: /* TBR */
 198         qemu_log_mask(LOG_UNIMP,
 199                       "GPTM: read of TBR but timer read not supported");
 200         return 0;
 201     default:
 202         qemu_log_mask(LOG_GUEST_ERROR,
 203                       "GPTM: read at bad offset 0x%x\n", (int)offset);
 204         return 0;
 205     }
 206 }
 207
 208 static void gptm_write(void *opaque, hwaddr offset,
 209                        uint64_t value, unsigned size)
 210 {
 211     gptm_state *s = (gptm_state *)opaque;
 212     uint32_t oldval;
 213
 214     /* The timers should be disabled before changing the configuration.
 215        We take advantage of this and defer everything until the timer
 216        is enabled.  */
 217     switch (offset) {
 218     case 0x00: /* CFG */
 219         s->config = value;
 220         break;
 221     case 0x04: /* TAMR */
 222         s->mode[0] = value;
 223         break;
 224     case 0x08: /* TBMR */
 225         s->mode[1] = value;
 226         break;
 227     case 0x0c: /* CTL */
 228         oldval = s->control;
 229         s->control = value;
 230         /* TODO: Implement pause.  */
 231         if ((oldval ^ value) & 1) {
 232             if (value & 1) {
 233                 gptm_reload(s, 0, 1);
 234             } else {
 235                 gptm_stop(s, 0);
 236             }
 237         }
 238         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 239             if (value & 0x100) {
 240                 gptm_reload(s, 1, 1);
 241             } else {
 242                 gptm_stop(s, 1);
 243             }
 244         }
 245         break;
 246     case 0x18: /* IMR */
 247         s->mask = value & 0x77;
 248         gptm_update_irq(s);
 249         break;
 250     case 0x24: /* CR */
 251         s->state &= ~value;
 252         break;
 253     case 0x28: /* TAILR */
 254         s->load[0] = value & 0xffff;
 255         if (s->config < 4) {
 256             s->load[1] = value >> 16;
 257         }
 258         break;
 259     case 0x2c: /* TBILR */
 260         s->load[1] = value & 0xffff;
 261         break;
 262     case 0x30: /* TAMARCHR */
 263         s->match[0] = value & 0xffff;
 264         if (s->config < 4) {
 265             s->match[1] = value >> 16;
 266         }
 267         break;
 268     case 0x34: /* TBMATCHR */
 269         s->match[1] = value >> 16;
 270         break;
 271     case 0x38: /* TAPR */
 272         s->prescale[0] = value;
 273         break;
 274     case 0x3c: /* TBPR */
 275         s->prescale[1] = value;
 276         break;
 277     case 0x40: /* TAPMR */
 278         s->match_prescale[0] = value;
 279         break;
 280     case 0x44: /* TBPMR */
 281         s->match_prescale[0] = value;
 282         break;
 283     default:
 284         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 285     }
 286     gptm_update_irq(s);
 287 }
 288
 289 static const MemoryRegionOps gptm_ops = {
 290     .read = gptm_read,
 291     .write = gptm_write,
 292     .endianness = DEVICE_NATIVE_ENDIAN,
 293 };
 294
 295 static const VMStateDescription vmstate_stellaris_gptm = {
 296     .name = "stellaris_gptm",
 297     .version_id = 1,
 298     .minimum_version_id = 1,
 299     .fields = (VMStateField[]) {
 300         VMSTATE_UINT32(config, gptm_state),
 301         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 302         VMSTATE_UINT32(control, gptm_state),
 303         VMSTATE_UINT32(state, gptm_state),
 304         VMSTATE_UINT32(mask, gptm_state),
 305         VMSTATE_UNUSED(8),
 306         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 307         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 308         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 309         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 310         VMSTATE_UINT32(rtc, gptm_state),
 311         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 312         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 313         VMSTATE_END_OF_LIST()
 314     }
 315 };
 316
 317 static int stellaris_gptm_init(SysBusDevice *sbd)
 318 {
 319     DeviceState *dev = DEVICE(sbd);
 320     gptm_state *s = STELLARIS_GPTM(dev);
 321
 322     sysbus_init_irq(sbd, &s->irq);
 323     qdev_init_gpio_out(dev, &s->trigger, 1);
 324
 325     memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s,
 326                           "gptm", 0x1000);
 327     sysbus_init_mmio(sbd, &s->iomem);
 328
 329     s->opaque[0] = s->opaque[1] = s;
 330     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 331     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 332     vmstate_register(dev, -1, &vmstate_stellaris_gptm, s);
 333     return 0;
 334 }
 335
 336
 337 /* System controller.  */
 338
 339 typedef struct {
 340     MemoryRegion iomem;
 341     uint32_t pborctl;
 342     uint32_t ldopctl;
 343     uint32_t int_status;
 344     uint32_t int_mask;
 345     uint32_t resc;
 346     uint32_t rcc;
 347     uint32_t rcc2;
 348     uint32_t rcgc[3];
 349     uint32_t scgc[3];
 350     uint32_t dcgc[3];
 351     uint32_t clkvclr;
 352     uint32_t ldoarst;
 353     uint32_t user0;
 354     uint32_t user1;
 355     qemu_irq irq;
 356     stellaris_board_info *board;
 357 } ssys_state;
 358
 359 static void ssys_update(ssys_state *s)
 360 {
 361   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 362 }
 363
 364 static uint32_t pllcfg_sandstorm[16] = {
 365     0x31c0, /* 1 Mhz */
 366     0x1ae0, /* 1.8432 Mhz */
 367     0x18c0, /* 2 Mhz */
 368     0xd573, /* 2.4576 Mhz */
 369     0x37a6, /* 3.57954 Mhz */
 370     0x1ae2, /* 3.6864 Mhz */
 371     0x0c40, /* 4 Mhz */
 372     0x98bc, /* 4.906 Mhz */
 373     0x935b, /* 4.9152 Mhz */
 374     0x09c0, /* 5 Mhz */
 375     0x4dee, /* 5.12 Mhz */
 376     0x0c41, /* 6 Mhz */
 377     0x75db, /* 6.144 Mhz */
 378     0x1ae6, /* 7.3728 Mhz */
 379     0x0600, /* 8 Mhz */
 380     0x585b /* 8.192 Mhz */
 381 };
 382
 383 static uint32_t pllcfg_fury[16] = {
 384     0x3200, /* 1 Mhz */
 385     0x1b20, /* 1.8432 Mhz */
 386     0x1900, /* 2 Mhz */
 387     0xf42b, /* 2.4576 Mhz */
 388     0x37e3, /* 3.57954 Mhz */
 389     0x1b21, /* 3.6864 Mhz */
 390     0x0c80, /* 4 Mhz */
 391     0x98ee, /* 4.906 Mhz */
 392     0xd5b4, /* 4.9152 Mhz */
 393     0x0a00, /* 5 Mhz */
 394     0x4e27, /* 5.12 Mhz */
 395     0x1902, /* 6 Mhz */
 396     0xec1c, /* 6.144 Mhz */
 397     0x1b23, /* 7.3728 Mhz */
 398     0x0640, /* 8 Mhz */
 399     0xb11c /* 8.192 Mhz */
 400 };
 401
 402 #define DID0_VER_MASK        0x70000000
 403 #define DID0_VER_0           0x00000000
 404 #define DID0_VER_1           0x10000000
 405
 406 #define DID0_CLASS_MASK      0x00FF0000
 407 #define DID0_CLASS_SANDSTORM 0x00000000
 408 #define DID0_CLASS_FURY      0x00010000
 409
 410 static int ssys_board_class(const ssys_state *s)
 411 {
 412     uint32_t did0 = s->board->did0;
 413     switch (did0 & DID0_VER_MASK) {
 414     case DID0_VER_0:
 415         return DID0_CLASS_SANDSTORM;
 416     case DID0_VER_1:
 417         switch (did0 & DID0_CLASS_MASK) {
 418         case DID0_CLASS_SANDSTORM:
 419         case DID0_CLASS_FURY:
 420             return did0 & DID0_CLASS_MASK;
 421         }
 422         /* for unknown classes, fall through */
 423     default:
 424         hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
 425     }
 426 }
 427
 428 static uint64_t ssys_read(void *opaque, hwaddr offset,
 429                           unsigned size)
 430 {
 431     ssys_state *s = (ssys_state *)opaque;
 432
 433     switch (offset) {
 434     case 0x000: /* DID0 */
 435         return s->board->did0;
 436     case 0x004: /* DID1 */
 437         return s->board->did1;
 438     case 0x008: /* DC0 */
 439         return s->board->dc0;
 440     case 0x010: /* DC1 */
 441         return s->board->dc1;
 442     case 0x014: /* DC2 */
 443         return s->board->dc2;
 444     case 0x018: /* DC3 */
 445         return s->board->dc3;
 446     case 0x01c: /* DC4 */
 447         return s->board->dc4;
 448     case 0x030: /* PBORCTL */
 449         return s->pborctl;
 450     case 0x034: /* LDOPCTL */
 451         return s->ldopctl;
 452     case 0x040: /* SRCR0 */
 453         return 0;
 454     case 0x044: /* SRCR1 */
 455         return 0;
 456     case 0x048: /* SRCR2 */
 457         return 0;
 458     case 0x050: /* RIS */
 459         return s->int_status;
 460     case 0x054: /* IMC */
 461         return s->int_mask;
 462     case 0x058: /* MISC */
 463         return s->int_status & s->int_mask;
 464     case 0x05c: /* RESC */
 465         return s->resc;
 466     case 0x060: /* RCC */
 467         return s->rcc;
 468     case 0x064: /* PLLCFG */
 469         {
 470             int xtal;
 471             xtal = (s->rcc >> 6) & 0xf;
 472             switch (ssys_board_class(s)) {
 473             case DID0_CLASS_FURY:
 474                 return pllcfg_fury[xtal];
 475             case DID0_CLASS_SANDSTORM:
 476                 return pllcfg_sandstorm[xtal];
 477             default:
 478                 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 479                 return 0;
 480             }
 481         }
 482     case 0x070: /* RCC2 */
 483         return s->rcc2;
 484     case 0x100: /* RCGC0 */
 485         return s->rcgc[0];
 486     case 0x104: /* RCGC1 */
 487         return s->rcgc[1];
 488     case 0x108: /* RCGC2 */
 489         return s->rcgc[2];
 490     case 0x110: /* SCGC0 */
 491         return s->scgc[0];
 492     case 0x114: /* SCGC1 */
 493         return s->scgc[1];
 494     case 0x118: /* SCGC2 */
 495         return s->scgc[2];
 496     case 0x120: /* DCGC0 */
 497         return s->dcgc[0];
 498     case 0x124: /* DCGC1 */
 499         return s->dcgc[1];
 500     case 0x128: /* DCGC2 */
 501         return s->dcgc[2];
 502     case 0x150: /* CLKVCLR */
 503         return s->clkvclr;
 504     case 0x160: /* LDOARST */
 505         return s->ldoarst;
 506     case 0x1e0: /* USER0 */
 507         return s->user0;
 508     case 0x1e4: /* USER1 */
 509         return s->user1;
 510     default:
 511         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 512         return 0;
 513     }
 514 }
 515
 516 static bool ssys_use_rcc2(ssys_state *s)
 517 {
 518     return (s->rcc2 >> 31) & 0x1;
 519 }
 520
 521 /*
 522  * Caculate the sys. clock period in ms.
 523  */
 524 static void ssys_calculate_system_clock(ssys_state *s)
 525 {
 526     if (ssys_use_rcc2(s)) {
 527         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 528     } else {
 529         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 530     }
 531 }
 532
 533 static void ssys_write(void *opaque, hwaddr offset,
 534                        uint64_t value, unsigned size)
 535 {
 536     ssys_state *s = (ssys_state *)opaque;
 537
 538     switch (offset) {
 539     case 0x030: /* PBORCTL */
 540         s->pborctl = value & 0xffff;
 541         break;
 542     case 0x034: /* LDOPCTL */
 543         s->ldopctl = value & 0x1f;
 544         break;
 545     case 0x040: /* SRCR0 */
 546     case 0x044: /* SRCR1 */
 547     case 0x048: /* SRCR2 */
 548         fprintf(stderr, "Peripheral reset not implemented\n");
 549         break;
 550     case 0x054: /* IMC */
 551         s->int_mask = value & 0x7f;
 552         break;
 553     case 0x058: /* MISC */
 554         s->int_status &= ~value;
 555         break;
 556     case 0x05c: /* RESC */
 557         s->resc = value & 0x3f;
 558         break;
 559     case 0x060: /* RCC */
 560         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 561             /* PLL enable.  */
 562             s->int_status |= (1 << 6);
 563         }
 564         s->rcc = value;
 565         ssys_calculate_system_clock(s);
 566         break;
 567     case 0x070: /* RCC2 */
 568         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 569             break;
 570         }
 571
 572         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 573             /* PLL enable.  */
 574             s->int_status |= (1 << 6);
 575         }
 576         s->rcc2 = value;
 577         ssys_calculate_system_clock(s);
 578         break;
 579     case 0x100: /* RCGC0 */
 580         s->rcgc[0] = value;
 581         break;
 582     case 0x104: /* RCGC1 */
 583         s->rcgc[1] = value;
 584         break;
 585     case 0x108: /* RCGC2 */
 586         s->rcgc[2] = value;
 587         break;
 588     case 0x110: /* SCGC0 */
 589         s->scgc[0] = value;
 590         break;
 591     case 0x114: /* SCGC1 */
 592         s->scgc[1] = value;
 593         break;
 594     case 0x118: /* SCGC2 */
 595         s->scgc[2] = value;
 596         break;
 597     case 0x120: /* DCGC0 */
 598         s->dcgc[0] = value;
 599         break;
 600     case 0x124: /* DCGC1 */
 601         s->dcgc[1] = value;
 602         break;
 603     case 0x128: /* DCGC2 */
 604         s->dcgc[2] = value;
 605         break;
 606     case 0x150: /* CLKVCLR */
 607         s->clkvclr = value;
 608         break;
 609     case 0x160: /* LDOARST */
 610         s->ldoarst = value;
 611         break;
 612     default:
 613         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 614     }
 615     ssys_update(s);
 616 }
 617
 618 static const MemoryRegionOps ssys_ops = {
 619     .read = ssys_read,
 620     .write = ssys_write,
 621     .endianness = DEVICE_NATIVE_ENDIAN,
 622 };
 623
 624 static void ssys_reset(void *opaque)
 625 {
 626     ssys_state *s = (ssys_state *)opaque;
 627
 628     s->pborctl = 0x7ffd;
 629     s->rcc = 0x078e3ac0;
 630
 631     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 632         s->rcc2 = 0;
 633     } else {
 634         s->rcc2 = 0x07802810;
 635     }
 636     s->rcgc[0] = 1;
 637     s->scgc[0] = 1;
 638     s->dcgc[0] = 1;
 639     ssys_calculate_system_clock(s);
 640 }
 641
 642 static int stellaris_sys_post_load(void *opaque, int version_id)
 643 {
 644     ssys_state *s = opaque;
 645
 646     ssys_calculate_system_clock(s);
 647
 648     return 0;
 649 }
 650
 651 static const VMStateDescription vmstate_stellaris_sys = {
 652     .name = "stellaris_sys",
 653     .version_id = 2,
 654     .minimum_version_id = 1,
 655     .post_load = stellaris_sys_post_load,
 656     .fields = (VMStateField[]) {
 657         VMSTATE_UINT32(pborctl, ssys_state),
 658         VMSTATE_UINT32(ldopctl, ssys_state),
 659         VMSTATE_UINT32(int_mask, ssys_state),
 660         VMSTATE_UINT32(int_status, ssys_state),
 661         VMSTATE_UINT32(resc, ssys_state),
 662         VMSTATE_UINT32(rcc, ssys_state),
 663         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 664         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 665         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 666         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 667         VMSTATE_UINT32(clkvclr, ssys_state),
 668         VMSTATE_UINT32(ldoarst, ssys_state),
 669         VMSTATE_END_OF_LIST()
 670     }
 671 };
 672
 673 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 674                               stellaris_board_info * board,
 675                               uint8_t *macaddr)
 676 {
 677     ssys_state *s;
 678
 679     s = g_new0(ssys_state, 1);
 680     s->irq = irq;
 681     s->board = board;
 682     /* Most devices come preprogrammed with a MAC address in the user data. */
 683     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 684     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 685
 686     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 687     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 688     ssys_reset(s);
 689     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 690     return 0;
 691 }
 692
 693
 694 /* I2C controller.  */
 695
 696 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 697 #define STELLARIS_I2C(obj) \
 698     OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
 699
 700 typedef struct {
 701     SysBusDevice parent_obj;
 702
 703     I2CBus *bus;
 704     qemu_irq irq;
 705     MemoryRegion iomem;
 706     uint32_t msa;
 707     uint32_t mcs;
 708     uint32_t mdr;
 709     uint32_t mtpr;
 710     uint32_t mimr;
 711     uint32_t mris;
 712     uint32_t mcr;
 713 } stellaris_i2c_state;
 714
 715 #define STELLARIS_I2C_MCS_BUSY    0x01
 716 #define STELLARIS_I2C_MCS_ERROR   0x02
 717 #define STELLARIS_I2C_MCS_ADRACK  0x04
 718 #define STELLARIS_I2C_MCS_DATACK  0x08
 719 #define STELLARIS_I2C_MCS_ARBLST  0x10
 720 #define STELLARIS_I2C_MCS_IDLE    0x20
 721 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 722
 723 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 724                                    unsigned size)
 725 {
 726     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 727
 728     switch (offset) {
 729     case 0x00: /* MSA */
 730         return s->msa;
 731     case 0x04: /* MCS */
 732         /* We don't emulate timing, so the controller is never busy.  */
 733         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 734     case 0x08: /* MDR */
 735         return s->mdr;
 736     case 0x0c: /* MTPR */
 737         return s->mtpr;
 738     case 0x10: /* MIMR */
 739         return s->mimr;
 740     case 0x14: /* MRIS */
 741         return s->mris;
 742     case 0x18: /* MMIS */
 743         return s->mris & s->mimr;
 744     case 0x20: /* MCR */
 745         return s->mcr;
 746     default:
 747         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 748         return 0;
 749     }
 750 }
 751
 752 static void stellaris_i2c_update(stellaris_i2c_state *s)
 753 {
 754     int level;
 755
 756     level = (s->mris & s->mimr) != 0;
 757     qemu_set_irq(s->irq, level);
 758 }
 759
 760 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 761                                 uint64_t value, unsigned size)
 762 {
 763     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 764
 765     switch (offset) {
 766     case 0x00: /* MSA */
 767         s->msa = value & 0xff;
 768         break;
 769     case 0x04: /* MCS */
 770         if ((s->mcr & 0x10) == 0) {
 771             /* Disabled.  Do nothing.  */
 772             break;
 773         }
 774         /* Grab the bus if this is starting a transfer.  */
 775         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 776             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 777                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 778             } else {
 779                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 780                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 781             }
 782         }
 783         /* If we don't have the bus then indicate an error.  */
 784         if (!i2c_bus_busy(s->bus)
 785                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 786             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 787             break;
 788         }
 789         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 790         if (value & 1) {
 791             /* Transfer a byte.  */
 792             /* TODO: Handle errors.  */
 793             if (s->msa & 1) {
 794                 /* Recv */
 795                 s->mdr = i2c_recv(s->bus) & 0xff;
 796             } else {
 797                 /* Send */
 798                 i2c_send(s->bus, s->mdr);
 799             }
 800             /* Raise an interrupt.  */
 801             s->mris |= 1;
 802         }
 803         if (value & 4) {
 804             /* Finish transfer.  */
 805             i2c_end_transfer(s->bus);
 806             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 807         }
 808         break;
 809     case 0x08: /* MDR */
 810         s->mdr = value & 0xff;
 811         break;
 812     case 0x0c: /* MTPR */
 813         s->mtpr = value & 0xff;
 814         break;
 815     case 0x10: /* MIMR */
 816         s->mimr = 1;
 817         break;
 818     case 0x1c: /* MICR */
 819         s->mris &= ~value;
 820         break;
 821     case 0x20: /* MCR */
 822         if (value & 1)
 823             hw_error(
 824                       "stellaris_i2c_write: Loopback not implemented\n");
 825         if (value & 0x20)
 826             hw_error(
 827                       "stellaris_i2c_write: Slave mode not implemented\n");
 828         s->mcr = value & 0x31;
 829         break;
 830     default:
 831         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 832                   (int)offset);
 833     }
 834     stellaris_i2c_update(s);
 835 }
 836
 837 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 838 {
 839     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 840         i2c_end_transfer(s->bus);
 841
 842     s->msa = 0;
 843     s->mcs = 0;
 844     s->mdr = 0;
 845     s->mtpr = 1;
 846     s->mimr = 0;
 847     s->mris = 0;
 848     s->mcr = 0;
 849     stellaris_i2c_update(s);
 850 }
 851
 852 static const MemoryRegionOps stellaris_i2c_ops = {
 853     .read = stellaris_i2c_read,
 854     .write = stellaris_i2c_write,
 855     .endianness = DEVICE_NATIVE_ENDIAN,
 856 };
 857
 858 static const VMStateDescription vmstate_stellaris_i2c = {
 859     .name = "stellaris_i2c",
 860     .version_id = 1,
 861     .minimum_version_id = 1,
 862     .fields = (VMStateField[]) {
 863         VMSTATE_UINT32(msa, stellaris_i2c_state),
 864         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 865         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 866         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 867         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 868         VMSTATE_UINT32(mris, stellaris_i2c_state),
 869         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 870         VMSTATE_END_OF_LIST()
 871     }
 872 };
 873
 874 static int stellaris_i2c_init(SysBusDevice *sbd)
 875 {
 876     DeviceState *dev = DEVICE(sbd);
 877     stellaris_i2c_state *s = STELLARIS_I2C(dev);
 878     I2CBus *bus;
 879
 880     sysbus_init_irq(sbd, &s->irq);
 881     bus = i2c_init_bus(dev, "i2c");
 882     s->bus = bus;
 883
 884     memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s,
 885                           "i2c", 0x1000);
 886     sysbus_init_mmio(sbd, &s->iomem);
 887     /* ??? For now we only implement the master interface.  */
 888     stellaris_i2c_reset(s);
 889     vmstate_register(dev, -1, &vmstate_stellaris_i2c, s);
 890     return 0;
 891 }
 892
 893 /* Analogue to Digital Converter.  This is only partially implemented,
 894    enough for applications that use a combined ADC and timer tick.  */
 895
 896 #define STELLARIS_ADC_EM_CONTROLLER 0
 897 #define STELLARIS_ADC_EM_COMP       1
 898 #define STELLARIS_ADC_EM_EXTERNAL   4
 899 #define STELLARIS_ADC_EM_TIMER      5
 900 #define STELLARIS_ADC_EM_PWM0       6
 901 #define STELLARIS_ADC_EM_PWM1       7
 902 #define STELLARIS_ADC_EM_PWM2       8
 903
 904 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 905 #define STELLARIS_ADC_FIFO_FULL     0x1000
 906
 907 #define TYPE_STELLARIS_ADC "stellaris-adc"
 908 #define STELLARIS_ADC(obj) \
 909     OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
 910
 911 typedef struct StellarisADCState {
 912     SysBusDevice parent_obj;
 913
 914     MemoryRegion iomem;
 915     uint32_t actss;
 916     uint32_t ris;
 917     uint32_t im;
 918     uint32_t emux;
 919     uint32_t ostat;
 920     uint32_t ustat;
 921     uint32_t sspri;
 922     uint32_t sac;
 923     struct {
 924         uint32_t state;
 925         uint32_t data[16];
 926     } fifo[4];
 927     uint32_t ssmux[4];
 928     uint32_t ssctl[4];
 929     uint32_t noise;
 930     qemu_irq irq[4];
 931 } stellaris_adc_state;
 932
 933 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 934 {
 935     int tail;
 936
 937     tail = s->fifo[n].state & 0xf;
 938     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 939         s->ustat |= 1 << n;
 940     } else {
 941         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 942         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 943         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 944             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 945     }
 946     return s->fifo[n].data[tail];
 947 }
 948
 949 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 950                                      uint32_t value)
 951 {
 952     int head;
 953
 954     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 955        FIFO fir each sequencer.  */
 956     head = (s->fifo[n].state >> 4) & 0xf;
 957     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 958         s->ostat |= 1 << n;
 959         return;
 960     }
 961     s->fifo[n].data[head] = value;
 962     head = (head + 1) & 0xf;
 963     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 964     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 965     if ((s->fifo[n].state & 0xf) == head)
 966         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 967 }
 968
 969 static void stellaris_adc_update(stellaris_adc_state *s)
 970 {
 971     int level;
 972     int n;
 973
 974     for (n = 0; n < 4; n++) {
 975         level = (s->ris & s->im & (1 << n)) != 0;
 976         qemu_set_irq(s->irq[n], level);
 977     }
 978 }
 979
 980 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 981 {
 982     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 983     int n;
 984
 985     for (n = 0; n < 4; n++) {
 986         if ((s->actss & (1 << n)) == 0) {
 987             continue;
 988         }
 989
 990         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 991             continue;
 992         }
 993
 994         /* Some applications use the ADC as a random number source, so introduce
 995            some variation into the signal.  */
 996         s->noise = s->noise * 314159 + 1;
 997         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
 998         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
 999         s->ris |= (1 << n);
1000         stellaris_adc_update(s);
1001     }
1002 }
1003
1004 static void stellaris_adc_reset(stellaris_adc_state *s)
1005 {
1006     int n;
1007
1008     for (n = 0; n < 4; n++) {
1009         s->ssmux[n] = 0;
1010         s->ssctl[n] = 0;
1011         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1012     }
1013 }
1014
1015 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1016                                    unsigned size)
1017 {
1018     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1019
1020     /* TODO: Implement this.  */
1021     if (offset >= 0x40 && offset < 0xc0) {
1022         int n;
1023         n = (offset - 0x40) >> 5;
1024         switch (offset & 0x1f) {
1025         case 0x00: /* SSMUX */
1026             return s->ssmux[n];
1027         case 0x04: /* SSCTL */
1028             return s->ssctl[n];
1029         case 0x08: /* SSFIFO */
1030             return stellaris_adc_fifo_read(s, n);
1031         case 0x0c: /* SSFSTAT */
1032             return s->fifo[n].state;
1033         default:
1034             break;
1035         }
1036     }
1037     switch (offset) {
1038     case 0x00: /* ACTSS */
1039         return s->actss;
1040     case 0x04: /* RIS */
1041         return s->ris;
1042     case 0x08: /* IM */
1043         return s->im;
1044     case 0x0c: /* ISC */
1045         return s->ris & s->im;
1046     case 0x10: /* OSTAT */
1047         return s->ostat;
1048     case 0x14: /* EMUX */
1049         return s->emux;
1050     case 0x18: /* USTAT */
1051         return s->ustat;
1052     case 0x20: /* SSPRI */
1053         return s->sspri;
1054     case 0x30: /* SAC */
1055         return s->sac;
1056     default:
1057         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1058                   (int)offset);
1059         return 0;
1060     }
1061 }
1062
1063 static void stellaris_adc_write(void *opaque, hwaddr offset,
1064                                 uint64_t value, unsigned size)
1065 {
1066     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1067
1068     /* TODO: Implement this.  */
1069     if (offset >= 0x40 && offset < 0xc0) {
1070         int n;
1071         n = (offset - 0x40) >> 5;
1072         switch (offset & 0x1f) {
1073         case 0x00: /* SSMUX */
1074             s->ssmux[n] = value & 0x33333333;
1075             return;
1076         case 0x04: /* SSCTL */
1077             if (value != 6) {
1078                 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
1079                           value);
1080             }
1081             s->ssctl[n] = value;
1082             return;
1083         default:
1084             break;
1085         }
1086     }
1087     switch (offset) {
1088     case 0x00: /* ACTSS */
1089         s->actss = value & 0xf;
1090         break;
1091     case 0x08: /* IM */
1092         s->im = value;
1093         break;
1094     case 0x0c: /* ISC */
1095         s->ris &= ~value;
1096         break;
1097     case 0x10: /* OSTAT */
1098         s->ostat &= ~value;
1099         break;
1100     case 0x14: /* EMUX */
1101         s->emux = value;
1102         break;
1103     case 0x18: /* USTAT */
1104         s->ustat &= ~value;
1105         break;
1106     case 0x20: /* SSPRI */
1107         s->sspri = value;
1108         break;
1109     case 0x28: /* PSSI */
1110         hw_error("Not implemented:  ADC sample initiate\n");
1111         break;
1112     case 0x30: /* SAC */
1113         s->sac = value;
1114         break;
1115     default:
1116         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1117     }
1118     stellaris_adc_update(s);
1119 }
1120
1121 static const MemoryRegionOps stellaris_adc_ops = {
1122     .read = stellaris_adc_read,
1123     .write = stellaris_adc_write,
1124     .endianness = DEVICE_NATIVE_ENDIAN,
1125 };
1126
1127 static const VMStateDescription vmstate_stellaris_adc = {
1128     .name = "stellaris_adc",
1129     .version_id = 1,
1130     .minimum_version_id = 1,
1131     .fields = (VMStateField[]) {
1132         VMSTATE_UINT32(actss, stellaris_adc_state),
1133         VMSTATE_UINT32(ris, stellaris_adc_state),
1134         VMSTATE_UINT32(im, stellaris_adc_state),
1135         VMSTATE_UINT32(emux, stellaris_adc_state),
1136         VMSTATE_UINT32(ostat, stellaris_adc_state),
1137         VMSTATE_UINT32(ustat, stellaris_adc_state),
1138         VMSTATE_UINT32(sspri, stellaris_adc_state),
1139         VMSTATE_UINT32(sac, stellaris_adc_state),
1140         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1141         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1142         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1143         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1144         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1145         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1146         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1147         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1148         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1149         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1150         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1151         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1152         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1153         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1154         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1155         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1156         VMSTATE_UINT32(noise, stellaris_adc_state),
1157         VMSTATE_END_OF_LIST()
1158     }
1159 };
1160
1161 static int stellaris_adc_init(SysBusDevice *sbd)
1162 {
1163     DeviceState *dev = DEVICE(sbd);
1164     stellaris_adc_state *s = STELLARIS_ADC(dev);
1165     int n;
1166
1167     for (n = 0; n < 4; n++) {
1168         sysbus_init_irq(sbd, &s->irq[n]);
1169     }
1170
1171     memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s,
1172                           "adc", 0x1000);
1173     sysbus_init_mmio(sbd, &s->iomem);
1174     stellaris_adc_reset(s);
1175     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1176     vmstate_register(dev, -1, &vmstate_stellaris_adc, s);
1177     return 0;
1178 }
1179
1180 static
1181 void do_sys_reset(void *opaque, int n, int level)
1182 {
1183     if (level) {
1184         qemu_system_reset_request();
1185     }
1186 }
1187
1188 /* Board init.  */
1189 static stellaris_board_info stellaris_boards[] = {
1190   { "LM3S811EVB",
1191     0,
1192     0x0032000e,
1193     0x001f001f, /* dc0 */
1194     0x001132bf,
1195     0x01071013,
1196     0x3f0f01ff,
1197     0x0000001f,
1198     BP_OLED_I2C
1199   },
1200   { "LM3S6965EVB",
1201     0x10010002,
1202     0x1073402e,
1203     0x00ff007f, /* dc0 */
1204     0x001133ff,
1205     0x030f5317,
1206     0x0f0f87ff,
1207     0x5000007f,
1208     BP_OLED_SSI | BP_GAMEPAD
1209   }
1210 };
1211
1212 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1213                            stellaris_board_info *board)
1214 {
1215     static const int uart_irq[] = {5, 6, 33, 34};
1216     static const int timer_irq[] = {19, 21, 23, 35};
1217     static const uint32_t gpio_addr[7] =
1218       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1219         0x40024000, 0x40025000, 0x40026000};
1220     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1221
1222     DeviceState *gpio_dev[7], *nvic;
1223     qemu_irq gpio_in[7][8];
1224     qemu_irq gpio_out[7][8];
1225     qemu_irq adc;
1226     int sram_size;
1227     int flash_size;
1228     I2CBus *i2c;
1229     DeviceState *dev;
1230     int i;
1231     int j;
1232
1233     MemoryRegion *sram = g_new(MemoryRegion, 1);
1234     MemoryRegion *flash = g_new(MemoryRegion, 1);
1235     MemoryRegion *system_memory = get_system_memory();
1236
1237     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1238     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1239
1240     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1241     memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
1242                            &error_fatal);
1243     vmstate_register_ram_global(flash);
1244     memory_region_set_readonly(flash, true);
1245     memory_region_add_subregion(system_memory, 0, flash);
1246
1247     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1248                            &error_fatal);
1249     vmstate_register_ram_global(sram);
1250     memory_region_add_subregion(system_memory, 0x20000000, sram);
1251
1252     nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
1253                       kernel_filename, cpu_model);
1254
1255     qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
1256                                 qemu_allocate_irq(&do_sys_reset, NULL, 0));
1257
1258     if (board->dc1 & (1 << 16)) {
1259         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1260                                     qdev_get_gpio_in(nvic, 14),
1261                                     qdev_get_gpio_in(nvic, 15),
1262                                     qdev_get_gpio_in(nvic, 16),
1263                                     qdev_get_gpio_in(nvic, 17),
1264                                     NULL);
1265         adc = qdev_get_gpio_in(dev, 0);
1266     } else {
1267         adc = NULL;
1268     }
1269     for (i = 0; i < 4; i++) {
1270         if (board->dc2 & (0x10000 << i)) {
1271             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1272                                        0x40030000 + i * 0x1000,
1273                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1274             /* TODO: This is incorrect, but we get away with it because
1275                the ADC output is only ever pulsed.  */
1276             qdev_connect_gpio_out(dev, 0, adc);
1277         }
1278     }
1279
1280     stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1281                        board, nd_table[0].macaddr.a);
1282
1283     for (i = 0; i < 7; i++) {
1284         if (board->dc4 & (1 << i)) {
1285             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1286                                                qdev_get_gpio_in(nvic,
1287                                                                 gpio_irq[i]));
1288             for (j = 0; j < 8; j++) {
1289                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1290                 gpio_out[i][j] = NULL;
1291             }
1292         }
1293     }
1294
1295     if (board->dc2 & (1 << 12)) {
1296         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1297                                    qdev_get_gpio_in(nvic, 8));
1298         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1299         if (board->peripherals & BP_OLED_I2C) {
1300             i2c_create_slave(i2c, "ssd0303", 0x3d);
1301         }
1302     }
1303
1304     for (i = 0; i < 4; i++) {
1305         if (board->dc2 & (1 << i)) {
1306             sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
1307                                  qdev_get_gpio_in(nvic, uart_irq[i]));
1308         }
1309     }
1310     if (board->dc2 & (1 << 4)) {
1311         dev = sysbus_create_simple("pl022", 0x40008000,
1312                                    qdev_get_gpio_in(nvic, 7));
1313         if (board->peripherals & BP_OLED_SSI) {
1314             void *bus;
1315             DeviceState *sddev;
1316             DeviceState *ssddev;
1317
1318             /* Some boards have both an OLED controller and SD card connected to
1319              * the same SSI port, with the SD card chip select connected to a
1320              * GPIO pin.  Technically the OLED chip select is connected to the
1321              * SSI Fss pin.  We do not bother emulating that as both devices
1322              * should never be selected simultaneously, and our OLED controller
1323              * ignores stray 0xff commands that occur when deselecting the SD
1324              * card.
1325              */
1326             bus = qdev_get_child_bus(dev, "ssi");
1327
1328             sddev = ssi_create_slave(bus, "ssi-sd");
1329             ssddev = ssi_create_slave(bus, "ssd0323");
1330             gpio_out[GPIO_D][0] = qemu_irq_split(
1331                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1332                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1333             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1334
1335             /* Make sure the select pin is high.  */
1336             qemu_irq_raise(gpio_out[GPIO_D][0]);
1337         }
1338     }
1339     if (board->dc4 & (1 << 28)) {
1340         DeviceState *enet;
1341
1342         qemu_check_nic_model(&nd_table[0], "stellaris");
1343
1344         enet = qdev_create(NULL, "stellaris_enet");
1345         qdev_set_nic_properties(enet, &nd_table[0]);
1346         qdev_init_nofail(enet);
1347         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1348         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1349     }
1350     if (board->peripherals & BP_GAMEPAD) {
1351         qemu_irq gpad_irq[5];
1352         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1353
1354         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1355         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1356         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1357         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1358         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1359
1360         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1361     }
1362     for (i = 0; i < 7; i++) {
1363         if (board->dc4 & (1 << i)) {
1364             for (j = 0; j < 8; j++) {
1365                 if (gpio_out[i][j]) {
1366                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1367                 }
1368             }
1369         }
1370     }
1371 }
1372
1373 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1374 static void lm3s811evb_init(MachineState *machine)
1375 {
1376     const char *cpu_model = machine->cpu_model;
1377     const char *kernel_filename = machine->kernel_filename;
1378     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1379 }
1380
1381 static void lm3s6965evb_init(MachineState *machine)
1382 {
1383     const char *cpu_model = machine->cpu_model;
1384     const char *kernel_filename = machine->kernel_filename;
1385     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1386 }
1387
1388 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1389 {
1390     MachineClass *mc = MACHINE_CLASS(oc);
1391
1392     mc->desc = "Stellaris LM3S811EVB";
1393     mc->init = lm3s811evb_init;
1394 }
1395
1396 static const TypeInfo lm3s811evb_type = {
1397     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1398     .parent = TYPE_MACHINE,
1399     .class_init = lm3s811evb_class_init,
1400 };
1401
1402 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1403 {
1404     MachineClass *mc = MACHINE_CLASS(oc);
1405
1406     mc->desc = "Stellaris LM3S6965EVB";
1407     mc->init = lm3s6965evb_init;
1408 }
1409
1410 static const TypeInfo lm3s6965evb_type = {
1411     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1412     .parent = TYPE_MACHINE,
1413     .class_init = lm3s6965evb_class_init,
1414 };
1415
1416 static void stellaris_machine_init(void)
1417 {
1418     type_register_static(&lm3s811evb_type);
1419     type_register_static(&lm3s6965evb_type);
1420 }
1421
1422 machine_init(stellaris_machine_init)
1423
1424 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1425 {
1426     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1427
1428     sdc->init = stellaris_i2c_init;
1429 }
1430
1431 static const TypeInfo stellaris_i2c_info = {
1432     .name          = TYPE_STELLARIS_I2C,
1433     .parent        = TYPE_SYS_BUS_DEVICE,
1434     .instance_size = sizeof(stellaris_i2c_state),
1435     .class_init    = stellaris_i2c_class_init,
1436 };
1437
1438 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1439 {
1440     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1441
1442     sdc->init = stellaris_gptm_init;
1443 }
1444
1445 static const TypeInfo stellaris_gptm_info = {
1446     .name          = TYPE_STELLARIS_GPTM,
1447     .parent        = TYPE_SYS_BUS_DEVICE,
1448     .instance_size = sizeof(gptm_state),
1449     .class_init    = stellaris_gptm_class_init,
1450 };
1451
1452 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1453 {
1454     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1455
1456     sdc->init = stellaris_adc_init;
1457 }
1458
1459 static const TypeInfo stellaris_adc_info = {
1460     .name          = TYPE_STELLARIS_ADC,
1461     .parent        = TYPE_SYS_BUS_DEVICE,
1462     .instance_size = sizeof(stellaris_adc_state),
1463     .class_init    = stellaris_adc_class_init,
1464 };
1465
1466 static void stellaris_register_types(void)
1467 {
1468     type_register_static(&stellaris_i2c_info);
1469     type_register_static(&stellaris_gptm_info);
1470     type_register_static(&stellaris_adc_info);
1471 }
1472
1473 type_init(stellaris_register_types)