hw/mips_r4k.c

   1 #include "vl.h"
   2
   3 #define BIOS_FILENAME "mips_bios.bin"
   4 //#define BIOS_FILENAME "system.bin"
   5 #define KERNEL_LOAD_ADDR 0x80010000
   6 #define INITRD_LOAD_ADDR 0x80800000
   7
   8 #define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
   9
  10 extern FILE *logfile;
  11
  12 static PITState *pit;
  13
  14 static void pic_irq_request(void *opaque, int level)
  15 {
  16     CPUState *env = first_cpu;
  17     if (level) {
  18         env->CP0_Cause |= 0x00000400;
  19         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  20     } else {
  21         env->CP0_Cause &= ~0x00000400;
  22         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  23     }
  24 }
  25
  26 void cpu_mips_irqctrl_init (void)
  27 {
  28 }
  29
  30 uint32_t cpu_mips_get_random (CPUState *env)
  31 {
  32     uint32_t now = qemu_get_clock(vm_clock);
  33
  34     return now % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
  35 }
  36
  37 /* MIPS R4K timer */
  38 uint32_t cpu_mips_get_count (CPUState *env)
  39 {
  40     return env->CP0_Count +
  41         (uint32_t)muldiv64(qemu_get_clock(vm_clock),
  42                            100 * 1000 * 1000, ticks_per_sec);
  43 }
  44
  45 static void cpu_mips_update_count (CPUState *env, uint32_t count,
  46                                    uint32_t compare)
  47 {
  48     uint64_t now, next;
  49     uint32_t tmp;
  50
  51     tmp = count;
  52     if (count == compare)
  53         tmp++;
  54     now = qemu_get_clock(vm_clock);
  55     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
  56     if (next == now)
  57         next++;
  58 #if 0
  59     if (logfile) {
  60         fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
  61                 __func__, now, count, compare, next - now);
  62     }
  63 #endif
  64     /* Store new count and compare registers */
  65     env->CP0_Compare = compare;
  66     env->CP0_Count =
  67         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
  68     /* Adjust timer */
  69     qemu_mod_timer(env->timer, next);
  70 }
  71
  72 void cpu_mips_store_count (CPUState *env, uint32_t value)
  73 {
  74     cpu_mips_update_count(env, value, env->CP0_Compare);
  75 }
  76
  77 void cpu_mips_store_compare (CPUState *env, uint32_t value)
  78 {
  79     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
  80     env->CP0_Cause &= ~0x00008000;
  81     cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  82 }
  83
  84 static void mips_timer_cb (void *opaque)
  85 {
  86     CPUState *env;
  87
  88     env = opaque;
  89 #if 0
  90     if (logfile) {
  91         fprintf(logfile, "%s\n", __func__);
  92     }
  93 #endif
  94     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
  95     env->CP0_Cause |= 0x00008000;
  96     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  97 }
  98
  99 void cpu_mips_clock_init (CPUState *env)
 100 {
 101     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
 102     env->CP0_Compare = 0;
 103     cpu_mips_update_count(env, 1, 0);
 104 }
 105
 106
 107 static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 108 {
 109 #if 0
 110     if (logfile)
 111         fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
 112 #endif
 113     cpu_outb(NULL, addr & 0xffff, value);
 114 }
 115
 116 static uint32_t io_readb (void *opaque, target_phys_addr_t addr)
 117 {
 118     uint32_t ret = cpu_inb(NULL, addr & 0xffff);
 119 #if 0
 120     if (logfile)
 121         fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
 122 #endif
 123     return ret;
 124 }
 125
 126 static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 127 {
 128 #if 0
 129     if (logfile)
 130         fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
 131 #endif
 132 #ifdef TARGET_WORDS_BIGENDIAN
 133     value = bswap16(value);
 134 #endif
 135     cpu_outw(NULL, addr & 0xffff, value);
 136 }
 137
 138 static uint32_t io_readw (void *opaque, target_phys_addr_t addr)
 139 {
 140     uint32_t ret = cpu_inw(NULL, addr & 0xffff);
 141 #ifdef TARGET_WORDS_BIGENDIAN
 142     ret = bswap16(ret);
 143 #endif
 144 #if 0
 145     if (logfile)
 146         fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
 147 #endif
 148     return ret;
 149 }
 150
 151 static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 152 {
 153 #if 0
 154     if (logfile)
 155         fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
 156 #endif
 157 #ifdef TARGET_WORDS_BIGENDIAN
 158     value = bswap32(value);
 159 #endif
 160     cpu_outl(NULL, addr & 0xffff, value);
 161 }
 162
 163 static uint32_t io_readl (void *opaque, target_phys_addr_t addr)
 164 {
 165     uint32_t ret = cpu_inl(NULL, addr & 0xffff);
 166
 167 #ifdef TARGET_WORDS_BIGENDIAN
 168     ret = bswap32(ret);
 169 #endif
 170 #if 0
 171     if (logfile)
 172         fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
 173 #endif
 174     return ret;
 175 }
 176
 177 CPUWriteMemoryFunc *io_write[] = {
 178     &io_writeb,
 179     &io_writew,
 180     &io_writel,
 181 };
 182
 183 CPUReadMemoryFunc *io_read[] = {
 184     &io_readb,
 185     &io_readw,
 186     &io_readl,
 187 };
 188
 189 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 190                     DisplayState *ds, const char **fd_filename, int snapshot,
 191                     const char *kernel_filename, const char *kernel_cmdline,
 192                     const char *initrd_filename)
 193 {
 194     char buf[1024];
 195     int64_t entry = 0;
 196     unsigned long bios_offset;
 197     int io_memory;
 198     int ret;
 199     CPUState *env;
 200     long kernel_size;
 201
 202     env = cpu_init();
 203     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 204
 205     /* allocate RAM */
 206     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 207
 208     /* Try to load a BIOS image. If this fails, we continue regardless,
 209        but initialize the hardware ourselves. When a kernel gets
 210        preloaded we also initialize the hardware, since the BIOS wasn't
 211        run. */
 212     bios_offset = ram_size + vga_ram_size;
 213     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 214     printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE);
 215     ret = load_image(buf, phys_ram_base + bios_offset);
 216     if (ret == BIOS_SIZE) {
 217         cpu_register_physical_memory((uint32_t)(0x1fc00000),
 218                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 219         env->PC = 0xBFC00000;
 220         if (!kernel_filename)
 221             return;
 222     } else {
 223         /* not fatal */
 224         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 225                 buf);
 226     }
 227
 228     kernel_size = 0;
 229     if (kernel_filename) {
 230         kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
 231         if (kernel_size >= 0)
 232             env->PC = entry;
 233         else {
 234             kernel_size = load_image(kernel_filename,
 235                                      phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
 236             if (kernel_size < 0) {
 237                 fprintf(stderr, "qemu: could not load kernel '%s'\n",
 238                         kernel_filename);
 239                 exit(1);
 240             }
 241             env->PC = KERNEL_LOAD_ADDR;
 242         }
 243
 244         /* load initrd */
 245         if (initrd_filename) {
 246             if (load_image(initrd_filename,
 247                            phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND)
 248                 == (target_ulong) -1) {
 249                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 250                         initrd_filename);
 251                 exit(1);
 252             }
 253         }
 254
 255         /* Store command line.  */
 256         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 257         /* FIXME: little endian support */
 258         *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 259         *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 260     }
 261
 262     /* Init internal devices */
 263     cpu_mips_clock_init(env);
 264     cpu_mips_irqctrl_init();
 265
 266     /* Register 64 KB of ISA IO space at 0x14000000 */
 267     io_memory = cpu_register_io_memory(0, io_read, io_write, NULL);
 268     cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
 269     isa_mem_base = 0x10000000;
 270
 271     isa_pic = pic_init(pic_irq_request, env);
 272     pit = pit_init(0x40, 0);
 273     serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
 274     vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
 275                    vga_ram_size, 0, 0);
 276
 277     if (nd_table[0].vlan) {
 278         if (nd_table[0].model == NULL
 279             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 280             isa_ne2000_init(0x300, 9, &nd_table[0]);
 281         } else {
 282             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 283             exit (1);
 284         }
 285     }
 286 }
 287
 288 QEMUMachine mips_machine = {
 289     "mips",
 290     "mips r4k platform",
 291     mips_r4k_init,
 292 };