user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #ifdef __linux__
  36 #include <sys/ucontext.h>
  37 #endif
  38
  39 //#define DEBUG_SIGNAL
  40
  41 static void exception_action(CPUArchState *env1)
  42 {
  43 #if defined(TARGET_I386)
  44     raise_exception_err(env1, env1->exception_index, env1->error_code);
  45 #else
  46     cpu_loop_exit(env1);
  47 #endif
  48 }
  49
  50 /* exit the current TB from a signal handler. The host registers are
  51    restored in a state compatible with the CPU emulator
  52  */
  53 void cpu_resume_from_signal(CPUArchState *env1, void *puc)
  54 {
  55 #ifdef __linux__
  56     struct ucontext *uc = puc;
  57 #elif defined(__OpenBSD__)
  58     struct sigcontext *uc = puc;
  59 #endif
  60
  61     if (puc) {
  62         /* XXX: use siglongjmp ? */
  63 #ifdef __linux__
  64 #ifdef __ia64
  65         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  66 #else
  67         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  68 #endif
  69 #elif defined(__OpenBSD__)
  70         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  71 #endif
  72     }
  73     env1->exception_index = -1;
  74     siglongjmp(env1->jmp_env, 1);
  75 }
  76
  77 /* 'pc' is the host PC at which the exception was raised. 'address' is
  78    the effective address of the memory exception. 'is_write' is 1 if a
  79    write caused the exception and otherwise 0'. 'old_set' is the
  80    signal set which should be restored */
  81 static inline int handle_cpu_signal(uintptr_t pc, void *ptr,
  82                                     int is_write, sigset_t *old_set,
  83                                     void *puc)
  84 {
  85     uintptr_t address = (uintptr_t)ptr;
  86     CPUArchState *env;
  87     int ret;
  88
  89 #if defined(DEBUG_SIGNAL)
  90     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  91                 pc, address, is_write, *(unsigned long *)old_set);
  92 #endif
  93     /* XXX: locking issue */
  94     if (is_write && h2g_valid(address)
  95         && page_unprotect(h2g(address), pc, puc)) {
  96         return 1;
  97     }
  98
  99     /* Convert forcefully to guest address space, invalid addresses
 100        are still valid segv ones */
 101     address = h2g_nocheck(address);
 102
 103     env = current_cpu->env_ptr;
 104     /* see if it is an MMU fault */
 105     ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
 106     if (ret < 0) {
 107         return 0; /* not an MMU fault */
 108     }
 109     if (ret == 0) {
 110         return 1; /* the MMU fault was handled without causing real CPU fault */
 111     }
 112     /* now we have a real cpu fault */
 113     cpu_restore_state(env, pc);
 114
 115     /* we restore the process signal mask as the sigreturn should
 116        do it (XXX: use sigsetjmp) */
 117     sigprocmask(SIG_SETMASK, old_set, NULL);
 118     exception_action(env);
 119
 120     /* never comes here */
 121     return 1;
 122 }
 123
 124 #if defined(__i386__)
 125
 126 #if defined(__APPLE__)
 127 #include <sys/ucontext.h>
 128
 129 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 130 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 131 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 132 #define MASK_sig(context)    ((context)->uc_sigmask)
 133 #elif defined(__NetBSD__)
 134 #include <ucontext.h>
 135
 136 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 137 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 138 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 139 #define MASK_sig(context)    ((context)->uc_sigmask)
 140 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 141 #include <ucontext.h>
 142
 143 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 144 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 145 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 146 #define MASK_sig(context)    ((context)->uc_sigmask)
 147 #elif defined(__OpenBSD__)
 148 #define EIP_sig(context)     ((context)->sc_eip)
 149 #define TRAP_sig(context)    ((context)->sc_trapno)
 150 #define ERROR_sig(context)   ((context)->sc_err)
 151 #define MASK_sig(context)    ((context)->sc_mask)
 152 #else
 153 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 154 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 155 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 156 #define MASK_sig(context)    ((context)->uc_sigmask)
 157 #endif
 158
 159 int cpu_signal_handler(int host_signum, void *pinfo,
 160                        void *puc)
 161 {
 162     siginfo_t *info = pinfo;
 163 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 164     ucontext_t *uc = puc;
 165 #elif defined(__OpenBSD__)
 166     struct sigcontext *uc = puc;
 167 #else
 168     struct ucontext *uc = puc;
 169 #endif
 170     uintptr_t pc;
 171     int trapno;
 172
 173 #ifndef REG_EIP
 174 /* for glibc 2.1 */
 175 #define REG_EIP    EIP
 176 #define REG_ERR    ERR
 177 #define REG_TRAPNO TRAPNO
 178 #endif
 179     pc = EIP_sig(uc);
 180     trapno = TRAP_sig(uc);
 181     return handle_cpu_signal(pc, info->si_addr,
 182                              trapno == 0xe ?
 183                              (ERROR_sig(uc) >> 1) & 1 : 0,
 184                              &MASK_sig(uc), puc);
 185 }
 186
 187 #elif defined(__x86_64__)
 188
 189 #ifdef __NetBSD__
 190 #define PC_sig(context)       _UC_MACHINE_PC(context)
 191 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 192 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 193 #define MASK_sig(context)     ((context)->uc_sigmask)
 194 #elif defined(__OpenBSD__)
 195 #define PC_sig(context)       ((context)->sc_rip)
 196 #define TRAP_sig(context)     ((context)->sc_trapno)
 197 #define ERROR_sig(context)    ((context)->sc_err)
 198 #define MASK_sig(context)     ((context)->sc_mask)
 199 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 200 #include <ucontext.h>
 201
 202 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 203 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 204 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 205 #define MASK_sig(context)     ((context)->uc_sigmask)
 206 #else
 207 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 208 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 209 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 210 #define MASK_sig(context)     ((context)->uc_sigmask)
 211 #endif
 212
 213 int cpu_signal_handler(int host_signum, void *pinfo,
 214                        void *puc)
 215 {
 216     siginfo_t *info = pinfo;
 217     uintptr_t pc;
 218 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 219     ucontext_t *uc = puc;
 220 #elif defined(__OpenBSD__)
 221     struct sigcontext *uc = puc;
 222 #else
 223     struct ucontext *uc = puc;
 224 #endif
 225
 226     pc = PC_sig(uc);
 227     return handle_cpu_signal(pc, info->si_addr,
 228                              TRAP_sig(uc) == 0xe ?
 229                              (ERROR_sig(uc) >> 1) & 1 : 0,
 230                              &MASK_sig(uc), puc);
 231 }
 232
 233 #elif defined(_ARCH_PPC)
 234
 235 /***********************************************************************
 236  * signal context platform-specific definitions
 237  * From Wine
 238  */
 239 #ifdef linux
 240 /* All Registers access - only for local access */
 241 #define REG_sig(reg_name, context)              \
 242     ((context)->uc_mcontext.regs->reg_name)
 243 /* Gpr Registers access  */
 244 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 245 /* Program counter */
 246 #define IAR_sig(context)                       REG_sig(nip, context)
 247 /* Machine State Register (Supervisor) */
 248 #define MSR_sig(context)                       REG_sig(msr, context)
 249 /* Count register */
 250 #define CTR_sig(context)                       REG_sig(ctr, context)
 251 /* User's integer exception register */
 252 #define XER_sig(context)                       REG_sig(xer, context)
 253 /* Link register */
 254 #define LR_sig(context)                        REG_sig(link, context)
 255 /* Condition register */
 256 #define CR_sig(context)                        REG_sig(ccr, context)
 257
 258 /* Float Registers access  */
 259 #define FLOAT_sig(reg_num, context)                                     \
 260     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 261 #define FPSCR_sig(context) \
 262     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 263 /* Exception Registers access */
 264 #define DAR_sig(context)                       REG_sig(dar, context)
 265 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 266 #define TRAP_sig(context)                      REG_sig(trap, context)
 267 #endif /* linux */
 268
 269 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 270 #include <ucontext.h>
 271 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 272 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 273 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 274 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 275 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 276 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 277 /* Exception Registers access */
 278 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 279 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 280 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 281 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 282
 283 #ifdef __APPLE__
 284 #include <sys/ucontext.h>
 285 typedef struct ucontext SIGCONTEXT;
 286 /* All Registers access - only for local access */
 287 #define REG_sig(reg_name, context)              \
 288     ((context)->uc_mcontext->ss.reg_name)
 289 #define FLOATREG_sig(reg_name, context)         \
 290     ((context)->uc_mcontext->fs.reg_name)
 291 #define EXCEPREG_sig(reg_name, context)         \
 292     ((context)->uc_mcontext->es.reg_name)
 293 #define VECREG_sig(reg_name, context)           \
 294     ((context)->uc_mcontext->vs.reg_name)
 295 /* Gpr Registers access */
 296 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 297 /* Program counter */
 298 #define IAR_sig(context)                       REG_sig(srr0, context)
 299 /* Machine State Register (Supervisor) */
 300 #define MSR_sig(context)                       REG_sig(srr1, context)
 301 #define CTR_sig(context)                       REG_sig(ctr, context)
 302 /* Link register */
 303 #define XER_sig(context)                       REG_sig(xer, context)
 304 /* User's integer exception register */
 305 #define LR_sig(context)                        REG_sig(lr, context)
 306 /* Condition register */
 307 #define CR_sig(context)                        REG_sig(cr, context)
 308 /* Float Registers access */
 309 #define FLOAT_sig(reg_num, context)             \
 310     FLOATREG_sig(fpregs[reg_num], context)
 311 #define FPSCR_sig(context)                      \
 312     ((double)FLOATREG_sig(fpscr, context))
 313 /* Exception Registers access */
 314 /* Fault registers for coredump */
 315 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 316 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 317 /* number of powerpc exception taken */
 318 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 319 #endif /* __APPLE__ */
 320
 321 int cpu_signal_handler(int host_signum, void *pinfo,
 322                        void *puc)
 323 {
 324     siginfo_t *info = pinfo;
 325 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 326     ucontext_t *uc = puc;
 327 #else
 328     struct ucontext *uc = puc;
 329 #endif
 330     uintptr_t pc;
 331     int is_write;
 332
 333     pc = IAR_sig(uc);
 334     is_write = 0;
 335 #if 0
 336     /* ppc 4xx case */
 337     if (DSISR_sig(uc) & 0x00800000) {
 338         is_write = 1;
 339     }
 340 #else
 341     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 342         is_write = 1;
 343     }
 344 #endif
 345     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 346 }
 347
 348 #elif defined(__alpha__)
 349
 350 int cpu_signal_handler(int host_signum, void *pinfo,
 351                            void *puc)
 352 {
 353     siginfo_t *info = pinfo;
 354     struct ucontext *uc = puc;
 355     uint32_t *pc = uc->uc_mcontext.sc_pc;
 356     uint32_t insn = *pc;
 357     int is_write = 0;
 358
 359     /* XXX: need kernel patch to get write flag faster */
 360     switch (insn >> 26) {
 361     case 0x0d: /* stw */
 362     case 0x0e: /* stb */
 363     case 0x0f: /* stq_u */
 364     case 0x24: /* stf */
 365     case 0x25: /* stg */
 366     case 0x26: /* sts */
 367     case 0x27: /* stt */
 368     case 0x2c: /* stl */
 369     case 0x2d: /* stq */
 370     case 0x2e: /* stl_c */
 371     case 0x2f: /* stq_c */
 372         is_write = 1;
 373     }
 374
 375     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 376 }
 377 #elif defined(__sparc__)
 378
 379 int cpu_signal_handler(int host_signum, void *pinfo,
 380                        void *puc)
 381 {
 382     siginfo_t *info = pinfo;
 383     int is_write;
 384     uint32_t insn;
 385 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 386     uint32_t *regs = (uint32_t *)(info + 1);
 387     void *sigmask = (regs + 20);
 388     /* XXX: is there a standard glibc define ? */
 389     uintptr_t pc = regs[1];
 390 #else
 391 #ifdef __linux__
 392     struct sigcontext *sc = puc;
 393     uintptr_t pc = sc->sigc_regs.tpc;
 394     void *sigmask = (void *)sc->sigc_mask;
 395 #elif defined(__OpenBSD__)
 396     struct sigcontext *uc = puc;
 397     uintptr_t pc = uc->sc_pc;
 398     void *sigmask = (void *)(long)uc->sc_mask;
 399 #endif
 400 #endif
 401
 402     /* XXX: need kernel patch to get write flag faster */
 403     is_write = 0;
 404     insn = *(uint32_t *)pc;
 405     if ((insn >> 30) == 3) {
 406         switch ((insn >> 19) & 0x3f) {
 407         case 0x05: /* stb */
 408         case 0x15: /* stba */
 409         case 0x06: /* sth */
 410         case 0x16: /* stha */
 411         case 0x04: /* st */
 412         case 0x14: /* sta */
 413         case 0x07: /* std */
 414         case 0x17: /* stda */
 415         case 0x0e: /* stx */
 416         case 0x1e: /* stxa */
 417         case 0x24: /* stf */
 418         case 0x34: /* stfa */
 419         case 0x27: /* stdf */
 420         case 0x37: /* stdfa */
 421         case 0x26: /* stqf */
 422         case 0x36: /* stqfa */
 423         case 0x25: /* stfsr */
 424         case 0x3c: /* casa */
 425         case 0x3e: /* casxa */
 426             is_write = 1;
 427             break;
 428         }
 429     }
 430     return handle_cpu_signal(pc, info->si_addr, is_write, sigmask, NULL);
 431 }
 432
 433 #elif defined(__arm__)
 434
 435 int cpu_signal_handler(int host_signum, void *pinfo,
 436                        void *puc)
 437 {
 438     siginfo_t *info = pinfo;
 439     struct ucontext *uc = puc;
 440     uintptr_t pc;
 441     int is_write;
 442
 443 #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 444     pc = uc->uc_mcontext.gregs[R15];
 445 #else
 446     pc = uc->uc_mcontext.arm_pc;
 447 #endif
 448
 449     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 450      * later processor; on v5 we will always report this as a read).
 451      */
 452     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 453     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 454 }
 455
 456 #elif defined(__aarch64__)
 457
 458 int cpu_signal_handler(int host_signum, void *pinfo,
 459                        void *puc)
 460 {
 461     siginfo_t *info = pinfo;
 462     struct ucontext *uc = puc;
 463     uint64_t pc;
 464     int is_write = 0; /* XXX how to determine? */
 465
 466     pc = uc->uc_mcontext.pc;
 467     return handle_cpu_signal(pc, (uint64_t)info->si_addr,
 468                              is_write, &uc->uc_sigmask, puc);
 469 }
 470
 471 #elif defined(__mc68000)
 472
 473 int cpu_signal_handler(int host_signum, void *pinfo,
 474                        void *puc)
 475 {
 476     siginfo_t *info = pinfo;
 477     struct ucontext *uc = puc;
 478     uintptr_t pc;
 479     int is_write;
 480
 481     pc = uc->uc_mcontext.gregs[16];
 482     /* XXX: compute is_write */
 483     is_write = 0;
 484     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 485 }
 486
 487 #elif defined(__ia64)
 488
 489 #ifndef __ISR_VALID
 490   /* This ought to be in <bits/siginfo.h>... */
 491 # define __ISR_VALID    1
 492 #endif
 493
 494 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 495 {
 496     siginfo_t *info = pinfo;
 497     struct ucontext *uc = puc;
 498     unsigned long ip;
 499     int is_write = 0;
 500
 501     ip = uc->uc_mcontext.sc_ip;
 502     switch (host_signum) {
 503     case SIGILL:
 504     case SIGFPE:
 505     case SIGSEGV:
 506     case SIGBUS:
 507     case SIGTRAP:
 508         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 509             /* ISR.W (write-access) is bit 33:  */
 510             is_write = (info->si_isr >> 33) & 1;
 511         }
 512         break;
 513
 514     default:
 515         break;
 516     }
 517     return handle_cpu_signal(ip, info->si_addr, is_write,
 518                              (sigset_t *)&uc->uc_sigmask, puc);
 519 }
 520
 521 #elif defined(__s390__)
 522
 523 int cpu_signal_handler(int host_signum, void *pinfo,
 524                        void *puc)
 525 {
 526     siginfo_t *info = pinfo;
 527     struct ucontext *uc = puc;
 528     uintptr_t pc;
 529     uint16_t *pinsn;
 530     int is_write = 0;
 531
 532     pc = uc->uc_mcontext.psw.addr;
 533
 534     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 535        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 536        from the hardware which does in fact contain the is_write value.
 537        The rt signal handler, as far as I can tell, does not give this value
 538        at all.  Not that we could get to it from here even if it were.  */
 539     /* ??? This is not even close to complete, since it ignores all
 540        of the read-modify-write instructions.  */
 541     pinsn = (uint16_t *)pc;
 542     switch (pinsn[0] >> 8) {
 543     case 0x50: /* ST */
 544     case 0x42: /* STC */
 545     case 0x40: /* STH */
 546         is_write = 1;
 547         break;
 548     case 0xc4: /* RIL format insns */
 549         switch (pinsn[0] & 0xf) {
 550         case 0xf: /* STRL */
 551         case 0xb: /* STGRL */
 552         case 0x7: /* STHRL */
 553             is_write = 1;
 554         }
 555         break;
 556     case 0xe3: /* RXY format insns */
 557         switch (pinsn[2] & 0xff) {
 558         case 0x50: /* STY */
 559         case 0x24: /* STG */
 560         case 0x72: /* STCY */
 561         case 0x70: /* STHY */
 562         case 0x8e: /* STPQ */
 563         case 0x3f: /* STRVH */
 564         case 0x3e: /* STRV */
 565         case 0x2f: /* STRVG */
 566             is_write = 1;
 567         }
 568         break;
 569     }
 570     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 571 }
 572
 573 #elif defined(__mips__)
 574
 575 int cpu_signal_handler(int host_signum, void *pinfo,
 576                        void *puc)
 577 {
 578     siginfo_t *info = pinfo;
 579     struct ucontext *uc = puc;
 580     greg_t pc = uc->uc_mcontext.pc;
 581     int is_write;
 582
 583     /* XXX: compute is_write */
 584     is_write = 0;
 585     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 586 }
 587
 588 #elif defined(__hppa__)
 589
 590 int cpu_signal_handler(int host_signum, void *pinfo,
 591                        void *puc)
 592 {
 593     siginfo_t *info = pinfo;
 594     struct ucontext *uc = puc;
 595     uintptr_t pc = uc->uc_mcontext.sc_iaoq[0];
 596     uint32_t insn = *(uint32_t *)pc;
 597     int is_write = 0;
 598
 599     /* XXX: need kernel patch to get write flag faster.  */
 600     switch (insn >> 26) {
 601     case 0x1a: /* STW */
 602     case 0x19: /* STH */
 603     case 0x18: /* STB */
 604     case 0x1b: /* STWM */
 605         is_write = 1;
 606         break;
 607
 608     case 0x09: /* CSTWX, FSTWX, FSTWS */
 609     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 610         /* Distinguish from coprocessor load ... */
 611         is_write = (insn >> 9) & 1;
 612         break;
 613
 614     case 0x03:
 615         switch ((insn >> 6) & 15) {
 616         case 0xa: /* STWS */
 617         case 0x9: /* STHS */
 618         case 0x8: /* STBS */
 619         case 0xe: /* STWAS */
 620         case 0xc: /* STBYS */
 621             is_write = 1;
 622         }
 623         break;
 624     }
 625
 626     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 627 }
 628
 629 #else
 630
 631 #error host CPU specific signal handler needed
 632
 633 #endif