2 * Copyright (c) 2019 Red Hat, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2 or later, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu-common.h"
21 #include "exec/hwaddr.h"
22 #include "qemu/notify.h"
24 #include "hw/i386/topology.h"
25 #include "hw/boards.h"
27 #include "hw/isa/isa.h"
28 #include "hw/i386/ioapic.h"
36 /* TSC rate migration: */
38 /* Enables contiguous-apic-ID mode */
39 bool compat_apic_id_mode
;
48 /* Pointers to devices and objects: */
52 GMappedFile
*initrd_mapped_file
;
54 /* RAM information (sizes, addresses, configuration): */
55 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
57 /* CPU and apic information: */
58 bool apic_xrupt_override
;
59 unsigned apic_id_limit
;
66 /* Apic id specific handlers */
67 uint32_t (*apicid_from_cpu_idx
)(X86CPUTopoInfo
*topo_info
,
69 void (*topo_ids_from_apicid
)(apic_id_t apicid
, X86CPUTopoInfo
*topo_info
,
70 X86CPUTopoIDs
*topo_ids
);
71 apic_id_t (*apicid_from_topo_ids
)(X86CPUTopoInfo
*topo_info
,
72 const X86CPUTopoIDs
*topo_ids
);
73 uint32_t (*apicid_pkg_offset
)(X86CPUTopoInfo
*topo_info
);
76 * Address space used by IOAPIC device. All IOAPIC interrupts
77 * will be translated to MSI messages in the address space.
79 AddressSpace
*ioapic_as
;
82 #define X86_MACHINE_SMM "smm"
83 #define X86_MACHINE_ACPI "acpi"
85 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
86 #define X86_MACHINE(obj) \
87 OBJECT_CHECK(X86MachineState, (obj), TYPE_X86_MACHINE)
88 #define X86_MACHINE_GET_CLASS(obj) \
89 OBJECT_GET_CLASS(X86MachineClass, obj, TYPE_X86_MACHINE)
90 #define X86_MACHINE_CLASS(class) \
91 OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
93 void init_topo_info(X86CPUTopoInfo
*topo_info
, const X86MachineState
*x86ms
);
95 uint32_t x86_cpu_apic_id_from_index(X86MachineState
*pcms
,
96 unsigned int cpu_index
);
98 void x86_cpu_new(X86MachineState
*pcms
, int64_t apic_id
, Error
**errp
);
99 void x86_cpus_init(X86MachineState
*pcms
, int default_cpu_version
);
100 CpuInstanceProperties
x86_cpu_index_to_props(MachineState
*ms
,
102 int64_t x86_get_default_cpu_node_id(const MachineState
*ms
, int idx
);
103 const CPUArchIdList
*x86_possible_cpu_arch_ids(MachineState
*ms
);
105 void x86_bios_rom_init(MemoryRegion
*rom_memory
, bool isapc_ram_fw
);
107 void x86_load_linux(X86MachineState
*x86ms
,
111 bool linuxboot_dma_enabled
);
113 bool x86_machine_is_smm_enabled(X86MachineState
*x86ms
);
114 bool x86_machine_is_acpi_enabled(X86MachineState
*x86ms
);
116 /* Global System Interrupts */
118 #define GSI_NUM_PINS IOAPIC_NUM_PINS
120 typedef struct GSIState
{
121 qemu_irq i8259_irq
[ISA_NUM_IRQS
];
122 qemu_irq ioapic_irq
[IOAPIC_NUM_PINS
];
125 qemu_irq
x86_allocate_cpu_irq(void);
126 void gsi_handler(void *opaque
, int n
, int level
);
127 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
);