hw/intc/puv3_intc.c

   1 /*
   2  * INTC device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/irq.h"
  14 #include "hw/sysbus.h"
  15
  16 #undef DEBUG_PUV3
  17 #include "hw/unicore32/puv3.h"
  18 #include "qemu/module.h"
  19 #include "qemu/log.h"
  20
  21 #define TYPE_PUV3_INTC "puv3_intc"
  22 #define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
  23
  24 typedef struct PUV3INTCState {
  25     SysBusDevice parent_obj;
  26
  27     MemoryRegion iomem;
  28     qemu_irq parent_irq;
  29
  30     uint32_t reg_ICMR;
  31     uint32_t reg_ICPR;
  32 } PUV3INTCState;
  33
  34 /* Update interrupt status after enabled or pending bits have been changed.  */
  35 static void puv3_intc_update(PUV3INTCState *s)
  36 {
  37     if (s->reg_ICMR & s->reg_ICPR) {
  38         qemu_irq_raise(s->parent_irq);
  39     } else {
  40         qemu_irq_lower(s->parent_irq);
  41     }
  42 }
  43
  44 /* Process a change in an external INTC input. */
  45 static void puv3_intc_handler(void *opaque, int irq, int level)
  46 {
  47     PUV3INTCState *s = opaque;
  48
  49     DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
  50     if (level) {
  51         s->reg_ICPR |= (1 << irq);
  52     } else {
  53         s->reg_ICPR &= ~(1 << irq);
  54     }
  55     puv3_intc_update(s);
  56 }
  57
  58 static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
  59         unsigned size)
  60 {
  61     PUV3INTCState *s = opaque;
  62     uint32_t ret = 0;
  63
  64     switch (offset) {
  65     case 0x04: /* INTC_ICMR */
  66         ret = s->reg_ICMR;
  67         break;
  68     case 0x0c: /* INTC_ICIP */
  69         ret = s->reg_ICPR; /* the same value with ICPR */
  70         break;
  71     default:
  72         qemu_log_mask(LOG_GUEST_ERROR,
  73                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  74                       __func__, offset);
  75     }
  76     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  77     return ret;
  78 }
  79
  80 static void puv3_intc_write(void *opaque, hwaddr offset,
  81         uint64_t value, unsigned size)
  82 {
  83     PUV3INTCState *s = opaque;
  84
  85     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  86     switch (offset) {
  87     case 0x00: /* INTC_ICLR */
  88     case 0x14: /* INTC_ICCR */
  89         break;
  90     case 0x04: /* INTC_ICMR */
  91         s->reg_ICMR = value;
  92         break;
  93     default:
  94         qemu_log_mask(LOG_GUEST_ERROR,
  95                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  96                       __func__, offset);
  97         return;
  98     }
  99     puv3_intc_update(s);
 100 }
 101
 102 static const MemoryRegionOps puv3_intc_ops = {
 103     .read = puv3_intc_read,
 104     .write = puv3_intc_write,
 105     .impl = {
 106         .min_access_size = 4,
 107         .max_access_size = 4,
 108     },
 109     .endianness = DEVICE_NATIVE_ENDIAN,
 110 };
 111
 112 static void puv3_intc_realize(DeviceState *dev, Error **errp)
 113 {
 114     PUV3INTCState *s = PUV3_INTC(dev);
 115     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 116
 117     qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
 118     sysbus_init_irq(sbd, &s->parent_irq);
 119
 120     s->reg_ICMR = 0;
 121     s->reg_ICPR = 0;
 122
 123     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
 124                           PUV3_REGS_OFFSET);
 125     sysbus_init_mmio(sbd, &s->iomem);
 126 }
 127
 128 static void puv3_intc_class_init(ObjectClass *klass, void *data)
 129 {
 130     DeviceClass *dc = DEVICE_CLASS(klass);
 131     dc->realize = puv3_intc_realize;
 132 }
 133
 134 static const TypeInfo puv3_intc_info = {
 135     .name = TYPE_PUV3_INTC,
 136     .parent = TYPE_SYS_BUS_DEVICE,
 137     .instance_size = sizeof(PUV3INTCState),
 138     .class_init = puv3_intc_class_init,
 139 };
 140
 141 static void puv3_intc_register_type(void)
 142 {
 143     type_register_static(&puv3_intc_info);
 144 }
 145
 146 type_init(puv3_intc_register_type)