hw/intc/ibex_plic.c

   1 /*
   2  * QEMU RISC-V lowRISC Ibex PLIC
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/core/cpu.h"
  25 #include "hw/boards.h"
  26 #include "hw/pci/msi.h"
  27 #include "target/riscv/cpu_bits.h"
  28 #include "target/riscv/cpu.h"
  29 #include "hw/intc/ibex_plic.h"
  30
  31 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
  32 {
  33     uint32_t end = base + (num * 0x04);
  34
  35     if (addr >= base && addr < end) {
  36         return true;
  37     }
  38
  39     return false;
  40 }
  41
  42 static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
  43 {
  44     int pending_num = irq / 32;
  45
  46     s->pending[pending_num] |= level << (irq % 32);
  47 }
  48
  49 static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
  50 {
  51     int i;
  52
  53     for (i = 0; i < s->pending_num; i++) {
  54         uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
  55
  56         if (!(s->pending[i] & s->enable[i])) {
  57             /* No pending and enabled IRQ */
  58             continue;
  59         }
  60
  61         if (s->priority[irq_num] > s->threshold) {
  62             if (!s->claim) {
  63                 s->claim = irq_num;
  64             }
  65             return true;
  66         }
  67     }
  68
  69     return false;
  70 }
  71
  72 static void ibex_plic_update(IbexPlicState *s)
  73 {
  74     CPUState *cpu;
  75     int level, i;
  76
  77     for (i = 0; i < s->num_cpus; i++) {
  78         cpu = qemu_get_cpu(i);
  79
  80         if (!cpu) {
  81             continue;
  82         }
  83
  84         level = ibex_plic_irqs_pending(s, 0);
  85
  86         riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
  87     }
  88 }
  89
  90 static void ibex_plic_reset(DeviceState *dev)
  91 {
  92     IbexPlicState *s = IBEX_PLIC(dev);
  93
  94     s->threshold = 0x00000000;
  95     s->claim = 0x00000000;
  96 }
  97
  98 static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
  99                                unsigned int size)
 100 {
 101     IbexPlicState *s = opaque;
 102     int offset;
 103     uint32_t ret = 0;
 104
 105     if (addr_between(addr, s->pending_base, s->pending_num)) {
 106         offset = (addr - s->pending_base) / 4;
 107         ret = s->pending[offset];
 108     } else if (addr_between(addr, s->source_base, s->source_num)) {
 109         qemu_log_mask(LOG_UNIMP,
 110                       "%s: Interrupt source mode not supported\n", __func__);
 111     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 112         offset = (addr - s->priority_base) / 4;
 113         ret = s->priority[offset];
 114     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 115         offset = (addr - s->enable_base) / 4;
 116         ret = s->enable[offset];
 117     } else if (addr_between(addr, s->threshold_base, 1)) {
 118         ret = s->threshold;
 119     } else if (addr_between(addr, s->claim_base, 1)) {
 120         int pending_num = s->claim / 32;
 121         s->pending[pending_num] &= ~(1 << (s->claim % 32));
 122
 123         ret = s->claim;
 124     }
 125
 126     return ret;
 127 }
 128
 129 static void ibex_plic_write(void *opaque, hwaddr addr,
 130                             uint64_t value, unsigned int size)
 131 {
 132     IbexPlicState *s = opaque;
 133
 134     if (addr_between(addr, s->pending_base, s->pending_num)) {
 135         qemu_log_mask(LOG_GUEST_ERROR,
 136                       "%s: Pending registers are read only\n", __func__);
 137     } else if (addr_between(addr, s->source_base, s->source_num)) {
 138         qemu_log_mask(LOG_UNIMP,
 139                       "%s: Interrupt source mode not supported\n", __func__);
 140     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 141         uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
 142         s->priority[irq] = value & 7;
 143     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 144         uint32_t enable_reg = (addr - s->enable_base) / 4;
 145
 146         s->enable[enable_reg] = value;
 147     } else if (addr_between(addr, s->threshold_base, 1)) {
 148         s->threshold = value & 3;
 149     } else if (addr_between(addr, s->claim_base, 1)) {
 150         if (s->claim == value) {
 151             /* Interrupt was completed */
 152             s->claim = 0;
 153         }
 154     }
 155
 156     ibex_plic_update(s);
 157 }
 158
 159 static const MemoryRegionOps ibex_plic_ops = {
 160     .read = ibex_plic_read,
 161     .write = ibex_plic_write,
 162     .endianness = DEVICE_NATIVE_ENDIAN,
 163     .valid = {
 164         .min_access_size = 4,
 165         .max_access_size = 4
 166     }
 167 };
 168
 169 static void ibex_plic_irq_request(void *opaque, int irq, int level)
 170 {
 171     IbexPlicState *s = opaque;
 172
 173     ibex_plic_irqs_set_pending(s, irq, level > 0);
 174     ibex_plic_update(s);
 175 }
 176
 177 static Property ibex_plic_properties[] = {
 178     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
 179     DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
 180
 181     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
 182     DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
 183
 184     DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
 185     DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
 186
 187     DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
 188     DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
 189
 190     DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
 191     DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
 192
 193     DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
 194
 195     DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
 196     DEFINE_PROP_END_OF_LIST(),
 197 };
 198
 199 static void ibex_plic_init(Object *obj)
 200 {
 201     IbexPlicState *s = IBEX_PLIC(obj);
 202
 203     memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
 204                           TYPE_IBEX_PLIC, 0x400);
 205     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 206 }
 207
 208 static void ibex_plic_realize(DeviceState *dev, Error **errp)
 209 {
 210     IbexPlicState *s = IBEX_PLIC(dev);
 211     int i;
 212
 213     s->pending = g_new0(uint32_t, s->pending_num);
 214     s->source = g_new0(uint32_t, s->source_num);
 215     s->priority = g_new0(uint32_t, s->priority_num);
 216     s->enable = g_new0(uint32_t, s->enable_num);
 217
 218     qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
 219
 220     /*
 221      * We can't allow the supervisor to control SEIP as this would allow the
 222      * supervisor to clear a pending external interrupt which will result in
 223      * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
 224      * hardware controlled when a PLIC is attached.
 225      */
 226     MachineState *ms = MACHINE(qdev_get_machine());
 227     unsigned int smp_cpus = ms->smp.cpus;
 228     for (i = 0; i < smp_cpus; i++) {
 229         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 230         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 231             error_report("SEIP already claimed");
 232             exit(1);
 233         }
 234     }
 235
 236     msi_nonbroken = true;
 237 }
 238
 239 static void ibex_plic_class_init(ObjectClass *klass, void *data)
 240 {
 241     DeviceClass *dc = DEVICE_CLASS(klass);
 242
 243     dc->reset = ibex_plic_reset;
 244     device_class_set_props(dc, ibex_plic_properties);
 245     dc->realize = ibex_plic_realize;
 246 }
 247
 248 static const TypeInfo ibex_plic_info = {
 249     .name          = TYPE_IBEX_PLIC,
 250     .parent        = TYPE_SYS_BUS_DEVICE,
 251     .instance_size = sizeof(IbexPlicState),
 252     .instance_init = ibex_plic_init,
 253     .class_init    = ibex_plic_class_init,
 254 };
 255
 256 static void ibex_plic_register_types(void)
 257 {
 258     type_register_static(&ibex_plic_info);
 259 }
 260
 261 type_init(ibex_plic_register_types)