4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
29 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
31 # define PIIX4_DPRINTF(format, ...) do { } while (0)
34 #define ACPI_DBG_IO_ADDR 0xb044
36 #define GPE_BASE 0xafe0
37 #define PCI_BASE 0xae00
38 #define PCI_EJ_BASE 0xae08
41 uint16_t sts
; /* status */
42 uint16_t en
; /* enabled */
50 typedef struct PIIX4PMState
{
59 int64_t tmr_overflow_time
;
71 struct pci_status pci0_status
;
74 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
);
76 #define ACPI_ENABLE 0xf1
77 #define ACPI_DISABLE 0xf0
79 static uint32_t get_pmtmr(PIIX4PMState
*s
)
82 d
= muldiv64(qemu_get_clock(vm_clock
), PM_TIMER_FREQUENCY
, get_ticks_per_sec());
86 static int get_pmsts(PIIX4PMState
*s
)
90 d
= muldiv64(qemu_get_clock(vm_clock
), PM_TIMER_FREQUENCY
,
92 if (d
>= s
->tmr_overflow_time
)
93 s
->pmsts
|= ACPI_BITMASK_TIMER_STATUS
;
97 static void pm_update_sci(PIIX4PMState
*s
)
102 pmsts
= get_pmsts(s
);
103 sci_level
= (((pmsts
& s
->pmen
) &
104 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
105 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
106 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
107 ACPI_BITMASK_TIMER_ENABLE
)) != 0);
108 qemu_set_irq(s
->irq
, sci_level
);
109 /* schedule a timer interruption if needed */
110 if ((s
->pmen
& ACPI_BITMASK_TIMER_ENABLE
) &&
111 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
)) {
112 expire_time
= muldiv64(s
->tmr_overflow_time
, get_ticks_per_sec(),
114 qemu_mod_timer(s
->tmr_timer
, expire_time
);
116 qemu_del_timer(s
->tmr_timer
);
120 static void pm_tmr_timer(void *opaque
)
122 PIIX4PMState
*s
= opaque
;
126 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
128 PIIX4PMState
*s
= opaque
;
135 pmsts
= get_pmsts(s
);
136 if (pmsts
& val
& ACPI_BITMASK_TIMER_STATUS
) {
137 /* if TMRSTS is reset, then compute the new overflow time */
138 d
= muldiv64(qemu_get_clock(vm_clock
), PM_TIMER_FREQUENCY
,
139 get_ticks_per_sec());
140 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
153 s
->pmcntrl
= val
& ~(ACPI_BITMASK_SLEEP_ENABLE
);
154 if (val
& ACPI_BITMASK_SLEEP_ENABLE
) {
155 /* change suspend type */
156 sus_typ
= (val
>> 10) & 7;
158 case 0: /* soft power off */
159 qemu_system_shutdown_request();
162 /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
163 Pretend that resume was caused by power button */
164 s
->pmsts
|= (ACPI_BITMASK_WAKE_STATUS
|
165 ACPI_BITMASK_POWER_BUTTON_STATUS
);
166 qemu_system_reset_request();
168 qemu_irq_raise(s
->cmos_s3
);
179 PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
182 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
184 PIIX4PMState
*s
= opaque
;
202 PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
206 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
208 // PIIX4PMState *s = opaque;
209 PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr
& 0x3f, val
);
212 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
214 PIIX4PMState
*s
= opaque
;
226 PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
230 static void apm_ctrl_changed(uint32_t val
, void *arg
)
232 PIIX4PMState
*s
= arg
;
234 /* ACPI specs 3.0, 4.7.2.5 */
235 if (val
== ACPI_ENABLE
) {
236 s
->pmcntrl
|= ACPI_BITMASK_SCI_ENABLE
;
237 } else if (val
== ACPI_DISABLE
) {
238 s
->pmcntrl
&= ~ACPI_BITMASK_SCI_ENABLE
;
241 if (s
->dev
.config
[0x5b] & (1 << 1)) {
243 qemu_irq_raise(s
->smi_irq
);
248 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
250 PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val
);
253 static void pm_io_space_update(PIIX4PMState
*s
)
257 if (s
->dev
.config
[0x80] & 1) {
258 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
259 pm_io_base
&= 0xffc0;
261 /* XXX: need to improve memory and ioport allocation */
262 PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base
);
263 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
264 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
265 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
266 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
270 static void pm_write_config(PCIDevice
*d
,
271 uint32_t address
, uint32_t val
, int len
)
273 pci_default_write_config(d
, address
, val
, len
);
274 if (range_covers_byte(address
, len
, 0x80))
275 pm_io_space_update((PIIX4PMState
*)d
);
278 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
280 PIIX4PMState
*s
= opaque
;
282 pm_io_space_update(s
);
286 static const VMStateDescription vmstate_acpi
= {
289 .minimum_version_id
= 1,
290 .minimum_version_id_old
= 1,
291 .post_load
= vmstate_acpi_post_load
,
292 .fields
= (VMStateField
[]) {
293 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
294 VMSTATE_UINT16(pmsts
, PIIX4PMState
),
295 VMSTATE_UINT16(pmen
, PIIX4PMState
),
296 VMSTATE_UINT16(pmcntrl
, PIIX4PMState
),
297 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
298 VMSTATE_TIMER(tmr_timer
, PIIX4PMState
),
299 VMSTATE_INT64(tmr_overflow_time
, PIIX4PMState
),
300 VMSTATE_END_OF_LIST()
304 static void piix4_reset(void *opaque
)
306 PIIX4PMState
*s
= opaque
;
307 uint8_t *pci_conf
= s
->dev
.config
;
314 if (s
->kvm_enabled
) {
315 /* Mark SMM as already inited (until KVM supports SMM). */
316 pci_conf
[0x5B] = 0x02;
320 static void piix4_powerdown(void *opaque
, int irq
, int power_failing
)
322 PIIX4PMState
*s
= opaque
;
325 qemu_system_shutdown_request();
326 } else if (s
->pmen
& ACPI_BITMASK_POWER_BUTTON_ENABLE
) {
327 s
->pmsts
|= ACPI_BITMASK_POWER_BUTTON_STATUS
;
332 static int piix4_pm_initfn(PCIDevice
*dev
)
334 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
337 pci_conf
= s
->dev
.config
;
338 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
339 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371AB_3
);
340 pci_conf
[0x06] = 0x80;
341 pci_conf
[0x07] = 0x02;
342 pci_conf
[0x08] = 0x03; // revision number
343 pci_conf
[0x09] = 0x00;
344 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_OTHER
);
345 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
346 pci_conf
[0x3d] = 0x01; // interrupt pin 1
348 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
351 apm_init(&s
->apm
, apm_ctrl_changed
, s
);
353 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
355 if (s
->kvm_enabled
) {
356 /* Mark SMM as already inited to prevent SMM from running. KVM does not
357 * support SMM mode. */
358 pci_conf
[0x5B] = 0x02;
361 /* XXX: which specification is used ? The i82731AB has different
363 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
364 pci_conf
[0x63] = 0x60;
365 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
366 (serial_hds
[1] != NULL
? 0x90 : 0);
368 pci_conf
[0x90] = s
->smb_io_base
| 1;
369 pci_conf
[0x91] = s
->smb_io_base
>> 8;
370 pci_conf
[0xd2] = 0x09;
371 register_ioport_write(s
->smb_io_base
, 64, 1, smb_ioport_writeb
, &s
->smb
);
372 register_ioport_read(s
->smb_io_base
, 64, 1, smb_ioport_readb
, &s
->smb
);
374 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
376 qemu_system_powerdown
= *qemu_allocate_irqs(piix4_powerdown
, s
, 1);
378 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
379 qemu_register_reset(piix4_reset
, s
);
380 piix4_acpi_system_hot_add_init(dev
->bus
, s
);
385 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
386 qemu_irq sci_irq
, qemu_irq cmos_s3
, qemu_irq smi_irq
,
392 dev
= pci_create(bus
, devfn
, "PIIX4_PM");
393 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
395 s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
397 s
->cmos_s3
= cmos_s3
;
398 s
->smi_irq
= smi_irq
;
399 s
->kvm_enabled
= kvm_enabled
;
401 qdev_init_nofail(&dev
->qdev
);
406 static PCIDeviceInfo piix4_pm_info
= {
407 .qdev
.name
= "PIIX4_PM",
409 .qdev
.size
= sizeof(PIIX4PMState
),
410 .qdev
.vmsd
= &vmstate_acpi
,
411 .init
= piix4_pm_initfn
,
412 .config_write
= pm_write_config
,
413 .qdev
.props
= (Property
[]) {
414 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
415 DEFINE_PROP_END_OF_LIST(),
419 static void piix4_pm_register(void)
421 pci_qdev_register(&piix4_pm_info
);
424 device_init(piix4_pm_register
);
426 static uint32_t gpe_read_val(uint16_t val
, uint32_t addr
)
429 return (val
>> 8) & 0xff;
433 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
436 struct gpe_regs
*g
= opaque
;
440 val
= gpe_read_val(g
->sts
, addr
);
444 val
= gpe_read_val(g
->en
, addr
);
450 PIIX4_DPRINTF("gpe read %x == %x\n", addr
, val
);
454 static void gpe_write_val(uint16_t *cur
, int addr
, uint32_t val
)
457 *cur
= (*cur
& 0xff) | (val
<< 8);
459 *cur
= (*cur
& 0xff00) | (val
& 0xff);
462 static void gpe_reset_val(uint16_t *cur
, int addr
, uint32_t val
)
464 uint16_t x1
, x0
= val
& 0xff;
465 int shift
= (addr
& 1) ? 8 : 0;
467 x1
= (*cur
>> shift
) & 0xff;
471 *cur
= (*cur
& (0xff << (8 - shift
))) | (x1
<< shift
);
474 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
476 struct gpe_regs
*g
= opaque
;
480 gpe_reset_val(&g
->sts
, addr
, val
);
484 gpe_write_val(&g
->en
, addr
, val
);
490 PIIX4_DPRINTF("gpe write %x <== %d\n", addr
, val
);
493 static uint32_t pcihotplug_read(void *opaque
, uint32_t addr
)
496 struct pci_status
*g
= opaque
;
508 PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr
, val
);
512 static void pcihotplug_write(void *opaque
, uint32_t addr
, uint32_t val
)
514 struct pci_status
*g
= opaque
;
524 PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr
, val
);
527 static uint32_t pciej_read(void *opaque
, uint32_t addr
)
529 PIIX4_DPRINTF("pciej read %x\n", addr
);
533 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
535 BusState
*bus
= opaque
;
536 DeviceState
*qdev
, *next
;
538 int slot
= ffs(val
) - 1;
540 QLIST_FOREACH_SAFE(qdev
, &bus
->children
, sibling
, next
) {
541 dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
542 if (PCI_SLOT(dev
->devfn
) == slot
) {
548 PIIX4_DPRINTF("pciej write %x <== %d\n", addr
, val
);
551 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
, int state
);
553 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
)
555 struct gpe_regs
*gpe
= &s
->gpe
;
556 struct pci_status
*pci0_status
= &s
->pci0_status
;
558 register_ioport_write(GPE_BASE
, 4, 1, gpe_writeb
, gpe
);
559 register_ioport_read(GPE_BASE
, 4, 1, gpe_readb
, gpe
);
561 register_ioport_write(PCI_BASE
, 8, 4, pcihotplug_write
, pci0_status
);
562 register_ioport_read(PCI_BASE
, 8, 4, pcihotplug_read
, pci0_status
);
564 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, bus
);
565 register_ioport_read(PCI_EJ_BASE
, 4, 4, pciej_read
, bus
);
567 pci_bus_hotplug(bus
, piix4_device_hotplug
, &s
->dev
.qdev
);
570 static void enable_device(PIIX4PMState
*s
, int slot
)
573 s
->pci0_status
.up
|= (1 << slot
);
576 static void disable_device(PIIX4PMState
*s
, int slot
)
579 s
->pci0_status
.down
|= (1 << slot
);
582 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
, int state
)
584 int slot
= PCI_SLOT(dev
->devfn
);
585 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
,
586 DO_UPCAST(PCIDevice
, qdev
, qdev
));
588 s
->pci0_status
.up
= 0;
589 s
->pci0_status
.down
= 0;
591 enable_device(s
, slot
);
593 disable_device(s
, slot
);
596 qemu_set_irq(s
->irq
, 1);
597 qemu_set_irq(s
->irq
, 0);