4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "exec/ioport.h"
24 #if !defined(CONFIG_USER_ONLY)
25 #include "exec/softmmu_exec.h"
26 #endif /* !defined(CONFIG_USER_ONLY) */
28 /* check if Port I/O is allowed in TSS */
29 static inline void check_io(CPUX86State
*env
, int addr
, int size
)
31 int io_offset
, val
, mask
;
33 /* TSS must be a valid 32 bit one */
34 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
35 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
36 env
->tr
.limit
< 103) {
39 io_offset
= cpu_lduw_kernel(env
, env
->tr
.base
+ 0x66);
40 io_offset
+= (addr
>> 3);
41 /* Note: the check needs two bytes */
42 if ((io_offset
+ 1) > env
->tr
.limit
) {
45 val
= cpu_lduw_kernel(env
, env
->tr
.base
+ io_offset
);
47 mask
= (1 << size
) - 1;
48 /* all bits must be zero to allow the I/O */
49 if ((val
& mask
) != 0) {
51 raise_exception_err(env
, EXCP0D_GPF
, 0);
55 void helper_check_iob(CPUX86State
*env
, uint32_t t0
)
60 void helper_check_iow(CPUX86State
*env
, uint32_t t0
)
65 void helper_check_iol(CPUX86State
*env
, uint32_t t0
)
70 void helper_outb(uint32_t port
, uint32_t data
)
72 cpu_outb(port
, data
& 0xff);
75 target_ulong
helper_inb(uint32_t port
)
80 void helper_outw(uint32_t port
, uint32_t data
)
82 cpu_outw(port
, data
& 0xffff);
85 target_ulong
helper_inw(uint32_t port
)
90 void helper_outl(uint32_t port
, uint32_t data
)
95 target_ulong
helper_inl(uint32_t port
)
100 void helper_into(CPUX86State
*env
, int next_eip_addend
)
104 eflags
= cpu_cc_compute_all(env
, CC_OP
);
106 raise_interrupt(env
, EXCP04_INTO
, 1, 0, next_eip_addend
);
110 void QEMU_NORETURN
helper_single_step(CPUX86State
*env
)
112 #ifndef CONFIG_USER_ONLY
113 check_hw_breakpoints(env
, true);
114 env
->dr
[6] |= DR6_BS
;
116 raise_exception(env
, EXCP01_DB
);
119 void helper_cpuid(CPUX86State
*env
)
121 uint32_t eax
, ebx
, ecx
, edx
;
123 cpu_svm_check_intercept_param(env
, SVM_EXIT_CPUID
, 0);
125 cpu_x86_cpuid(env
, (uint32_t)env
->regs
[R_EAX
], (uint32_t)env
->regs
[R_ECX
],
126 &eax
, &ebx
, &ecx
, &edx
);
127 env
->regs
[R_EAX
] = eax
;
128 env
->regs
[R_EBX
] = ebx
;
129 env
->regs
[R_ECX
] = ecx
;
130 env
->regs
[R_EDX
] = edx
;
133 #if defined(CONFIG_USER_ONLY)
134 target_ulong
helper_read_crN(CPUX86State
*env
, int reg
)
139 void helper_write_crN(CPUX86State
*env
, int reg
, target_ulong t0
)
143 void helper_movl_drN_T0(CPUX86State
*env
, int reg
, target_ulong t0
)
147 target_ulong
helper_read_crN(CPUX86State
*env
, int reg
)
151 cpu_svm_check_intercept_param(env
, SVM_EXIT_READ_CR0
+ reg
, 0);
157 if (!(env
->hflags2
& HF2_VINTR_MASK
)) {
158 val
= cpu_get_apic_tpr(x86_env_get_cpu(env
)->apic_state
);
167 void helper_write_crN(CPUX86State
*env
, int reg
, target_ulong t0
)
169 cpu_svm_check_intercept_param(env
, SVM_EXIT_WRITE_CR0
+ reg
, 0);
172 cpu_x86_update_cr0(env
, t0
);
175 cpu_x86_update_cr3(env
, t0
);
178 cpu_x86_update_cr4(env
, t0
);
181 if (!(env
->hflags2
& HF2_VINTR_MASK
)) {
182 cpu_set_apic_tpr(x86_env_get_cpu(env
)->apic_state
, t0
);
184 env
->v_tpr
= t0
& 0x0f;
192 void helper_movl_drN_T0(CPUX86State
*env
, int reg
, target_ulong t0
)
197 hw_breakpoint_remove(env
, reg
);
199 hw_breakpoint_insert(env
, reg
);
200 } else if (reg
== 7) {
201 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
202 hw_breakpoint_remove(env
, i
);
205 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
206 hw_breakpoint_insert(env
, i
);
214 void helper_lmsw(CPUX86State
*env
, target_ulong t0
)
216 /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
217 if already set to one. */
218 t0
= (env
->cr
[0] & ~0xe) | (t0
& 0xf);
219 helper_write_crN(env
, 0, t0
);
222 void helper_invlpg(CPUX86State
*env
, target_ulong addr
)
224 X86CPU
*cpu
= x86_env_get_cpu(env
);
226 cpu_svm_check_intercept_param(env
, SVM_EXIT_INVLPG
, 0);
227 tlb_flush_page(CPU(cpu
), addr
);
230 void helper_rdtsc(CPUX86State
*env
)
234 if ((env
->cr
[4] & CR4_TSD_MASK
) && ((env
->hflags
& HF_CPL_MASK
) != 0)) {
235 raise_exception(env
, EXCP0D_GPF
);
237 cpu_svm_check_intercept_param(env
, SVM_EXIT_RDTSC
, 0);
239 val
= cpu_get_tsc(env
) + env
->tsc_offset
;
240 env
->regs
[R_EAX
] = (uint32_t)(val
);
241 env
->regs
[R_EDX
] = (uint32_t)(val
>> 32);
244 void helper_rdtscp(CPUX86State
*env
)
247 env
->regs
[R_ECX
] = (uint32_t)(env
->tsc_aux
);
250 void QEMU_NORETURN
helper_rdpmc(CPUX86State
*env
)
252 if ((env
->cr
[4] & CR4_PCE_MASK
) && ((env
->hflags
& HF_CPL_MASK
) != 0)) {
253 raise_exception(env
, EXCP0D_GPF
);
255 cpu_svm_check_intercept_param(env
, SVM_EXIT_RDPMC
, 0);
257 /* currently unimplemented */
258 qemu_log_mask(LOG_UNIMP
, "x86: unimplemented rdpmc\n");
259 raise_exception_err(env
, EXCP06_ILLOP
, 0);
262 #if defined(CONFIG_USER_ONLY)
263 void helper_wrmsr(CPUX86State
*env
)
267 void helper_rdmsr(CPUX86State
*env
)
271 void helper_wrmsr(CPUX86State
*env
)
275 cpu_svm_check_intercept_param(env
, SVM_EXIT_MSR
, 1);
277 val
= ((uint32_t)env
->regs
[R_EAX
]) |
278 ((uint64_t)((uint32_t)env
->regs
[R_EDX
]) << 32);
280 switch ((uint32_t)env
->regs
[R_ECX
]) {
281 case MSR_IA32_SYSENTER_CS
:
282 env
->sysenter_cs
= val
& 0xffff;
284 case MSR_IA32_SYSENTER_ESP
:
285 env
->sysenter_esp
= val
;
287 case MSR_IA32_SYSENTER_EIP
:
288 env
->sysenter_eip
= val
;
290 case MSR_IA32_APICBASE
:
291 cpu_set_apic_base(x86_env_get_cpu(env
)->apic_state
, val
);
295 uint64_t update_mask
;
298 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_SYSCALL
) {
299 update_mask
|= MSR_EFER_SCE
;
301 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
302 update_mask
|= MSR_EFER_LME
;
304 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_FFXSR
) {
305 update_mask
|= MSR_EFER_FFXSR
;
307 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_NX
) {
308 update_mask
|= MSR_EFER_NXE
;
310 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
311 update_mask
|= MSR_EFER_SVME
;
313 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_FFXSR
) {
314 update_mask
|= MSR_EFER_FFXSR
;
316 cpu_load_efer(env
, (env
->efer
& ~update_mask
) |
317 (val
& update_mask
));
326 case MSR_VM_HSAVE_PA
:
340 env
->segs
[R_FS
].base
= val
;
343 env
->segs
[R_GS
].base
= val
;
345 case MSR_KERNELGSBASE
:
346 env
->kernelgsbase
= val
;
349 case MSR_MTRRphysBase(0):
350 case MSR_MTRRphysBase(1):
351 case MSR_MTRRphysBase(2):
352 case MSR_MTRRphysBase(3):
353 case MSR_MTRRphysBase(4):
354 case MSR_MTRRphysBase(5):
355 case MSR_MTRRphysBase(6):
356 case MSR_MTRRphysBase(7):
357 env
->mtrr_var
[((uint32_t)env
->regs
[R_ECX
] -
358 MSR_MTRRphysBase(0)) / 2].base
= val
;
360 case MSR_MTRRphysMask(0):
361 case MSR_MTRRphysMask(1):
362 case MSR_MTRRphysMask(2):
363 case MSR_MTRRphysMask(3):
364 case MSR_MTRRphysMask(4):
365 case MSR_MTRRphysMask(5):
366 case MSR_MTRRphysMask(6):
367 case MSR_MTRRphysMask(7):
368 env
->mtrr_var
[((uint32_t)env
->regs
[R_ECX
] -
369 MSR_MTRRphysMask(0)) / 2].mask
= val
;
371 case MSR_MTRRfix64K_00000
:
372 env
->mtrr_fixed
[(uint32_t)env
->regs
[R_ECX
] -
373 MSR_MTRRfix64K_00000
] = val
;
375 case MSR_MTRRfix16K_80000
:
376 case MSR_MTRRfix16K_A0000
:
377 env
->mtrr_fixed
[(uint32_t)env
->regs
[R_ECX
] -
378 MSR_MTRRfix16K_80000
+ 1] = val
;
380 case MSR_MTRRfix4K_C0000
:
381 case MSR_MTRRfix4K_C8000
:
382 case MSR_MTRRfix4K_D0000
:
383 case MSR_MTRRfix4K_D8000
:
384 case MSR_MTRRfix4K_E0000
:
385 case MSR_MTRRfix4K_E8000
:
386 case MSR_MTRRfix4K_F0000
:
387 case MSR_MTRRfix4K_F8000
:
388 env
->mtrr_fixed
[(uint32_t)env
->regs
[R_ECX
] -
389 MSR_MTRRfix4K_C0000
+ 3] = val
;
391 case MSR_MTRRdefType
:
392 env
->mtrr_deftype
= val
;
395 env
->mcg_status
= val
;
398 if ((env
->mcg_cap
& MCG_CTL_P
)
399 && (val
== 0 || val
== ~(uint64_t)0)) {
406 case MSR_IA32_MISC_ENABLE
:
407 env
->msr_ia32_misc_enable
= val
;
410 if ((uint32_t)env
->regs
[R_ECX
] >= MSR_MC0_CTL
411 && (uint32_t)env
->regs
[R_ECX
] < MSR_MC0_CTL
+
412 (4 * env
->mcg_cap
& 0xff)) {
413 uint32_t offset
= (uint32_t)env
->regs
[R_ECX
] - MSR_MC0_CTL
;
414 if ((offset
& 0x3) != 0
415 || (val
== 0 || val
== ~(uint64_t)0)) {
416 env
->mce_banks
[offset
] = val
;
420 /* XXX: exception? */
425 void helper_rdmsr(CPUX86State
*env
)
429 cpu_svm_check_intercept_param(env
, SVM_EXIT_MSR
, 0);
431 switch ((uint32_t)env
->regs
[R_ECX
]) {
432 case MSR_IA32_SYSENTER_CS
:
433 val
= env
->sysenter_cs
;
435 case MSR_IA32_SYSENTER_ESP
:
436 val
= env
->sysenter_esp
;
438 case MSR_IA32_SYSENTER_EIP
:
439 val
= env
->sysenter_eip
;
441 case MSR_IA32_APICBASE
:
442 val
= cpu_get_apic_base(x86_env_get_cpu(env
)->apic_state
);
453 case MSR_VM_HSAVE_PA
:
456 case MSR_IA32_PERF_STATUS
:
457 /* tsc_increment_by_tick */
460 val
|= (((uint64_t)4ULL) << 40);
473 val
= env
->segs
[R_FS
].base
;
476 val
= env
->segs
[R_GS
].base
;
478 case MSR_KERNELGSBASE
:
479 val
= env
->kernelgsbase
;
485 case MSR_MTRRphysBase(0):
486 case MSR_MTRRphysBase(1):
487 case MSR_MTRRphysBase(2):
488 case MSR_MTRRphysBase(3):
489 case MSR_MTRRphysBase(4):
490 case MSR_MTRRphysBase(5):
491 case MSR_MTRRphysBase(6):
492 case MSR_MTRRphysBase(7):
493 val
= env
->mtrr_var
[((uint32_t)env
->regs
[R_ECX
] -
494 MSR_MTRRphysBase(0)) / 2].base
;
496 case MSR_MTRRphysMask(0):
497 case MSR_MTRRphysMask(1):
498 case MSR_MTRRphysMask(2):
499 case MSR_MTRRphysMask(3):
500 case MSR_MTRRphysMask(4):
501 case MSR_MTRRphysMask(5):
502 case MSR_MTRRphysMask(6):
503 case MSR_MTRRphysMask(7):
504 val
= env
->mtrr_var
[((uint32_t)env
->regs
[R_ECX
] -
505 MSR_MTRRphysMask(0)) / 2].mask
;
507 case MSR_MTRRfix64K_00000
:
508 val
= env
->mtrr_fixed
[0];
510 case MSR_MTRRfix16K_80000
:
511 case MSR_MTRRfix16K_A0000
:
512 val
= env
->mtrr_fixed
[(uint32_t)env
->regs
[R_ECX
] -
513 MSR_MTRRfix16K_80000
+ 1];
515 case MSR_MTRRfix4K_C0000
:
516 case MSR_MTRRfix4K_C8000
:
517 case MSR_MTRRfix4K_D0000
:
518 case MSR_MTRRfix4K_D8000
:
519 case MSR_MTRRfix4K_E0000
:
520 case MSR_MTRRfix4K_E8000
:
521 case MSR_MTRRfix4K_F0000
:
522 case MSR_MTRRfix4K_F8000
:
523 val
= env
->mtrr_fixed
[(uint32_t)env
->regs
[R_ECX
] -
524 MSR_MTRRfix4K_C0000
+ 3];
526 case MSR_MTRRdefType
:
527 val
= env
->mtrr_deftype
;
530 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
531 val
= MSR_MTRRcap_VCNT
| MSR_MTRRcap_FIXRANGE_SUPPORT
|
532 MSR_MTRRcap_WC_SUPPORTED
;
534 /* XXX: exception? */
542 if (env
->mcg_cap
& MCG_CTL_P
) {
549 val
= env
->mcg_status
;
551 case MSR_IA32_MISC_ENABLE
:
552 val
= env
->msr_ia32_misc_enable
;
555 if ((uint32_t)env
->regs
[R_ECX
] >= MSR_MC0_CTL
556 && (uint32_t)env
->regs
[R_ECX
] < MSR_MC0_CTL
+
557 (4 * env
->mcg_cap
& 0xff)) {
558 uint32_t offset
= (uint32_t)env
->regs
[R_ECX
] - MSR_MC0_CTL
;
559 val
= env
->mce_banks
[offset
];
562 /* XXX: exception? */
566 env
->regs
[R_EAX
] = (uint32_t)(val
);
567 env
->regs
[R_EDX
] = (uint32_t)(val
>> 32);
571 static void QEMU_NORETURN
do_pause(X86CPU
*cpu
)
573 CPUState
*cs
= CPU(cpu
);
575 /* Just let another CPU run. */
576 cs
->exception_index
= EXCP_INTERRUPT
;
580 static void QEMU_NORETURN
do_hlt(X86CPU
*cpu
)
582 CPUState
*cs
= CPU(cpu
);
583 CPUX86State
*env
= &cpu
->env
;
585 env
->hflags
&= ~HF_INHIBIT_IRQ_MASK
; /* needed if sti is just before */
587 cs
->exception_index
= EXCP_HLT
;
591 void QEMU_NORETURN
helper_hlt(CPUX86State
*env
, int next_eip_addend
)
593 X86CPU
*cpu
= x86_env_get_cpu(env
);
595 cpu_svm_check_intercept_param(env
, SVM_EXIT_HLT
, 0);
596 env
->eip
+= next_eip_addend
;
601 void helper_monitor(CPUX86State
*env
, target_ulong ptr
)
603 if ((uint32_t)env
->regs
[R_ECX
] != 0) {
604 raise_exception(env
, EXCP0D_GPF
);
606 /* XXX: store address? */
607 cpu_svm_check_intercept_param(env
, SVM_EXIT_MONITOR
, 0);
610 void QEMU_NORETURN
helper_mwait(CPUX86State
*env
, int next_eip_addend
)
615 if ((uint32_t)env
->regs
[R_ECX
] != 0) {
616 raise_exception(env
, EXCP0D_GPF
);
618 cpu_svm_check_intercept_param(env
, SVM_EXIT_MWAIT
, 0);
619 env
->eip
+= next_eip_addend
;
621 cpu
= x86_env_get_cpu(env
);
623 /* XXX: not complete but not completely erroneous */
624 if (cs
->cpu_index
!= 0 || CPU_NEXT(cs
) != NULL
) {
631 void QEMU_NORETURN
helper_pause(CPUX86State
*env
, int next_eip_addend
)
633 X86CPU
*cpu
= x86_env_get_cpu(env
);
635 cpu_svm_check_intercept_param(env
, SVM_EXIT_PAUSE
, 0);
636 env
->eip
+= next_eip_addend
;
641 void QEMU_NORETURN
helper_debug(CPUX86State
*env
)
643 CPUState
*cs
= CPU(x86_env_get_cpu(env
));
645 cs
->exception_index
= EXCP_DEBUG
;