target/arm/translate-m-nocp.c

   1 /*
   2  *  ARM translation: M-profile NOCP special-case instructions
   3  *
   4  *  Copyright (c) 2020 Linaro, Ltd.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "tcg/tcg-op.h"
  22 #include "translate.h"
  23 #include "translate-a32.h"
  24
  25 #include "decode-m-nocp.c.inc"
  26
  27 /*
  28  * Decode VLLDM and VLSTM are nonstandard because:
  29  *  * if there is no FPU then these insns must NOP in
  30  *    Secure state and UNDEF in Nonsecure state
  31  *  * if there is an FPU then these insns do not have
  32  *    the usual behaviour that vfp_access_check() provides of
  33  *    being controlled by CPACR/NSACR enable bits or the
  34  *    lazy-stacking logic.
  35  */
  36 static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
  37 {
  38     TCGv_i32 fptr;
  39
  40     if (!arm_dc_feature(s, ARM_FEATURE_M) ||
  41         !arm_dc_feature(s, ARM_FEATURE_V8)) {
  42         return false;
  43     }
  44
  45     if (a->op) {
  46         /*
  47          * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
  48          * to take the IMPDEF option to make memory accesses to the stack
  49          * slots that correspond to the D16-D31 registers (discarding
  50          * read data and writing UNKNOWN values), so for us the T2
  51          * encoding behaves identically to the T1 encoding.
  52          */
  53         if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
  54             return false;
  55         }
  56     } else {
  57         /*
  58          * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
  59          * This is currently architecturally impossible, but we add the
  60          * check to stay in line with the pseudocode. Note that we must
  61          * emit code for the UNDEF so it takes precedence over the NOCP.
  62          */
  63         if (dc_isar_feature(aa32_simd_r32, s)) {
  64             unallocated_encoding(s);
  65             return true;
  66         }
  67     }
  68
  69     /*
  70      * If not secure, UNDEF. We must emit code for this
  71      * rather than returning false so that this takes
  72      * precedence over the m-nocp.decode NOCP fallback.
  73      */
  74     if (!s->v8m_secure) {
  75         unallocated_encoding(s);
  76         return true;
  77     }
  78     /* If no fpu, NOP. */
  79     if (!dc_isar_feature(aa32_vfp, s)) {
  80         return true;
  81     }
  82
  83     fptr = load_reg(s, a->rn);
  84     if (a->l) {
  85         gen_helper_v7m_vlldm(cpu_env, fptr);
  86     } else {
  87         gen_helper_v7m_vlstm(cpu_env, fptr);
  88     }
  89     tcg_temp_free_i32(fptr);
  90
  91     /* End the TB, because we have updated FP control bits */
  92     s->base.is_jmp = DISAS_UPDATE_EXIT;
  93     return true;
  94 }
  95
  96 static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
  97 {
  98     int btmreg, topreg;
  99     TCGv_i64 zero;
 100     TCGv_i32 aspen, sfpa;
 101
 102     if (!dc_isar_feature(aa32_m_sec_state, s)) {
 103         /* Before v8.1M, fall through in decode to NOCP check */
 104         return false;
 105     }
 106
 107     /* Explicitly UNDEF because this takes precedence over NOCP */
 108     if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
 109         unallocated_encoding(s);
 110         return true;
 111     }
 112
 113     if (!dc_isar_feature(aa32_vfp_simd, s)) {
 114         /* NOP if we have neither FP nor MVE */
 115         return true;
 116     }
 117
 118     /*
 119      * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
 120      * active floating point context so we must NOP (without doing
 121      * any lazy state preservation or the NOCP check).
 122      */
 123     aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
 124     sfpa = load_cpu_field(v7m.control[M_REG_S]);
 125     tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
 126     tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
 127     tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
 128     tcg_gen_or_i32(sfpa, sfpa, aspen);
 129     arm_gen_condlabel(s);
 130     tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
 131
 132     if (s->fp_excp_el != 0) {
 133         gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
 134                            syn_uncategorized(), s->fp_excp_el);
 135         return true;
 136     }
 137
 138     topreg = a->vd + a->imm - 1;
 139     btmreg = a->vd;
 140
 141     /* Convert to Sreg numbers if the insn specified in Dregs */
 142     if (a->size == 3) {
 143         topreg = topreg * 2 + 1;
 144         btmreg *= 2;
 145     }
 146
 147     if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
 148         /* UNPREDICTABLE: we choose to undef */
 149         unallocated_encoding(s);
 150         return true;
 151     }
 152
 153     /* Silently ignore requests to clear D16-D31 if they don't exist */
 154     if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
 155         topreg = 31;
 156     }
 157
 158     if (!vfp_access_check(s)) {
 159         return true;
 160     }
 161
 162     /* Zero the Sregs from btmreg to topreg inclusive. */
 163     zero = tcg_const_i64(0);
 164     if (btmreg & 1) {
 165         write_neon_element64(zero, btmreg >> 1, 1, MO_32);
 166         btmreg++;
 167     }
 168     for (; btmreg + 1 <= topreg; btmreg += 2) {
 169         write_neon_element64(zero, btmreg >> 1, 0, MO_64);
 170     }
 171     if (btmreg == topreg) {
 172         write_neon_element64(zero, btmreg >> 1, 0, MO_32);
 173         btmreg++;
 174     }
 175     assert(btmreg == topreg + 1);
 176     /* TODO: when MVE is implemented, zero VPR here */
 177     return true;
 178 }
 179
 180 static bool trans_NOCP(DisasContext *s, arg_nocp *a)
 181 {
 182     /*
 183      * Handle M-profile early check for disabled coprocessor:
 184      * all we need to do here is emit the NOCP exception if
 185      * the coprocessor is disabled. Otherwise we return false
 186      * and the real VFP/etc decode will handle the insn.
 187      */
 188     assert(arm_dc_feature(s, ARM_FEATURE_M));
 189
 190     if (a->cp == 11) {
 191         a->cp = 10;
 192     }
 193     if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
 194         (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
 195         /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
 196         a->cp = 10;
 197     }
 198
 199     if (a->cp != 10) {
 200         gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
 201                            syn_uncategorized(), default_exception_el(s));
 202         return true;
 203     }
 204
 205     if (s->fp_excp_el != 0) {
 206         gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
 207                            syn_uncategorized(), s->fp_excp_el);
 208         return true;
 209     }
 210
 211     return false;
 212 }
 213
 214 static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
 215 {
 216     /* This range needs a coprocessor check for v8.1M and later only */
 217     if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 218         return false;
 219     }
 220     return trans_NOCP(s, a);
 221 }