target/arm/cpu_tcg.c

   1 /*
   2  * QEMU ARM TCG CPUs.
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This code is licensed under the GNU GPL v2 or later.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "cpu.h"
  13 #ifdef CONFIG_TCG
  14 #include "hw/core/tcg-cpu-ops.h"
  15 #endif /* CONFIG_TCG */
  16 #include "internals.h"
  17 #include "target/arm/idau.h"
  18 #if !defined(CONFIG_USER_ONLY)
  19 #include "hw/boards.h"
  20 #endif
  21
  22 /* CPU models. These are not needed for the AArch64 linux-user build. */
  23 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
  24
  25 #ifdef CONFIG_TCG
  26 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  27 {
  28     CPUClass *cc = CPU_GET_CLASS(cs);
  29     ARMCPU *cpu = ARM_CPU(cs);
  30     CPUARMState *env = &cpu->env;
  31     bool ret = false;
  32
  33     /*
  34      * ARMv7-M interrupt masking works differently than -A or -R.
  35      * There is no FIQ/IRQ distinction. Instead of I and F bits
  36      * masking FIQ and IRQ interrupts, an exception is taken only
  37      * if it is higher priority than the current execution priority
  38      * (which depends on state like BASEPRI, FAULTMASK and the
  39      * currently active exception).
  40      */
  41     if (interrupt_request & CPU_INTERRUPT_HARD
  42         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
  43         cs->exception_index = EXCP_IRQ;
  44         cc->tcg_ops->do_interrupt(cs);
  45         ret = true;
  46     }
  47     return ret;
  48 }
  49 #endif /* CONFIG_TCG */
  50
  51 static void arm926_initfn(Object *obj)
  52 {
  53     ARMCPU *cpu = ARM_CPU(obj);
  54
  55     cpu->dtb_compatible = "arm,arm926";
  56     set_feature(&cpu->env, ARM_FEATURE_V5);
  57     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  58     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
  59     cpu->midr = 0x41069265;
  60     cpu->reset_fpsid = 0x41011090;
  61     cpu->ctr = 0x1dd20d2;
  62     cpu->reset_sctlr = 0x00090078;
  63
  64     /*
  65      * ARMv5 does not have the ID_ISAR registers, but we can still
  66      * set the field to indicate Jazelle support within QEMU.
  67      */
  68     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
  69     /*
  70      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
  71      * support even though ARMv5 doesn't have this register.
  72      */
  73     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
  74     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
  75     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
  76 }
  77
  78 static void arm946_initfn(Object *obj)
  79 {
  80     ARMCPU *cpu = ARM_CPU(obj);
  81
  82     cpu->dtb_compatible = "arm,arm946";
  83     set_feature(&cpu->env, ARM_FEATURE_V5);
  84     set_feature(&cpu->env, ARM_FEATURE_PMSA);
  85     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  86     cpu->midr = 0x41059461;
  87     cpu->ctr = 0x0f004006;
  88     cpu->reset_sctlr = 0x00000078;
  89 }
  90
  91 static void arm1026_initfn(Object *obj)
  92 {
  93     ARMCPU *cpu = ARM_CPU(obj);
  94
  95     cpu->dtb_compatible = "arm,arm1026";
  96     set_feature(&cpu->env, ARM_FEATURE_V5);
  97     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
  98     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  99     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 100     cpu->midr = 0x4106a262;
 101     cpu->reset_fpsid = 0x410110a0;
 102     cpu->ctr = 0x1dd20d2;
 103     cpu->reset_sctlr = 0x00090078;
 104     cpu->reset_auxcr = 1;
 105
 106     /*
 107      * ARMv5 does not have the ID_ISAR registers, but we can still
 108      * set the field to indicate Jazelle support within QEMU.
 109      */
 110     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 111     /*
 112      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 113      * support even though ARMv5 doesn't have this register.
 114      */
 115     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 116     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 117     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 118
 119     {
 120         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 121         ARMCPRegInfo ifar = {
 122             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 123             .access = PL1_RW,
 124             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 125             .resetvalue = 0
 126         };
 127         define_one_arm_cp_reg(cpu, &ifar);
 128     }
 129 }
 130
 131 static void arm1136_r2_initfn(Object *obj)
 132 {
 133     ARMCPU *cpu = ARM_CPU(obj);
 134     /*
 135      * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 136      * older core than plain "arm1136". In particular this does not
 137      * have the v6K features.
 138      * These ID register values are correct for 1136 but may be wrong
 139      * for 1136_r2 (in particular r0p2 does not actually implement most
 140      * of the ID registers).
 141      */
 142
 143     cpu->dtb_compatible = "arm,arm1136";
 144     set_feature(&cpu->env, ARM_FEATURE_V6);
 145     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 146     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 147     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 148     cpu->midr = 0x4107b362;
 149     cpu->reset_fpsid = 0x410120b4;
 150     cpu->isar.mvfr0 = 0x11111111;
 151     cpu->isar.mvfr1 = 0x00000000;
 152     cpu->ctr = 0x1dd20d2;
 153     cpu->reset_sctlr = 0x00050078;
 154     cpu->isar.id_pfr0 = 0x111;
 155     cpu->isar.id_pfr1 = 0x1;
 156     cpu->isar.id_dfr0 = 0x2;
 157     cpu->id_afr0 = 0x3;
 158     cpu->isar.id_mmfr0 = 0x01130003;
 159     cpu->isar.id_mmfr1 = 0x10030302;
 160     cpu->isar.id_mmfr2 = 0x01222110;
 161     cpu->isar.id_isar0 = 0x00140011;
 162     cpu->isar.id_isar1 = 0x12002111;
 163     cpu->isar.id_isar2 = 0x11231111;
 164     cpu->isar.id_isar3 = 0x01102131;
 165     cpu->isar.id_isar4 = 0x141;
 166     cpu->reset_auxcr = 7;
 167 }
 168
 169 static void arm1136_initfn(Object *obj)
 170 {
 171     ARMCPU *cpu = ARM_CPU(obj);
 172
 173     cpu->dtb_compatible = "arm,arm1136";
 174     set_feature(&cpu->env, ARM_FEATURE_V6K);
 175     set_feature(&cpu->env, ARM_FEATURE_V6);
 176     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 177     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 178     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 179     cpu->midr = 0x4117b363;
 180     cpu->reset_fpsid = 0x410120b4;
 181     cpu->isar.mvfr0 = 0x11111111;
 182     cpu->isar.mvfr1 = 0x00000000;
 183     cpu->ctr = 0x1dd20d2;
 184     cpu->reset_sctlr = 0x00050078;
 185     cpu->isar.id_pfr0 = 0x111;
 186     cpu->isar.id_pfr1 = 0x1;
 187     cpu->isar.id_dfr0 = 0x2;
 188     cpu->id_afr0 = 0x3;
 189     cpu->isar.id_mmfr0 = 0x01130003;
 190     cpu->isar.id_mmfr1 = 0x10030302;
 191     cpu->isar.id_mmfr2 = 0x01222110;
 192     cpu->isar.id_isar0 = 0x00140011;
 193     cpu->isar.id_isar1 = 0x12002111;
 194     cpu->isar.id_isar2 = 0x11231111;
 195     cpu->isar.id_isar3 = 0x01102131;
 196     cpu->isar.id_isar4 = 0x141;
 197     cpu->reset_auxcr = 7;
 198 }
 199
 200 static void arm1176_initfn(Object *obj)
 201 {
 202     ARMCPU *cpu = ARM_CPU(obj);
 203
 204     cpu->dtb_compatible = "arm,arm1176";
 205     set_feature(&cpu->env, ARM_FEATURE_V6K);
 206     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 207     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 208     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 209     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 210     set_feature(&cpu->env, ARM_FEATURE_EL3);
 211     cpu->midr = 0x410fb767;
 212     cpu->reset_fpsid = 0x410120b5;
 213     cpu->isar.mvfr0 = 0x11111111;
 214     cpu->isar.mvfr1 = 0x00000000;
 215     cpu->ctr = 0x1dd20d2;
 216     cpu->reset_sctlr = 0x00050078;
 217     cpu->isar.id_pfr0 = 0x111;
 218     cpu->isar.id_pfr1 = 0x11;
 219     cpu->isar.id_dfr0 = 0x33;
 220     cpu->id_afr0 = 0;
 221     cpu->isar.id_mmfr0 = 0x01130003;
 222     cpu->isar.id_mmfr1 = 0x10030302;
 223     cpu->isar.id_mmfr2 = 0x01222100;
 224     cpu->isar.id_isar0 = 0x0140011;
 225     cpu->isar.id_isar1 = 0x12002111;
 226     cpu->isar.id_isar2 = 0x11231121;
 227     cpu->isar.id_isar3 = 0x01102131;
 228     cpu->isar.id_isar4 = 0x01141;
 229     cpu->reset_auxcr = 7;
 230 }
 231
 232 static void arm11mpcore_initfn(Object *obj)
 233 {
 234     ARMCPU *cpu = ARM_CPU(obj);
 235
 236     cpu->dtb_compatible = "arm,arm11mpcore";
 237     set_feature(&cpu->env, ARM_FEATURE_V6K);
 238     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 239     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 240     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 241     cpu->midr = 0x410fb022;
 242     cpu->reset_fpsid = 0x410120b4;
 243     cpu->isar.mvfr0 = 0x11111111;
 244     cpu->isar.mvfr1 = 0x00000000;
 245     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 246     cpu->isar.id_pfr0 = 0x111;
 247     cpu->isar.id_pfr1 = 0x1;
 248     cpu->isar.id_dfr0 = 0;
 249     cpu->id_afr0 = 0x2;
 250     cpu->isar.id_mmfr0 = 0x01100103;
 251     cpu->isar.id_mmfr1 = 0x10020302;
 252     cpu->isar.id_mmfr2 = 0x01222000;
 253     cpu->isar.id_isar0 = 0x00100011;
 254     cpu->isar.id_isar1 = 0x12002111;
 255     cpu->isar.id_isar2 = 0x11221011;
 256     cpu->isar.id_isar3 = 0x01102131;
 257     cpu->isar.id_isar4 = 0x141;
 258     cpu->reset_auxcr = 1;
 259 }
 260
 261 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 262     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 263       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 264     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 265       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 266     REGINFO_SENTINEL
 267 };
 268
 269 static void cortex_a8_initfn(Object *obj)
 270 {
 271     ARMCPU *cpu = ARM_CPU(obj);
 272
 273     cpu->dtb_compatible = "arm,cortex-a8";
 274     set_feature(&cpu->env, ARM_FEATURE_V7);
 275     set_feature(&cpu->env, ARM_FEATURE_NEON);
 276     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 277     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 278     set_feature(&cpu->env, ARM_FEATURE_EL3);
 279     cpu->midr = 0x410fc080;
 280     cpu->reset_fpsid = 0x410330c0;
 281     cpu->isar.mvfr0 = 0x11110222;
 282     cpu->isar.mvfr1 = 0x00011111;
 283     cpu->ctr = 0x82048004;
 284     cpu->reset_sctlr = 0x00c50078;
 285     cpu->isar.id_pfr0 = 0x1031;
 286     cpu->isar.id_pfr1 = 0x11;
 287     cpu->isar.id_dfr0 = 0x400;
 288     cpu->id_afr0 = 0;
 289     cpu->isar.id_mmfr0 = 0x31100003;
 290     cpu->isar.id_mmfr1 = 0x20000000;
 291     cpu->isar.id_mmfr2 = 0x01202000;
 292     cpu->isar.id_mmfr3 = 0x11;
 293     cpu->isar.id_isar0 = 0x00101111;
 294     cpu->isar.id_isar1 = 0x12112111;
 295     cpu->isar.id_isar2 = 0x21232031;
 296     cpu->isar.id_isar3 = 0x11112131;
 297     cpu->isar.id_isar4 = 0x00111142;
 298     cpu->isar.dbgdidr = 0x15141000;
 299     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 300     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 301     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 302     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 303     cpu->reset_auxcr = 2;
 304     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 305 }
 306
 307 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 308     /*
 309      * power_control should be set to maximum latency. Again,
 310      * default to 0 and set by private hook
 311      */
 312     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 313       .access = PL1_RW, .resetvalue = 0,
 314       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 315     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 316       .access = PL1_RW, .resetvalue = 0,
 317       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 318     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 319       .access = PL1_RW, .resetvalue = 0,
 320       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 321     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 322       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 323     /* TLB lockdown control */
 324     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 325       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 326     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 327       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 328     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 329       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 330     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 331       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 332     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 333       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 334     REGINFO_SENTINEL
 335 };
 336
 337 static void cortex_a9_initfn(Object *obj)
 338 {
 339     ARMCPU *cpu = ARM_CPU(obj);
 340
 341     cpu->dtb_compatible = "arm,cortex-a9";
 342     set_feature(&cpu->env, ARM_FEATURE_V7);
 343     set_feature(&cpu->env, ARM_FEATURE_NEON);
 344     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 345     set_feature(&cpu->env, ARM_FEATURE_EL3);
 346     /*
 347      * Note that A9 supports the MP extensions even for
 348      * A9UP and single-core A9MP (which are both different
 349      * and valid configurations; we don't model A9UP).
 350      */
 351     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 352     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 353     cpu->midr = 0x410fc090;
 354     cpu->reset_fpsid = 0x41033090;
 355     cpu->isar.mvfr0 = 0x11110222;
 356     cpu->isar.mvfr1 = 0x01111111;
 357     cpu->ctr = 0x80038003;
 358     cpu->reset_sctlr = 0x00c50078;
 359     cpu->isar.id_pfr0 = 0x1031;
 360     cpu->isar.id_pfr1 = 0x11;
 361     cpu->isar.id_dfr0 = 0x000;
 362     cpu->id_afr0 = 0;
 363     cpu->isar.id_mmfr0 = 0x00100103;
 364     cpu->isar.id_mmfr1 = 0x20000000;
 365     cpu->isar.id_mmfr2 = 0x01230000;
 366     cpu->isar.id_mmfr3 = 0x00002111;
 367     cpu->isar.id_isar0 = 0x00101111;
 368     cpu->isar.id_isar1 = 0x13112111;
 369     cpu->isar.id_isar2 = 0x21232041;
 370     cpu->isar.id_isar3 = 0x11112131;
 371     cpu->isar.id_isar4 = 0x00111142;
 372     cpu->isar.dbgdidr = 0x35141000;
 373     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 374     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 375     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 376     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 377 }
 378
 379 #ifndef CONFIG_USER_ONLY
 380 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 381 {
 382     MachineState *ms = MACHINE(qdev_get_machine());
 383
 384     /*
 385      * Linux wants the number of processors from here.
 386      * Might as well set the interrupt-controller bit too.
 387      */
 388     return ((ms->smp.cpus - 1) << 24) | (1 << 23);
 389 }
 390 #endif
 391
 392 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 393 #ifndef CONFIG_USER_ONLY
 394     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 395       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 396       .writefn = arm_cp_write_ignore, },
 397 #endif
 398     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 399       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 400     REGINFO_SENTINEL
 401 };
 402
 403 static void cortex_a7_initfn(Object *obj)
 404 {
 405     ARMCPU *cpu = ARM_CPU(obj);
 406
 407     cpu->dtb_compatible = "arm,cortex-a7";
 408     set_feature(&cpu->env, ARM_FEATURE_V7VE);
 409     set_feature(&cpu->env, ARM_FEATURE_NEON);
 410     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 411     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 412     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 413     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 414     set_feature(&cpu->env, ARM_FEATURE_EL2);
 415     set_feature(&cpu->env, ARM_FEATURE_EL3);
 416     set_feature(&cpu->env, ARM_FEATURE_PMU);
 417     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
 418     cpu->midr = 0x410fc075;
 419     cpu->reset_fpsid = 0x41023075;
 420     cpu->isar.mvfr0 = 0x10110222;
 421     cpu->isar.mvfr1 = 0x11111111;
 422     cpu->ctr = 0x84448003;
 423     cpu->reset_sctlr = 0x00c50078;
 424     cpu->isar.id_pfr0 = 0x00001131;
 425     cpu->isar.id_pfr1 = 0x00011011;
 426     cpu->isar.id_dfr0 = 0x02010555;
 427     cpu->id_afr0 = 0x00000000;
 428     cpu->isar.id_mmfr0 = 0x10101105;
 429     cpu->isar.id_mmfr1 = 0x40000000;
 430     cpu->isar.id_mmfr2 = 0x01240000;
 431     cpu->isar.id_mmfr3 = 0x02102211;
 432     /*
 433      * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
 434      * table 4-41 gives 0x02101110, which includes the arm div insns.
 435      */
 436     cpu->isar.id_isar0 = 0x02101110;
 437     cpu->isar.id_isar1 = 0x13112111;
 438     cpu->isar.id_isar2 = 0x21232041;
 439     cpu->isar.id_isar3 = 0x11112131;
 440     cpu->isar.id_isar4 = 0x10011142;
 441     cpu->isar.dbgdidr = 0x3515f005;
 442     cpu->clidr = 0x0a200023;
 443     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 444     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 445     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 446     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
 447 }
 448
 449 static void cortex_a15_initfn(Object *obj)
 450 {
 451     ARMCPU *cpu = ARM_CPU(obj);
 452
 453     cpu->dtb_compatible = "arm,cortex-a15";
 454     set_feature(&cpu->env, ARM_FEATURE_V7VE);
 455     set_feature(&cpu->env, ARM_FEATURE_NEON);
 456     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 457     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 458     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 459     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 460     set_feature(&cpu->env, ARM_FEATURE_EL2);
 461     set_feature(&cpu->env, ARM_FEATURE_EL3);
 462     set_feature(&cpu->env, ARM_FEATURE_PMU);
 463     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 464     cpu->midr = 0x412fc0f1;
 465     cpu->reset_fpsid = 0x410430f0;
 466     cpu->isar.mvfr0 = 0x10110222;
 467     cpu->isar.mvfr1 = 0x11111111;
 468     cpu->ctr = 0x8444c004;
 469     cpu->reset_sctlr = 0x00c50078;
 470     cpu->isar.id_pfr0 = 0x00001131;
 471     cpu->isar.id_pfr1 = 0x00011011;
 472     cpu->isar.id_dfr0 = 0x02010555;
 473     cpu->id_afr0 = 0x00000000;
 474     cpu->isar.id_mmfr0 = 0x10201105;
 475     cpu->isar.id_mmfr1 = 0x20000000;
 476     cpu->isar.id_mmfr2 = 0x01240000;
 477     cpu->isar.id_mmfr3 = 0x02102211;
 478     cpu->isar.id_isar0 = 0x02101110;
 479     cpu->isar.id_isar1 = 0x13112111;
 480     cpu->isar.id_isar2 = 0x21232041;
 481     cpu->isar.id_isar3 = 0x11112131;
 482     cpu->isar.id_isar4 = 0x10011142;
 483     cpu->isar.dbgdidr = 0x3515f021;
 484     cpu->clidr = 0x0a200023;
 485     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 486     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 487     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 488     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 489 }
 490
 491 static void cortex_m0_initfn(Object *obj)
 492 {
 493     ARMCPU *cpu = ARM_CPU(obj);
 494     set_feature(&cpu->env, ARM_FEATURE_V6);
 495     set_feature(&cpu->env, ARM_FEATURE_M);
 496
 497     cpu->midr = 0x410cc200;
 498
 499     /*
 500      * These ID register values are not guest visible, because
 501      * we do not implement the Main Extension. They must be set
 502      * to values corresponding to the Cortex-M0's implemented
 503      * features, because QEMU generally controls its emulation
 504      * by looking at ID register fields. We use the same values as
 505      * for the M3.
 506      */
 507     cpu->isar.id_pfr0 = 0x00000030;
 508     cpu->isar.id_pfr1 = 0x00000200;
 509     cpu->isar.id_dfr0 = 0x00100000;
 510     cpu->id_afr0 = 0x00000000;
 511     cpu->isar.id_mmfr0 = 0x00000030;
 512     cpu->isar.id_mmfr1 = 0x00000000;
 513     cpu->isar.id_mmfr2 = 0x00000000;
 514     cpu->isar.id_mmfr3 = 0x00000000;
 515     cpu->isar.id_isar0 = 0x01141110;
 516     cpu->isar.id_isar1 = 0x02111000;
 517     cpu->isar.id_isar2 = 0x21112231;
 518     cpu->isar.id_isar3 = 0x01111110;
 519     cpu->isar.id_isar4 = 0x01310102;
 520     cpu->isar.id_isar5 = 0x00000000;
 521     cpu->isar.id_isar6 = 0x00000000;
 522 }
 523
 524 static void cortex_m3_initfn(Object *obj)
 525 {
 526     ARMCPU *cpu = ARM_CPU(obj);
 527     set_feature(&cpu->env, ARM_FEATURE_V7);
 528     set_feature(&cpu->env, ARM_FEATURE_M);
 529     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 530     cpu->midr = 0x410fc231;
 531     cpu->pmsav7_dregion = 8;
 532     cpu->isar.id_pfr0 = 0x00000030;
 533     cpu->isar.id_pfr1 = 0x00000200;
 534     cpu->isar.id_dfr0 = 0x00100000;
 535     cpu->id_afr0 = 0x00000000;
 536     cpu->isar.id_mmfr0 = 0x00000030;
 537     cpu->isar.id_mmfr1 = 0x00000000;
 538     cpu->isar.id_mmfr2 = 0x00000000;
 539     cpu->isar.id_mmfr3 = 0x00000000;
 540     cpu->isar.id_isar0 = 0x01141110;
 541     cpu->isar.id_isar1 = 0x02111000;
 542     cpu->isar.id_isar2 = 0x21112231;
 543     cpu->isar.id_isar3 = 0x01111110;
 544     cpu->isar.id_isar4 = 0x01310102;
 545     cpu->isar.id_isar5 = 0x00000000;
 546     cpu->isar.id_isar6 = 0x00000000;
 547 }
 548
 549 static void cortex_m4_initfn(Object *obj)
 550 {
 551     ARMCPU *cpu = ARM_CPU(obj);
 552
 553     set_feature(&cpu->env, ARM_FEATURE_V7);
 554     set_feature(&cpu->env, ARM_FEATURE_M);
 555     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 556     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 557     cpu->midr = 0x410fc240; /* r0p0 */
 558     cpu->pmsav7_dregion = 8;
 559     cpu->isar.mvfr0 = 0x10110021;
 560     cpu->isar.mvfr1 = 0x11000011;
 561     cpu->isar.mvfr2 = 0x00000000;
 562     cpu->isar.id_pfr0 = 0x00000030;
 563     cpu->isar.id_pfr1 = 0x00000200;
 564     cpu->isar.id_dfr0 = 0x00100000;
 565     cpu->id_afr0 = 0x00000000;
 566     cpu->isar.id_mmfr0 = 0x00000030;
 567     cpu->isar.id_mmfr1 = 0x00000000;
 568     cpu->isar.id_mmfr2 = 0x00000000;
 569     cpu->isar.id_mmfr3 = 0x00000000;
 570     cpu->isar.id_isar0 = 0x01141110;
 571     cpu->isar.id_isar1 = 0x02111000;
 572     cpu->isar.id_isar2 = 0x21112231;
 573     cpu->isar.id_isar3 = 0x01111110;
 574     cpu->isar.id_isar4 = 0x01310102;
 575     cpu->isar.id_isar5 = 0x00000000;
 576     cpu->isar.id_isar6 = 0x00000000;
 577 }
 578
 579 static void cortex_m7_initfn(Object *obj)
 580 {
 581     ARMCPU *cpu = ARM_CPU(obj);
 582
 583     set_feature(&cpu->env, ARM_FEATURE_V7);
 584     set_feature(&cpu->env, ARM_FEATURE_M);
 585     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 586     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 587     cpu->midr = 0x411fc272; /* r1p2 */
 588     cpu->pmsav7_dregion = 8;
 589     cpu->isar.mvfr0 = 0x10110221;
 590     cpu->isar.mvfr1 = 0x12000011;
 591     cpu->isar.mvfr2 = 0x00000040;
 592     cpu->isar.id_pfr0 = 0x00000030;
 593     cpu->isar.id_pfr1 = 0x00000200;
 594     cpu->isar.id_dfr0 = 0x00100000;
 595     cpu->id_afr0 = 0x00000000;
 596     cpu->isar.id_mmfr0 = 0x00100030;
 597     cpu->isar.id_mmfr1 = 0x00000000;
 598     cpu->isar.id_mmfr2 = 0x01000000;
 599     cpu->isar.id_mmfr3 = 0x00000000;
 600     cpu->isar.id_isar0 = 0x01101110;
 601     cpu->isar.id_isar1 = 0x02112000;
 602     cpu->isar.id_isar2 = 0x20232231;
 603     cpu->isar.id_isar3 = 0x01111131;
 604     cpu->isar.id_isar4 = 0x01310132;
 605     cpu->isar.id_isar5 = 0x00000000;
 606     cpu->isar.id_isar6 = 0x00000000;
 607 }
 608
 609 static void cortex_m33_initfn(Object *obj)
 610 {
 611     ARMCPU *cpu = ARM_CPU(obj);
 612
 613     set_feature(&cpu->env, ARM_FEATURE_V8);
 614     set_feature(&cpu->env, ARM_FEATURE_M);
 615     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 616     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 617     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 618     cpu->midr = 0x410fd213; /* r0p3 */
 619     cpu->pmsav7_dregion = 16;
 620     cpu->sau_sregion = 8;
 621     cpu->isar.mvfr0 = 0x10110021;
 622     cpu->isar.mvfr1 = 0x11000011;
 623     cpu->isar.mvfr2 = 0x00000040;
 624     cpu->isar.id_pfr0 = 0x00000030;
 625     cpu->isar.id_pfr1 = 0x00000210;
 626     cpu->isar.id_dfr0 = 0x00200000;
 627     cpu->id_afr0 = 0x00000000;
 628     cpu->isar.id_mmfr0 = 0x00101F40;
 629     cpu->isar.id_mmfr1 = 0x00000000;
 630     cpu->isar.id_mmfr2 = 0x01000000;
 631     cpu->isar.id_mmfr3 = 0x00000000;
 632     cpu->isar.id_isar0 = 0x01101110;
 633     cpu->isar.id_isar1 = 0x02212000;
 634     cpu->isar.id_isar2 = 0x20232232;
 635     cpu->isar.id_isar3 = 0x01111131;
 636     cpu->isar.id_isar4 = 0x01310132;
 637     cpu->isar.id_isar5 = 0x00000000;
 638     cpu->isar.id_isar6 = 0x00000000;
 639     cpu->clidr = 0x00000000;
 640     cpu->ctr = 0x8000c000;
 641 }
 642
 643 static void cortex_m55_initfn(Object *obj)
 644 {
 645     ARMCPU *cpu = ARM_CPU(obj);
 646
 647     set_feature(&cpu->env, ARM_FEATURE_V8);
 648     set_feature(&cpu->env, ARM_FEATURE_V8_1M);
 649     set_feature(&cpu->env, ARM_FEATURE_M);
 650     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 651     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 652     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 653     cpu->midr = 0x410fd221; /* r0p1 */
 654     cpu->revidr = 0;
 655     cpu->pmsav7_dregion = 16;
 656     cpu->sau_sregion = 8;
 657     /*
 658      * These are the MVFR* values for the FPU, no MVE configuration;
 659      * we will update them later when we implement MVE
 660      */
 661     cpu->isar.mvfr0 = 0x10110221;
 662     cpu->isar.mvfr1 = 0x12100011;
 663     cpu->isar.mvfr2 = 0x00000040;
 664     cpu->isar.id_pfr0 = 0x20000030;
 665     cpu->isar.id_pfr1 = 0x00000230;
 666     cpu->isar.id_dfr0 = 0x10200000;
 667     cpu->id_afr0 = 0x00000000;
 668     cpu->isar.id_mmfr0 = 0x00111040;
 669     cpu->isar.id_mmfr1 = 0x00000000;
 670     cpu->isar.id_mmfr2 = 0x01000000;
 671     cpu->isar.id_mmfr3 = 0x00000011;
 672     cpu->isar.id_isar0 = 0x01103110;
 673     cpu->isar.id_isar1 = 0x02212000;
 674     cpu->isar.id_isar2 = 0x20232232;
 675     cpu->isar.id_isar3 = 0x01111131;
 676     cpu->isar.id_isar4 = 0x01310132;
 677     cpu->isar.id_isar5 = 0x00000000;
 678     cpu->isar.id_isar6 = 0x00000000;
 679     cpu->clidr = 0x00000000; /* caches not implemented */
 680     cpu->ctr = 0x8303c003;
 681 }
 682
 683 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 684     /* Dummy the TCM region regs for the moment */
 685     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 686       .access = PL1_RW, .type = ARM_CP_CONST },
 687     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 688       .access = PL1_RW, .type = ARM_CP_CONST },
 689     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
 690       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 691     REGINFO_SENTINEL
 692 };
 693
 694 static void cortex_r5_initfn(Object *obj)
 695 {
 696     ARMCPU *cpu = ARM_CPU(obj);
 697
 698     set_feature(&cpu->env, ARM_FEATURE_V7);
 699     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 700     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 701     set_feature(&cpu->env, ARM_FEATURE_PMU);
 702     cpu->midr = 0x411fc153; /* r1p3 */
 703     cpu->isar.id_pfr0 = 0x0131;
 704     cpu->isar.id_pfr1 = 0x001;
 705     cpu->isar.id_dfr0 = 0x010400;
 706     cpu->id_afr0 = 0x0;
 707     cpu->isar.id_mmfr0 = 0x0210030;
 708     cpu->isar.id_mmfr1 = 0x00000000;
 709     cpu->isar.id_mmfr2 = 0x01200000;
 710     cpu->isar.id_mmfr3 = 0x0211;
 711     cpu->isar.id_isar0 = 0x02101111;
 712     cpu->isar.id_isar1 = 0x13112111;
 713     cpu->isar.id_isar2 = 0x21232141;
 714     cpu->isar.id_isar3 = 0x01112131;
 715     cpu->isar.id_isar4 = 0x0010142;
 716     cpu->isar.id_isar5 = 0x0;
 717     cpu->isar.id_isar6 = 0x0;
 718     cpu->mp_is_up = true;
 719     cpu->pmsav7_dregion = 16;
 720     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 721 }
 722
 723 static void cortex_r5f_initfn(Object *obj)
 724 {
 725     ARMCPU *cpu = ARM_CPU(obj);
 726
 727     cortex_r5_initfn(obj);
 728     cpu->isar.mvfr0 = 0x10110221;
 729     cpu->isar.mvfr1 = 0x00000011;
 730 }
 731
 732 static void ti925t_initfn(Object *obj)
 733 {
 734     ARMCPU *cpu = ARM_CPU(obj);
 735     set_feature(&cpu->env, ARM_FEATURE_V4T);
 736     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 737     cpu->midr = ARM_CPUID_TI925T;
 738     cpu->ctr = 0x5109149;
 739     cpu->reset_sctlr = 0x00000070;
 740 }
 741
 742 static void sa1100_initfn(Object *obj)
 743 {
 744     ARMCPU *cpu = ARM_CPU(obj);
 745
 746     cpu->dtb_compatible = "intel,sa1100";
 747     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 748     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 749     cpu->midr = 0x4401A11B;
 750     cpu->reset_sctlr = 0x00000070;
 751 }
 752
 753 static void sa1110_initfn(Object *obj)
 754 {
 755     ARMCPU *cpu = ARM_CPU(obj);
 756     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 757     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 758     cpu->midr = 0x6901B119;
 759     cpu->reset_sctlr = 0x00000070;
 760 }
 761
 762 static void pxa250_initfn(Object *obj)
 763 {
 764     ARMCPU *cpu = ARM_CPU(obj);
 765
 766     cpu->dtb_compatible = "marvell,xscale";
 767     set_feature(&cpu->env, ARM_FEATURE_V5);
 768     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 769     cpu->midr = 0x69052100;
 770     cpu->ctr = 0xd172172;
 771     cpu->reset_sctlr = 0x00000078;
 772 }
 773
 774 static void pxa255_initfn(Object *obj)
 775 {
 776     ARMCPU *cpu = ARM_CPU(obj);
 777
 778     cpu->dtb_compatible = "marvell,xscale";
 779     set_feature(&cpu->env, ARM_FEATURE_V5);
 780     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 781     cpu->midr = 0x69052d00;
 782     cpu->ctr = 0xd172172;
 783     cpu->reset_sctlr = 0x00000078;
 784 }
 785
 786 static void pxa260_initfn(Object *obj)
 787 {
 788     ARMCPU *cpu = ARM_CPU(obj);
 789
 790     cpu->dtb_compatible = "marvell,xscale";
 791     set_feature(&cpu->env, ARM_FEATURE_V5);
 792     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 793     cpu->midr = 0x69052903;
 794     cpu->ctr = 0xd172172;
 795     cpu->reset_sctlr = 0x00000078;
 796 }
 797
 798 static void pxa261_initfn(Object *obj)
 799 {
 800     ARMCPU *cpu = ARM_CPU(obj);
 801
 802     cpu->dtb_compatible = "marvell,xscale";
 803     set_feature(&cpu->env, ARM_FEATURE_V5);
 804     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 805     cpu->midr = 0x69052d05;
 806     cpu->ctr = 0xd172172;
 807     cpu->reset_sctlr = 0x00000078;
 808 }
 809
 810 static void pxa262_initfn(Object *obj)
 811 {
 812     ARMCPU *cpu = ARM_CPU(obj);
 813
 814     cpu->dtb_compatible = "marvell,xscale";
 815     set_feature(&cpu->env, ARM_FEATURE_V5);
 816     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 817     cpu->midr = 0x69052d06;
 818     cpu->ctr = 0xd172172;
 819     cpu->reset_sctlr = 0x00000078;
 820 }
 821
 822 static void pxa270a0_initfn(Object *obj)
 823 {
 824     ARMCPU *cpu = ARM_CPU(obj);
 825
 826     cpu->dtb_compatible = "marvell,xscale";
 827     set_feature(&cpu->env, ARM_FEATURE_V5);
 828     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 829     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 830     cpu->midr = 0x69054110;
 831     cpu->ctr = 0xd172172;
 832     cpu->reset_sctlr = 0x00000078;
 833 }
 834
 835 static void pxa270a1_initfn(Object *obj)
 836 {
 837     ARMCPU *cpu = ARM_CPU(obj);
 838
 839     cpu->dtb_compatible = "marvell,xscale";
 840     set_feature(&cpu->env, ARM_FEATURE_V5);
 841     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 842     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 843     cpu->midr = 0x69054111;
 844     cpu->ctr = 0xd172172;
 845     cpu->reset_sctlr = 0x00000078;
 846 }
 847
 848 static void pxa270b0_initfn(Object *obj)
 849 {
 850     ARMCPU *cpu = ARM_CPU(obj);
 851
 852     cpu->dtb_compatible = "marvell,xscale";
 853     set_feature(&cpu->env, ARM_FEATURE_V5);
 854     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 855     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 856     cpu->midr = 0x69054112;
 857     cpu->ctr = 0xd172172;
 858     cpu->reset_sctlr = 0x00000078;
 859 }
 860
 861 static void pxa270b1_initfn(Object *obj)
 862 {
 863     ARMCPU *cpu = ARM_CPU(obj);
 864
 865     cpu->dtb_compatible = "marvell,xscale";
 866     set_feature(&cpu->env, ARM_FEATURE_V5);
 867     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 868     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 869     cpu->midr = 0x69054113;
 870     cpu->ctr = 0xd172172;
 871     cpu->reset_sctlr = 0x00000078;
 872 }
 873
 874 static void pxa270c0_initfn(Object *obj)
 875 {
 876     ARMCPU *cpu = ARM_CPU(obj);
 877
 878     cpu->dtb_compatible = "marvell,xscale";
 879     set_feature(&cpu->env, ARM_FEATURE_V5);
 880     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 881     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 882     cpu->midr = 0x69054114;
 883     cpu->ctr = 0xd172172;
 884     cpu->reset_sctlr = 0x00000078;
 885 }
 886
 887 static void pxa270c5_initfn(Object *obj)
 888 {
 889     ARMCPU *cpu = ARM_CPU(obj);
 890
 891     cpu->dtb_compatible = "marvell,xscale";
 892     set_feature(&cpu->env, ARM_FEATURE_V5);
 893     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 894     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 895     cpu->midr = 0x69054117;
 896     cpu->ctr = 0xd172172;
 897     cpu->reset_sctlr = 0x00000078;
 898 }
 899
 900 #ifdef CONFIG_TCG
 901 static struct TCGCPUOps arm_v7m_tcg_ops = {
 902     .initialize = arm_translate_init,
 903     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
 904     .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
 905     .tlb_fill = arm_cpu_tlb_fill,
 906     .debug_excp_handler = arm_debug_excp_handler,
 907
 908 #if !defined(CONFIG_USER_ONLY)
 909     .do_interrupt = arm_v7m_cpu_do_interrupt,
 910     .do_transaction_failed = arm_cpu_do_transaction_failed,
 911     .do_unaligned_access = arm_cpu_do_unaligned_access,
 912     .adjust_watchpoint_address = arm_adjust_watchpoint_address,
 913     .debug_check_watchpoint = arm_debug_check_watchpoint,
 914 #endif /* !CONFIG_USER_ONLY */
 915 };
 916 #endif /* CONFIG_TCG */
 917
 918 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 919 {
 920     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 921     CPUClass *cc = CPU_CLASS(oc);
 922
 923     acc->info = data;
 924 #ifdef CONFIG_TCG
 925     cc->tcg_ops = &arm_v7m_tcg_ops;
 926 #endif /* CONFIG_TCG */
 927
 928     cc->gdb_core_xml_file = "arm-m-profile.xml";
 929 }
 930
 931 #ifndef TARGET_AARCH64
 932 /*
 933  * -cpu max: a CPU with as many features enabled as our emulation supports.
 934  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
 935  * this only needs to handle 32 bits, and need not care about KVM.
 936  */
 937 static void arm_max_initfn(Object *obj)
 938 {
 939     ARMCPU *cpu = ARM_CPU(obj);
 940
 941     cortex_a15_initfn(obj);
 942
 943     /* old-style VFP short-vector support */
 944     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 945
 946 #ifdef CONFIG_USER_ONLY
 947     /*
 948      * We don't set these in system emulation mode for the moment,
 949      * since we don't correctly set (all of) the ID registers to
 950      * advertise them.
 951      */
 952     set_feature(&cpu->env, ARM_FEATURE_V8);
 953     {
 954         uint32_t t;
 955
 956         t = cpu->isar.id_isar5;
 957         t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 958         t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 959         t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 960         t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 961         t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 962         t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 963         cpu->isar.id_isar5 = t;
 964
 965         t = cpu->isar.id_isar6;
 966         t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 967         t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 968         t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 969         t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 970         t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 971         t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 972         cpu->isar.id_isar6 = t;
 973
 974         t = cpu->isar.mvfr1;
 975         t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 976         t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 977         cpu->isar.mvfr1 = t;
 978
 979         t = cpu->isar.mvfr2;
 980         t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 981         t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 982         cpu->isar.mvfr2 = t;
 983
 984         t = cpu->isar.id_mmfr3;
 985         t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 986         cpu->isar.id_mmfr3 = t;
 987
 988         t = cpu->isar.id_mmfr4;
 989         t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 990         t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 991         t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 992         t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 993         cpu->isar.id_mmfr4 = t;
 994
 995         t = cpu->isar.id_pfr0;
 996         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 997         cpu->isar.id_pfr0 = t;
 998
 999         t = cpu->isar.id_pfr2;
1000         t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
1001         cpu->isar.id_pfr2 = t;
1002     }
1003 #endif /* CONFIG_USER_ONLY */
1004 }
1005 #endif /* !TARGET_AARCH64 */
1006
1007 static const ARMCPUInfo arm_tcg_cpus[] = {
1008     { .name = "arm926",      .initfn = arm926_initfn },
1009     { .name = "arm946",      .initfn = arm946_initfn },
1010     { .name = "arm1026",     .initfn = arm1026_initfn },
1011     /*
1012      * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1013      * older core than plain "arm1136". In particular this does not
1014      * have the v6K features.
1015      */
1016     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1017     { .name = "arm1136",     .initfn = arm1136_initfn },
1018     { .name = "arm1176",     .initfn = arm1176_initfn },
1019     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1020     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1021     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1022     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1023     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1024     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
1025                              .class_init = arm_v7m_class_init },
1026     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1027                              .class_init = arm_v7m_class_init },
1028     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1029                              .class_init = arm_v7m_class_init },
1030     { .name = "cortex-m7",   .initfn = cortex_m7_initfn,
1031                              .class_init = arm_v7m_class_init },
1032     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
1033                              .class_init = arm_v7m_class_init },
1034     { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
1035                              .class_init = arm_v7m_class_init },
1036     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1037     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
1038     { .name = "ti925t",      .initfn = ti925t_initfn },
1039     { .name = "sa1100",      .initfn = sa1100_initfn },
1040     { .name = "sa1110",      .initfn = sa1110_initfn },
1041     { .name = "pxa250",      .initfn = pxa250_initfn },
1042     { .name = "pxa255",      .initfn = pxa255_initfn },
1043     { .name = "pxa260",      .initfn = pxa260_initfn },
1044     { .name = "pxa261",      .initfn = pxa261_initfn },
1045     { .name = "pxa262",      .initfn = pxa262_initfn },
1046     /* "pxa270" is an alias for "pxa270-a0" */
1047     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1048     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1049     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1050     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1051     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1052     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1053     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1054 #ifndef TARGET_AARCH64
1055     { .name = "max",         .initfn = arm_max_initfn },
1056 #endif
1057 #ifdef CONFIG_USER_ONLY
1058     { .name = "any",         .initfn = arm_max_initfn },
1059 #endif
1060 };
1061
1062 static const TypeInfo idau_interface_type_info = {
1063     .name = TYPE_IDAU_INTERFACE,
1064     .parent = TYPE_INTERFACE,
1065     .class_size = sizeof(IDAUInterfaceClass),
1066 };
1067
1068 static void arm_tcg_cpu_register_types(void)
1069 {
1070     size_t i;
1071
1072     type_register_static(&idau_interface_type_info);
1073     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1074         arm_cpu_register(&arm_tcg_cpus[i]);
1075     }
1076 }
1077
1078 type_init(arm_tcg_cpu_register_types)
1079
1080 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */