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prep: do not use CPU_LOG_IOPORT, convert to tracepoints
[qemu/ar7.git] / hw / block / fdc.c
blob6686a72803b52666bbca52fac642bef9321c6c08
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw/hw.h"
31 #include "hw/block/fdc.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/isa/isa.h"
35 #include "hw/sysbus.h"
36 #include "sysemu/block-backend.h"
37 #include "sysemu/blockdev.h"
38 #include "sysemu/sysemu.h"
39 #include "qemu/log.h"
40
41 /********************************************************/
42 /* debug Floppy devices */
43 //#define DEBUG_FLOPPY
44
45 #ifdef DEBUG_FLOPPY
46 #define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
48 #else
49 #define FLOPPY_DPRINTF(fmt, ...)
50 #endif
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 typedef enum FDriveRate {
56 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
57 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
58 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
59 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
60 } FDriveRate;
61
62 typedef struct FDFormat {
63 FDriveType drive;
64 uint8_t last_sect;
65 uint8_t max_track;
66 uint8_t max_head;
67 FDriveRate rate;
68 } FDFormat;
69
70 static const FDFormat fd_formats[] = {
71 /* First entry is default format */
72 /* 1.44 MB 3"1/2 floppy disks */
73 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, },
74 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, },
75 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, },
76 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, },
77 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, },
78 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, },
79 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, },
80 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, },
81 /* 2.88 MB 3"1/2 floppy disks */
82 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, },
83 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, },
84 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, },
85 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, },
86 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, },
87 /* 720 kB 3"1/2 floppy disks */
88 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, },
89 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, },
90 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, },
91 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, },
92 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, },
93 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, },
94 /* 1.2 MB 5"1/4 floppy disks */
95 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, },
96 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, },
97 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, },
98 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, },
99 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, },
100 /* 720 kB 5"1/4 floppy disks */
101 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, },
102 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, },
103 /* 360 kB 5"1/4 floppy disks */
104 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, },
105 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, },
106 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, },
107 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, },
108 /* 320 kB 5"1/4 floppy disks */
109 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, },
110 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, },
111 /* 360 kB must match 5"1/4 better than 3"1/2... */
112 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, },
113 /* end */
114 { FDRIVE_DRV_NONE, -1, -1, 0, 0, },
115 };
116
117 static void pick_geometry(BlockBackend *blk, int *nb_heads,
118 int *max_track, int *last_sect,
119 FDriveType drive_in, FDriveType *drive,
120 FDriveRate *rate)
121 {
122 const FDFormat *parse;
123 uint64_t nb_sectors, size;
124 int i, first_match, match;
125
126 blk_get_geometry(blk, &nb_sectors);
127 match = -1;
128 first_match = -1;
129 for (i = 0; ; i++) {
130 parse = &fd_formats[i];
131 if (parse->drive == FDRIVE_DRV_NONE) {
132 break;
133 }
134 if (drive_in == parse->drive ||
135 drive_in == FDRIVE_DRV_NONE) {
136 size = (parse->max_head + 1) * parse->max_track *
137 parse->last_sect;
138 if (nb_sectors == size) {
139 match = i;
140 break;
141 }
142 if (first_match == -1) {
143 first_match = i;
144 }
145 }
146 }
147 if (match == -1) {
148 if (first_match == -1) {
149 match = 1;
150 } else {
151 match = first_match;
152 }
153 parse = &fd_formats[match];
154 }
155 *nb_heads = parse->max_head + 1;
156 *max_track = parse->max_track;
157 *last_sect = parse->last_sect;
158 *drive = parse->drive;
159 *rate = parse->rate;
160 }
161
162 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
163 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
164
165 /* Will always be a fixed parameter for us */
166 #define FD_SECTOR_LEN 512
167 #define FD_SECTOR_SC 2 /* Sector size code */
168 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
169
170 typedef struct FDCtrl FDCtrl;
171
172 /* Floppy disk drive emulation */
173 typedef enum FDiskFlags {
174 FDISK_DBL_SIDES = 0x01,
175 } FDiskFlags;
176
177 typedef struct FDrive {
178 FDCtrl *fdctrl;
179 BlockBackend *blk;
180 /* Drive status */
181 FDriveType drive;
182 uint8_t perpendicular; /* 2.88 MB access mode */
183 /* Position */
184 uint8_t head;
185 uint8_t track;
186 uint8_t sect;
187 /* Media */
188 FDiskFlags flags;
189 uint8_t last_sect; /* Nb sector per track */
190 uint8_t max_track; /* Nb of tracks */
191 uint16_t bps; /* Bytes per sector */
192 uint8_t ro; /* Is read-only */
193 uint8_t media_changed; /* Is media changed */
194 uint8_t media_rate; /* Data rate of medium */
195 } FDrive;
196
197 static void fd_init(FDrive *drv)
198 {
199 /* Drive */
200 drv->drive = FDRIVE_DRV_NONE;
201 drv->perpendicular = 0;
202 /* Disk */
203 drv->last_sect = 0;
204 drv->max_track = 0;
205 }
206
207 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
208
209 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
210 uint8_t last_sect, uint8_t num_sides)
211 {
212 return (((track * num_sides) + head) * last_sect) + sect - 1;
213 }
214
215 /* Returns current position, in sectors, for given drive */
216 static int fd_sector(FDrive *drv)
217 {
218 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
219 NUM_SIDES(drv));
220 }
221
222 /* Seek to a new position:
223 * returns 0 if already on right track
224 * returns 1 if track changed
225 * returns 2 if track is invalid
226 * returns 3 if sector is invalid
227 * returns 4 if seek is disabled
228 */
229 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
230 int enable_seek)
231 {
232 uint32_t sector;
233 int ret;
234
235 if (track > drv->max_track ||
236 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
237 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
238 head, track, sect, 1,
239 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
240 drv->max_track, drv->last_sect);
241 return 2;
242 }
243 if (sect > drv->last_sect) {
244 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
245 head, track, sect, 1,
246 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
247 drv->max_track, drv->last_sect);
248 return 3;
249 }
250 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
251 ret = 0;
252 if (sector != fd_sector(drv)) {
253 #if 0
254 if (!enable_seek) {
255 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
256 " (max=%d %02x %02x)\n",
257 head, track, sect, 1, drv->max_track,
258 drv->last_sect);
259 return 4;
260 }
261 #endif
262 drv->head = head;
263 if (drv->track != track) {
264 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
265 drv->media_changed = 0;
266 }
267 ret = 1;
268 }
269 drv->track = track;
270 drv->sect = sect;
271 }
272
273 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
274 ret = 2;
275 }
276
277 return ret;
278 }
279
280 /* Set drive back to track 0 */
281 static void fd_recalibrate(FDrive *drv)
282 {
283 FLOPPY_DPRINTF("recalibrate\n");
284 fd_seek(drv, 0, 0, 1, 1);
285 }
286
287 /* Revalidate a disk drive after a disk change */
288 static void fd_revalidate(FDrive *drv)
289 {
290 int nb_heads, max_track, last_sect, ro;
291 FDriveType drive;
292 FDriveRate rate;
293
294 FLOPPY_DPRINTF("revalidate\n");
295 if (drv->blk != NULL) {
296 ro = blk_is_read_only(drv->blk);
297 pick_geometry(drv->blk, &nb_heads, &max_track,
298 &last_sect, drv->drive, &drive, &rate);
299 if (!blk_is_inserted(drv->blk)) {
300 FLOPPY_DPRINTF("No disk in drive\n");
301 } else {
302 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
303 max_track, last_sect, ro ? "ro" : "rw");
304 }
305 if (nb_heads == 1) {
306 drv->flags &= ~FDISK_DBL_SIDES;
307 } else {
308 drv->flags |= FDISK_DBL_SIDES;
309 }
310 drv->max_track = max_track;
311 drv->last_sect = last_sect;
312 drv->ro = ro;
313 drv->drive = drive;
314 drv->media_rate = rate;
315 } else {
316 FLOPPY_DPRINTF("No drive connected\n");
317 drv->last_sect = 0;
318 drv->max_track = 0;
319 drv->flags &= ~FDISK_DBL_SIDES;
320 }
321 }
322
323 /********************************************************/
324 /* Intel 82078 floppy disk controller emulation */
325
326 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
327 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
328 static int fdctrl_transfer_handler (void *opaque, int nchan,
329 int dma_pos, int dma_len);
330 static void fdctrl_raise_irq(FDCtrl *fdctrl);
331 static FDrive *get_cur_drv(FDCtrl *fdctrl);
332
333 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
334 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
335 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
336 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
337 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
338 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
339 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
340 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
341 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
342 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
343 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
344 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
345
346 enum {
347 FD_DIR_WRITE = 0,
348 FD_DIR_READ = 1,
349 FD_DIR_SCANE = 2,
350 FD_DIR_SCANL = 3,
351 FD_DIR_SCANH = 4,
352 FD_DIR_VERIFY = 5,
353 };
354
355 enum {
356 FD_STATE_MULTI = 0x01, /* multi track flag */
357 FD_STATE_FORMAT = 0x02, /* format flag */
358 };
359
360 enum {
361 FD_REG_SRA = 0x00,
362 FD_REG_SRB = 0x01,
363 FD_REG_DOR = 0x02,
364 FD_REG_TDR = 0x03,
365 FD_REG_MSR = 0x04,
366 FD_REG_DSR = 0x04,
367 FD_REG_FIFO = 0x05,
368 FD_REG_DIR = 0x07,
369 FD_REG_CCR = 0x07,
370 };
371
372 enum {
373 FD_CMD_READ_TRACK = 0x02,
374 FD_CMD_SPECIFY = 0x03,
375 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
376 FD_CMD_WRITE = 0x05,
377 FD_CMD_READ = 0x06,
378 FD_CMD_RECALIBRATE = 0x07,
379 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
380 FD_CMD_WRITE_DELETED = 0x09,
381 FD_CMD_READ_ID = 0x0a,
382 FD_CMD_READ_DELETED = 0x0c,
383 FD_CMD_FORMAT_TRACK = 0x0d,
384 FD_CMD_DUMPREG = 0x0e,
385 FD_CMD_SEEK = 0x0f,
386 FD_CMD_VERSION = 0x10,
387 FD_CMD_SCAN_EQUAL = 0x11,
388 FD_CMD_PERPENDICULAR_MODE = 0x12,
389 FD_CMD_CONFIGURE = 0x13,
390 FD_CMD_LOCK = 0x14,
391 FD_CMD_VERIFY = 0x16,
392 FD_CMD_POWERDOWN_MODE = 0x17,
393 FD_CMD_PART_ID = 0x18,
394 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
395 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
396 FD_CMD_SAVE = 0x2e,
397 FD_CMD_OPTION = 0x33,
398 FD_CMD_RESTORE = 0x4e,
399 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
400 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
401 FD_CMD_FORMAT_AND_WRITE = 0xcd,
402 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
403 };
404
405 enum {
406 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
407 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
408 FD_CONFIG_POLL = 0x10, /* Poll enabled */
409 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
410 FD_CONFIG_EIS = 0x40, /* No implied seeks */
411 };
412
413 enum {
414 FD_SR0_DS0 = 0x01,
415 FD_SR0_DS1 = 0x02,
416 FD_SR0_HEAD = 0x04,
417 FD_SR0_EQPMT = 0x10,
418 FD_SR0_SEEK = 0x20,
419 FD_SR0_ABNTERM = 0x40,
420 FD_SR0_INVCMD = 0x80,
421 FD_SR0_RDYCHG = 0xc0,
422 };
423
424 enum {
425 FD_SR1_MA = 0x01, /* Missing address mark */
426 FD_SR1_NW = 0x02, /* Not writable */
427 FD_SR1_EC = 0x80, /* End of cylinder */
428 };
429
430 enum {
431 FD_SR2_SNS = 0x04, /* Scan not satisfied */
432 FD_SR2_SEH = 0x08, /* Scan equal hit */
433 };
434
435 enum {
436 FD_SRA_DIR = 0x01,
437 FD_SRA_nWP = 0x02,
438 FD_SRA_nINDX = 0x04,
439 FD_SRA_HDSEL = 0x08,
440 FD_SRA_nTRK0 = 0x10,
441 FD_SRA_STEP = 0x20,
442 FD_SRA_nDRV2 = 0x40,
443 FD_SRA_INTPEND = 0x80,
444 };
445
446 enum {
447 FD_SRB_MTR0 = 0x01,
448 FD_SRB_MTR1 = 0x02,
449 FD_SRB_WGATE = 0x04,
450 FD_SRB_RDATA = 0x08,
451 FD_SRB_WDATA = 0x10,
452 FD_SRB_DR0 = 0x20,
453 };
454
455 enum {
456 #if MAX_FD == 4
457 FD_DOR_SELMASK = 0x03,
458 #else
459 FD_DOR_SELMASK = 0x01,
460 #endif
461 FD_DOR_nRESET = 0x04,
462 FD_DOR_DMAEN = 0x08,
463 FD_DOR_MOTEN0 = 0x10,
464 FD_DOR_MOTEN1 = 0x20,
465 FD_DOR_MOTEN2 = 0x40,
466 FD_DOR_MOTEN3 = 0x80,
467 };
468
469 enum {
470 #if MAX_FD == 4
471 FD_TDR_BOOTSEL = 0x0c,
472 #else
473 FD_TDR_BOOTSEL = 0x04,
474 #endif
475 };
476
477 enum {
478 FD_DSR_DRATEMASK= 0x03,
479 FD_DSR_PWRDOWN = 0x40,
480 FD_DSR_SWRESET = 0x80,
481 };
482
483 enum {
484 FD_MSR_DRV0BUSY = 0x01,
485 FD_MSR_DRV1BUSY = 0x02,
486 FD_MSR_DRV2BUSY = 0x04,
487 FD_MSR_DRV3BUSY = 0x08,
488 FD_MSR_CMDBUSY = 0x10,
489 FD_MSR_NONDMA = 0x20,
490 FD_MSR_DIO = 0x40,
491 FD_MSR_RQM = 0x80,
492 };
493
494 enum {
495 FD_DIR_DSKCHG = 0x80,
496 };
497
498 /*
499 * See chapter 5.0 "Controller phases" of the spec:
500 *
501 * Command phase:
502 * The host writes a command and its parameters into the FIFO. The command
503 * phase is completed when all parameters for the command have been supplied,
504 * and execution phase is entered.
505 *
506 * Execution phase:
507 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
508 * contains the payload now, otherwise it's unused. When all bytes of the
509 * required data have been transferred, the state is switched to either result
510 * phase (if the command produces status bytes) or directly back into the
511 * command phase for the next command.
512 *
513 * Result phase:
514 * The host reads out the FIFO, which contains one or more result bytes now.
515 */
516 enum {
517 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
518 FD_PHASE_RECONSTRUCT = 0,
519
520 FD_PHASE_COMMAND = 1,
521 FD_PHASE_EXECUTION = 2,
522 FD_PHASE_RESULT = 3,
523 };
524
525 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
526 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
527
528 struct FDCtrl {
529 MemoryRegion iomem;
530 qemu_irq irq;
531 /* Controller state */
532 QEMUTimer *result_timer;
533 int dma_chann;
534 uint8_t phase;
535 /* Controller's identification */
536 uint8_t version;
537 /* HW */
538 uint8_t sra;
539 uint8_t srb;
540 uint8_t dor;
541 uint8_t dor_vmstate; /* only used as temp during vmstate */
542 uint8_t tdr;
543 uint8_t dsr;
544 uint8_t msr;
545 uint8_t cur_drv;
546 uint8_t status0;
547 uint8_t status1;
548 uint8_t status2;
549 /* Command FIFO */
550 uint8_t *fifo;
551 int32_t fifo_size;
552 uint32_t data_pos;
553 uint32_t data_len;
554 uint8_t data_state;
555 uint8_t data_dir;
556 uint8_t eot; /* last wanted sector */
557 /* States kept only to be returned back */
558 /* precompensation */
559 uint8_t precomp_trk;
560 uint8_t config;
561 uint8_t lock;
562 /* Power down config (also with status regB access mode */
563 uint8_t pwrd;
564 /* Floppy drives */
565 uint8_t num_floppies;
566 FDrive drives[MAX_FD];
567 int reset_sensei;
568 uint32_t check_media_rate;
569 /* Timers state */
570 uint8_t timer0;
571 uint8_t timer1;
572 };
573
574 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
575 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
576
577 typedef struct FDCtrlSysBus {
578 /*< private >*/
579 SysBusDevice parent_obj;
580 /*< public >*/
581
582 struct FDCtrl state;
583 } FDCtrlSysBus;
584
585 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
586
587 typedef struct FDCtrlISABus {
588 ISADevice parent_obj;
589
590 uint32_t iobase;
591 uint32_t irq;
592 uint32_t dma;
593 struct FDCtrl state;
594 int32_t bootindexA;
595 int32_t bootindexB;
596 } FDCtrlISABus;
597
598 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
599 {
600 FDCtrl *fdctrl = opaque;
601 uint32_t retval;
602
603 reg &= 7;
604 switch (reg) {
605 case FD_REG_SRA:
606 retval = fdctrl_read_statusA(fdctrl);
607 break;
608 case FD_REG_SRB:
609 retval = fdctrl_read_statusB(fdctrl);
610 break;
611 case FD_REG_DOR:
612 retval = fdctrl_read_dor(fdctrl);
613 break;
614 case FD_REG_TDR:
615 retval = fdctrl_read_tape(fdctrl);
616 break;
617 case FD_REG_MSR:
618 retval = fdctrl_read_main_status(fdctrl);
619 break;
620 case FD_REG_FIFO:
621 retval = fdctrl_read_data(fdctrl);
622 break;
623 case FD_REG_DIR:
624 retval = fdctrl_read_dir(fdctrl);
625 break;
626 default:
627 retval = (uint32_t)(-1);
628 break;
629 }
630 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
631
632 return retval;
633 }
634
635 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
636 {
637 FDCtrl *fdctrl = opaque;
638
639 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
640
641 reg &= 7;
642 switch (reg) {
643 case FD_REG_DOR:
644 fdctrl_write_dor(fdctrl, value);
645 break;
646 case FD_REG_TDR:
647 fdctrl_write_tape(fdctrl, value);
648 break;
649 case FD_REG_DSR:
650 fdctrl_write_rate(fdctrl, value);
651 break;
652 case FD_REG_FIFO:
653 fdctrl_write_data(fdctrl, value);
654 break;
655 case FD_REG_CCR:
656 fdctrl_write_ccr(fdctrl, value);
657 break;
658 default:
659 break;
660 }
661 }
662
663 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
664 unsigned ize)
665 {
666 return fdctrl_read(opaque, (uint32_t)reg);
667 }
668
669 static void fdctrl_write_mem (void *opaque, hwaddr reg,
670 uint64_t value, unsigned size)
671 {
672 fdctrl_write(opaque, (uint32_t)reg, value);
673 }
674
675 static const MemoryRegionOps fdctrl_mem_ops = {
676 .read = fdctrl_read_mem,
677 .write = fdctrl_write_mem,
678 .endianness = DEVICE_NATIVE_ENDIAN,
679 };
680
681 static const MemoryRegionOps fdctrl_mem_strict_ops = {
682 .read = fdctrl_read_mem,
683 .write = fdctrl_write_mem,
684 .endianness = DEVICE_NATIVE_ENDIAN,
685 .valid = {
686 .min_access_size = 1,
687 .max_access_size = 1,
688 },
689 };
690
691 static bool fdrive_media_changed_needed(void *opaque)
692 {
693 FDrive *drive = opaque;
694
695 return (drive->blk != NULL && drive->media_changed != 1);
696 }
697
698 static const VMStateDescription vmstate_fdrive_media_changed = {
699 .name = "fdrive/media_changed",
700 .version_id = 1,
701 .minimum_version_id = 1,
702 .needed = fdrive_media_changed_needed,
703 .fields = (VMStateField[]) {
704 VMSTATE_UINT8(media_changed, FDrive),
705 VMSTATE_END_OF_LIST()
706 }
707 };
708
709 static bool fdrive_media_rate_needed(void *opaque)
710 {
711 FDrive *drive = opaque;
712
713 return drive->fdctrl->check_media_rate;
714 }
715
716 static const VMStateDescription vmstate_fdrive_media_rate = {
717 .name = "fdrive/media_rate",
718 .version_id = 1,
719 .minimum_version_id = 1,
720 .needed = fdrive_media_rate_needed,
721 .fields = (VMStateField[]) {
722 VMSTATE_UINT8(media_rate, FDrive),
723 VMSTATE_END_OF_LIST()
724 }
725 };
726
727 static bool fdrive_perpendicular_needed(void *opaque)
728 {
729 FDrive *drive = opaque;
730
731 return drive->perpendicular != 0;
732 }
733
734 static const VMStateDescription vmstate_fdrive_perpendicular = {
735 .name = "fdrive/perpendicular",
736 .version_id = 1,
737 .minimum_version_id = 1,
738 .needed = fdrive_perpendicular_needed,
739 .fields = (VMStateField[]) {
740 VMSTATE_UINT8(perpendicular, FDrive),
741 VMSTATE_END_OF_LIST()
742 }
743 };
744
745 static int fdrive_post_load(void *opaque, int version_id)
746 {
747 fd_revalidate(opaque);
748 return 0;
749 }
750
751 static const VMStateDescription vmstate_fdrive = {
752 .name = "fdrive",
753 .version_id = 1,
754 .minimum_version_id = 1,
755 .post_load = fdrive_post_load,
756 .fields = (VMStateField[]) {
757 VMSTATE_UINT8(head, FDrive),
758 VMSTATE_UINT8(track, FDrive),
759 VMSTATE_UINT8(sect, FDrive),
760 VMSTATE_END_OF_LIST()
761 },
762 .subsections = (const VMStateDescription*[]) {
763 &vmstate_fdrive_media_changed,
764 &vmstate_fdrive_media_rate,
765 &vmstate_fdrive_perpendicular,
766 NULL
767 }
768 };
769
770 /*
771 * Reconstructs the phase from register values according to the logic that was
772 * implemented in qemu 2.3. This is the default value that is used if the phase
773 * subsection is not present on migration.
774 *
775 * Don't change this function to reflect newer qemu versions, it is part of
776 * the migration ABI.
777 */
778 static int reconstruct_phase(FDCtrl *fdctrl)
779 {
780 if (fdctrl->msr & FD_MSR_NONDMA) {
781 return FD_PHASE_EXECUTION;
782 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
783 /* qemu 2.3 disabled RQM only during DMA transfers */
784 return FD_PHASE_EXECUTION;
785 } else if (fdctrl->msr & FD_MSR_DIO) {
786 return FD_PHASE_RESULT;
787 } else {
788 return FD_PHASE_COMMAND;
789 }
790 }
791
792 static void fdc_pre_save(void *opaque)
793 {
794 FDCtrl *s = opaque;
795
796 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
797 }
798
799 static int fdc_pre_load(void *opaque)
800 {
801 FDCtrl *s = opaque;
802 s->phase = FD_PHASE_RECONSTRUCT;
803 return 0;
804 }
805
806 static int fdc_post_load(void *opaque, int version_id)
807 {
808 FDCtrl *s = opaque;
809
810 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
811 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
812
813 if (s->phase == FD_PHASE_RECONSTRUCT) {
814 s->phase = reconstruct_phase(s);
815 }
816
817 return 0;
818 }
819
820 static bool fdc_reset_sensei_needed(void *opaque)
821 {
822 FDCtrl *s = opaque;
823
824 return s->reset_sensei != 0;
825 }
826
827 static const VMStateDescription vmstate_fdc_reset_sensei = {
828 .name = "fdc/reset_sensei",
829 .version_id = 1,
830 .minimum_version_id = 1,
831 .needed = fdc_reset_sensei_needed,
832 .fields = (VMStateField[]) {
833 VMSTATE_INT32(reset_sensei, FDCtrl),
834 VMSTATE_END_OF_LIST()
835 }
836 };
837
838 static bool fdc_result_timer_needed(void *opaque)
839 {
840 FDCtrl *s = opaque;
841
842 return timer_pending(s->result_timer);
843 }
844
845 static const VMStateDescription vmstate_fdc_result_timer = {
846 .name = "fdc/result_timer",
847 .version_id = 1,
848 .minimum_version_id = 1,
849 .needed = fdc_result_timer_needed,
850 .fields = (VMStateField[]) {
851 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
852 VMSTATE_END_OF_LIST()
853 }
854 };
855
856 static bool fdc_phase_needed(void *opaque)
857 {
858 FDCtrl *fdctrl = opaque;
859
860 return reconstruct_phase(fdctrl) != fdctrl->phase;
861 }
862
863 static const VMStateDescription vmstate_fdc_phase = {
864 .name = "fdc/phase",
865 .version_id = 1,
866 .minimum_version_id = 1,
867 .needed = fdc_phase_needed,
868 .fields = (VMStateField[]) {
869 VMSTATE_UINT8(phase, FDCtrl),
870 VMSTATE_END_OF_LIST()
871 }
872 };
873
874 static const VMStateDescription vmstate_fdc = {
875 .name = "fdc",
876 .version_id = 2,
877 .minimum_version_id = 2,
878 .pre_save = fdc_pre_save,
879 .pre_load = fdc_pre_load,
880 .post_load = fdc_post_load,
881 .fields = (VMStateField[]) {
882 /* Controller State */
883 VMSTATE_UINT8(sra, FDCtrl),
884 VMSTATE_UINT8(srb, FDCtrl),
885 VMSTATE_UINT8(dor_vmstate, FDCtrl),
886 VMSTATE_UINT8(tdr, FDCtrl),
887 VMSTATE_UINT8(dsr, FDCtrl),
888 VMSTATE_UINT8(msr, FDCtrl),
889 VMSTATE_UINT8(status0, FDCtrl),
890 VMSTATE_UINT8(status1, FDCtrl),
891 VMSTATE_UINT8(status2, FDCtrl),
892 /* Command FIFO */
893 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
894 uint8_t),
895 VMSTATE_UINT32(data_pos, FDCtrl),
896 VMSTATE_UINT32(data_len, FDCtrl),
897 VMSTATE_UINT8(data_state, FDCtrl),
898 VMSTATE_UINT8(data_dir, FDCtrl),
899 VMSTATE_UINT8(eot, FDCtrl),
900 /* States kept only to be returned back */
901 VMSTATE_UINT8(timer0, FDCtrl),
902 VMSTATE_UINT8(timer1, FDCtrl),
903 VMSTATE_UINT8(precomp_trk, FDCtrl),
904 VMSTATE_UINT8(config, FDCtrl),
905 VMSTATE_UINT8(lock, FDCtrl),
906 VMSTATE_UINT8(pwrd, FDCtrl),
907 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
908 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
909 vmstate_fdrive, FDrive),
910 VMSTATE_END_OF_LIST()
911 },
912 .subsections = (const VMStateDescription*[]) {
913 &vmstate_fdc_reset_sensei,
914 &vmstate_fdc_result_timer,
915 &vmstate_fdc_phase,
916 NULL
917 }
918 };
919
920 static void fdctrl_external_reset_sysbus(DeviceState *d)
921 {
922 FDCtrlSysBus *sys = SYSBUS_FDC(d);
923 FDCtrl *s = &sys->state;
924
925 fdctrl_reset(s, 0);
926 }
927
928 static void fdctrl_external_reset_isa(DeviceState *d)
929 {
930 FDCtrlISABus *isa = ISA_FDC(d);
931 FDCtrl *s = &isa->state;
932
933 fdctrl_reset(s, 0);
934 }
935
936 static void fdctrl_handle_tc(void *opaque, int irq, int level)
937 {
938 //FDCtrl *s = opaque;
939
940 if (level) {
941 // XXX
942 FLOPPY_DPRINTF("TC pulsed\n");
943 }
944 }
945
946 /* Change IRQ state */
947 static void fdctrl_reset_irq(FDCtrl *fdctrl)
948 {
949 fdctrl->status0 = 0;
950 if (!(fdctrl->sra & FD_SRA_INTPEND))
951 return;
952 FLOPPY_DPRINTF("Reset interrupt\n");
953 qemu_set_irq(fdctrl->irq, 0);
954 fdctrl->sra &= ~FD_SRA_INTPEND;
955 }
956
957 static void fdctrl_raise_irq(FDCtrl *fdctrl)
958 {
959 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
960 qemu_set_irq(fdctrl->irq, 1);
961 fdctrl->sra |= FD_SRA_INTPEND;
962 }
963
964 fdctrl->reset_sensei = 0;
965 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
966 }
967
968 /* Reset controller */
969 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
970 {
971 int i;
972
973 FLOPPY_DPRINTF("reset controller\n");
974 fdctrl_reset_irq(fdctrl);
975 /* Initialise controller */
976 fdctrl->sra = 0;
977 fdctrl->srb = 0xc0;
978 if (!fdctrl->drives[1].blk) {
979 fdctrl->sra |= FD_SRA_nDRV2;
980 }
981 fdctrl->cur_drv = 0;
982 fdctrl->dor = FD_DOR_nRESET;
983 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
984 fdctrl->msr = FD_MSR_RQM;
985 fdctrl->reset_sensei = 0;
986 timer_del(fdctrl->result_timer);
987 /* FIFO state */
988 fdctrl->data_pos = 0;
989 fdctrl->data_len = 0;
990 fdctrl->data_state = 0;
991 fdctrl->data_dir = FD_DIR_WRITE;
992 for (i = 0; i < MAX_FD; i++)
993 fd_recalibrate(&fdctrl->drives[i]);
994 fdctrl_to_command_phase(fdctrl);
995 if (do_irq) {
996 fdctrl->status0 |= FD_SR0_RDYCHG;
997 fdctrl_raise_irq(fdctrl);
998 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
999 }
1000 }
1001
1002 static inline FDrive *drv0(FDCtrl *fdctrl)
1003 {
1004 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1005 }
1006
1007 static inline FDrive *drv1(FDCtrl *fdctrl)
1008 {
1009 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1010 return &fdctrl->drives[1];
1011 else
1012 return &fdctrl->drives[0];
1013 }
1014
1015 #if MAX_FD == 4
1016 static inline FDrive *drv2(FDCtrl *fdctrl)
1017 {
1018 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1019 return &fdctrl->drives[2];
1020 else
1021 return &fdctrl->drives[1];
1022 }
1023
1024 static inline FDrive *drv3(FDCtrl *fdctrl)
1025 {
1026 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1027 return &fdctrl->drives[3];
1028 else
1029 return &fdctrl->drives[2];
1030 }
1031 #endif
1032
1033 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1034 {
1035 switch (fdctrl->cur_drv) {
1036 case 0: return drv0(fdctrl);
1037 case 1: return drv1(fdctrl);
1038 #if MAX_FD == 4
1039 case 2: return drv2(fdctrl);
1040 case 3: return drv3(fdctrl);
1041 #endif
1042 default: return NULL;
1043 }
1044 }
1045
1046 /* Status A register : 0x00 (read-only) */
1047 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1048 {
1049 uint32_t retval = fdctrl->sra;
1050
1051 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1052
1053 return retval;
1054 }
1055
1056 /* Status B register : 0x01 (read-only) */
1057 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1058 {
1059 uint32_t retval = fdctrl->srb;
1060
1061 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1062
1063 return retval;
1064 }
1065
1066 /* Digital output register : 0x02 */
1067 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1068 {
1069 uint32_t retval = fdctrl->dor;
1070
1071 /* Selected drive */
1072 retval |= fdctrl->cur_drv;
1073 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1074
1075 return retval;
1076 }
1077
1078 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1079 {
1080 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1081
1082 /* Motors */
1083 if (value & FD_DOR_MOTEN0)
1084 fdctrl->srb |= FD_SRB_MTR0;
1085 else
1086 fdctrl->srb &= ~FD_SRB_MTR0;
1087 if (value & FD_DOR_MOTEN1)
1088 fdctrl->srb |= FD_SRB_MTR1;
1089 else
1090 fdctrl->srb &= ~FD_SRB_MTR1;
1091
1092 /* Drive */
1093 if (value & 1)
1094 fdctrl->srb |= FD_SRB_DR0;
1095 else
1096 fdctrl->srb &= ~FD_SRB_DR0;
1097
1098 /* Reset */
1099 if (!(value & FD_DOR_nRESET)) {
1100 if (fdctrl->dor & FD_DOR_nRESET) {
1101 FLOPPY_DPRINTF("controller enter RESET state\n");
1102 }
1103 } else {
1104 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1105 FLOPPY_DPRINTF("controller out of RESET state\n");
1106 fdctrl_reset(fdctrl, 1);
1107 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1108 }
1109 }
1110 /* Selected drive */
1111 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1112
1113 fdctrl->dor = value;
1114 }
1115
1116 /* Tape drive register : 0x03 */
1117 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1118 {
1119 uint32_t retval = fdctrl->tdr;
1120
1121 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1122
1123 return retval;
1124 }
1125
1126 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1127 {
1128 /* Reset mode */
1129 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1130 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1131 return;
1132 }
1133 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1134 /* Disk boot selection indicator */
1135 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1136 /* Tape indicators: never allow */
1137 }
1138
1139 /* Main status register : 0x04 (read) */
1140 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1141 {
1142 uint32_t retval = fdctrl->msr;
1143
1144 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1145 fdctrl->dor |= FD_DOR_nRESET;
1146
1147 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1148
1149 return retval;
1150 }
1151
1152 /* Data select rate register : 0x04 (write) */
1153 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1154 {
1155 /* Reset mode */
1156 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1157 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1158 return;
1159 }
1160 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1161 /* Reset: autoclear */
1162 if (value & FD_DSR_SWRESET) {
1163 fdctrl->dor &= ~FD_DOR_nRESET;
1164 fdctrl_reset(fdctrl, 1);
1165 fdctrl->dor |= FD_DOR_nRESET;
1166 }
1167 if (value & FD_DSR_PWRDOWN) {
1168 fdctrl_reset(fdctrl, 1);
1169 }
1170 fdctrl->dsr = value;
1171 }
1172
1173 /* Configuration control register: 0x07 (write) */
1174 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1175 {
1176 /* Reset mode */
1177 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1178 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1179 return;
1180 }
1181 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1182
1183 /* Only the rate selection bits used in AT mode, and we
1184 * store those in the DSR.
1185 */
1186 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1187 (value & FD_DSR_DRATEMASK);
1188 }
1189
1190 static int fdctrl_media_changed(FDrive *drv)
1191 {
1192 return drv->media_changed;
1193 }
1194
1195 /* Digital input register : 0x07 (read-only) */
1196 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1197 {
1198 uint32_t retval = 0;
1199
1200 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1201 retval |= FD_DIR_DSKCHG;
1202 }
1203 if (retval != 0) {
1204 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1205 }
1206
1207 return retval;
1208 }
1209
1210 /* Clear the FIFO and update the state for receiving the next command */
1211 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1212 {
1213 fdctrl->phase = FD_PHASE_COMMAND;
1214 fdctrl->data_dir = FD_DIR_WRITE;
1215 fdctrl->data_pos = 0;
1216 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1217 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1218 fdctrl->msr |= FD_MSR_RQM;
1219 }
1220
1221 /* Update the state to allow the guest to read out the command status.
1222 * @fifo_len is the number of result bytes to be read out. */
1223 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1224 {
1225 fdctrl->phase = FD_PHASE_RESULT;
1226 fdctrl->data_dir = FD_DIR_READ;
1227 fdctrl->data_len = fifo_len;
1228 fdctrl->data_pos = 0;
1229 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1230 }
1231
1232 /* Set an error: unimplemented/unknown command */
1233 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1234 {
1235 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1236 fdctrl->fifo[0]);
1237 fdctrl->fifo[0] = FD_SR0_INVCMD;
1238 fdctrl_to_result_phase(fdctrl, 1);
1239 }
1240
1241 /* Seek to next sector
1242 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1243 * otherwise returns 1
1244 */
1245 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1246 {
1247 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1248 cur_drv->head, cur_drv->track, cur_drv->sect,
1249 fd_sector(cur_drv));
1250 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1251 error in fact */
1252 uint8_t new_head = cur_drv->head;
1253 uint8_t new_track = cur_drv->track;
1254 uint8_t new_sect = cur_drv->sect;
1255
1256 int ret = 1;
1257
1258 if (new_sect >= cur_drv->last_sect ||
1259 new_sect == fdctrl->eot) {
1260 new_sect = 1;
1261 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1262 if (new_head == 0 &&
1263 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1264 new_head = 1;
1265 } else {
1266 new_head = 0;
1267 new_track++;
1268 fdctrl->status0 |= FD_SR0_SEEK;
1269 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1270 ret = 0;
1271 }
1272 }
1273 } else {
1274 fdctrl->status0 |= FD_SR0_SEEK;
1275 new_track++;
1276 ret = 0;
1277 }
1278 if (ret == 1) {
1279 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1280 new_head, new_track, new_sect, fd_sector(cur_drv));
1281 }
1282 } else {
1283 new_sect++;
1284 }
1285 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1286 return ret;
1287 }
1288
1289 /* Callback for transfer end (stop or abort) */
1290 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1291 uint8_t status1, uint8_t status2)
1292 {
1293 FDrive *cur_drv;
1294 cur_drv = get_cur_drv(fdctrl);
1295
1296 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1297 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1298 if (cur_drv->head) {
1299 fdctrl->status0 |= FD_SR0_HEAD;
1300 }
1301 fdctrl->status0 |= status0;
1302
1303 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1304 status0, status1, status2, fdctrl->status0);
1305 fdctrl->fifo[0] = fdctrl->status0;
1306 fdctrl->fifo[1] = status1;
1307 fdctrl->fifo[2] = status2;
1308 fdctrl->fifo[3] = cur_drv->track;
1309 fdctrl->fifo[4] = cur_drv->head;
1310 fdctrl->fifo[5] = cur_drv->sect;
1311 fdctrl->fifo[6] = FD_SECTOR_SC;
1312 fdctrl->data_dir = FD_DIR_READ;
1313 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1314 DMA_release_DREQ(fdctrl->dma_chann);
1315 }
1316 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1317 fdctrl->msr &= ~FD_MSR_NONDMA;
1318
1319 fdctrl_to_result_phase(fdctrl, 7);
1320 fdctrl_raise_irq(fdctrl);
1321 }
1322
1323 /* Prepare a data transfer (either DMA or FIFO) */
1324 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1325 {
1326 FDrive *cur_drv;
1327 uint8_t kh, kt, ks;
1328
1329 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1330 cur_drv = get_cur_drv(fdctrl);
1331 kt = fdctrl->fifo[2];
1332 kh = fdctrl->fifo[3];
1333 ks = fdctrl->fifo[4];
1334 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1335 GET_CUR_DRV(fdctrl), kh, kt, ks,
1336 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1337 NUM_SIDES(cur_drv)));
1338 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1339 case 2:
1340 /* sect too big */
1341 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1342 fdctrl->fifo[3] = kt;
1343 fdctrl->fifo[4] = kh;
1344 fdctrl->fifo[5] = ks;
1345 return;
1346 case 3:
1347 /* track too big */
1348 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1349 fdctrl->fifo[3] = kt;
1350 fdctrl->fifo[4] = kh;
1351 fdctrl->fifo[5] = ks;
1352 return;
1353 case 4:
1354 /* No seek enabled */
1355 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1356 fdctrl->fifo[3] = kt;
1357 fdctrl->fifo[4] = kh;
1358 fdctrl->fifo[5] = ks;
1359 return;
1360 case 1:
1361 fdctrl->status0 |= FD_SR0_SEEK;
1362 break;
1363 default:
1364 break;
1365 }
1366
1367 /* Check the data rate. If the programmed data rate does not match
1368 * the currently inserted medium, the operation has to fail. */
1369 if (fdctrl->check_media_rate &&
1370 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1371 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1372 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1373 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1374 fdctrl->fifo[3] = kt;
1375 fdctrl->fifo[4] = kh;
1376 fdctrl->fifo[5] = ks;
1377 return;
1378 }
1379
1380 /* Set the FIFO state */
1381 fdctrl->data_dir = direction;
1382 fdctrl->data_pos = 0;
1383 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1384 if (fdctrl->fifo[0] & 0x80)
1385 fdctrl->data_state |= FD_STATE_MULTI;
1386 else
1387 fdctrl->data_state &= ~FD_STATE_MULTI;
1388 if (fdctrl->fifo[5] == 0) {
1389 fdctrl->data_len = fdctrl->fifo[8];
1390 } else {
1391 int tmp;
1392 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1393 tmp = (fdctrl->fifo[6] - ks + 1);
1394 if (fdctrl->fifo[0] & 0x80)
1395 tmp += fdctrl->fifo[6];
1396 fdctrl->data_len *= tmp;
1397 }
1398 fdctrl->eot = fdctrl->fifo[6];
1399 if (fdctrl->dor & FD_DOR_DMAEN) {
1400 int dma_mode;
1401 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1402 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1403 dma_mode = (dma_mode >> 2) & 3;
1404 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1405 dma_mode, direction,
1406 (128 << fdctrl->fifo[5]) *
1407 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1408 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1409 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1410 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1411 (direction == FD_DIR_READ && dma_mode == 1) ||
1412 (direction == FD_DIR_VERIFY)) {
1413 /* No access is allowed until DMA transfer has completed */
1414 fdctrl->msr &= ~FD_MSR_RQM;
1415 if (direction != FD_DIR_VERIFY) {
1416 /* Now, we just have to wait for the DMA controller to
1417 * recall us...
1418 */
1419 DMA_hold_DREQ(fdctrl->dma_chann);
1420 DMA_schedule();
1421 } else {
1422 /* Start transfer */
1423 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1424 fdctrl->data_len);
1425 }
1426 return;
1427 } else {
1428 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1429 direction);
1430 }
1431 }
1432 FLOPPY_DPRINTF("start non-DMA transfer\n");
1433 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1434 if (direction != FD_DIR_WRITE)
1435 fdctrl->msr |= FD_MSR_DIO;
1436 /* IO based transfer: calculate len */
1437 fdctrl_raise_irq(fdctrl);
1438 }
1439
1440 /* Prepare a transfer of deleted data */
1441 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1442 {
1443 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1444
1445 /* We don't handle deleted data,
1446 * so we don't return *ANYTHING*
1447 */
1448 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1449 }
1450
1451 /* handlers for DMA transfers */
1452 static int fdctrl_transfer_handler (void *opaque, int nchan,
1453 int dma_pos, int dma_len)
1454 {
1455 FDCtrl *fdctrl;
1456 FDrive *cur_drv;
1457 int len, start_pos, rel_pos;
1458 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1459
1460 fdctrl = opaque;
1461 if (fdctrl->msr & FD_MSR_RQM) {
1462 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1463 return 0;
1464 }
1465 cur_drv = get_cur_drv(fdctrl);
1466 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1467 fdctrl->data_dir == FD_DIR_SCANH)
1468 status2 = FD_SR2_SNS;
1469 if (dma_len > fdctrl->data_len)
1470 dma_len = fdctrl->data_len;
1471 if (cur_drv->blk == NULL) {
1472 if (fdctrl->data_dir == FD_DIR_WRITE)
1473 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1474 else
1475 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1476 len = 0;
1477 goto transfer_error;
1478 }
1479 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1480 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1481 len = dma_len - fdctrl->data_pos;
1482 if (len + rel_pos > FD_SECTOR_LEN)
1483 len = FD_SECTOR_LEN - rel_pos;
1484 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1485 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1486 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1487 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1488 fd_sector(cur_drv) * FD_SECTOR_LEN);
1489 if (fdctrl->data_dir != FD_DIR_WRITE ||
1490 len < FD_SECTOR_LEN || rel_pos != 0) {
1491 /* READ & SCAN commands and realign to a sector for WRITE */
1492 if (blk_read(cur_drv->blk, fd_sector(cur_drv),
1493 fdctrl->fifo, 1) < 0) {
1494 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1495 fd_sector(cur_drv));
1496 /* Sure, image size is too small... */
1497 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1498 }
1499 }
1500 switch (fdctrl->data_dir) {
1501 case FD_DIR_READ:
1502 /* READ commands */
1503 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1504 fdctrl->data_pos, len);
1505 break;
1506 case FD_DIR_WRITE:
1507 /* WRITE commands */
1508 if (cur_drv->ro) {
1509 /* Handle readonly medium early, no need to do DMA, touch the
1510 * LED or attempt any writes. A real floppy doesn't attempt
1511 * to write to readonly media either. */
1512 fdctrl_stop_transfer(fdctrl,
1513 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1514 0x00);
1515 goto transfer_error;
1516 }
1517
1518 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1519 fdctrl->data_pos, len);
1520 if (blk_write(cur_drv->blk, fd_sector(cur_drv),
1521 fdctrl->fifo, 1) < 0) {
1522 FLOPPY_DPRINTF("error writing sector %d\n",
1523 fd_sector(cur_drv));
1524 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1525 goto transfer_error;
1526 }
1527 break;
1528 case FD_DIR_VERIFY:
1529 /* VERIFY commands */
1530 break;
1531 default:
1532 /* SCAN commands */
1533 {
1534 uint8_t tmpbuf[FD_SECTOR_LEN];
1535 int ret;
1536 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1537 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1538 if (ret == 0) {
1539 status2 = FD_SR2_SEH;
1540 goto end_transfer;
1541 }
1542 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1543 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1544 status2 = 0x00;
1545 goto end_transfer;
1546 }
1547 }
1548 break;
1549 }
1550 fdctrl->data_pos += len;
1551 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1552 if (rel_pos == 0) {
1553 /* Seek to next sector */
1554 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1555 break;
1556 }
1557 }
1558 end_transfer:
1559 len = fdctrl->data_pos - start_pos;
1560 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1561 fdctrl->data_pos, len, fdctrl->data_len);
1562 if (fdctrl->data_dir == FD_DIR_SCANE ||
1563 fdctrl->data_dir == FD_DIR_SCANL ||
1564 fdctrl->data_dir == FD_DIR_SCANH)
1565 status2 = FD_SR2_SEH;
1566 fdctrl->data_len -= len;
1567 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1568 transfer_error:
1569
1570 return len;
1571 }
1572
1573 /* Data register : 0x05 */
1574 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1575 {
1576 FDrive *cur_drv;
1577 uint32_t retval = 0;
1578 uint32_t pos;
1579
1580 cur_drv = get_cur_drv(fdctrl);
1581 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1582 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1583 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1584 return 0;
1585 }
1586
1587 /* If data_len spans multiple sectors, the current position in the FIFO
1588 * wraps around while fdctrl->data_pos is the real position in the whole
1589 * request. */
1590 pos = fdctrl->data_pos;
1591 pos %= FD_SECTOR_LEN;
1592
1593 switch (fdctrl->phase) {
1594 case FD_PHASE_EXECUTION:
1595 assert(fdctrl->msr & FD_MSR_NONDMA);
1596 if (pos == 0) {
1597 if (fdctrl->data_pos != 0)
1598 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1599 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1600 fd_sector(cur_drv));
1601 return 0;
1602 }
1603 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1604 < 0) {
1605 FLOPPY_DPRINTF("error getting sector %d\n",
1606 fd_sector(cur_drv));
1607 /* Sure, image size is too small... */
1608 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1609 }
1610 }
1611
1612 if (++fdctrl->data_pos == fdctrl->data_len) {
1613 fdctrl->msr &= ~FD_MSR_RQM;
1614 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1615 }
1616 break;
1617
1618 case FD_PHASE_RESULT:
1619 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1620 if (++fdctrl->data_pos == fdctrl->data_len) {
1621 fdctrl->msr &= ~FD_MSR_RQM;
1622 fdctrl_to_command_phase(fdctrl);
1623 fdctrl_reset_irq(fdctrl);
1624 }
1625 break;
1626
1627 case FD_PHASE_COMMAND:
1628 default:
1629 abort();
1630 }
1631
1632 retval = fdctrl->fifo[pos];
1633 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1634
1635 return retval;
1636 }
1637
1638 static void fdctrl_format_sector(FDCtrl *fdctrl)
1639 {
1640 FDrive *cur_drv;
1641 uint8_t kh, kt, ks;
1642
1643 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1644 cur_drv = get_cur_drv(fdctrl);
1645 kt = fdctrl->fifo[6];
1646 kh = fdctrl->fifo[7];
1647 ks = fdctrl->fifo[8];
1648 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1649 GET_CUR_DRV(fdctrl), kh, kt, ks,
1650 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1651 NUM_SIDES(cur_drv)));
1652 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1653 case 2:
1654 /* sect too big */
1655 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1656 fdctrl->fifo[3] = kt;
1657 fdctrl->fifo[4] = kh;
1658 fdctrl->fifo[5] = ks;
1659 return;
1660 case 3:
1661 /* track too big */
1662 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1663 fdctrl->fifo[3] = kt;
1664 fdctrl->fifo[4] = kh;
1665 fdctrl->fifo[5] = ks;
1666 return;
1667 case 4:
1668 /* No seek enabled */
1669 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1670 fdctrl->fifo[3] = kt;
1671 fdctrl->fifo[4] = kh;
1672 fdctrl->fifo[5] = ks;
1673 return;
1674 case 1:
1675 fdctrl->status0 |= FD_SR0_SEEK;
1676 break;
1677 default:
1678 break;
1679 }
1680 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1681 if (cur_drv->blk == NULL ||
1682 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1683 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1684 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1685 } else {
1686 if (cur_drv->sect == cur_drv->last_sect) {
1687 fdctrl->data_state &= ~FD_STATE_FORMAT;
1688 /* Last sector done */
1689 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1690 } else {
1691 /* More to do */
1692 fdctrl->data_pos = 0;
1693 fdctrl->data_len = 4;
1694 }
1695 }
1696 }
1697
1698 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1699 {
1700 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1701 fdctrl->fifo[0] = fdctrl->lock << 4;
1702 fdctrl_to_result_phase(fdctrl, 1);
1703 }
1704
1705 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1706 {
1707 FDrive *cur_drv = get_cur_drv(fdctrl);
1708
1709 /* Drives position */
1710 fdctrl->fifo[0] = drv0(fdctrl)->track;
1711 fdctrl->fifo[1] = drv1(fdctrl)->track;
1712 #if MAX_FD == 4
1713 fdctrl->fifo[2] = drv2(fdctrl)->track;
1714 fdctrl->fifo[3] = drv3(fdctrl)->track;
1715 #else
1716 fdctrl->fifo[2] = 0;
1717 fdctrl->fifo[3] = 0;
1718 #endif
1719 /* timers */
1720 fdctrl->fifo[4] = fdctrl->timer0;
1721 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1722 fdctrl->fifo[6] = cur_drv->last_sect;
1723 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1724 (cur_drv->perpendicular << 2);
1725 fdctrl->fifo[8] = fdctrl->config;
1726 fdctrl->fifo[9] = fdctrl->precomp_trk;
1727 fdctrl_to_result_phase(fdctrl, 10);
1728 }
1729
1730 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1731 {
1732 /* Controller's version */
1733 fdctrl->fifo[0] = fdctrl->version;
1734 fdctrl_to_result_phase(fdctrl, 1);
1735 }
1736
1737 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1738 {
1739 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1740 fdctrl_to_result_phase(fdctrl, 1);
1741 }
1742
1743 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1744 {
1745 FDrive *cur_drv = get_cur_drv(fdctrl);
1746
1747 /* Drives position */
1748 drv0(fdctrl)->track = fdctrl->fifo[3];
1749 drv1(fdctrl)->track = fdctrl->fifo[4];
1750 #if MAX_FD == 4
1751 drv2(fdctrl)->track = fdctrl->fifo[5];
1752 drv3(fdctrl)->track = fdctrl->fifo[6];
1753 #endif
1754 /* timers */
1755 fdctrl->timer0 = fdctrl->fifo[7];
1756 fdctrl->timer1 = fdctrl->fifo[8];
1757 cur_drv->last_sect = fdctrl->fifo[9];
1758 fdctrl->lock = fdctrl->fifo[10] >> 7;
1759 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1760 fdctrl->config = fdctrl->fifo[11];
1761 fdctrl->precomp_trk = fdctrl->fifo[12];
1762 fdctrl->pwrd = fdctrl->fifo[13];
1763 fdctrl_to_command_phase(fdctrl);
1764 }
1765
1766 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1767 {
1768 FDrive *cur_drv = get_cur_drv(fdctrl);
1769
1770 fdctrl->fifo[0] = 0;
1771 fdctrl->fifo[1] = 0;
1772 /* Drives position */
1773 fdctrl->fifo[2] = drv0(fdctrl)->track;
1774 fdctrl->fifo[3] = drv1(fdctrl)->track;
1775 #if MAX_FD == 4
1776 fdctrl->fifo[4] = drv2(fdctrl)->track;
1777 fdctrl->fifo[5] = drv3(fdctrl)->track;
1778 #else
1779 fdctrl->fifo[4] = 0;
1780 fdctrl->fifo[5] = 0;
1781 #endif
1782 /* timers */
1783 fdctrl->fifo[6] = fdctrl->timer0;
1784 fdctrl->fifo[7] = fdctrl->timer1;
1785 fdctrl->fifo[8] = cur_drv->last_sect;
1786 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1787 (cur_drv->perpendicular << 2);
1788 fdctrl->fifo[10] = fdctrl->config;
1789 fdctrl->fifo[11] = fdctrl->precomp_trk;
1790 fdctrl->fifo[12] = fdctrl->pwrd;
1791 fdctrl->fifo[13] = 0;
1792 fdctrl->fifo[14] = 0;
1793 fdctrl_to_result_phase(fdctrl, 15);
1794 }
1795
1796 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1797 {
1798 FDrive *cur_drv = get_cur_drv(fdctrl);
1799
1800 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1801 timer_mod(fdctrl->result_timer,
1802 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
1803 }
1804
1805 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1806 {
1807 FDrive *cur_drv;
1808
1809 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1810 cur_drv = get_cur_drv(fdctrl);
1811 fdctrl->data_state |= FD_STATE_FORMAT;
1812 if (fdctrl->fifo[0] & 0x80)
1813 fdctrl->data_state |= FD_STATE_MULTI;
1814 else
1815 fdctrl->data_state &= ~FD_STATE_MULTI;
1816 cur_drv->bps =
1817 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1818 #if 0
1819 cur_drv->last_sect =
1820 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1821 fdctrl->fifo[3] / 2;
1822 #else
1823 cur_drv->last_sect = fdctrl->fifo[3];
1824 #endif
1825 /* TODO: implement format using DMA expected by the Bochs BIOS
1826 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1827 * the sector with the specified fill byte
1828 */
1829 fdctrl->data_state &= ~FD_STATE_FORMAT;
1830 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1831 }
1832
1833 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1834 {
1835 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1836 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1837 if (fdctrl->fifo[2] & 1)
1838 fdctrl->dor &= ~FD_DOR_DMAEN;
1839 else
1840 fdctrl->dor |= FD_DOR_DMAEN;
1841 /* No result back */
1842 fdctrl_to_command_phase(fdctrl);
1843 }
1844
1845 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1846 {
1847 FDrive *cur_drv;
1848
1849 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1850 cur_drv = get_cur_drv(fdctrl);
1851 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1852 /* 1 Byte status back */
1853 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1854 (cur_drv->track == 0 ? 0x10 : 0x00) |
1855 (cur_drv->head << 2) |
1856 GET_CUR_DRV(fdctrl) |
1857 0x28;
1858 fdctrl_to_result_phase(fdctrl, 1);
1859 }
1860
1861 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1862 {
1863 FDrive *cur_drv;
1864
1865 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1866 cur_drv = get_cur_drv(fdctrl);
1867 fd_recalibrate(cur_drv);
1868 fdctrl_to_command_phase(fdctrl);
1869 /* Raise Interrupt */
1870 fdctrl->status0 |= FD_SR0_SEEK;
1871 fdctrl_raise_irq(fdctrl);
1872 }
1873
1874 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1875 {
1876 FDrive *cur_drv = get_cur_drv(fdctrl);
1877
1878 if (fdctrl->reset_sensei > 0) {
1879 fdctrl->fifo[0] =
1880 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1881 fdctrl->reset_sensei--;
1882 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1883 fdctrl->fifo[0] = FD_SR0_INVCMD;
1884 fdctrl_to_result_phase(fdctrl, 1);
1885 return;
1886 } else {
1887 fdctrl->fifo[0] =
1888 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1889 | GET_CUR_DRV(fdctrl);
1890 }
1891
1892 fdctrl->fifo[1] = cur_drv->track;
1893 fdctrl_to_result_phase(fdctrl, 2);
1894 fdctrl_reset_irq(fdctrl);
1895 fdctrl->status0 = FD_SR0_RDYCHG;
1896 }
1897
1898 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1899 {
1900 FDrive *cur_drv;
1901
1902 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1903 cur_drv = get_cur_drv(fdctrl);
1904 fdctrl_to_command_phase(fdctrl);
1905 /* The seek command just sends step pulses to the drive and doesn't care if
1906 * there is a medium inserted of if it's banging the head against the drive.
1907 */
1908 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1909 /* Raise Interrupt */
1910 fdctrl->status0 |= FD_SR0_SEEK;
1911 fdctrl_raise_irq(fdctrl);
1912 }
1913
1914 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1915 {
1916 FDrive *cur_drv = get_cur_drv(fdctrl);
1917
1918 if (fdctrl->fifo[1] & 0x80)
1919 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1920 /* No result back */
1921 fdctrl_to_command_phase(fdctrl);
1922 }
1923
1924 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1925 {
1926 fdctrl->config = fdctrl->fifo[2];
1927 fdctrl->precomp_trk = fdctrl->fifo[3];
1928 /* No result back */
1929 fdctrl_to_command_phase(fdctrl);
1930 }
1931
1932 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1933 {
1934 fdctrl->pwrd = fdctrl->fifo[1];
1935 fdctrl->fifo[0] = fdctrl->fifo[1];
1936 fdctrl_to_result_phase(fdctrl, 1);
1937 }
1938
1939 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1940 {
1941 /* No result back */
1942 fdctrl_to_command_phase(fdctrl);
1943 }
1944
1945 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1946 {
1947 FDrive *cur_drv = get_cur_drv(fdctrl);
1948 uint32_t pos;
1949
1950 pos = fdctrl->data_pos - 1;
1951 pos %= FD_SECTOR_LEN;
1952 if (fdctrl->fifo[pos] & 0x80) {
1953 /* Command parameters done */
1954 if (fdctrl->fifo[pos] & 0x40) {
1955 fdctrl->fifo[0] = fdctrl->fifo[1];
1956 fdctrl->fifo[2] = 0;
1957 fdctrl->fifo[3] = 0;
1958 fdctrl_to_result_phase(fdctrl, 4);
1959 } else {
1960 fdctrl_to_command_phase(fdctrl);
1961 }
1962 } else if (fdctrl->data_len > 7) {
1963 /* ERROR */
1964 fdctrl->fifo[0] = 0x80 |
1965 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1966 fdctrl_to_result_phase(fdctrl, 1);
1967 }
1968 }
1969
1970 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1971 {
1972 FDrive *cur_drv;
1973
1974 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1975 cur_drv = get_cur_drv(fdctrl);
1976 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1977 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1978 cur_drv->sect, 1);
1979 } else {
1980 fd_seek(cur_drv, cur_drv->head,
1981 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
1982 }
1983 fdctrl_to_command_phase(fdctrl);
1984 /* Raise Interrupt */
1985 fdctrl->status0 |= FD_SR0_SEEK;
1986 fdctrl_raise_irq(fdctrl);
1987 }
1988
1989 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1990 {
1991 FDrive *cur_drv;
1992
1993 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1994 cur_drv = get_cur_drv(fdctrl);
1995 if (fdctrl->fifo[2] > cur_drv->track) {
1996 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1997 } else {
1998 fd_seek(cur_drv, cur_drv->head,
1999 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2000 }
2001 fdctrl_to_command_phase(fdctrl);
2002 /* Raise Interrupt */
2003 fdctrl->status0 |= FD_SR0_SEEK;
2004 fdctrl_raise_irq(fdctrl);
2005 }
2006
2007 /*
2008 * Handlers for the execution phase of each command
2009 */
2010 typedef struct FDCtrlCommand {
2011 uint8_t value;
2012 uint8_t mask;
2013 const char* name;
2014 int parameters;
2015 void (*handler)(FDCtrl *fdctrl, int direction);
2016 int direction;
2017 } FDCtrlCommand;
2018
2019 static const FDCtrlCommand handlers[] = {
2020 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2021 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2022 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2023 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2024 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2025 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2026 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2027 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2028 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2029 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2030 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2031 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2032 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2033 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2034 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2035 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2036 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2037 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2038 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2039 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2040 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2041 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2042 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2043 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2044 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2045 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2046 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2047 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2048 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2049 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2050 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2051 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2052 };
2053 /* Associate command to an index in the 'handlers' array */
2054 static uint8_t command_to_handler[256];
2055
2056 static const FDCtrlCommand *get_command(uint8_t cmd)
2057 {
2058 int idx;
2059
2060 idx = command_to_handler[cmd];
2061 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2062 return &handlers[idx];
2063 }
2064
2065 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2066 {
2067 FDrive *cur_drv;
2068 const FDCtrlCommand *cmd;
2069 uint32_t pos;
2070
2071 /* Reset mode */
2072 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2073 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2074 return;
2075 }
2076 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2077 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2078 return;
2079 }
2080 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2081
2082 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2083
2084 /* If data_len spans multiple sectors, the current position in the FIFO
2085 * wraps around while fdctrl->data_pos is the real position in the whole
2086 * request. */
2087 pos = fdctrl->data_pos++;
2088 pos %= FD_SECTOR_LEN;
2089 fdctrl->fifo[pos] = value;
2090
2091 if (fdctrl->data_pos == fdctrl->data_len) {
2092 fdctrl->msr &= ~FD_MSR_RQM;
2093 }
2094
2095 switch (fdctrl->phase) {
2096 case FD_PHASE_EXECUTION:
2097 /* For DMA requests, RQM should be cleared during execution phase, so
2098 * we would have errored out above. */
2099 assert(fdctrl->msr & FD_MSR_NONDMA);
2100
2101 /* FIFO data write */
2102 if (pos == FD_SECTOR_LEN - 1 ||
2103 fdctrl->data_pos == fdctrl->data_len) {
2104 cur_drv = get_cur_drv(fdctrl);
2105 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
2106 < 0) {
2107 FLOPPY_DPRINTF("error writing sector %d\n",
2108 fd_sector(cur_drv));
2109 break;
2110 }
2111 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2112 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2113 fd_sector(cur_drv));
2114 break;
2115 }
2116 }
2117
2118 /* Switch to result phase when done with the transfer */
2119 if (fdctrl->data_pos == fdctrl->data_len) {
2120 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2121 }
2122 break;
2123
2124 case FD_PHASE_COMMAND:
2125 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2126 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2127
2128 if (pos == 0) {
2129 /* The first byte specifies the command. Now we start reading
2130 * as many parameters as this command requires. */
2131 cmd = get_command(value);
2132 fdctrl->data_len = cmd->parameters + 1;
2133 if (cmd->parameters) {
2134 fdctrl->msr |= FD_MSR_RQM;
2135 }
2136 fdctrl->msr |= FD_MSR_CMDBUSY;
2137 }
2138
2139 if (fdctrl->data_pos == fdctrl->data_len) {
2140 /* We have all parameters now, execute the command */
2141 fdctrl->phase = FD_PHASE_EXECUTION;
2142
2143 if (fdctrl->data_state & FD_STATE_FORMAT) {
2144 fdctrl_format_sector(fdctrl);
2145 break;
2146 }
2147
2148 cmd = get_command(fdctrl->fifo[0]);
2149 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2150 cmd->handler(fdctrl, cmd->direction);
2151 }
2152 break;
2153
2154 case FD_PHASE_RESULT:
2155 default:
2156 abort();
2157 }
2158 }
2159
2160 static void fdctrl_result_timer(void *opaque)
2161 {
2162 FDCtrl *fdctrl = opaque;
2163 FDrive *cur_drv = get_cur_drv(fdctrl);
2164
2165 /* Pretend we are spinning.
2166 * This is needed for Coherent, which uses READ ID to check for
2167 * sector interleaving.
2168 */
2169 if (cur_drv->last_sect != 0) {
2170 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2171 }
2172 /* READ_ID can't automatically succeed! */
2173 if (fdctrl->check_media_rate &&
2174 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2175 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2176 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2177 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2178 } else {
2179 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2180 }
2181 }
2182
2183 static void fdctrl_change_cb(void *opaque, bool load)
2184 {
2185 FDrive *drive = opaque;
2186
2187 drive->media_changed = 1;
2188 fd_revalidate(drive);
2189 }
2190
2191 static const BlockDevOps fdctrl_block_ops = {
2192 .change_media_cb = fdctrl_change_cb,
2193 };
2194
2195 /* Init functions */
2196 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
2197 {
2198 unsigned int i;
2199 FDrive *drive;
2200
2201 for (i = 0; i < MAX_FD; i++) {
2202 drive = &fdctrl->drives[i];
2203 drive->fdctrl = fdctrl;
2204
2205 if (drive->blk) {
2206 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2207 error_setg(errp, "fdc doesn't support drive option werror");
2208 return;
2209 }
2210 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2211 error_setg(errp, "fdc doesn't support drive option rerror");
2212 return;
2213 }
2214 }
2215
2216 fd_init(drive);
2217 fdctrl_change_cb(drive, 0);
2218 if (drive->blk) {
2219 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2220 }
2221 }
2222 }
2223
2224 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2225 {
2226 DeviceState *dev;
2227 ISADevice *isadev;
2228
2229 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2230 if (!isadev) {
2231 return NULL;
2232 }
2233 dev = DEVICE(isadev);
2234
2235 if (fds[0]) {
2236 qdev_prop_set_drive_nofail(dev, "driveA", blk_by_legacy_dinfo(fds[0]));
2237 }
2238 if (fds[1]) {
2239 qdev_prop_set_drive_nofail(dev, "driveB", blk_by_legacy_dinfo(fds[1]));
2240 }
2241 qdev_init_nofail(dev);
2242
2243 return isadev;
2244 }
2245
2246 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2247 hwaddr mmio_base, DriveInfo **fds)
2248 {
2249 FDCtrl *fdctrl;
2250 DeviceState *dev;
2251 SysBusDevice *sbd;
2252 FDCtrlSysBus *sys;
2253
2254 dev = qdev_create(NULL, "sysbus-fdc");
2255 sys = SYSBUS_FDC(dev);
2256 fdctrl = &sys->state;
2257 fdctrl->dma_chann = dma_chann; /* FIXME */
2258 if (fds[0]) {
2259 qdev_prop_set_drive_nofail(dev, "driveA", blk_by_legacy_dinfo(fds[0]));
2260 }
2261 if (fds[1]) {
2262 qdev_prop_set_drive_nofail(dev, "driveB", blk_by_legacy_dinfo(fds[1]));
2263 }
2264 qdev_init_nofail(dev);
2265 sbd = SYS_BUS_DEVICE(dev);
2266 sysbus_connect_irq(sbd, 0, irq);
2267 sysbus_mmio_map(sbd, 0, mmio_base);
2268 }
2269
2270 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2271 DriveInfo **fds, qemu_irq *fdc_tc)
2272 {
2273 DeviceState *dev;
2274 FDCtrlSysBus *sys;
2275
2276 dev = qdev_create(NULL, "SUNW,fdtwo");
2277 if (fds[0]) {
2278 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(fds[0]));
2279 }
2280 qdev_init_nofail(dev);
2281 sys = SYSBUS_FDC(dev);
2282 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2283 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2284 *fdc_tc = qdev_get_gpio_in(dev, 0);
2285 }
2286
2287 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
2288 {
2289 int i, j;
2290 static int command_tables_inited = 0;
2291
2292 /* Fill 'command_to_handler' lookup table */
2293 if (!command_tables_inited) {
2294 command_tables_inited = 1;
2295 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2296 for (j = 0; j < sizeof(command_to_handler); j++) {
2297 if ((j & handlers[i].mask) == handlers[i].value) {
2298 command_to_handler[j] = i;
2299 }
2300 }
2301 }
2302 }
2303
2304 FLOPPY_DPRINTF("init controller\n");
2305 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2306 fdctrl->fifo_size = 512;
2307 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2308 fdctrl_result_timer, fdctrl);
2309
2310 fdctrl->version = 0x90; /* Intel 82078 controller */
2311 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2312 fdctrl->num_floppies = MAX_FD;
2313
2314 if (fdctrl->dma_chann != -1) {
2315 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2316 }
2317 fdctrl_connect_drives(fdctrl, errp);
2318 }
2319
2320 static const MemoryRegionPortio fdc_portio_list[] = {
2321 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2322 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2323 PORTIO_END_OF_LIST(),
2324 };
2325
2326 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2327 {
2328 ISADevice *isadev = ISA_DEVICE(dev);
2329 FDCtrlISABus *isa = ISA_FDC(dev);
2330 FDCtrl *fdctrl = &isa->state;
2331 Error *err = NULL;
2332
2333 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2334 "fdc");
2335
2336 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2337 fdctrl->dma_chann = isa->dma;
2338
2339 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2340 fdctrl_realize_common(fdctrl, &err);
2341 if (err != NULL) {
2342 error_propagate(errp, err);
2343 return;
2344 }
2345 }
2346
2347 static void sysbus_fdc_initfn(Object *obj)
2348 {
2349 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2350 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2351 FDCtrl *fdctrl = &sys->state;
2352
2353 fdctrl->dma_chann = -1;
2354
2355 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2356 "fdc", 0x08);
2357 sysbus_init_mmio(sbd, &fdctrl->iomem);
2358 }
2359
2360 static void sun4m_fdc_initfn(Object *obj)
2361 {
2362 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2363 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2364 FDCtrl *fdctrl = &sys->state;
2365
2366 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2367 fdctrl, "fdctrl", 0x08);
2368 sysbus_init_mmio(sbd, &fdctrl->iomem);
2369 }
2370
2371 static void sysbus_fdc_common_initfn(Object *obj)
2372 {
2373 DeviceState *dev = DEVICE(obj);
2374 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2375 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2376 FDCtrl *fdctrl = &sys->state;
2377
2378 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2379
2380 sysbus_init_irq(sbd, &fdctrl->irq);
2381 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2382 }
2383
2384 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2385 {
2386 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2387 FDCtrl *fdctrl = &sys->state;
2388
2389 fdctrl_realize_common(fdctrl, errp);
2390 }
2391
2392 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2393 {
2394 FDCtrlISABus *isa = ISA_FDC(fdc);
2395
2396 return isa->state.drives[i].drive;
2397 }
2398
2399 static const VMStateDescription vmstate_isa_fdc ={
2400 .name = "fdc",
2401 .version_id = 2,
2402 .minimum_version_id = 2,
2403 .fields = (VMStateField[]) {
2404 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2405 VMSTATE_END_OF_LIST()
2406 }
2407 };
2408
2409 static Property isa_fdc_properties[] = {
2410 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2411 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2412 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2413 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2414 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
2415 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2416 0, true),
2417 DEFINE_PROP_END_OF_LIST(),
2418 };
2419
2420 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2421 {
2422 DeviceClass *dc = DEVICE_CLASS(klass);
2423
2424 dc->realize = isabus_fdc_realize;
2425 dc->fw_name = "fdc";
2426 dc->reset = fdctrl_external_reset_isa;
2427 dc->vmsd = &vmstate_isa_fdc;
2428 dc->props = isa_fdc_properties;
2429 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2430 }
2431
2432 static void isabus_fdc_instance_init(Object *obj)
2433 {
2434 FDCtrlISABus *isa = ISA_FDC(obj);
2435
2436 device_add_bootindex_property(obj, &isa->bootindexA,
2437 "bootindexA", "/floppy@0",
2438 DEVICE(obj), NULL);
2439 device_add_bootindex_property(obj, &isa->bootindexB,
2440 "bootindexB", "/floppy@1",
2441 DEVICE(obj), NULL);
2442 }
2443
2444 static const TypeInfo isa_fdc_info = {
2445 .name = TYPE_ISA_FDC,
2446 .parent = TYPE_ISA_DEVICE,
2447 .instance_size = sizeof(FDCtrlISABus),
2448 .class_init = isabus_fdc_class_init,
2449 .instance_init = isabus_fdc_instance_init,
2450 };
2451
2452 static const VMStateDescription vmstate_sysbus_fdc ={
2453 .name = "fdc",
2454 .version_id = 2,
2455 .minimum_version_id = 2,
2456 .fields = (VMStateField[]) {
2457 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2458 VMSTATE_END_OF_LIST()
2459 }
2460 };
2461
2462 static Property sysbus_fdc_properties[] = {
2463 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2464 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
2465 DEFINE_PROP_END_OF_LIST(),
2466 };
2467
2468 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2469 {
2470 DeviceClass *dc = DEVICE_CLASS(klass);
2471
2472 dc->props = sysbus_fdc_properties;
2473 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2474 }
2475
2476 static const TypeInfo sysbus_fdc_info = {
2477 .name = "sysbus-fdc",
2478 .parent = TYPE_SYSBUS_FDC,
2479 .instance_init = sysbus_fdc_initfn,
2480 .class_init = sysbus_fdc_class_init,
2481 };
2482
2483 static Property sun4m_fdc_properties[] = {
2484 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
2485 DEFINE_PROP_END_OF_LIST(),
2486 };
2487
2488 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2489 {
2490 DeviceClass *dc = DEVICE_CLASS(klass);
2491
2492 dc->props = sun4m_fdc_properties;
2493 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2494 }
2495
2496 static const TypeInfo sun4m_fdc_info = {
2497 .name = "SUNW,fdtwo",
2498 .parent = TYPE_SYSBUS_FDC,
2499 .instance_init = sun4m_fdc_initfn,
2500 .class_init = sun4m_fdc_class_init,
2501 };
2502
2503 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2504 {
2505 DeviceClass *dc = DEVICE_CLASS(klass);
2506
2507 dc->realize = sysbus_fdc_common_realize;
2508 dc->reset = fdctrl_external_reset_sysbus;
2509 dc->vmsd = &vmstate_sysbus_fdc;
2510 }
2511
2512 static const TypeInfo sysbus_fdc_type_info = {
2513 .name = TYPE_SYSBUS_FDC,
2514 .parent = TYPE_SYS_BUS_DEVICE,
2515 .instance_size = sizeof(FDCtrlSysBus),
2516 .instance_init = sysbus_fdc_common_initfn,
2517 .abstract = true,
2518 .class_init = sysbus_fdc_common_class_init,
2519 };
2520
2521 static void fdc_register_types(void)
2522 {
2523 type_register_static(&isa_fdc_info);
2524 type_register_static(&sysbus_fdc_type_info);
2525 type_register_static(&sysbus_fdc_info);
2526 type_register_static(&sun4m_fdc_info);
2527 }
2528
2529 type_init(fdc_register_types)
AR7 emulation for QEMU