target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
  24                               int mmu_idx)
  25 {
  26     int prot;
  27
  28     address &= TARGET_PAGE_MASK;
  29     prot = PAGE_BITS;
  30     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  31         tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
  32                 TARGET_PAGE_SIZE);
  33     } else {
  34         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  35     }
  36
  37     return 0;
  38 }
  39
  40 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
  41 {
  42     LM32CPU *cpu = LM32_CPU(cs);
  43
  44     addr &= TARGET_PAGE_MASK;
  45     if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
  46         return addr & 0x7fffffff;
  47     } else {
  48         return addr;
  49     }
  50 }
  51
  52 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
  53 {
  54     cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]);
  55 }
  56
  57 void lm32_breakpoint_remove(CPULM32State *env, int idx)
  58 {
  59     if (!env->cpu_breakpoint[idx]) {
  60         return;
  61     }
  62
  63     cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]);
  64     env->cpu_breakpoint[idx] = NULL;
  65 }
  66
  67 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
  68                             lm32_wp_t wp_type)
  69 {
  70     int flags = 0;
  71
  72     switch (wp_type) {
  73     case LM32_WP_DISABLED:
  74         /* nothing to to */
  75         break;
  76     case LM32_WP_READ:
  77         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
  78         break;
  79     case LM32_WP_WRITE:
  80         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
  81         break;
  82     case LM32_WP_READ_WRITE:
  83         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
  84         break;
  85     }
  86
  87     if (flags != 0) {
  88         cpu_watchpoint_insert(env, address, 1, flags,
  89                 &env->cpu_watchpoint[idx]);
  90     }
  91 }
  92
  93 void lm32_watchpoint_remove(CPULM32State *env, int idx)
  94 {
  95     if (!env->cpu_watchpoint[idx]) {
  96         return;
  97     }
  98
  99     cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]);
 100     env->cpu_watchpoint[idx] = NULL;
 101 }
 102
 103 static bool check_watchpoints(CPULM32State *env)
 104 {
 105     LM32CPU *cpu = lm32_env_get_cpu(env);
 106     int i;
 107
 108     for (i = 0; i < cpu->num_watchpoints; i++) {
 109         if (env->cpu_watchpoint[i] &&
 110                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
 111             return true;
 112         }
 113     }
 114     return false;
 115 }
 116
 117 void lm32_debug_excp_handler(CPULM32State *env)
 118 {
 119     CPUBreakpoint *bp;
 120
 121     if (env->watchpoint_hit) {
 122         if (env->watchpoint_hit->flags & BP_CPU) {
 123             env->watchpoint_hit = NULL;
 124             if (check_watchpoints(env)) {
 125                 raise_exception(env, EXCP_WATCHPOINT);
 126             } else {
 127                 cpu_resume_from_signal(env, NULL);
 128             }
 129         }
 130     } else {
 131         QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
 132             if (bp->pc == env->pc) {
 133                 if (bp->flags & BP_CPU) {
 134                     raise_exception(env, EXCP_BREAKPOINT);
 135                 }
 136                 break;
 137             }
 138         }
 139     }
 140 }
 141
 142 void lm32_cpu_do_interrupt(CPUState *cs)
 143 {
 144     LM32CPU *cpu = LM32_CPU(cs);
 145     CPULM32State *env = &cpu->env;
 146
 147     qemu_log_mask(CPU_LOG_INT,
 148             "exception at pc=%x type=%x\n", env->pc, env->exception_index);
 149
 150     switch (env->exception_index) {
 151     case EXCP_INSN_BUS_ERROR:
 152     case EXCP_DATA_BUS_ERROR:
 153     case EXCP_DIVIDE_BY_ZERO:
 154     case EXCP_IRQ:
 155     case EXCP_SYSTEMCALL:
 156         /* non-debug exceptions */
 157         env->regs[R_EA] = env->pc;
 158         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
 159         env->ie &= ~IE_IE;
 160         if (env->dc & DC_RE) {
 161             env->pc = env->deba + (env->exception_index * 32);
 162         } else {
 163             env->pc = env->eba + (env->exception_index * 32);
 164         }
 165         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 166         break;
 167     case EXCP_BREAKPOINT:
 168     case EXCP_WATCHPOINT:
 169         /* debug exceptions */
 170         env->regs[R_BA] = env->pc;
 171         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
 172         env->ie &= ~IE_IE;
 173         env->pc = env->deba + (env->exception_index * 32);
 174         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 175         break;
 176     default:
 177         cpu_abort(env, "unhandled exception type=%d\n",
 178                   env->exception_index);
 179         break;
 180     }
 181 }
 182
 183 LM32CPU *cpu_lm32_init(const char *cpu_model)
 184 {
 185     LM32CPU *cpu;
 186     ObjectClass *oc;
 187
 188     oc = cpu_class_by_name(TYPE_LM32_CPU, cpu_model);
 189     if (oc == NULL) {
 190         return NULL;
 191     }
 192     cpu = LM32_CPU(object_new(object_class_get_name(oc)));
 193
 194     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 195
 196     return cpu;
 197 }
 198
 199 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 200  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 201  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 202 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 203 {
 204     if (value) {
 205         env->flags |= LM32_FLAG_IGNORE_MSB;
 206     } else {
 207         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 208     }
 209 }