fsdev: improve error handling of backend init
[qemu/ar7.git] / target / xtensa / op_helper.c
blob3d990c0caa44f722c509953a777883a46ec6b489
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qemu/main-loop.h"
30 #include "cpu.h"
31 #include "exec/helper-proto.h"
32 #include "qemu/host-utils.h"
33 #include "exec/exec-all.h"
34 #include "exec/cpu_ldst.h"
35 #include "exec/address-spaces.h"
36 #include "qemu/timer.h"
38 void xtensa_cpu_do_unaligned_access(CPUState *cs,
39 vaddr addr, MMUAccessType access_type,
40 int mmu_idx, uintptr_t retaddr)
42 XtensaCPU *cpu = XTENSA_CPU(cs);
43 CPUXtensaState *env = &cpu->env;
45 if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
46 !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
47 cpu_restore_state(CPU(cpu), retaddr);
48 HELPER(exception_cause_vaddr)(env,
49 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
53 void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAccessType access_type,
54 int mmu_idx, uintptr_t retaddr)
56 XtensaCPU *cpu = XTENSA_CPU(cs);
57 CPUXtensaState *env = &cpu->env;
58 uint32_t paddr;
59 uint32_t page_size;
60 unsigned access;
61 int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx,
62 &paddr, &page_size, &access);
64 qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
65 __func__, vaddr, access_type, mmu_idx, paddr, ret);
67 if (ret == 0) {
68 tlb_set_page(cs,
69 vaddr & TARGET_PAGE_MASK,
70 paddr & TARGET_PAGE_MASK,
71 access, mmu_idx, page_size);
72 } else {
73 cpu_restore_state(cs, retaddr);
74 HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
78 void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,
79 bool is_write, bool is_exec, int opaque,
80 unsigned size)
82 XtensaCPU *cpu = XTENSA_CPU(cs);
83 CPUXtensaState *env = &cpu->env;
85 HELPER(exception_cause_vaddr)(env, env->pc,
86 is_exec ?
87 INSTR_PIF_ADDR_ERROR_CAUSE :
88 LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
89 is_exec ? addr : cs->mem_io_vaddr);
92 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
94 uint32_t paddr;
95 uint32_t page_size;
96 unsigned access;
97 int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
98 &paddr, &page_size, &access);
99 if (ret == 0) {
100 tb_invalidate_phys_addr(&address_space_memory, paddr);
104 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
106 CPUState *cs = CPU(xtensa_env_get_cpu(env));
108 cs->exception_index = excp;
109 if (excp == EXCP_YIELD) {
110 env->yield_needed = 0;
112 if (excp == EXCP_DEBUG) {
113 env->exception_taken = 0;
115 cpu_loop_exit(cs);
118 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
120 uint32_t vector;
122 env->pc = pc;
123 if (env->sregs[PS] & PS_EXCM) {
124 if (env->config->ndepc) {
125 env->sregs[DEPC] = pc;
126 } else {
127 env->sregs[EPC1] = pc;
129 vector = EXC_DOUBLE;
130 } else {
131 env->sregs[EPC1] = pc;
132 vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
135 env->sregs[EXCCAUSE] = cause;
136 env->sregs[PS] |= PS_EXCM;
138 HELPER(exception)(env, vector);
141 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
142 uint32_t pc, uint32_t cause, uint32_t vaddr)
144 env->sregs[EXCVADDR] = vaddr;
145 HELPER(exception_cause)(env, pc, cause);
148 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
150 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
151 HELPER(debug_exception)(env, env->pc, cause);
155 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
157 unsigned level = env->config->debug_level;
159 env->pc = pc;
160 env->sregs[DEBUGCAUSE] = cause;
161 env->sregs[EPC1 + level - 1] = pc;
162 env->sregs[EPS2 + level - 2] = env->sregs[PS];
163 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
164 (level << PS_INTLEVEL_SHIFT);
165 HELPER(exception)(env, EXC_DEBUG);
168 static void copy_window_from_phys(CPUXtensaState *env,
169 uint32_t window, uint32_t phys, uint32_t n)
171 assert(phys < env->config->nareg);
172 if (phys + n <= env->config->nareg) {
173 memcpy(env->regs + window, env->phys_regs + phys,
174 n * sizeof(uint32_t));
175 } else {
176 uint32_t n1 = env->config->nareg - phys;
177 memcpy(env->regs + window, env->phys_regs + phys,
178 n1 * sizeof(uint32_t));
179 memcpy(env->regs + window + n1, env->phys_regs,
180 (n - n1) * sizeof(uint32_t));
184 static void copy_phys_from_window(CPUXtensaState *env,
185 uint32_t phys, uint32_t window, uint32_t n)
187 assert(phys < env->config->nareg);
188 if (phys + n <= env->config->nareg) {
189 memcpy(env->phys_regs + phys, env->regs + window,
190 n * sizeof(uint32_t));
191 } else {
192 uint32_t n1 = env->config->nareg - phys;
193 memcpy(env->phys_regs + phys, env->regs + window,
194 n1 * sizeof(uint32_t));
195 memcpy(env->phys_regs, env->regs + window + n1,
196 (n - n1) * sizeof(uint32_t));
201 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
203 return a & (env->config->nareg / 4 - 1);
206 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
208 return 1 << windowbase_bound(a, env);
211 void xtensa_sync_window_from_phys(CPUXtensaState *env)
213 copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
216 void xtensa_sync_phys_from_window(CPUXtensaState *env)
218 copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
221 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
223 xtensa_sync_phys_from_window(env);
224 env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
225 xtensa_sync_window_from_phys(env);
228 static void rotate_window(CPUXtensaState *env, uint32_t delta)
230 rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
233 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
235 rotate_window_abs(env, v);
238 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
240 int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
241 if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
242 qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n",
243 pc, env->sregs[PS]);
244 HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
245 } else {
246 uint32_t windowstart = xtensa_replicate_windowstart(env) >>
247 (env->sregs[WINDOW_BASE] + 1);
249 if (windowstart & ((1 << callinc) - 1)) {
250 HELPER(window_check)(env, pc, callinc);
252 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
253 rotate_window(env, callinc);
254 env->sregs[WINDOW_START] |=
255 windowstart_bit(env->sregs[WINDOW_BASE], env);
259 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
261 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
262 uint32_t windowstart = xtensa_replicate_windowstart(env) >>
263 (env->sregs[WINDOW_BASE] + 1);
264 uint32_t n = ctz32(windowstart) + 1;
266 assert(n <= w);
268 rotate_window(env, n);
269 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
270 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
271 env->sregs[EPC1] = env->pc = pc;
273 switch (ctz32(windowstart >> n)) {
274 case 0:
275 HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
276 break;
277 case 1:
278 HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
279 break;
280 default:
281 HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
282 break;
286 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
288 int n = (env->regs[0] >> 30) & 0x3;
289 int m = 0;
290 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
291 uint32_t windowstart = env->sregs[WINDOW_START];
292 uint32_t ret_pc = 0;
294 if (windowstart & windowstart_bit(windowbase - 1, env)) {
295 m = 1;
296 } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
297 m = 2;
298 } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
299 m = 3;
302 if (n == 0 || (m != 0 && m != n) ||
303 ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
304 qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), "
305 "PS = %08x, m = %d, n = %d\n",
306 pc, env->sregs[PS], m, n);
307 HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
308 } else {
309 int owb = windowbase;
311 ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
313 rotate_window(env, -n);
314 if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
315 env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
316 } else {
317 /* window underflow */
318 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
319 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
320 env->sregs[EPC1] = env->pc = pc;
322 if (n == 1) {
323 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
324 } else if (n == 2) {
325 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
326 } else if (n == 3) {
327 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
331 return ret_pc;
334 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
336 rotate_window(env, imm4);
339 void HELPER(restore_owb)(CPUXtensaState *env)
341 rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
344 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
346 if ((env->sregs[WINDOW_START] &
347 (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
348 windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
349 windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
350 HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
354 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
356 if (env->sregs[LBEG] != v) {
357 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
358 env->sregs[LBEG] = v;
362 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
364 if (env->sregs[LEND] != v) {
365 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
366 env->sregs[LEND] = v;
367 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
371 void HELPER(dump_state)(CPUXtensaState *env)
373 XtensaCPU *cpu = xtensa_env_get_cpu(env);
375 cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
378 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
380 CPUState *cpu;
382 env->pc = pc;
383 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
384 (intlevel << PS_INTLEVEL_SHIFT);
386 qemu_mutex_lock_iothread();
387 check_interrupts(env);
388 qemu_mutex_unlock_iothread();
390 if (env->pending_irq_level) {
391 cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
392 return;
395 cpu = CPU(xtensa_env_get_cpu(env));
396 cpu->halted = 1;
397 HELPER(exception)(env, EXCP_HLT);
400 void HELPER(update_ccount)(CPUXtensaState *env)
402 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
404 env->ccount_time = now;
405 env->sregs[CCOUNT] = env->ccount_base +
406 (uint32_t)((now - env->time_base) *
407 env->config->clock_freq_khz / 1000000);
410 void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
412 int i;
414 HELPER(update_ccount)(env);
415 env->ccount_base += v - env->sregs[CCOUNT];
416 for (i = 0; i < env->config->nccompare; ++i) {
417 HELPER(update_ccompare)(env, i);
421 void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
423 uint64_t dcc;
425 HELPER(update_ccount)(env);
426 dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
427 timer_mod(env->ccompare[i].timer,
428 env->ccount_time + (dcc * 1000000) / env->config->clock_freq_khz);
429 env->yield_needed = 1;
432 void HELPER(check_interrupts)(CPUXtensaState *env)
434 qemu_mutex_lock_iothread();
435 check_interrupts(env);
436 qemu_mutex_unlock_iothread();
439 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
441 get_page_addr_code(env, vaddr);
445 * Check vaddr accessibility/cache attributes and raise an exception if
446 * specified by the ATOMCTL SR.
448 * Note: local memory exclusion is not implemented
450 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
452 uint32_t paddr, page_size, access;
453 uint32_t atomctl = env->sregs[ATOMCTL];
454 int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
455 xtensa_get_cring(env), &paddr, &page_size, &access);
458 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
459 * see opcode description in the ISA
461 if (rc == 0 &&
462 (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
463 rc = STORE_PROHIBITED_CAUSE;
466 if (rc) {
467 HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
471 * When data cache is not configured use ATOMCTL bypass field.
472 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
473 * under the Conditional Store Option.
475 if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
476 access = PAGE_CACHE_BYPASS;
479 switch (access & PAGE_CACHE_MASK) {
480 case PAGE_CACHE_WB:
481 atomctl >>= 2;
482 /* fall through */
483 case PAGE_CACHE_WT:
484 atomctl >>= 2;
485 /* fall through */
486 case PAGE_CACHE_BYPASS:
487 if ((atomctl & 0x3) == 0) {
488 HELPER(exception_cause_vaddr)(env, pc,
489 LOAD_STORE_ERROR_CAUSE, vaddr);
491 break;
493 case PAGE_CACHE_ISOLATE:
494 HELPER(exception_cause_vaddr)(env, pc,
495 LOAD_STORE_ERROR_CAUSE, vaddr);
496 break;
498 default:
499 break;
503 void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v)
505 if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) {
506 if (extract32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN) >
507 env->config->icache_ways) {
508 deposit32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN,
509 env->config->icache_ways);
512 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
513 if (extract32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN) >
514 env->config->dcache_ways) {
515 deposit32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN,
516 env->config->dcache_ways);
518 if (extract32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN) >
519 env->config->dcache_ways) {
520 deposit32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN,
521 env->config->dcache_ways);
524 env->sregs[MEMCTL] = v & env->config->memctl_mask;
527 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
529 XtensaCPU *cpu = xtensa_env_get_cpu(env);
531 v = (v & 0xffffff00) | 0x1;
532 if (v != env->sregs[RASID]) {
533 env->sregs[RASID] = v;
534 tlb_flush(CPU(cpu));
538 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
540 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
542 switch (way) {
543 case 4:
544 return (tlbcfg >> 16) & 0x3;
546 case 5:
547 return (tlbcfg >> 20) & 0x1;
549 case 6:
550 return (tlbcfg >> 24) & 0x1;
552 default:
553 return 0;
558 * Get bit mask for the virtual address bits translated by the TLB way
560 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
562 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
563 bool varway56 = dtlb ?
564 env->config->dtlb.varway56 :
565 env->config->itlb.varway56;
567 switch (way) {
568 case 4:
569 return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
571 case 5:
572 if (varway56) {
573 return 0xf8000000 << get_page_size(env, dtlb, way);
574 } else {
575 return 0xf8000000;
578 case 6:
579 if (varway56) {
580 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
581 } else {
582 return 0xf0000000;
585 default:
586 return 0xfffff000;
588 } else {
589 return REGION_PAGE_MASK;
594 * Get bit mask for the 'VPN without index' field.
595 * See ISA, 4.6.5.6, data format for RxTLB0
597 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
599 if (way < 4) {
600 bool is32 = (dtlb ?
601 env->config->dtlb.nrefillentries :
602 env->config->itlb.nrefillentries) == 32;
603 return is32 ? 0xffff8000 : 0xffffc000;
604 } else if (way == 4) {
605 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
606 } else if (way <= 6) {
607 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
608 bool varway56 = dtlb ?
609 env->config->dtlb.varway56 :
610 env->config->itlb.varway56;
612 if (varway56) {
613 return mask << (way == 5 ? 2 : 3);
614 } else {
615 return mask << 1;
617 } else {
618 return 0xfffff000;
623 * Split virtual address into VPN (with index) and entry index
624 * for the given TLB way
626 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
627 uint32_t *vpn, uint32_t wi, uint32_t *ei)
629 bool varway56 = dtlb ?
630 env->config->dtlb.varway56 :
631 env->config->itlb.varway56;
633 if (!dtlb) {
634 wi &= 7;
637 if (wi < 4) {
638 bool is32 = (dtlb ?
639 env->config->dtlb.nrefillentries :
640 env->config->itlb.nrefillentries) == 32;
641 *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
642 } else {
643 switch (wi) {
644 case 4:
646 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
647 *ei = (v >> eibase) & 0x3;
649 break;
651 case 5:
652 if (varway56) {
653 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
654 *ei = (v >> eibase) & 0x3;
655 } else {
656 *ei = (v >> 27) & 0x1;
658 break;
660 case 6:
661 if (varway56) {
662 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
663 *ei = (v >> eibase) & 0x7;
664 } else {
665 *ei = (v >> 28) & 0x1;
667 break;
669 default:
670 *ei = 0;
671 break;
674 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
678 * Split TLB address into TLB way, entry index and VPN (with index).
679 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
681 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
682 uint32_t *vpn, uint32_t *wi, uint32_t *ei)
684 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
685 *wi = v & (dtlb ? 0xf : 0x7);
686 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
687 } else {
688 *vpn = v & REGION_PAGE_MASK;
689 *wi = 0;
690 *ei = (v >> 29) & 0x7;
694 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
695 uint32_t v, bool dtlb, uint32_t *pwi)
697 uint32_t vpn;
698 uint32_t wi;
699 uint32_t ei;
701 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
702 if (pwi) {
703 *pwi = wi;
705 return xtensa_tlb_get_entry(env, dtlb, wi, ei);
708 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
710 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
711 uint32_t wi;
712 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
713 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
714 } else {
715 return v & REGION_PAGE_MASK;
719 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
721 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
722 return entry->paddr | entry->attr;
725 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
727 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
728 uint32_t wi;
729 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
730 if (entry->variable && entry->asid) {
731 tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
732 entry->asid = 0;
737 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
739 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
740 uint32_t wi;
741 uint32_t ei;
742 uint8_t ring;
743 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
745 switch (res) {
746 case 0:
747 if (ring >= xtensa_get_ring(env)) {
748 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
750 break;
752 case INST_TLB_MULTI_HIT_CAUSE:
753 case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
754 HELPER(exception_cause_vaddr)(env, env->pc, res, v);
755 break;
757 return 0;
758 } else {
759 return (v & REGION_PAGE_MASK) | 0x1;
763 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
764 xtensa_tlb_entry *entry, bool dtlb,
765 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
767 entry->vaddr = vpn;
768 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
769 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
770 entry->attr = pte & 0xf;
773 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
774 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
776 XtensaCPU *cpu = xtensa_env_get_cpu(env);
777 CPUState *cs = CPU(cpu);
778 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
780 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
781 if (entry->variable) {
782 if (entry->asid) {
783 tlb_flush_page(cs, entry->vaddr);
785 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
786 tlb_flush_page(cs, entry->vaddr);
787 } else {
788 qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set immutable entry\n",
789 __func__, dtlb, wi, ei);
791 } else {
792 tlb_flush_page(cs, entry->vaddr);
793 if (xtensa_option_enabled(env->config,
794 XTENSA_OPTION_REGION_TRANSLATION)) {
795 entry->paddr = pte & REGION_PAGE_MASK;
797 entry->attr = pte & 0xf;
801 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
803 uint32_t vpn;
804 uint32_t wi;
805 uint32_t ei;
806 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
807 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
811 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
813 uint32_t change = v ^ env->sregs[IBREAKENABLE];
814 unsigned i;
816 for (i = 0; i < env->config->nibreak; ++i) {
817 if (change & (1 << i)) {
818 tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
821 env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
824 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
826 if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
827 tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
828 tb_invalidate_virtual_addr(env, v);
830 env->sregs[IBREAKA + i] = v;
833 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
834 uint32_t dbreakc)
836 CPUState *cs = CPU(xtensa_env_get_cpu(env));
837 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
838 uint32_t mask = dbreakc | ~DBREAKC_MASK;
840 if (env->cpu_watchpoint[i]) {
841 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
843 if (dbreakc & DBREAKC_SB) {
844 flags |= BP_MEM_WRITE;
846 if (dbreakc & DBREAKC_LB) {
847 flags |= BP_MEM_READ;
849 /* contiguous mask after inversion is one less than some power of 2 */
850 if ((~mask + 1) & ~mask) {
851 qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
852 /* cut mask after the first zero bit */
853 mask = 0xffffffff << (32 - clo32(mask));
855 if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
856 flags, &env->cpu_watchpoint[i])) {
857 env->cpu_watchpoint[i] = NULL;
858 qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n",
859 dbreaka & mask, ~mask + 1);
863 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
865 uint32_t dbreakc = env->sregs[DBREAKC + i];
867 if ((dbreakc & DBREAKC_SB_LB) &&
868 env->sregs[DBREAKA + i] != v) {
869 set_dbreak(env, i, v, dbreakc);
871 env->sregs[DBREAKA + i] = v;
874 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
876 if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
877 if (v & DBREAKC_SB_LB) {
878 set_dbreak(env, i, env->sregs[DBREAKA + i], v);
879 } else {
880 if (env->cpu_watchpoint[i]) {
881 CPUState *cs = CPU(xtensa_env_get_cpu(env));
883 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
884 env->cpu_watchpoint[i] = NULL;
888 env->sregs[DBREAKC + i] = v;
891 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
893 static const int rounding_mode[] = {
894 float_round_nearest_even,
895 float_round_to_zero,
896 float_round_up,
897 float_round_down,
900 env->uregs[FCR] = v & 0xfffff07f;
901 set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
904 float32 HELPER(abs_s)(float32 v)
906 return float32_abs(v);
909 float32 HELPER(neg_s)(float32 v)
911 return float32_chs(v);
914 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
916 return float32_add(a, b, &env->fp_status);
919 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
921 return float32_sub(a, b, &env->fp_status);
924 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
926 return float32_mul(a, b, &env->fp_status);
929 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
931 return float32_muladd(b, c, a, 0,
932 &env->fp_status);
935 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
937 return float32_muladd(b, c, a, float_muladd_negate_product,
938 &env->fp_status);
941 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
943 float_status fp_status = {0};
945 set_float_rounding_mode(rounding_mode, &fp_status);
946 return float32_to_int32(
947 float32_scalbn(v, scale, &fp_status), &fp_status);
950 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
952 float_status fp_status = {0};
953 float32 res;
955 set_float_rounding_mode(rounding_mode, &fp_status);
957 res = float32_scalbn(v, scale, &fp_status);
959 if (float32_is_neg(v) && !float32_is_any_nan(v)) {
960 return float32_to_int32(res, &fp_status);
961 } else {
962 return float32_to_uint32(res, &fp_status);
966 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
968 return float32_scalbn(int32_to_float32(v, &env->fp_status),
969 (int32_t)scale, &env->fp_status);
972 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
974 return float32_scalbn(uint32_to_float32(v, &env->fp_status),
975 (int32_t)scale, &env->fp_status);
978 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
980 if (v) {
981 env->sregs[BR] |= br;
982 } else {
983 env->sregs[BR] &= ~br;
987 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
989 set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
992 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
994 set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
997 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
999 int v = float32_compare_quiet(a, b, &env->fp_status);
1000 set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
1003 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
1005 set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
1008 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
1010 int v = float32_compare_quiet(a, b, &env->fp_status);
1011 set_br(env, v == float_relation_less || v == float_relation_unordered, br);
1014 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
1016 set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
1019 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
1021 int v = float32_compare_quiet(a, b, &env->fp_status);
1022 set_br(env, v != float_relation_greater, br);
1025 uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr)
1027 return address_space_ldl(env->address_space_er, addr,
1028 MEMTXATTRS_UNSPECIFIED, NULL);
1031 void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr)
1033 address_space_stl(env->address_space_er, addr, data,
1034 MEMTXATTRS_UNSPECIFIED, NULL);