2 * Channel subsystem base support.
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "qapi/visitor.h"
16 #include "qemu/bitops.h"
17 #include "qemu/error-report.h"
18 #include "exec/address-spaces.h"
20 #include "hw/s390x/ioinst.h"
21 #include "hw/s390x/css.h"
23 #include "hw/s390x/s390_flic.h"
24 #include "hw/s390x/s390-virtio-ccw.h"
26 typedef struct CrwContainer
{
28 QTAILQ_ENTRY(CrwContainer
) sibling
;
31 static const VMStateDescription vmstate_crw
= {
34 .minimum_version_id
= 1,
35 .fields
= (VMStateField
[]) {
36 VMSTATE_UINT16(flags
, CRW
),
37 VMSTATE_UINT16(rsid
, CRW
),
42 static const VMStateDescription vmstate_crw_container
= {
43 .name
= "s390_crw_container",
45 .minimum_version_id
= 1,
46 .fields
= (VMStateField
[]) {
47 VMSTATE_STRUCT(crw
, CrwContainer
, 0, vmstate_crw
, CRW
),
52 typedef struct ChpInfo
{
58 static const VMStateDescription vmstate_chp_info
= {
59 .name
= "s390_chp_info",
61 .minimum_version_id
= 1,
62 .fields
= (VMStateField
[]) {
63 VMSTATE_UINT8(in_use
, ChpInfo
),
64 VMSTATE_UINT8(type
, ChpInfo
),
65 VMSTATE_UINT8(is_virtual
, ChpInfo
),
70 typedef struct SubchSet
{
71 SubchDev
*sch
[MAX_SCHID
+ 1];
72 unsigned long schids_used
[BITS_TO_LONGS(MAX_SCHID
+ 1)];
73 unsigned long devnos_used
[BITS_TO_LONGS(MAX_SCHID
+ 1)];
76 static const VMStateDescription vmstate_scsw
= {
79 .minimum_version_id
= 1,
80 .fields
= (VMStateField
[]) {
81 VMSTATE_UINT16(flags
, SCSW
),
82 VMSTATE_UINT16(ctrl
, SCSW
),
83 VMSTATE_UINT32(cpa
, SCSW
),
84 VMSTATE_UINT8(dstat
, SCSW
),
85 VMSTATE_UINT8(cstat
, SCSW
),
86 VMSTATE_UINT16(count
, SCSW
),
91 static const VMStateDescription vmstate_pmcw
= {
94 .minimum_version_id
= 1,
95 .fields
= (VMStateField
[]) {
96 VMSTATE_UINT32(intparm
, PMCW
),
97 VMSTATE_UINT16(flags
, PMCW
),
98 VMSTATE_UINT16(devno
, PMCW
),
99 VMSTATE_UINT8(lpm
, PMCW
),
100 VMSTATE_UINT8(pnom
, PMCW
),
101 VMSTATE_UINT8(lpum
, PMCW
),
102 VMSTATE_UINT8(pim
, PMCW
),
103 VMSTATE_UINT16(mbi
, PMCW
),
104 VMSTATE_UINT8(pom
, PMCW
),
105 VMSTATE_UINT8(pam
, PMCW
),
106 VMSTATE_UINT8_ARRAY(chpid
, PMCW
, 8),
107 VMSTATE_UINT32(chars
, PMCW
),
108 VMSTATE_END_OF_LIST()
112 static const VMStateDescription vmstate_schib
= {
113 .name
= "s390_schib",
115 .minimum_version_id
= 1,
116 .fields
= (VMStateField
[]) {
117 VMSTATE_STRUCT(pmcw
, SCHIB
, 0, vmstate_pmcw
, PMCW
),
118 VMSTATE_STRUCT(scsw
, SCHIB
, 0, vmstate_scsw
, SCSW
),
119 VMSTATE_UINT64(mba
, SCHIB
),
120 VMSTATE_UINT8_ARRAY(mda
, SCHIB
, 4),
121 VMSTATE_END_OF_LIST()
126 static const VMStateDescription vmstate_ccw1
= {
129 .minimum_version_id
= 1,
130 .fields
= (VMStateField
[]) {
131 VMSTATE_UINT8(cmd_code
, CCW1
),
132 VMSTATE_UINT8(flags
, CCW1
),
133 VMSTATE_UINT16(count
, CCW1
),
134 VMSTATE_UINT32(cda
, CCW1
),
135 VMSTATE_END_OF_LIST()
139 static const VMStateDescription vmstate_ciw
= {
142 .minimum_version_id
= 1,
143 .fields
= (VMStateField
[]) {
144 VMSTATE_UINT8(type
, CIW
),
145 VMSTATE_UINT8(command
, CIW
),
146 VMSTATE_UINT16(count
, CIW
),
147 VMSTATE_END_OF_LIST()
151 static const VMStateDescription vmstate_sense_id
= {
152 .name
= "s390_sense_id",
154 .minimum_version_id
= 1,
155 .fields
= (VMStateField
[]) {
156 VMSTATE_UINT8(reserved
, SenseId
),
157 VMSTATE_UINT16(cu_type
, SenseId
),
158 VMSTATE_UINT8(cu_model
, SenseId
),
159 VMSTATE_UINT16(dev_type
, SenseId
),
160 VMSTATE_UINT8(dev_model
, SenseId
),
161 VMSTATE_UINT8(unused
, SenseId
),
162 VMSTATE_STRUCT_ARRAY(ciw
, SenseId
, MAX_CIWS
, 0, vmstate_ciw
, CIW
),
163 VMSTATE_END_OF_LIST()
167 static const VMStateDescription vmstate_orb
= {
170 .minimum_version_id
= 1,
171 .fields
= (VMStateField
[]) {
172 VMSTATE_UINT32(intparm
, ORB
),
173 VMSTATE_UINT16(ctrl0
, ORB
),
174 VMSTATE_UINT8(lpm
, ORB
),
175 VMSTATE_UINT8(ctrl1
, ORB
),
176 VMSTATE_UINT32(cpa
, ORB
),
177 VMSTATE_END_OF_LIST()
181 static bool vmstate_schdev_orb_needed(void *opaque
)
183 return css_migration_enabled();
186 static const VMStateDescription vmstate_schdev_orb
= {
187 .name
= "s390_subch_dev/orb",
189 .minimum_version_id
= 1,
190 .needed
= vmstate_schdev_orb_needed
,
191 .fields
= (VMStateField
[]) {
192 VMSTATE_STRUCT(orb
, SubchDev
, 1, vmstate_orb
, ORB
),
193 VMSTATE_END_OF_LIST()
197 static int subch_dev_post_load(void *opaque
, int version_id
);
198 static int subch_dev_pre_save(void *opaque
);
200 const char err_hint_devno
[] = "Devno mismatch, tried to load wrong section!"
201 " Likely reason: some sequences of plug and unplug can break"
202 " migration for machine versions prior to 2.7 (known design flaw).";
204 const VMStateDescription vmstate_subch_dev
= {
205 .name
= "s390_subch_dev",
207 .minimum_version_id
= 1,
208 .post_load
= subch_dev_post_load
,
209 .pre_save
= subch_dev_pre_save
,
210 .fields
= (VMStateField
[]) {
211 VMSTATE_UINT8_EQUAL(cssid
, SubchDev
, "Bug!"),
212 VMSTATE_UINT8_EQUAL(ssid
, SubchDev
, "Bug!"),
213 VMSTATE_UINT16(migrated_schid
, SubchDev
),
214 VMSTATE_UINT16_EQUAL(devno
, SubchDev
, err_hint_devno
),
215 VMSTATE_BOOL(thinint_active
, SubchDev
),
216 VMSTATE_STRUCT(curr_status
, SubchDev
, 0, vmstate_schib
, SCHIB
),
217 VMSTATE_UINT8_ARRAY(sense_data
, SubchDev
, 32),
218 VMSTATE_UINT64(channel_prog
, SubchDev
),
219 VMSTATE_STRUCT(last_cmd
, SubchDev
, 0, vmstate_ccw1
, CCW1
),
220 VMSTATE_BOOL(last_cmd_valid
, SubchDev
),
221 VMSTATE_STRUCT(id
, SubchDev
, 0, vmstate_sense_id
, SenseId
),
222 VMSTATE_BOOL(ccw_fmt_1
, SubchDev
),
223 VMSTATE_UINT8(ccw_no_data_cnt
, SubchDev
),
224 VMSTATE_END_OF_LIST()
226 .subsections
= (const VMStateDescription
* []) {
232 typedef struct IndAddrPtrTmp
{
238 static int post_load_ind_addr(void *opaque
, int version_id
)
240 IndAddrPtrTmp
*ptmp
= opaque
;
241 IndAddr
**ind_addr
= ptmp
->parent
;
243 if (ptmp
->len
!= 0) {
244 *ind_addr
= get_indicator(ptmp
->addr
, ptmp
->len
);
251 static int pre_save_ind_addr(void *opaque
)
253 IndAddrPtrTmp
*ptmp
= opaque
;
254 IndAddr
*ind_addr
= *(ptmp
->parent
);
256 if (ind_addr
!= NULL
) {
257 ptmp
->len
= ind_addr
->len
;
258 ptmp
->addr
= ind_addr
->addr
;
267 const VMStateDescription vmstate_ind_addr_tmp
= {
268 .name
= "s390_ind_addr_tmp",
269 .pre_save
= pre_save_ind_addr
,
270 .post_load
= post_load_ind_addr
,
272 .fields
= (VMStateField
[]) {
273 VMSTATE_INT32(len
, IndAddrPtrTmp
),
274 VMSTATE_UINT64(addr
, IndAddrPtrTmp
),
275 VMSTATE_END_OF_LIST()
279 const VMStateDescription vmstate_ind_addr
= {
280 .name
= "s390_ind_addr_tmp",
281 .fields
= (VMStateField
[]) {
282 VMSTATE_WITH_TMP(IndAddr
*, IndAddrPtrTmp
, vmstate_ind_addr_tmp
),
283 VMSTATE_END_OF_LIST()
287 typedef struct CssImage
{
288 SubchSet
*sch_set
[MAX_SSID
+ 1];
289 ChpInfo chpids
[MAX_CHPID
+ 1];
292 static const VMStateDescription vmstate_css_img
= {
293 .name
= "s390_css_img",
295 .minimum_version_id
= 1,
296 .fields
= (VMStateField
[]) {
297 /* Subchannel sets have no relevant state. */
298 VMSTATE_STRUCT_ARRAY(chpids
, CssImage
, MAX_CHPID
+ 1, 0,
299 vmstate_chp_info
, ChpInfo
),
300 VMSTATE_END_OF_LIST()
305 typedef struct IoAdapter
{
312 typedef struct ChannelSubSys
{
313 QTAILQ_HEAD(, CrwContainer
) pending_crws
;
320 uint64_t chnmon_area
;
321 CssImage
*css
[MAX_CSSID
+ 1];
322 uint8_t default_cssid
;
323 /* don't migrate, see css_register_io_adapters */
324 IoAdapter
*io_adapters
[CSS_IO_ADAPTER_TYPE_NUMS
][MAX_ISC
+ 1];
325 /* don't migrate, see get_indicator and IndAddrPtrTmp */
326 QTAILQ_HEAD(, IndAddr
) indicator_addresses
;
329 static const VMStateDescription vmstate_css
= {
332 .minimum_version_id
= 1,
333 .fields
= (VMStateField
[]) {
334 VMSTATE_QTAILQ_V(pending_crws
, ChannelSubSys
, 1, vmstate_crw_container
,
335 CrwContainer
, sibling
),
336 VMSTATE_BOOL(sei_pending
, ChannelSubSys
),
337 VMSTATE_BOOL(do_crw_mchk
, ChannelSubSys
),
338 VMSTATE_BOOL(crws_lost
, ChannelSubSys
),
339 /* These were kind of migrated by virtio */
340 VMSTATE_UINT8(max_cssid
, ChannelSubSys
),
341 VMSTATE_UINT8(max_ssid
, ChannelSubSys
),
342 VMSTATE_BOOL(chnmon_active
, ChannelSubSys
),
343 VMSTATE_UINT64(chnmon_area
, ChannelSubSys
),
344 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css
, ChannelSubSys
, MAX_CSSID
+ 1,
345 0, vmstate_css_img
, CssImage
),
346 VMSTATE_UINT8(default_cssid
, ChannelSubSys
),
347 VMSTATE_END_OF_LIST()
351 static ChannelSubSys channel_subsys
= {
352 .pending_crws
= QTAILQ_HEAD_INITIALIZER(channel_subsys
.pending_crws
),
354 .sei_pending
= false,
357 .chnmon_active
= false,
358 .indicator_addresses
=
359 QTAILQ_HEAD_INITIALIZER(channel_subsys
.indicator_addresses
),
362 static int subch_dev_pre_save(void *opaque
)
364 SubchDev
*s
= opaque
;
366 /* Prepare remote_schid for save */
367 s
->migrated_schid
= s
->schid
;
372 static int subch_dev_post_load(void *opaque
, int version_id
)
375 SubchDev
*s
= opaque
;
377 /* Re-assign the subchannel to remote_schid if necessary */
378 if (s
->migrated_schid
!= s
->schid
) {
379 if (css_find_subch(true, s
->cssid
, s
->ssid
, s
->schid
) == s
) {
381 * Cleanup the slot before moving to s->migrated_schid provided
382 * it still belongs to us, i.e. it was not changed by previous
383 * invocation of this function.
385 css_subch_assign(s
->cssid
, s
->ssid
, s
->schid
, s
->devno
, NULL
);
387 /* It's OK to re-assign without a prior de-assign. */
388 s
->schid
= s
->migrated_schid
;
389 css_subch_assign(s
->cssid
, s
->ssid
, s
->schid
, s
->devno
, s
);
392 if (css_migration_enabled()) {
393 /* No compat voodoo to do ;) */
397 * Hack alert. If we don't migrate the channel subsystem status
398 * we still need to find out if the guest enabled mss/mcss-e.
399 * If the subchannel is enabled, it certainly was able to access it,
400 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
401 * values. This is not watertight, but better than nothing.
403 if (s
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ENA
) {
405 channel_subsys
.max_ssid
= MAX_SSID
;
407 if (s
->cssid
!= channel_subsys
.default_cssid
) {
408 channel_subsys
.max_cssid
= MAX_CSSID
;
414 void css_register_vmstate(void)
416 vmstate_register(NULL
, 0, &vmstate_css
, &channel_subsys
);
419 IndAddr
*get_indicator(hwaddr ind_addr
, int len
)
423 QTAILQ_FOREACH(indicator
, &channel_subsys
.indicator_addresses
, sibling
) {
424 if (indicator
->addr
== ind_addr
) {
429 indicator
= g_new0(IndAddr
, 1);
430 indicator
->addr
= ind_addr
;
431 indicator
->len
= len
;
432 indicator
->refcnt
= 1;
433 QTAILQ_INSERT_TAIL(&channel_subsys
.indicator_addresses
,
438 static int s390_io_adapter_map(AdapterInfo
*adapter
, uint64_t map_addr
,
441 S390FLICState
*fs
= s390_get_flic();
442 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
444 return fsc
->io_adapter_map(fs
, adapter
->adapter_id
, map_addr
, do_map
);
447 void release_indicator(AdapterInfo
*adapter
, IndAddr
*indicator
)
449 assert(indicator
->refcnt
> 0);
451 if (indicator
->refcnt
> 0) {
454 QTAILQ_REMOVE(&channel_subsys
.indicator_addresses
, indicator
, sibling
);
455 if (indicator
->map
) {
456 s390_io_adapter_map(adapter
, indicator
->map
, false);
461 int map_indicator(AdapterInfo
*adapter
, IndAddr
*indicator
)
465 if (indicator
->map
) {
466 return 0; /* already mapped is not an error */
468 indicator
->map
= indicator
->addr
;
469 ret
= s390_io_adapter_map(adapter
, indicator
->map
, true);
470 if ((ret
!= 0) && (ret
!= -ENOSYS
)) {
480 int css_create_css_image(uint8_t cssid
, bool default_image
)
482 trace_css_new_image(cssid
, default_image
? "(default)" : "");
483 /* 255 is reserved */
487 if (channel_subsys
.css
[cssid
]) {
490 channel_subsys
.css
[cssid
] = g_new0(CssImage
, 1);
492 channel_subsys
.default_cssid
= cssid
;
497 uint32_t css_get_adapter_id(CssIoAdapterType type
, uint8_t isc
)
499 if (type
>= CSS_IO_ADAPTER_TYPE_NUMS
|| isc
> MAX_ISC
||
500 !channel_subsys
.io_adapters
[type
][isc
]) {
504 return channel_subsys
.io_adapters
[type
][isc
]->id
;
508 * css_register_io_adapters: Register I/O adapters per ISC during init
510 * @swap: an indication if byte swap is needed.
511 * @maskable: an indication if the adapter is subject to the mask operation.
512 * @flags: further characteristics of the adapter.
513 * e.g. suppressible, an indication if the adapter is subject to AIS.
514 * @errp: location to store error information.
516 void css_register_io_adapters(CssIoAdapterType type
, bool swap
, bool maskable
,
517 uint8_t flags
, Error
**errp
)
522 S390FLICState
*fs
= s390_get_flic();
523 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
526 * Disallow multiple registrations for the same device type.
527 * Report an error if registering for an already registered type.
529 if (channel_subsys
.io_adapters
[type
][0]) {
530 error_setg(errp
, "Adapters for type %d already registered", type
);
533 for (isc
= 0; isc
<= MAX_ISC
; isc
++) {
534 id
= (type
<< 3) | isc
;
535 ret
= fsc
->register_io_adapter(fs
, id
, isc
, swap
, maskable
, flags
);
537 adapter
= g_new0(IoAdapter
, 1);
540 adapter
->type
= type
;
541 adapter
->flags
= flags
;
542 channel_subsys
.io_adapters
[type
][isc
] = adapter
;
544 error_setg_errno(errp
, -ret
, "Unexpected error %d when "
545 "registering adapter %d", ret
, id
);
551 * No need to free registered adapters in kvm: kvm will clean up
552 * when the machine goes away.
555 for (isc
--; isc
>= 0; isc
--) {
556 g_free(channel_subsys
.io_adapters
[type
][isc
]);
557 channel_subsys
.io_adapters
[type
][isc
] = NULL
;
563 static void css_clear_io_interrupt(uint16_t subchannel_id
,
564 uint16_t subchannel_nr
)
567 static bool no_clear_irq
;
568 S390FLICState
*fs
= s390_get_flic();
569 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
572 if (unlikely(no_clear_irq
)) {
575 r
= fsc
->clear_io_irq(fs
, subchannel_id
, subchannel_nr
);
582 * Ignore unavailability, as the user can't do anything
587 error_setg_errno(&err
, -r
, "unexpected error condition");
588 error_propagate(&error_abort
, err
);
592 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid
, uint8_t ssid
)
594 if (channel_subsys
.max_cssid
> 0) {
595 return (cssid
<< 8) | (1 << 3) | (ssid
<< 1) | 1;
597 return (ssid
<< 1) | 1;
600 uint16_t css_build_subchannel_id(SubchDev
*sch
)
602 return css_do_build_subchannel_id(sch
->cssid
, sch
->ssid
);
605 void css_inject_io_interrupt(SubchDev
*sch
)
607 uint8_t isc
= (sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ISC
) >> 11;
609 trace_css_io_interrupt(sch
->cssid
, sch
->ssid
, sch
->schid
,
610 sch
->curr_status
.pmcw
.intparm
, isc
, "");
611 s390_io_interrupt(css_build_subchannel_id(sch
),
613 sch
->curr_status
.pmcw
.intparm
,
617 void css_conditional_io_interrupt(SubchDev
*sch
)
620 * If the subchannel is not currently status pending, make it pending
623 if (!(sch
->curr_status
.scsw
.ctrl
& SCSW_STCTL_STATUS_PEND
)) {
624 uint8_t isc
= (sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ISC
) >> 11;
626 trace_css_io_interrupt(sch
->cssid
, sch
->ssid
, sch
->schid
,
627 sch
->curr_status
.pmcw
.intparm
, isc
,
629 sch
->curr_status
.scsw
.ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
630 sch
->curr_status
.scsw
.ctrl
|=
631 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
632 /* Inject an I/O interrupt. */
633 s390_io_interrupt(css_build_subchannel_id(sch
),
635 sch
->curr_status
.pmcw
.intparm
,
640 int css_do_sic(CPUS390XState
*env
, uint8_t isc
, uint16_t mode
)
642 S390FLICState
*fs
= s390_get_flic();
643 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
646 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
651 trace_css_do_sic(mode
, isc
);
653 case SIC_IRQ_MODE_ALL
:
654 case SIC_IRQ_MODE_SINGLE
:
661 r
= fsc
->modify_ais_mode(fs
, isc
, mode
) ? -PGM_OPERATION
: 0;
666 void css_adapter_interrupt(CssIoAdapterType type
, uint8_t isc
)
668 S390FLICState
*fs
= s390_get_flic();
669 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
670 uint32_t io_int_word
= (isc
<< 27) | IO_INT_WORD_AI
;
671 IoAdapter
*adapter
= channel_subsys
.io_adapters
[type
][isc
];
677 trace_css_adapter_interrupt(isc
);
678 if (fs
->ais_supported
) {
679 if (fsc
->inject_airq(fs
, type
, isc
, adapter
->flags
)) {
680 error_report("Failed to inject airq with AIS supported");
684 s390_io_interrupt(0, 0, 0, io_int_word
);
688 static void sch_handle_clear_func(SubchDev
*sch
)
690 PMCW
*p
= &sch
->curr_status
.pmcw
;
691 SCSW
*s
= &sch
->curr_status
.scsw
;
694 /* Path management: In our simple css, we always choose the only path. */
697 /* Reset values prior to 'issuing the clear signal'. */
700 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
702 /* We always 'attempt to issue the clear signal', and we always succeed. */
703 sch
->channel_prog
= 0x0;
704 sch
->last_cmd_valid
= false;
705 s
->ctrl
&= ~SCSW_ACTL_CLEAR_PEND
;
706 s
->ctrl
|= SCSW_STCTL_STATUS_PEND
;
714 static void sch_handle_halt_func(SubchDev
*sch
)
717 PMCW
*p
= &sch
->curr_status
.pmcw
;
718 SCSW
*s
= &sch
->curr_status
.scsw
;
719 hwaddr curr_ccw
= sch
->channel_prog
;
722 /* Path management: In our simple css, we always choose the only path. */
725 /* We always 'attempt to issue the halt signal', and we always succeed. */
726 sch
->channel_prog
= 0x0;
727 sch
->last_cmd_valid
= false;
728 s
->ctrl
&= ~SCSW_ACTL_HALT_PEND
;
729 s
->ctrl
|= SCSW_STCTL_STATUS_PEND
;
731 if ((s
->ctrl
& (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) ||
732 !((s
->ctrl
& SCSW_ACTL_START_PEND
) ||
733 (s
->ctrl
& SCSW_ACTL_SUSP
))) {
734 s
->dstat
= SCSW_DSTAT_DEVICE_END
;
736 if ((s
->ctrl
& (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) ||
737 (s
->ctrl
& SCSW_ACTL_SUSP
)) {
738 s
->cpa
= curr_ccw
+ 8;
745 static void copy_sense_id_to_guest(SenseId
*dest
, SenseId
*src
)
749 dest
->reserved
= src
->reserved
;
750 dest
->cu_type
= cpu_to_be16(src
->cu_type
);
751 dest
->cu_model
= src
->cu_model
;
752 dest
->dev_type
= cpu_to_be16(src
->dev_type
);
753 dest
->dev_model
= src
->dev_model
;
754 dest
->unused
= src
->unused
;
755 for (i
= 0; i
< ARRAY_SIZE(dest
->ciw
); i
++) {
756 dest
->ciw
[i
].type
= src
->ciw
[i
].type
;
757 dest
->ciw
[i
].command
= src
->ciw
[i
].command
;
758 dest
->ciw
[i
].count
= cpu_to_be16(src
->ciw
[i
].count
);
762 static CCW1
copy_ccw_from_guest(hwaddr addr
, bool fmt1
)
769 cpu_physical_memory_read(addr
, &tmp1
, sizeof(tmp1
));
770 ret
.cmd_code
= tmp1
.cmd_code
;
771 ret
.flags
= tmp1
.flags
;
772 ret
.count
= be16_to_cpu(tmp1
.count
);
773 ret
.cda
= be32_to_cpu(tmp1
.cda
);
775 cpu_physical_memory_read(addr
, &tmp0
, sizeof(tmp0
));
776 if ((tmp0
.cmd_code
& 0x0f) == CCW_CMD_TIC
) {
777 ret
.cmd_code
= CCW_CMD_TIC
;
781 ret
.cmd_code
= tmp0
.cmd_code
;
782 ret
.flags
= tmp0
.flags
;
783 ret
.count
= be16_to_cpu(tmp0
.count
);
785 ret
.cda
= be16_to_cpu(tmp0
.cda1
) | (tmp0
.cda0
<< 16);
790 * If out of bounds marks the stream broken. If broken returns -EINVAL,
791 * otherwise the requested length (may be zero)
793 static inline int cds_check_len(CcwDataStream
*cds
, int len
)
795 if (cds
->at_byte
+ len
> cds
->count
) {
796 cds
->flags
|= CDS_F_STREAM_BROKEN
;
798 return cds
->flags
& CDS_F_STREAM_BROKEN
? -EINVAL
: len
;
801 static inline bool cds_ccw_addrs_ok(hwaddr addr
, int len
, bool ccw_fmt1
)
803 return (addr
+ len
) < (ccw_fmt1
? (1UL << 31) : (1UL << 24));
806 static int ccw_dstream_rw_noflags(CcwDataStream
*cds
, void *buff
, int len
,
811 ret
= cds_check_len(cds
, len
);
815 if (!cds_ccw_addrs_ok(cds
->cda
, len
, cds
->flags
& CDS_F_FMT
)) {
816 return -EINVAL
; /* channel program check */
818 if (op
== CDS_OP_A
) {
821 ret
= address_space_rw(&address_space_memory
, cds
->cda
,
822 MEMTXATTRS_UNSPECIFIED
, buff
, len
, op
);
823 if (ret
!= MEMTX_OK
) {
824 cds
->flags
|= CDS_F_STREAM_BROKEN
;
833 /* returns values between 1 and bsz, where bsz is a power of 2 */
834 static inline uint16_t ida_continuous_left(hwaddr cda
, uint64_t bsz
)
836 return bsz
- (cda
& (bsz
- 1));
839 static inline uint64_t ccw_ida_block_size(uint8_t flags
)
841 if ((flags
& CDS_F_C64
) && !(flags
& CDS_F_I2K
)) {
847 static inline int ida_read_next_idaw(CcwDataStream
*cds
)
849 union {uint64_t fmt2
; uint32_t fmt1
; } idaw
;
852 bool idaw_fmt2
= cds
->flags
& CDS_F_C64
;
853 bool ccw_fmt1
= cds
->flags
& CDS_F_FMT
;
856 idaw_addr
= cds
->cda_orig
+ sizeof(idaw
.fmt2
) * cds
->at_idaw
;
857 if (idaw_addr
& 0x07 || !cds_ccw_addrs_ok(idaw_addr
, 0, ccw_fmt1
)) {
858 return -EINVAL
; /* channel program check */
860 ret
= address_space_rw(&address_space_memory
, idaw_addr
,
861 MEMTXATTRS_UNSPECIFIED
, (void *) &idaw
.fmt2
,
862 sizeof(idaw
.fmt2
), false);
863 cds
->cda
= be64_to_cpu(idaw
.fmt2
);
865 idaw_addr
= cds
->cda_orig
+ sizeof(idaw
.fmt1
) * cds
->at_idaw
;
866 if (idaw_addr
& 0x03 || !cds_ccw_addrs_ok(idaw_addr
, 0, ccw_fmt1
)) {
867 return -EINVAL
; /* channel program check */
869 ret
= address_space_rw(&address_space_memory
, idaw_addr
,
870 MEMTXATTRS_UNSPECIFIED
, (void *) &idaw
.fmt1
,
871 sizeof(idaw
.fmt1
), false);
872 cds
->cda
= be64_to_cpu(idaw
.fmt1
);
873 if (cds
->cda
& 0x80000000) {
874 return -EINVAL
; /* channel program check */
878 if (ret
!= MEMTX_OK
) {
879 /* assume inaccessible address */
880 return -EINVAL
; /* channel program check */
885 static int ccw_dstream_rw_ida(CcwDataStream
*cds
, void *buff
, int len
,
888 uint64_t bsz
= ccw_ida_block_size(cds
->flags
);
890 uint16_t cont_left
, iter_len
;
892 ret
= cds_check_len(cds
, len
);
897 /* read first idaw */
898 ret
= ida_read_next_idaw(cds
);
902 cont_left
= ida_continuous_left(cds
->cda
, bsz
);
904 cont_left
= ida_continuous_left(cds
->cda
, bsz
);
905 if (cont_left
== bsz
) {
906 ret
= ida_read_next_idaw(cds
);
910 if (cds
->cda
& (bsz
- 1)) {
911 ret
= -EINVAL
; /* channel program check */
917 iter_len
= MIN(len
, cont_left
);
918 if (op
!= CDS_OP_A
) {
919 ret
= address_space_rw(&address_space_memory
, cds
->cda
,
920 MEMTXATTRS_UNSPECIFIED
, buff
, iter_len
, op
);
921 if (ret
!= MEMTX_OK
) {
922 /* assume inaccessible address */
923 ret
= -EINVAL
; /* channel program check */
927 cds
->at_byte
+= iter_len
;
928 cds
->cda
+= iter_len
;
933 ret
= ida_read_next_idaw(cds
);
941 cds
->flags
|= CDS_F_STREAM_BROKEN
;
945 void ccw_dstream_init(CcwDataStream
*cds
, CCW1
const *ccw
, ORB
const *orb
)
948 * We don't support MIDA (an optional facility) yet and we
949 * catch this earlier. Just for expressing the precondition.
951 g_assert(!(orb
->ctrl1
& ORB_CTRL1_MASK_MIDAW
));
952 cds
->flags
= (orb
->ctrl0
& ORB_CTRL0_MASK_I2K
? CDS_F_I2K
: 0) |
953 (orb
->ctrl0
& ORB_CTRL0_MASK_C64
? CDS_F_C64
: 0) |
954 (orb
->ctrl0
& ORB_CTRL0_MASK_FMT
? CDS_F_FMT
: 0) |
955 (ccw
->flags
& CCW_FLAG_IDA
? CDS_F_IDA
: 0);
957 cds
->count
= ccw
->count
;
958 cds
->cda_orig
= ccw
->cda
;
959 ccw_dstream_rewind(cds
);
960 if (!(cds
->flags
& CDS_F_IDA
)) {
961 cds
->op_handler
= ccw_dstream_rw_noflags
;
963 cds
->op_handler
= ccw_dstream_rw_ida
;
967 static int css_interpret_ccw(SubchDev
*sch
, hwaddr ccw_addr
,
968 bool suspend_allowed
)
976 return -EINVAL
; /* channel-program check */
978 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
979 if (ccw_addr
& (sch
->ccw_fmt_1
? 0x80000007 : 0xff000007)) {
983 /* Translate everything to format-1 ccws - the information is the same. */
984 ccw
= copy_ccw_from_guest(ccw_addr
, sch
->ccw_fmt_1
);
986 /* Check for invalid command codes. */
987 if ((ccw
.cmd_code
& 0x0f) == 0) {
990 if (((ccw
.cmd_code
& 0x0f) == CCW_CMD_TIC
) &&
991 ((ccw
.cmd_code
& 0xf0) != 0)) {
994 if (!sch
->ccw_fmt_1
&& (ccw
.count
== 0) &&
995 (ccw
.cmd_code
!= CCW_CMD_TIC
)) {
999 /* We don't support MIDA. */
1000 if (ccw
.flags
& CCW_FLAG_MIDA
) {
1004 if (ccw
.flags
& CCW_FLAG_SUSPEND
) {
1005 return suspend_allowed
? -EINPROGRESS
: -EINVAL
;
1008 check_len
= !((ccw
.flags
& CCW_FLAG_SLI
) && !(ccw
.flags
& CCW_FLAG_DC
));
1011 if (sch
->ccw_no_data_cnt
== 255) {
1014 sch
->ccw_no_data_cnt
++;
1017 /* Look at the command. */
1018 ccw_dstream_init(&sch
->cds
, &ccw
, &(sch
->orb
));
1019 switch (ccw
.cmd_code
) {
1021 /* Nothing to do. */
1024 case CCW_CMD_BASIC_SENSE
:
1026 if (ccw
.count
!= sizeof(sch
->sense_data
)) {
1031 len
= MIN(ccw
.count
, sizeof(sch
->sense_data
));
1032 ccw_dstream_write_buf(&sch
->cds
, sch
->sense_data
, len
);
1033 sch
->curr_status
.scsw
.count
= ccw_dstream_residual_count(&sch
->cds
);
1034 memset(sch
->sense_data
, 0, sizeof(sch
->sense_data
));
1037 case CCW_CMD_SENSE_ID
:
1041 copy_sense_id_to_guest(&sense_id
, &sch
->id
);
1042 /* Sense ID information is device specific. */
1044 if (ccw
.count
!= sizeof(sense_id
)) {
1049 len
= MIN(ccw
.count
, sizeof(sense_id
));
1051 * Only indicate 0xff in the first sense byte if we actually
1052 * have enough place to store at least bytes 0-3.
1055 sense_id
.reserved
= 0xff;
1057 sense_id
.reserved
= 0;
1059 ccw_dstream_write_buf(&sch
->cds
, &sense_id
, len
);
1060 sch
->curr_status
.scsw
.count
= ccw_dstream_residual_count(&sch
->cds
);
1065 if (sch
->last_cmd_valid
&& (sch
->last_cmd
.cmd_code
== CCW_CMD_TIC
)) {
1069 if (ccw
.flags
|| ccw
.count
) {
1070 /* We have already sanitized these if converted from fmt 0. */
1074 sch
->channel_prog
= ccw
.cda
;
1079 /* Handle device specific commands. */
1080 ret
= sch
->ccw_cb(sch
, ccw
);
1086 sch
->last_cmd
= ccw
;
1087 sch
->last_cmd_valid
= true;
1089 if (ccw
.flags
& CCW_FLAG_CC
) {
1090 sch
->channel_prog
+= 8;
1098 static void sch_handle_start_func_virtual(SubchDev
*sch
)
1101 PMCW
*p
= &sch
->curr_status
.pmcw
;
1102 SCSW
*s
= &sch
->curr_status
.scsw
;
1105 bool suspend_allowed
;
1107 /* Path management: In our simple css, we always choose the only path. */
1110 if (!(s
->ctrl
& SCSW_ACTL_SUSP
)) {
1111 /* Start Function triggered via ssch, i.e. we have an ORB */
1112 ORB
*orb
= &sch
->orb
;
1115 /* Look at the orb and try to execute the channel program. */
1116 p
->intparm
= orb
->intparm
;
1117 if (!(orb
->lpm
& path
)) {
1118 /* Generate a deferred cc 3 condition. */
1119 s
->flags
|= SCSW_FLAGS_MASK_CC
;
1120 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1121 s
->ctrl
|= (SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
);
1124 sch
->ccw_fmt_1
= !!(orb
->ctrl0
& ORB_CTRL0_MASK_FMT
);
1125 s
->flags
|= (sch
->ccw_fmt_1
) ? SCSW_FLAGS_MASK_FMT
: 0;
1126 sch
->ccw_no_data_cnt
= 0;
1127 suspend_allowed
= !!(orb
->ctrl0
& ORB_CTRL0_MASK_SPND
);
1129 /* Start Function resumed via rsch */
1130 s
->ctrl
&= ~(SCSW_ACTL_SUSP
| SCSW_ACTL_RESUME_PEND
);
1131 /* The channel program had been suspended before. */
1132 suspend_allowed
= true;
1134 sch
->last_cmd_valid
= false;
1136 ret
= css_interpret_ccw(sch
, sch
->channel_prog
, suspend_allowed
);
1139 /* ccw chain, continue processing */
1143 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1144 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1145 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
1146 SCSW_STCTL_STATUS_PEND
;
1147 s
->dstat
= SCSW_DSTAT_CHANNEL_END
| SCSW_DSTAT_DEVICE_END
;
1148 s
->cpa
= sch
->channel_prog
+ 8;
1151 /* I/O errors, status depends on specific devices */
1154 /* unsupported command, generate unit check (command reject) */
1155 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1156 s
->dstat
= SCSW_DSTAT_UNIT_CHECK
;
1157 /* Set sense bit 0 in ecw0. */
1158 sch
->sense_data
[0] = 0x80;
1159 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1160 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
1161 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
1162 s
->cpa
= sch
->channel_prog
+ 8;
1165 /* channel program has been suspended */
1166 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1167 s
->ctrl
|= SCSW_ACTL_SUSP
;
1170 /* error, generate channel program check */
1171 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1172 s
->cstat
= SCSW_CSTAT_PROG_CHECK
;
1173 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1174 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
1175 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
1176 s
->cpa
= sch
->channel_prog
+ 8;
1179 } while (ret
== -EAGAIN
);
1183 static IOInstEnding
sch_handle_start_func_passthrough(SubchDev
*sch
)
1186 PMCW
*p
= &sch
->curr_status
.pmcw
;
1187 SCSW
*s
= &sch
->curr_status
.scsw
;
1189 ORB
*orb
= &sch
->orb
;
1190 if (!(s
->ctrl
& SCSW_ACTL_SUSP
)) {
1191 assert(orb
!= NULL
);
1192 p
->intparm
= orb
->intparm
;
1196 * Only support prefetch enable mode.
1197 * Only support 64bit addressing idal.
1199 if (!(orb
->ctrl0
& ORB_CTRL0_MASK_PFCH
) ||
1200 !(orb
->ctrl0
& ORB_CTRL0_MASK_C64
)) {
1201 warn_report("vfio-ccw requires PFCH and C64 flags set");
1202 sch_gen_unit_exception(sch
);
1203 css_inject_io_interrupt(sch
);
1204 return IOINST_CC_EXPECTED
;
1206 return s390_ccw_cmd_request(sch
);
1210 * On real machines, this would run asynchronously to the main vcpus.
1211 * We might want to make some parts of the ssch handling (interpreting
1212 * read/writes) asynchronous later on if we start supporting more than
1213 * our current very simple devices.
1215 IOInstEnding
do_subchannel_work_virtual(SubchDev
*sch
)
1218 SCSW
*s
= &sch
->curr_status
.scsw
;
1220 if (s
->ctrl
& SCSW_FCTL_CLEAR_FUNC
) {
1221 sch_handle_clear_func(sch
);
1222 } else if (s
->ctrl
& SCSW_FCTL_HALT_FUNC
) {
1223 sch_handle_halt_func(sch
);
1224 } else if (s
->ctrl
& SCSW_FCTL_START_FUNC
) {
1225 /* Triggered by both ssch and rsch. */
1226 sch_handle_start_func_virtual(sch
);
1228 css_inject_io_interrupt(sch
);
1229 /* inst must succeed if this func is called */
1230 return IOINST_CC_EXPECTED
;
1233 IOInstEnding
do_subchannel_work_passthrough(SubchDev
*sch
)
1235 SCSW
*s
= &sch
->curr_status
.scsw
;
1237 if (s
->ctrl
& SCSW_FCTL_CLEAR_FUNC
) {
1238 /* TODO: Clear handling */
1239 sch_handle_clear_func(sch
);
1240 } else if (s
->ctrl
& SCSW_FCTL_HALT_FUNC
) {
1241 /* TODO: Halt handling */
1242 sch_handle_halt_func(sch
);
1243 } else if (s
->ctrl
& SCSW_FCTL_START_FUNC
) {
1244 return sch_handle_start_func_passthrough(sch
);
1246 return IOINST_CC_EXPECTED
;
1249 static IOInstEnding
do_subchannel_work(SubchDev
*sch
)
1251 if (!sch
->do_subchannel_work
) {
1252 return IOINST_CC_STATUS_PRESENT
;
1254 g_assert(sch
->curr_status
.scsw
.ctrl
& SCSW_CTRL_MASK_FCTL
);
1255 return sch
->do_subchannel_work(sch
);
1258 static void copy_pmcw_to_guest(PMCW
*dest
, const PMCW
*src
)
1262 dest
->intparm
= cpu_to_be32(src
->intparm
);
1263 dest
->flags
= cpu_to_be16(src
->flags
);
1264 dest
->devno
= cpu_to_be16(src
->devno
);
1265 dest
->lpm
= src
->lpm
;
1266 dest
->pnom
= src
->pnom
;
1267 dest
->lpum
= src
->lpum
;
1268 dest
->pim
= src
->pim
;
1269 dest
->mbi
= cpu_to_be16(src
->mbi
);
1270 dest
->pom
= src
->pom
;
1271 dest
->pam
= src
->pam
;
1272 for (i
= 0; i
< ARRAY_SIZE(dest
->chpid
); i
++) {
1273 dest
->chpid
[i
] = src
->chpid
[i
];
1275 dest
->chars
= cpu_to_be32(src
->chars
);
1278 void copy_scsw_to_guest(SCSW
*dest
, const SCSW
*src
)
1280 dest
->flags
= cpu_to_be16(src
->flags
);
1281 dest
->ctrl
= cpu_to_be16(src
->ctrl
);
1282 dest
->cpa
= cpu_to_be32(src
->cpa
);
1283 dest
->dstat
= src
->dstat
;
1284 dest
->cstat
= src
->cstat
;
1285 dest
->count
= cpu_to_be16(src
->count
);
1288 static void copy_schib_to_guest(SCHIB
*dest
, const SCHIB
*src
)
1292 copy_pmcw_to_guest(&dest
->pmcw
, &src
->pmcw
);
1293 copy_scsw_to_guest(&dest
->scsw
, &src
->scsw
);
1294 dest
->mba
= cpu_to_be64(src
->mba
);
1295 for (i
= 0; i
< ARRAY_SIZE(dest
->mda
); i
++) {
1296 dest
->mda
[i
] = src
->mda
[i
];
1300 int css_do_stsch(SubchDev
*sch
, SCHIB
*schib
)
1302 /* Use current status. */
1303 copy_schib_to_guest(schib
, &sch
->curr_status
);
1307 static void copy_pmcw_from_guest(PMCW
*dest
, const PMCW
*src
)
1311 dest
->intparm
= be32_to_cpu(src
->intparm
);
1312 dest
->flags
= be16_to_cpu(src
->flags
);
1313 dest
->devno
= be16_to_cpu(src
->devno
);
1314 dest
->lpm
= src
->lpm
;
1315 dest
->pnom
= src
->pnom
;
1316 dest
->lpum
= src
->lpum
;
1317 dest
->pim
= src
->pim
;
1318 dest
->mbi
= be16_to_cpu(src
->mbi
);
1319 dest
->pom
= src
->pom
;
1320 dest
->pam
= src
->pam
;
1321 for (i
= 0; i
< ARRAY_SIZE(dest
->chpid
); i
++) {
1322 dest
->chpid
[i
] = src
->chpid
[i
];
1324 dest
->chars
= be32_to_cpu(src
->chars
);
1327 static void copy_scsw_from_guest(SCSW
*dest
, const SCSW
*src
)
1329 dest
->flags
= be16_to_cpu(src
->flags
);
1330 dest
->ctrl
= be16_to_cpu(src
->ctrl
);
1331 dest
->cpa
= be32_to_cpu(src
->cpa
);
1332 dest
->dstat
= src
->dstat
;
1333 dest
->cstat
= src
->cstat
;
1334 dest
->count
= be16_to_cpu(src
->count
);
1337 static void copy_schib_from_guest(SCHIB
*dest
, const SCHIB
*src
)
1341 copy_pmcw_from_guest(&dest
->pmcw
, &src
->pmcw
);
1342 copy_scsw_from_guest(&dest
->scsw
, &src
->scsw
);
1343 dest
->mba
= be64_to_cpu(src
->mba
);
1344 for (i
= 0; i
< ARRAY_SIZE(dest
->mda
); i
++) {
1345 dest
->mda
[i
] = src
->mda
[i
];
1349 IOInstEnding
css_do_msch(SubchDev
*sch
, const SCHIB
*orig_schib
)
1351 SCSW
*s
= &sch
->curr_status
.scsw
;
1352 PMCW
*p
= &sch
->curr_status
.pmcw
;
1356 if (!(sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_DNV
)) {
1357 return IOINST_CC_EXPECTED
;
1360 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
1361 return IOINST_CC_STATUS_PRESENT
;
1365 (SCSW_FCTL_START_FUNC
|SCSW_FCTL_HALT_FUNC
|SCSW_FCTL_CLEAR_FUNC
)) {
1366 return IOINST_CC_BUSY
;
1369 copy_schib_from_guest(&schib
, orig_schib
);
1370 /* Only update the program-modifiable fields. */
1371 p
->intparm
= schib
.pmcw
.intparm
;
1372 oldflags
= p
->flags
;
1373 p
->flags
&= ~(PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
1374 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
1375 PMCW_FLAGS_MASK_MP
);
1376 p
->flags
|= schib
.pmcw
.flags
&
1377 (PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
1378 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
1379 PMCW_FLAGS_MASK_MP
);
1380 p
->lpm
= schib
.pmcw
.lpm
;
1381 p
->mbi
= schib
.pmcw
.mbi
;
1382 p
->pom
= schib
.pmcw
.pom
;
1383 p
->chars
&= ~(PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_CSENSE
);
1384 p
->chars
|= schib
.pmcw
.chars
&
1385 (PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_CSENSE
);
1386 sch
->curr_status
.mba
= schib
.mba
;
1388 /* Has the channel been disabled? */
1389 if (sch
->disable_cb
&& (oldflags
& PMCW_FLAGS_MASK_ENA
) != 0
1390 && (p
->flags
& PMCW_FLAGS_MASK_ENA
) == 0) {
1391 sch
->disable_cb(sch
);
1393 return IOINST_CC_EXPECTED
;
1396 IOInstEnding
css_do_xsch(SubchDev
*sch
)
1398 SCSW
*s
= &sch
->curr_status
.scsw
;
1399 PMCW
*p
= &sch
->curr_status
.pmcw
;
1401 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1402 return IOINST_CC_NOT_OPERATIONAL
;
1405 if (s
->ctrl
& SCSW_CTRL_MASK_STCTL
) {
1406 return IOINST_CC_STATUS_PRESENT
;
1409 if (!(s
->ctrl
& SCSW_CTRL_MASK_FCTL
) ||
1410 ((s
->ctrl
& SCSW_CTRL_MASK_FCTL
) != SCSW_FCTL_START_FUNC
) ||
1412 (SCSW_ACTL_RESUME_PEND
| SCSW_ACTL_START_PEND
| SCSW_ACTL_SUSP
))) ||
1413 (s
->ctrl
& SCSW_ACTL_SUBCH_ACTIVE
)) {
1414 return IOINST_CC_BUSY
;
1417 /* Cancel the current operation. */
1418 s
->ctrl
&= ~(SCSW_FCTL_START_FUNC
|
1419 SCSW_ACTL_RESUME_PEND
|
1420 SCSW_ACTL_START_PEND
|
1422 sch
->channel_prog
= 0x0;
1423 sch
->last_cmd_valid
= false;
1426 return IOINST_CC_EXPECTED
;
1429 IOInstEnding
css_do_csch(SubchDev
*sch
)
1431 SCSW
*s
= &sch
->curr_status
.scsw
;
1432 PMCW
*p
= &sch
->curr_status
.pmcw
;
1434 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1435 return IOINST_CC_NOT_OPERATIONAL
;
1438 /* Trigger the clear function. */
1439 s
->ctrl
&= ~(SCSW_CTRL_MASK_FCTL
| SCSW_CTRL_MASK_ACTL
);
1440 s
->ctrl
|= SCSW_FCTL_CLEAR_FUNC
| SCSW_ACTL_CLEAR_PEND
;
1442 return do_subchannel_work(sch
);
1445 IOInstEnding
css_do_hsch(SubchDev
*sch
)
1447 SCSW
*s
= &sch
->curr_status
.scsw
;
1448 PMCW
*p
= &sch
->curr_status
.pmcw
;
1450 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1451 return IOINST_CC_NOT_OPERATIONAL
;
1454 if (((s
->ctrl
& SCSW_CTRL_MASK_STCTL
) == SCSW_STCTL_STATUS_PEND
) ||
1455 (s
->ctrl
& (SCSW_STCTL_PRIMARY
|
1456 SCSW_STCTL_SECONDARY
|
1457 SCSW_STCTL_ALERT
))) {
1458 return IOINST_CC_STATUS_PRESENT
;
1461 if (s
->ctrl
& (SCSW_FCTL_HALT_FUNC
| SCSW_FCTL_CLEAR_FUNC
)) {
1462 return IOINST_CC_BUSY
;
1465 /* Trigger the halt function. */
1466 s
->ctrl
|= SCSW_FCTL_HALT_FUNC
;
1467 s
->ctrl
&= ~SCSW_FCTL_START_FUNC
;
1468 if (((s
->ctrl
& SCSW_CTRL_MASK_ACTL
) ==
1469 (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) &&
1470 ((s
->ctrl
& SCSW_CTRL_MASK_STCTL
) == SCSW_STCTL_INTERMEDIATE
)) {
1471 s
->ctrl
&= ~SCSW_STCTL_STATUS_PEND
;
1473 s
->ctrl
|= SCSW_ACTL_HALT_PEND
;
1475 return do_subchannel_work(sch
);
1478 static void css_update_chnmon(SubchDev
*sch
)
1480 if (!(sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_MME
)) {
1484 /* The counter is conveniently located at the beginning of the struct. */
1485 if (sch
->curr_status
.pmcw
.chars
& PMCW_CHARS_MASK_MBFC
) {
1486 /* Format 1, per-subchannel area. */
1489 count
= address_space_ldl(&address_space_memory
,
1490 sch
->curr_status
.mba
,
1491 MEMTXATTRS_UNSPECIFIED
,
1494 address_space_stl(&address_space_memory
, sch
->curr_status
.mba
, count
,
1495 MEMTXATTRS_UNSPECIFIED
, NULL
);
1497 /* Format 0, global area. */
1501 offset
= sch
->curr_status
.pmcw
.mbi
<< 5;
1502 count
= address_space_lduw(&address_space_memory
,
1503 channel_subsys
.chnmon_area
+ offset
,
1504 MEMTXATTRS_UNSPECIFIED
,
1507 address_space_stw(&address_space_memory
,
1508 channel_subsys
.chnmon_area
+ offset
, count
,
1509 MEMTXATTRS_UNSPECIFIED
, NULL
);
1513 IOInstEnding
css_do_ssch(SubchDev
*sch
, ORB
*orb
)
1515 SCSW
*s
= &sch
->curr_status
.scsw
;
1516 PMCW
*p
= &sch
->curr_status
.pmcw
;
1518 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1519 return IOINST_CC_NOT_OPERATIONAL
;
1522 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
1523 return IOINST_CC_STATUS_PRESENT
;
1526 if (s
->ctrl
& (SCSW_FCTL_START_FUNC
|
1527 SCSW_FCTL_HALT_FUNC
|
1528 SCSW_FCTL_CLEAR_FUNC
)) {
1529 return IOINST_CC_BUSY
;
1532 /* If monitoring is active, update counter. */
1533 if (channel_subsys
.chnmon_active
) {
1534 css_update_chnmon(sch
);
1537 sch
->channel_prog
= orb
->cpa
;
1538 /* Trigger the start function. */
1539 s
->ctrl
|= (SCSW_FCTL_START_FUNC
| SCSW_ACTL_START_PEND
);
1540 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
1542 return do_subchannel_work(sch
);
1545 static void copy_irb_to_guest(IRB
*dest
, const IRB
*src
, PMCW
*pmcw
,
1549 uint16_t stctl
= src
->scsw
.ctrl
& SCSW_CTRL_MASK_STCTL
;
1550 uint16_t actl
= src
->scsw
.ctrl
& SCSW_CTRL_MASK_ACTL
;
1552 copy_scsw_to_guest(&dest
->scsw
, &src
->scsw
);
1554 for (i
= 0; i
< ARRAY_SIZE(dest
->esw
); i
++) {
1555 dest
->esw
[i
] = cpu_to_be32(src
->esw
[i
]);
1557 for (i
= 0; i
< ARRAY_SIZE(dest
->ecw
); i
++) {
1558 dest
->ecw
[i
] = cpu_to_be32(src
->ecw
[i
]);
1560 *irb_len
= sizeof(*dest
) - sizeof(dest
->emw
);
1562 /* extended measurements enabled? */
1563 if ((src
->scsw
.flags
& SCSW_FLAGS_MASK_ESWF
) ||
1564 !(pmcw
->flags
& PMCW_FLAGS_MASK_TF
) ||
1565 !(pmcw
->chars
& PMCW_CHARS_MASK_XMWME
)) {
1568 /* extended measurements pending? */
1569 if (!(stctl
& SCSW_STCTL_STATUS_PEND
)) {
1572 if ((stctl
& SCSW_STCTL_PRIMARY
) ||
1573 (stctl
== SCSW_STCTL_SECONDARY
) ||
1574 ((stctl
& SCSW_STCTL_INTERMEDIATE
) && (actl
& SCSW_ACTL_SUSP
))) {
1575 for (i
= 0; i
< ARRAY_SIZE(dest
->emw
); i
++) {
1576 dest
->emw
[i
] = cpu_to_be32(src
->emw
[i
]);
1579 *irb_len
= sizeof(*dest
);
1582 int css_do_tsch_get_irb(SubchDev
*sch
, IRB
*target_irb
, int *irb_len
)
1584 SCSW
*s
= &sch
->curr_status
.scsw
;
1585 PMCW
*p
= &sch
->curr_status
.pmcw
;
1589 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1593 stctl
= s
->ctrl
& SCSW_CTRL_MASK_STCTL
;
1595 /* Prepare the irb for the guest. */
1596 memset(&irb
, 0, sizeof(IRB
));
1598 /* Copy scsw from current status. */
1599 memcpy(&irb
.scsw
, s
, sizeof(SCSW
));
1600 if (stctl
& SCSW_STCTL_STATUS_PEND
) {
1601 if (s
->cstat
& (SCSW_CSTAT_DATA_CHECK
|
1602 SCSW_CSTAT_CHN_CTRL_CHK
|
1603 SCSW_CSTAT_INTF_CTRL_CHK
)) {
1604 irb
.scsw
.flags
|= SCSW_FLAGS_MASK_ESWF
;
1605 irb
.esw
[0] = 0x04804000;
1607 irb
.esw
[0] = 0x00800000;
1609 /* If a unit check is pending, copy sense data. */
1610 if ((s
->dstat
& SCSW_DSTAT_UNIT_CHECK
) &&
1611 (p
->chars
& PMCW_CHARS_MASK_CSENSE
)) {
1614 irb
.scsw
.flags
|= SCSW_FLAGS_MASK_ESWF
| SCSW_FLAGS_MASK_ECTL
;
1615 /* Attention: sense_data is already BE! */
1616 memcpy(irb
.ecw
, sch
->sense_data
, sizeof(sch
->sense_data
));
1617 for (i
= 0; i
< ARRAY_SIZE(irb
.ecw
); i
++) {
1618 irb
.ecw
[i
] = be32_to_cpu(irb
.ecw
[i
]);
1620 irb
.esw
[1] = 0x01000000 | (sizeof(sch
->sense_data
) << 8);
1623 /* Store the irb to the guest. */
1624 copy_irb_to_guest(target_irb
, &irb
, p
, irb_len
);
1626 return ((stctl
& SCSW_STCTL_STATUS_PEND
) == 0);
1629 void css_do_tsch_update_subch(SubchDev
*sch
)
1631 SCSW
*s
= &sch
->curr_status
.scsw
;
1632 PMCW
*p
= &sch
->curr_status
.pmcw
;
1637 stctl
= s
->ctrl
& SCSW_CTRL_MASK_STCTL
;
1638 fctl
= s
->ctrl
& SCSW_CTRL_MASK_FCTL
;
1639 actl
= s
->ctrl
& SCSW_CTRL_MASK_ACTL
;
1641 /* Clear conditions on subchannel, if applicable. */
1642 if (stctl
& SCSW_STCTL_STATUS_PEND
) {
1643 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1644 if ((stctl
!= (SCSW_STCTL_INTERMEDIATE
| SCSW_STCTL_STATUS_PEND
)) ||
1645 ((fctl
& SCSW_FCTL_HALT_FUNC
) &&
1646 (actl
& SCSW_ACTL_SUSP
))) {
1647 s
->ctrl
&= ~SCSW_CTRL_MASK_FCTL
;
1649 if (stctl
!= (SCSW_STCTL_INTERMEDIATE
| SCSW_STCTL_STATUS_PEND
)) {
1650 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
1651 s
->ctrl
&= ~(SCSW_ACTL_RESUME_PEND
|
1652 SCSW_ACTL_START_PEND
|
1653 SCSW_ACTL_HALT_PEND
|
1654 SCSW_ACTL_CLEAR_PEND
|
1657 if ((actl
& SCSW_ACTL_SUSP
) &&
1658 (fctl
& SCSW_FCTL_START_FUNC
)) {
1659 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
1660 if (fctl
& SCSW_FCTL_HALT_FUNC
) {
1661 s
->ctrl
&= ~(SCSW_ACTL_RESUME_PEND
|
1662 SCSW_ACTL_START_PEND
|
1663 SCSW_ACTL_HALT_PEND
|
1664 SCSW_ACTL_CLEAR_PEND
|
1667 s
->ctrl
&= ~SCSW_ACTL_RESUME_PEND
;
1671 /* Clear pending sense data. */
1672 if (p
->chars
& PMCW_CHARS_MASK_CSENSE
) {
1673 memset(sch
->sense_data
, 0 , sizeof(sch
->sense_data
));
1678 static void copy_crw_to_guest(CRW
*dest
, const CRW
*src
)
1680 dest
->flags
= cpu_to_be16(src
->flags
);
1681 dest
->rsid
= cpu_to_be16(src
->rsid
);
1684 int css_do_stcrw(CRW
*crw
)
1686 CrwContainer
*crw_cont
;
1689 crw_cont
= QTAILQ_FIRST(&channel_subsys
.pending_crws
);
1691 QTAILQ_REMOVE(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
1692 copy_crw_to_guest(crw
, &crw_cont
->crw
);
1696 /* List was empty, turn crw machine checks on again. */
1697 memset(crw
, 0, sizeof(*crw
));
1698 channel_subsys
.do_crw_mchk
= true;
1705 static void copy_crw_from_guest(CRW
*dest
, const CRW
*src
)
1707 dest
->flags
= be16_to_cpu(src
->flags
);
1708 dest
->rsid
= be16_to_cpu(src
->rsid
);
1711 void css_undo_stcrw(CRW
*crw
)
1713 CrwContainer
*crw_cont
;
1715 crw_cont
= g_try_new0(CrwContainer
, 1);
1717 channel_subsys
.crws_lost
= true;
1720 copy_crw_from_guest(&crw_cont
->crw
, crw
);
1722 QTAILQ_INSERT_HEAD(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
1725 int css_collect_chp_desc(int m
, uint8_t cssid
, uint8_t f_chpid
, uint8_t l_chpid
,
1726 int rfmt
, void *buf
)
1730 uint32_t chpid_type_word
;
1734 css
= channel_subsys
.css
[channel_subsys
.default_cssid
];
1736 css
= channel_subsys
.css
[cssid
];
1742 for (i
= f_chpid
; i
<= l_chpid
; i
++) {
1743 if (css
->chpids
[i
].in_use
) {
1744 chpid_type_word
= 0x80000000 | (css
->chpids
[i
].type
<< 8) | i
;
1746 words
[0] = cpu_to_be32(chpid_type_word
);
1748 memcpy(buf
+ desc_size
, words
, 8);
1750 } else if (rfmt
== 1) {
1751 words
[0] = cpu_to_be32(chpid_type_word
);
1759 memcpy(buf
+ desc_size
, words
, 32);
1767 void css_do_schm(uint8_t mbk
, int update
, int dct
, uint64_t mbo
)
1769 /* dct is currently ignored (not really meaningful for our devices) */
1770 /* TODO: Don't ignore mbk. */
1771 if (update
&& !channel_subsys
.chnmon_active
) {
1772 /* Enable measuring. */
1773 channel_subsys
.chnmon_area
= mbo
;
1774 channel_subsys
.chnmon_active
= true;
1776 if (!update
&& channel_subsys
.chnmon_active
) {
1777 /* Disable measuring. */
1778 channel_subsys
.chnmon_area
= 0;
1779 channel_subsys
.chnmon_active
= false;
1783 IOInstEnding
css_do_rsch(SubchDev
*sch
)
1785 SCSW
*s
= &sch
->curr_status
.scsw
;
1786 PMCW
*p
= &sch
->curr_status
.pmcw
;
1788 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1789 return IOINST_CC_NOT_OPERATIONAL
;
1792 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
1793 return IOINST_CC_STATUS_PRESENT
;
1796 if (((s
->ctrl
& SCSW_CTRL_MASK_FCTL
) != SCSW_FCTL_START_FUNC
) ||
1797 (s
->ctrl
& SCSW_ACTL_RESUME_PEND
) ||
1798 (!(s
->ctrl
& SCSW_ACTL_SUSP
))) {
1799 return IOINST_CC_BUSY
;
1802 /* If monitoring is active, update counter. */
1803 if (channel_subsys
.chnmon_active
) {
1804 css_update_chnmon(sch
);
1807 s
->ctrl
|= SCSW_ACTL_RESUME_PEND
;
1808 return do_subchannel_work(sch
);
1811 int css_do_rchp(uint8_t cssid
, uint8_t chpid
)
1815 if (cssid
> channel_subsys
.max_cssid
) {
1818 if (channel_subsys
.max_cssid
== 0) {
1819 real_cssid
= channel_subsys
.default_cssid
;
1823 if (!channel_subsys
.css
[real_cssid
]) {
1827 if (!channel_subsys
.css
[real_cssid
]->chpids
[chpid
].in_use
) {
1831 if (!channel_subsys
.css
[real_cssid
]->chpids
[chpid
].is_virtual
) {
1833 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1838 /* We don't really use a channel path, so we're done here. */
1839 css_queue_crw(CRW_RSC_CHP
, CRW_ERC_INIT
, 1,
1840 channel_subsys
.max_cssid
> 0 ? 1 : 0, chpid
);
1841 if (channel_subsys
.max_cssid
> 0) {
1842 css_queue_crw(CRW_RSC_CHP
, CRW_ERC_INIT
, 1, 0, real_cssid
<< 8);
1847 bool css_schid_final(int m
, uint8_t cssid
, uint8_t ssid
, uint16_t schid
)
1852 real_cssid
= (!m
&& (cssid
== 0)) ? channel_subsys
.default_cssid
: cssid
;
1853 if (ssid
> MAX_SSID
||
1854 !channel_subsys
.css
[real_cssid
] ||
1855 !channel_subsys
.css
[real_cssid
]->sch_set
[ssid
]) {
1858 set
= channel_subsys
.css
[real_cssid
]->sch_set
[ssid
];
1859 return schid
> find_last_bit(set
->schids_used
,
1860 (MAX_SCHID
+ 1) / sizeof(unsigned long));
1863 unsigned int css_find_free_chpid(uint8_t cssid
)
1865 CssImage
*css
= channel_subsys
.css
[cssid
];
1869 return MAX_CHPID
+ 1;
1872 for (chpid
= 0; chpid
<= MAX_CHPID
; chpid
++) {
1873 /* skip reserved chpid */
1874 if (chpid
== VIRTIO_CCW_CHPID
) {
1877 if (!css
->chpids
[chpid
].in_use
) {
1881 return MAX_CHPID
+ 1;
1884 static int css_add_chpid(uint8_t cssid
, uint8_t chpid
, uint8_t type
,
1889 trace_css_chpid_add(cssid
, chpid
, type
);
1890 css
= channel_subsys
.css
[cssid
];
1894 if (css
->chpids
[chpid
].in_use
) {
1897 css
->chpids
[chpid
].in_use
= 1;
1898 css
->chpids
[chpid
].type
= type
;
1899 css
->chpids
[chpid
].is_virtual
= is_virt
;
1901 css_generate_chp_crws(cssid
, chpid
);
1906 void css_sch_build_virtual_schib(SubchDev
*sch
, uint8_t chpid
, uint8_t type
)
1908 PMCW
*p
= &sch
->curr_status
.pmcw
;
1909 SCSW
*s
= &sch
->curr_status
.scsw
;
1911 CssImage
*css
= channel_subsys
.css
[sch
->cssid
];
1913 assert(css
!= NULL
);
1914 memset(p
, 0, sizeof(PMCW
));
1915 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
1916 p
->devno
= sch
->devno
;
1921 p
->chpid
[0] = chpid
;
1922 if (!css
->chpids
[chpid
].in_use
) {
1923 css_add_chpid(sch
->cssid
, chpid
, type
, true);
1926 memset(s
, 0, sizeof(SCSW
));
1927 sch
->curr_status
.mba
= 0;
1928 for (i
= 0; i
< ARRAY_SIZE(sch
->curr_status
.mda
); i
++) {
1929 sch
->curr_status
.mda
[i
] = 0;
1933 SubchDev
*css_find_subch(uint8_t m
, uint8_t cssid
, uint8_t ssid
, uint16_t schid
)
1937 real_cssid
= (!m
&& (cssid
== 0)) ? channel_subsys
.default_cssid
: cssid
;
1939 if (!channel_subsys
.css
[real_cssid
]) {
1943 if (!channel_subsys
.css
[real_cssid
]->sch_set
[ssid
]) {
1947 return channel_subsys
.css
[real_cssid
]->sch_set
[ssid
]->sch
[schid
];
1951 * Return free device number in subchannel set.
1953 * Return index of the first free device number in the subchannel set
1954 * identified by @p cssid and @p ssid, beginning the search at @p
1955 * start and wrapping around at MAX_DEVNO. Return a value exceeding
1956 * MAX_SCHID if there are no free device numbers in the subchannel
1959 static uint32_t css_find_free_devno(uint8_t cssid
, uint8_t ssid
,
1964 for (round
= 0; round
<= MAX_DEVNO
; round
++) {
1965 uint16_t devno
= (start
+ round
) % MAX_DEVNO
;
1967 if (!css_devno_used(cssid
, ssid
, devno
)) {
1971 return MAX_DEVNO
+ 1;
1975 * Return first free subchannel (id) in subchannel set.
1977 * Return index of the first free subchannel in the subchannel set
1978 * identified by @p cssid and @p ssid, if there is any. Return a value
1979 * exceeding MAX_SCHID if there are no free subchannels in the
1982 static uint32_t css_find_free_subch(uint8_t cssid
, uint8_t ssid
)
1986 for (schid
= 0; schid
<= MAX_SCHID
; schid
++) {
1987 if (!css_find_subch(1, cssid
, ssid
, schid
)) {
1991 return MAX_SCHID
+ 1;
1995 * Return first free subchannel (id) in subchannel set for a device number
1997 * Verify the device number @p devno is not used yet in the subchannel
1998 * set identified by @p cssid and @p ssid. Set @p schid to the index
1999 * of the first free subchannel in the subchannel set, if there is
2000 * any. Return true if everything succeeded and false otherwise.
2002 static bool css_find_free_subch_for_devno(uint8_t cssid
, uint8_t ssid
,
2003 uint16_t devno
, uint16_t *schid
,
2006 uint32_t free_schid
;
2009 if (css_devno_used(cssid
, ssid
, devno
)) {
2010 error_setg(errp
, "Device %x.%x.%04x already exists",
2011 cssid
, ssid
, devno
);
2014 free_schid
= css_find_free_subch(cssid
, ssid
);
2015 if (free_schid
> MAX_SCHID
) {
2016 error_setg(errp
, "No free subchannel found for %x.%x.%04x",
2017 cssid
, ssid
, devno
);
2020 *schid
= free_schid
;
2025 * Return first free subchannel (id) and device number
2027 * Locate the first free subchannel and first free device number in
2028 * any of the subchannel sets of the channel subsystem identified by
2029 * @p cssid. Return false if no free subchannel / device number could
2030 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
2031 * the available subchannel and device number and return true.
2033 * May modify @p ssid, @p devno and / or @p schid even if no free
2034 * subchannel / device number could be found.
2036 static bool css_find_free_subch_and_devno(uint8_t cssid
, uint8_t *ssid
,
2037 uint16_t *devno
, uint16_t *schid
,
2040 uint32_t free_schid
, free_devno
;
2042 assert(ssid
&& devno
&& schid
);
2043 for (*ssid
= 0; *ssid
<= MAX_SSID
; (*ssid
)++) {
2044 free_schid
= css_find_free_subch(cssid
, *ssid
);
2045 if (free_schid
> MAX_SCHID
) {
2048 free_devno
= css_find_free_devno(cssid
, *ssid
, free_schid
);
2049 if (free_devno
> MAX_DEVNO
) {
2052 *schid
= free_schid
;
2053 *devno
= free_devno
;
2056 error_setg(errp
, "Virtual channel subsystem is full!");
2060 bool css_subch_visible(SubchDev
*sch
)
2062 if (sch
->ssid
> channel_subsys
.max_ssid
) {
2066 if (sch
->cssid
!= channel_subsys
.default_cssid
) {
2067 return (channel_subsys
.max_cssid
> 0);
2073 bool css_present(uint8_t cssid
)
2075 return (channel_subsys
.css
[cssid
] != NULL
);
2078 bool css_devno_used(uint8_t cssid
, uint8_t ssid
, uint16_t devno
)
2080 if (!channel_subsys
.css
[cssid
]) {
2083 if (!channel_subsys
.css
[cssid
]->sch_set
[ssid
]) {
2087 return !!test_bit(devno
,
2088 channel_subsys
.css
[cssid
]->sch_set
[ssid
]->devnos_used
);
2091 void css_subch_assign(uint8_t cssid
, uint8_t ssid
, uint16_t schid
,
2092 uint16_t devno
, SubchDev
*sch
)
2097 trace_css_assign_subch(sch
? "assign" : "deassign", cssid
, ssid
, schid
,
2099 if (!channel_subsys
.css
[cssid
]) {
2101 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2102 __func__
, cssid
, ssid
, schid
);
2105 css
= channel_subsys
.css
[cssid
];
2107 if (!css
->sch_set
[ssid
]) {
2108 css
->sch_set
[ssid
] = g_new0(SubchSet
, 1);
2110 s_set
= css
->sch_set
[ssid
];
2112 s_set
->sch
[schid
] = sch
;
2114 set_bit(schid
, s_set
->schids_used
);
2115 set_bit(devno
, s_set
->devnos_used
);
2117 clear_bit(schid
, s_set
->schids_used
);
2118 clear_bit(devno
, s_set
->devnos_used
);
2122 void css_queue_crw(uint8_t rsc
, uint8_t erc
, int solicited
,
2123 int chain
, uint16_t rsid
)
2125 CrwContainer
*crw_cont
;
2127 trace_css_crw(rsc
, erc
, rsid
, chain
? "(chained)" : "");
2128 /* TODO: Maybe use a static crw pool? */
2129 crw_cont
= g_try_new0(CrwContainer
, 1);
2131 channel_subsys
.crws_lost
= true;
2134 crw_cont
->crw
.flags
= (rsc
<< 8) | erc
;
2136 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_S
;
2139 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_C
;
2141 crw_cont
->crw
.rsid
= rsid
;
2142 if (channel_subsys
.crws_lost
) {
2143 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_R
;
2144 channel_subsys
.crws_lost
= false;
2147 QTAILQ_INSERT_TAIL(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
2149 if (channel_subsys
.do_crw_mchk
) {
2150 channel_subsys
.do_crw_mchk
= false;
2151 /* Inject crw pending machine check. */
2156 void css_generate_sch_crws(uint8_t cssid
, uint8_t ssid
, uint16_t schid
,
2157 int hotplugged
, int add
)
2159 uint8_t guest_cssid
;
2162 if (add
&& !hotplugged
) {
2165 if (channel_subsys
.max_cssid
== 0) {
2166 /* Default cssid shows up as 0. */
2167 guest_cssid
= (cssid
== channel_subsys
.default_cssid
) ? 0 : cssid
;
2169 /* Show real cssid to the guest. */
2170 guest_cssid
= cssid
;
2173 * Only notify for higher subchannel sets/channel subsystems if the
2174 * guest has enabled it.
2176 if ((ssid
> channel_subsys
.max_ssid
) ||
2177 (guest_cssid
> channel_subsys
.max_cssid
) ||
2178 ((channel_subsys
.max_cssid
== 0) &&
2179 (cssid
!= channel_subsys
.default_cssid
))) {
2182 chain_crw
= (channel_subsys
.max_ssid
> 0) ||
2183 (channel_subsys
.max_cssid
> 0);
2184 css_queue_crw(CRW_RSC_SUBCH
, CRW_ERC_IPI
, 0, chain_crw
? 1 : 0, schid
);
2186 css_queue_crw(CRW_RSC_SUBCH
, CRW_ERC_IPI
, 0, 0,
2187 (guest_cssid
<< 8) | (ssid
<< 4));
2189 /* RW_ERC_IPI --> clear pending interrupts */
2190 css_clear_io_interrupt(css_do_build_subchannel_id(cssid
, ssid
), schid
);
2193 void css_generate_chp_crws(uint8_t cssid
, uint8_t chpid
)
2198 void css_generate_css_crws(uint8_t cssid
)
2200 if (!channel_subsys
.sei_pending
) {
2201 css_queue_crw(CRW_RSC_CSS
, CRW_ERC_EVENT
, 0, 0, cssid
);
2203 channel_subsys
.sei_pending
= true;
2206 void css_clear_sei_pending(void)
2208 channel_subsys
.sei_pending
= false;
2211 int css_enable_mcsse(void)
2213 trace_css_enable_facility("mcsse");
2214 channel_subsys
.max_cssid
= MAX_CSSID
;
2218 int css_enable_mss(void)
2220 trace_css_enable_facility("mss");
2221 channel_subsys
.max_ssid
= MAX_SSID
;
2225 void css_reset_sch(SubchDev
*sch
)
2227 PMCW
*p
= &sch
->curr_status
.pmcw
;
2229 if ((p
->flags
& PMCW_FLAGS_MASK_ENA
) != 0 && sch
->disable_cb
) {
2230 sch
->disable_cb(sch
);
2234 p
->flags
&= ~(PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
2235 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
2236 PMCW_FLAGS_MASK_MP
| PMCW_FLAGS_MASK_TF
);
2237 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
2238 p
->devno
= sch
->devno
;
2246 p
->chars
&= ~(PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_XMWME
|
2247 PMCW_CHARS_MASK_CSENSE
);
2249 memset(&sch
->curr_status
.scsw
, 0, sizeof(sch
->curr_status
.scsw
));
2250 sch
->curr_status
.mba
= 0;
2252 sch
->channel_prog
= 0x0;
2253 sch
->last_cmd_valid
= false;
2254 sch
->thinint_active
= false;
2257 void css_reset(void)
2259 CrwContainer
*crw_cont
;
2261 /* Clean up monitoring. */
2262 channel_subsys
.chnmon_active
= false;
2263 channel_subsys
.chnmon_area
= 0;
2265 /* Clear pending CRWs. */
2266 while ((crw_cont
= QTAILQ_FIRST(&channel_subsys
.pending_crws
))) {
2267 QTAILQ_REMOVE(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
2270 channel_subsys
.sei_pending
= false;
2271 channel_subsys
.do_crw_mchk
= true;
2272 channel_subsys
.crws_lost
= false;
2274 /* Reset maximum ids. */
2275 channel_subsys
.max_cssid
= 0;
2276 channel_subsys
.max_ssid
= 0;
2279 static void get_css_devid(Object
*obj
, Visitor
*v
, const char *name
,
2280 void *opaque
, Error
**errp
)
2282 DeviceState
*dev
= DEVICE(obj
);
2283 Property
*prop
= opaque
;
2284 CssDevId
*dev_id
= qdev_get_prop_ptr(dev
, prop
);
2285 char buffer
[] = "xx.x.xxxx";
2289 if (dev_id
->valid
) {
2291 r
= snprintf(buffer
, sizeof(buffer
), "%02x.%1x.%04x", dev_id
->cssid
,
2292 dev_id
->ssid
, dev_id
->devid
);
2293 assert(r
== sizeof(buffer
) - 1);
2295 /* drop leading zero */
2296 if (dev_id
->cssid
<= 0xf) {
2300 snprintf(buffer
, sizeof(buffer
), "<unset>");
2303 visit_type_str(v
, name
, &p
, errp
);
2307 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2309 static void set_css_devid(Object
*obj
, Visitor
*v
, const char *name
,
2310 void *opaque
, Error
**errp
)
2312 DeviceState
*dev
= DEVICE(obj
);
2313 Property
*prop
= opaque
;
2314 CssDevId
*dev_id
= qdev_get_prop_ptr(dev
, prop
);
2315 Error
*local_err
= NULL
;
2318 unsigned int cssid
, ssid
, devid
;
2320 if (dev
->realized
) {
2321 qdev_prop_set_after_realize(dev
, name
, errp
);
2325 visit_type_str(v
, name
, &str
, &local_err
);
2327 error_propagate(errp
, local_err
);
2331 num
= sscanf(str
, "%2x.%1x%n.%4x%n", &cssid
, &ssid
, &n1
, &devid
, &n2
);
2332 if (num
!= 3 || (n2
- n1
) != 5 || strlen(str
) != n2
) {
2333 error_set_from_qdev_prop_error(errp
, EINVAL
, dev
, prop
, str
);
2336 if ((cssid
> MAX_CSSID
) || (ssid
> MAX_SSID
)) {
2337 error_setg(errp
, "Invalid cssid or ssid: cssid %x, ssid %x",
2342 dev_id
->cssid
= cssid
;
2343 dev_id
->ssid
= ssid
;
2344 dev_id
->devid
= devid
;
2345 dev_id
->valid
= true;
2351 const PropertyInfo css_devid_propinfo
= {
2353 .description
= "Identifier of an I/O device in the channel "
2354 "subsystem, example: fe.1.23ab",
2355 .get
= get_css_devid
,
2356 .set
= set_css_devid
,
2359 const PropertyInfo css_devid_ro_propinfo
= {
2361 .description
= "Read-only identifier of an I/O device in the channel "
2362 "subsystem, example: fe.1.23ab",
2363 .get
= get_css_devid
,
2366 SubchDev
*css_create_sch(CssDevId bus_id
, bool squash_mcss
, Error
**errp
)
2373 bus_id
.cssid
= channel_subsys
.default_cssid
;
2374 } else if (!channel_subsys
.css
[bus_id
.cssid
]) {
2375 css_create_css_image(bus_id
.cssid
, false);
2378 if (!css_find_free_subch_for_devno(bus_id
.cssid
, bus_id
.ssid
,
2379 bus_id
.devid
, &schid
, errp
)) {
2383 for (bus_id
.cssid
= channel_subsys
.default_cssid
;;) {
2384 if (!channel_subsys
.css
[bus_id
.cssid
]) {
2385 css_create_css_image(bus_id
.cssid
, false);
2388 if (css_find_free_subch_and_devno(bus_id
.cssid
, &bus_id
.ssid
,
2389 &bus_id
.devid
, &schid
,
2393 bus_id
.cssid
= (bus_id
.cssid
+ 1) % MAX_CSSID
;
2394 if (bus_id
.cssid
== channel_subsys
.default_cssid
) {
2395 error_setg(errp
, "Virtual channel subsystem is full!");
2401 sch
= g_new0(SubchDev
, 1);
2402 sch
->cssid
= bus_id
.cssid
;
2403 sch
->ssid
= bus_id
.ssid
;
2404 sch
->devno
= bus_id
.devid
;
2406 css_subch_assign(sch
->cssid
, sch
->ssid
, schid
, sch
->devno
, sch
);
2410 static int css_sch_get_chpids(SubchDev
*sch
, CssDevId
*dev_id
)
2416 PMCW
*p
= &sch
->curr_status
.pmcw
;
2418 fid_path
= g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2419 dev_id
->cssid
, dev_id
->ssid
, dev_id
->devid
);
2420 fd
= fopen(fid_path
, "r");
2422 error_report("%s: open %s failed", __func__
, fid_path
);
2427 if (fscanf(fd
, "%x %x %x %x %x %x %x %x",
2428 &chpid
[0], &chpid
[1], &chpid
[2], &chpid
[3],
2429 &chpid
[4], &chpid
[5], &chpid
[6], &chpid
[7]) != 8) {
2435 for (i
= 0; i
< ARRAY_SIZE(p
->chpid
); i
++) {
2436 p
->chpid
[i
] = chpid
[i
];
2445 static int css_sch_get_path_masks(SubchDev
*sch
, CssDevId
*dev_id
)
2449 uint32_t pim
, pam
, pom
;
2450 PMCW
*p
= &sch
->curr_status
.pmcw
;
2452 fid_path
= g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2453 dev_id
->cssid
, dev_id
->ssid
, dev_id
->devid
);
2454 fd
= fopen(fid_path
, "r");
2456 error_report("%s: open %s failed", __func__
, fid_path
);
2461 if (fscanf(fd
, "%x %x %x", &pim
, &pam
, &pom
) != 3) {
2476 static int css_sch_get_chpid_type(uint8_t chpid
, uint32_t *type
,
2482 fid_path
= g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2483 dev_id
->cssid
, chpid
);
2484 fd
= fopen(fid_path
, "r");
2486 error_report("%s: open %s failed", __func__
, fid_path
);
2491 if (fscanf(fd
, "%x", type
) != 1) {
2504 * We currently retrieve the real device information from sysfs to build the
2505 * guest subchannel information block without considering the migration feature.
2506 * We need to revisit this problem when we want to add migration support.
2508 int css_sch_build_schib(SubchDev
*sch
, CssDevId
*dev_id
)
2510 CssImage
*css
= channel_subsys
.css
[sch
->cssid
];
2511 PMCW
*p
= &sch
->curr_status
.pmcw
;
2512 SCSW
*s
= &sch
->curr_status
.scsw
;
2516 assert(css
!= NULL
);
2517 memset(p
, 0, sizeof(PMCW
));
2518 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
2519 /* We are dealing with I/O subchannels only. */
2520 p
->devno
= sch
->devno
;
2522 /* Grab path mask from sysfs. */
2523 ret
= css_sch_get_path_masks(sch
, dev_id
);
2528 /* Grab chpids from sysfs. */
2529 ret
= css_sch_get_chpids(sch
, dev_id
);
2534 /* Build chpid type. */
2535 for (i
= 0; i
< ARRAY_SIZE(p
->chpid
); i
++) {
2536 if (p
->chpid
[i
] && !css
->chpids
[p
->chpid
[i
]].in_use
) {
2537 ret
= css_sch_get_chpid_type(p
->chpid
[i
], &type
, dev_id
);
2541 css_add_chpid(sch
->cssid
, p
->chpid
[i
], type
, false);
2545 memset(s
, 0, sizeof(SCSW
));
2546 sch
->curr_status
.mba
= 0;
2547 for (i
= 0; i
< ARRAY_SIZE(sch
->curr_status
.mda
); i
++) {
2548 sch
->curr_status
.mda
[i
] = 0;