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hw/arm/allwinner: add Security Identifier device
[qemu/ar7.git] / hw / arm / allwinner-h3.c
blobdeeea63f5f3ef68b3015f2fe7dcf58f5acb80ecd
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/usb/hcd-ehci.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/arm/allwinner-h3.h"
34
35 /* Memory map */
36 const hwaddr allwinner_h3_memmap[] = {
37 [AW_H3_SRAM_A1] = 0x00000000,
38 [AW_H3_SRAM_A2] = 0x00044000,
39 [AW_H3_SRAM_C] = 0x00010000,
40 [AW_H3_SYSCTRL] = 0x01c00000,
41 [AW_H3_SID] = 0x01c14000,
42 [AW_H3_EHCI0] = 0x01c1a000,
43 [AW_H3_OHCI0] = 0x01c1a400,
44 [AW_H3_EHCI1] = 0x01c1b000,
45 [AW_H3_OHCI1] = 0x01c1b400,
46 [AW_H3_EHCI2] = 0x01c1c000,
47 [AW_H3_OHCI2] = 0x01c1c400,
48 [AW_H3_EHCI3] = 0x01c1d000,
49 [AW_H3_OHCI3] = 0x01c1d400,
50 [AW_H3_CCU] = 0x01c20000,
51 [AW_H3_PIT] = 0x01c20c00,
52 [AW_H3_UART0] = 0x01c28000,
53 [AW_H3_UART1] = 0x01c28400,
54 [AW_H3_UART2] = 0x01c28800,
55 [AW_H3_UART3] = 0x01c28c00,
56 [AW_H3_GIC_DIST] = 0x01c81000,
57 [AW_H3_GIC_CPU] = 0x01c82000,
58 [AW_H3_GIC_HYP] = 0x01c84000,
59 [AW_H3_GIC_VCPU] = 0x01c86000,
60 [AW_H3_CPUCFG] = 0x01f01c00,
61 [AW_H3_SDRAM] = 0x40000000
62 };
63
64 /* List of unimplemented devices */
65 struct AwH3Unimplemented {
66 const char *device_name;
67 hwaddr base;
68 hwaddr size;
69 } unimplemented[] = {
70 { "d-engine", 0x01000000, 4 * MiB },
71 { "d-inter", 0x01400000, 128 * KiB },
72 { "dma", 0x01c02000, 4 * KiB },
73 { "nfdc", 0x01c03000, 4 * KiB },
74 { "ts", 0x01c06000, 4 * KiB },
75 { "keymem", 0x01c0b000, 4 * KiB },
76 { "lcd0", 0x01c0c000, 4 * KiB },
77 { "lcd1", 0x01c0d000, 4 * KiB },
78 { "ve", 0x01c0e000, 4 * KiB },
79 { "mmc0", 0x01c0f000, 4 * KiB },
80 { "mmc1", 0x01c10000, 4 * KiB },
81 { "mmc2", 0x01c11000, 4 * KiB },
82 { "crypto", 0x01c15000, 4 * KiB },
83 { "msgbox", 0x01c17000, 4 * KiB },
84 { "spinlock", 0x01c18000, 4 * KiB },
85 { "usb0-otg", 0x01c19000, 4 * KiB },
86 { "usb0-phy", 0x01c1a000, 4 * KiB },
87 { "usb1-phy", 0x01c1b000, 4 * KiB },
88 { "usb2-phy", 0x01c1c000, 4 * KiB },
89 { "usb3-phy", 0x01c1d000, 4 * KiB },
90 { "smc", 0x01c1e000, 4 * KiB },
91 { "pio", 0x01c20800, 1 * KiB },
92 { "owa", 0x01c21000, 1 * KiB },
93 { "pwm", 0x01c21400, 1 * KiB },
94 { "keyadc", 0x01c21800, 1 * KiB },
95 { "pcm0", 0x01c22000, 1 * KiB },
96 { "pcm1", 0x01c22400, 1 * KiB },
97 { "pcm2", 0x01c22800, 1 * KiB },
98 { "audio", 0x01c22c00, 2 * KiB },
99 { "smta", 0x01c23400, 1 * KiB },
100 { "ths", 0x01c25000, 1 * KiB },
101 { "uart0", 0x01c28000, 1 * KiB },
102 { "uart1", 0x01c28400, 1 * KiB },
103 { "uart2", 0x01c28800, 1 * KiB },
104 { "uart3", 0x01c28c00, 1 * KiB },
105 { "twi0", 0x01c2ac00, 1 * KiB },
106 { "twi1", 0x01c2b000, 1 * KiB },
107 { "twi2", 0x01c2b400, 1 * KiB },
108 { "scr", 0x01c2c400, 1 * KiB },
109 { "emac", 0x01c30000, 64 * KiB },
110 { "gpu", 0x01c40000, 64 * KiB },
111 { "hstmr", 0x01c60000, 4 * KiB },
112 { "dramcom", 0x01c62000, 4 * KiB },
113 { "dramctl0", 0x01c63000, 4 * KiB },
114 { "dramphy0", 0x01c65000, 4 * KiB },
115 { "spi0", 0x01c68000, 4 * KiB },
116 { "spi1", 0x01c69000, 4 * KiB },
117 { "csi", 0x01cb0000, 320 * KiB },
118 { "tve", 0x01e00000, 64 * KiB },
119 { "hdmi", 0x01ee0000, 128 * KiB },
120 { "rtc", 0x01f00000, 1 * KiB },
121 { "r_timer", 0x01f00800, 1 * KiB },
122 { "r_intc", 0x01f00c00, 1 * KiB },
123 { "r_wdog", 0x01f01000, 1 * KiB },
124 { "r_prcm", 0x01f01400, 1 * KiB },
125 { "r_twd", 0x01f01800, 1 * KiB },
126 { "r_cir-rx", 0x01f02000, 1 * KiB },
127 { "r_twi", 0x01f02400, 1 * KiB },
128 { "r_uart", 0x01f02800, 1 * KiB },
129 { "r_pio", 0x01f02c00, 1 * KiB },
130 { "r_pwm", 0x01f03800, 1 * KiB },
131 { "core-dbg", 0x3f500000, 128 * KiB },
132 { "tsgen-ro", 0x3f506000, 4 * KiB },
133 { "tsgen-ctl", 0x3f507000, 4 * KiB },
134 { "ddr-mem", 0x40000000, 2 * GiB },
135 { "n-brom", 0xffff0000, 32 * KiB },
136 { "s-brom", 0xffff0000, 64 * KiB }
137 };
138
139 /* Per Processor Interrupts */
140 enum {
141 AW_H3_GIC_PPI_MAINT = 9,
142 AW_H3_GIC_PPI_HYPTIMER = 10,
143 AW_H3_GIC_PPI_VIRTTIMER = 11,
144 AW_H3_GIC_PPI_SECTIMER = 13,
145 AW_H3_GIC_PPI_PHYSTIMER = 14
146 };
147
148 /* Shared Processor Interrupts */
149 enum {
150 AW_H3_GIC_SPI_UART0 = 0,
151 AW_H3_GIC_SPI_UART1 = 1,
152 AW_H3_GIC_SPI_UART2 = 2,
153 AW_H3_GIC_SPI_UART3 = 3,
154 AW_H3_GIC_SPI_TIMER0 = 18,
155 AW_H3_GIC_SPI_TIMER1 = 19,
156 AW_H3_GIC_SPI_EHCI0 = 72,
157 AW_H3_GIC_SPI_OHCI0 = 73,
158 AW_H3_GIC_SPI_EHCI1 = 74,
159 AW_H3_GIC_SPI_OHCI1 = 75,
160 AW_H3_GIC_SPI_EHCI2 = 76,
161 AW_H3_GIC_SPI_OHCI2 = 77,
162 AW_H3_GIC_SPI_EHCI3 = 78,
163 AW_H3_GIC_SPI_OHCI3 = 79,
164 };
165
166 /* Allwinner H3 general constants */
167 enum {
168 AW_H3_GIC_NUM_SPI = 128
169 };
170
171 static void allwinner_h3_init(Object *obj)
172 {
173 AwH3State *s = AW_H3(obj);
174
175 s->memmap = allwinner_h3_memmap;
176
177 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
178 object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
179 ARM_CPU_TYPE_NAME("cortex-a7"),
180 &error_abort, NULL);
181 }
182
183 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
184 TYPE_ARM_GIC);
185
186 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
187 TYPE_AW_A10_PIT);
188 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
189 "clk0-freq", &error_abort);
190 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
191 "clk1-freq", &error_abort);
192
193 sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
194 TYPE_AW_H3_CCU);
195
196 sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
197 TYPE_AW_H3_SYSCTRL);
198
199 sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
200 TYPE_AW_CPUCFG);
201
202 sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
203 TYPE_AW_SID);
204 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
205 "identifier", &error_abort);
206 }
207
208 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
209 {
210 AwH3State *s = AW_H3(dev);
211 unsigned i;
212
213 /* CPUs */
214 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
215
216 /* Provide Power State Coordination Interface */
217 qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
218 QEMU_PSCI_CONDUIT_HVC);
219
220 /* Disable secondary CPUs */
221 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
222 i > 0);
223
224 /* All exception levels required */
225 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
226 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
227
228 /* Mark realized */
229 qdev_init_nofail(DEVICE(&s->cpus[i]));
230 }
231
232 /* Generic Interrupt Controller */
233 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
234 GIC_INTERNAL);
235 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
236 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
237 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
238 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
239 qdev_init_nofail(DEVICE(&s->gic));
240
241 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
242 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
243 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
244 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
245
246 /*
247 * Wire the outputs from each CPU's generic timer and the GICv3
248 * maintenance interrupt signal to the appropriate GIC PPI inputs,
249 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
250 */
251 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
252 DeviceState *cpudev = DEVICE(&s->cpus[i]);
253 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
254 int irq;
255 /*
256 * Mapping from the output timer irq lines from the CPU to the
257 * GIC PPI inputs used for this board.
258 */
259 const int timer_irq[] = {
260 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
261 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
262 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
263 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
264 };
265
266 /* Connect CPU timer outputs to GIC PPI inputs */
267 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
268 qdev_connect_gpio_out(cpudev, irq,
269 qdev_get_gpio_in(DEVICE(&s->gic),
270 ppibase + timer_irq[irq]));
271 }
272
273 /* Connect GIC outputs to CPU interrupt inputs */
274 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
275 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
277 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
278 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
279 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
280 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
281 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
282
283 /* GIC maintenance signal */
284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
285 qdev_get_gpio_in(DEVICE(&s->gic),
286 ppibase + AW_H3_GIC_PPI_MAINT));
287 }
288
289 /* Timer */
290 qdev_init_nofail(DEVICE(&s->timer));
291 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
292 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
293 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
294 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
295 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
296
297 /* SRAM */
298 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
299 64 * KiB, &error_abort);
300 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
301 32 * KiB, &error_abort);
302 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
303 44 * KiB, &error_abort);
304 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
305 &s->sram_a1);
306 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
307 &s->sram_a2);
308 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
309 &s->sram_c);
310
311 /* Clock Control Unit */
312 qdev_init_nofail(DEVICE(&s->ccu));
313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
314
315 /* System Control */
316 qdev_init_nofail(DEVICE(&s->sysctrl));
317 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
318
319 /* CPU Configuration */
320 qdev_init_nofail(DEVICE(&s->cpucfg));
321 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
322
323 /* Security Identifier */
324 qdev_init_nofail(DEVICE(&s->sid));
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
326
327 /* Universal Serial Bus */
328 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
329 qdev_get_gpio_in(DEVICE(&s->gic),
330 AW_H3_GIC_SPI_EHCI0));
331 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
332 qdev_get_gpio_in(DEVICE(&s->gic),
333 AW_H3_GIC_SPI_EHCI1));
334 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
335 qdev_get_gpio_in(DEVICE(&s->gic),
336 AW_H3_GIC_SPI_EHCI2));
337 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
338 qdev_get_gpio_in(DEVICE(&s->gic),
339 AW_H3_GIC_SPI_EHCI3));
340
341 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
342 qdev_get_gpio_in(DEVICE(&s->gic),
343 AW_H3_GIC_SPI_OHCI0));
344 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
345 qdev_get_gpio_in(DEVICE(&s->gic),
346 AW_H3_GIC_SPI_OHCI1));
347 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
348 qdev_get_gpio_in(DEVICE(&s->gic),
349 AW_H3_GIC_SPI_OHCI2));
350 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
351 qdev_get_gpio_in(DEVICE(&s->gic),
352 AW_H3_GIC_SPI_OHCI3));
353
354 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
355 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
356 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
357 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
358 /* UART1 */
359 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
360 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
361 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
362 /* UART2 */
363 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
364 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
365 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
366 /* UART3 */
367 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
368 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
369 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
370
371 /* Unimplemented devices */
372 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
373 create_unimplemented_device(unimplemented[i].device_name,
374 unimplemented[i].base,
375 unimplemented[i].size);
376 }
377 }
378
379 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
380 {
381 DeviceClass *dc = DEVICE_CLASS(oc);
382
383 dc->realize = allwinner_h3_realize;
384 /* Reason: uses serial_hd() in realize function */
385 dc->user_creatable = false;
386 }
387
388 static const TypeInfo allwinner_h3_type_info = {
389 .name = TYPE_AW_H3,
390 .parent = TYPE_DEVICE,
391 .instance_size = sizeof(AwH3State),
392 .instance_init = allwinner_h3_init,
393 .class_init = allwinner_h3_class_init,
394 };
395
396 static void allwinner_h3_register_types(void)
397 {
398 type_register_static(&allwinner_h3_type_info);
399 }
400
401 type_init(allwinner_h3_register_types)
AR7 emulation for QEMU