target-arm/cpu-qom.h

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_ARM_CPU_QOM_H
  21 #define QEMU_ARM_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24
  25 #define TYPE_ARM_CPU "arm-cpu"
  26
  27 #define ARM_CPU_CLASS(klass) \
  28     OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
  29 #define ARM_CPU(obj) \
  30     OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
  31 #define ARM_CPU_GET_CLASS(obj) \
  32     OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
  33
  34 /**
  35  * ARMCPUClass:
  36  * @parent_realize: The parent class' realize handler.
  37  * @parent_reset: The parent class' reset handler.
  38  *
  39  * An ARM CPU model.
  40  */
  41 typedef struct ARMCPUClass {
  42     /*< private >*/
  43     CPUClass parent_class;
  44     /*< public >*/
  45
  46     DeviceRealize parent_realize;
  47     void (*parent_reset)(CPUState *cpu);
  48 } ARMCPUClass;
  49
  50 /**
  51  * ARMCPU:
  52  * @env: #CPUARMState
  53  *
  54  * An ARM CPU core.
  55  */
  56 typedef struct ARMCPU {
  57     /*< private >*/
  58     CPUState parent_obj;
  59     /*< public >*/
  60
  61     CPUARMState env;
  62
  63     /* Coprocessor information */
  64     GHashTable *cp_regs;
  65
  66     /* The instance init functions for implementation-specific subclasses
  67      * set these fields to specify the implementation-dependent values of
  68      * various constant registers and reset values of non-constant
  69      * registers.
  70      * Some of these might become QOM properties eventually.
  71      * Field names match the official register names as defined in the
  72      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
  73      * is used for reset values of non-constant registers; no reset_
  74      * prefix means a constant register.
  75      */
  76     uint32_t midr;
  77     uint32_t reset_fpsid;
  78     uint32_t mvfr0;
  79     uint32_t mvfr1;
  80     uint32_t ctr;
  81     uint32_t reset_sctlr;
  82     uint32_t id_pfr0;
  83     uint32_t id_pfr1;
  84     uint32_t id_dfr0;
  85     uint32_t id_afr0;
  86     uint32_t id_mmfr0;
  87     uint32_t id_mmfr1;
  88     uint32_t id_mmfr2;
  89     uint32_t id_mmfr3;
  90     uint32_t id_isar0;
  91     uint32_t id_isar1;
  92     uint32_t id_isar2;
  93     uint32_t id_isar3;
  94     uint32_t id_isar4;
  95     uint32_t id_isar5;
  96     uint32_t clidr;
  97     /* The elements of this array are the CCSIDR values for each cache,
  98      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
  99      */
 100     uint32_t ccsidr[16];
 101     uint32_t reset_cbar;
 102     uint32_t reset_auxcr;
 103 } ARMCPU;
 104
 105 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
 106 {
 107     return ARM_CPU(container_of(env, ARMCPU, env));
 108 }
 109
 110 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
 111
 112 void register_cp_regs_for_features(ARMCPU *cpu);
 113
 114 #endif