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target-mips: add unions to access DSP elements
[qemu/ar7.git] / target-mips / dsp_helper.c
blobaed4c637c3bd35a533541487ca71032abb72184a
1 /*
2 * MIPS ASE DSP Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 * Dongxue Zhang <elta.era@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 /* As the byte ordering doesn't matter, i.e. all columns are treated
24 identically, these unions can be used directly. */
25 typedef union {
26 uint8_t ub[4];
27 int8_t sb[4];
28 uint16_t uh[2];
29 int16_t sh[2];
30 uint32_t uw[1];
31 int32_t sw[1];
32 } DSP32Value;
33
34 typedef union {
35 uint8_t ub[8];
36 int8_t sb[8];
37 uint16_t uh[4];
38 int16_t sh[4];
39 uint32_t uw[2];
40 int32_t sw[2];
41 uint64_t ul[1];
42 int64_t sl[1];
43 } DSP64Value;
44
45 /*** MIPS DSP internal functions begin ***/
46 #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
47 #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
48
49 static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
50 CPUMIPSState *env)
51 {
52 env->active_tc.DSPControl |= (target_ulong)flag << position;
53 }
54
55 static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
56 {
57 env->active_tc.DSPControl |= (target_ulong)flag << 13;
58 }
59
60 static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
61 {
62 return (env->active_tc.DSPControl >> 13) & 0x01;
63 }
64
65 static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
66 {
67 uint32_t filter;
68
69 filter = ((0x01 << len) - 1) << 24;
70 filter = ~filter;
71
72 env->active_tc.DSPControl &= filter;
73 env->active_tc.DSPControl |= (target_ulong)flag << 24;
74 }
75
76 static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
77 {
78 uint32_t filter;
79
80 filter = (0x01 << len) - 1;
81
82 return (env->active_tc.DSPControl >> 24) & filter;
83 }
84
85 static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
86 {
87 target_ulong dspc;
88
89 dspc = env->active_tc.DSPControl;
90 #ifndef TARGET_MIPS64
91 dspc = dspc & 0xFFFFFFC0;
92 dspc |= pos;
93 #else
94 dspc = dspc & 0xFFFFFF80;
95 dspc |= pos;
96 #endif
97 env->active_tc.DSPControl = dspc;
98 }
99
100 static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
101 {
102 target_ulong dspc;
103 uint32_t pos;
104
105 dspc = env->active_tc.DSPControl;
106
107 #ifndef TARGET_MIPS64
108 pos = dspc & 0x3F;
109 #else
110 pos = dspc & 0x7F;
111 #endif
112
113 return pos;
114 }
115
116 static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
117 {
118 env->active_tc.DSPControl &= 0xFFFFBFFF;
119 env->active_tc.DSPControl |= (target_ulong)flag << 14;
120 }
121
122 #define DO_MIPS_SAT_ABS(size) \
123 static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \
124 CPUMIPSState *env) \
125 { \
126 if (a == INT##size##_MIN) { \
127 set_DSPControl_overflow_flag(1, 20, env); \
128 return INT##size##_MAX; \
129 } else { \
130 return MIPSDSP_ABS(a); \
131 } \
132 }
133 DO_MIPS_SAT_ABS(8)
134 DO_MIPS_SAT_ABS(16)
135 DO_MIPS_SAT_ABS(32)
136 #undef DO_MIPS_SAT_ABS
137
138 /* get sum value */
139 static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env)
140 {
141 int16_t tempI;
142
143 tempI = a + b;
144
145 if (MIPSDSP_OVERFLOW(a, b, tempI, 0x8000)) {
146 set_DSPControl_overflow_flag(1, 20, env);
147 }
148
149 return tempI;
150 }
151
152 static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b,
153 CPUMIPSState *env)
154 {
155 int16_t tempS;
156
157 tempS = a + b;
158
159 if (MIPSDSP_OVERFLOW(a, b, tempS, 0x8000)) {
160 if (a > 0) {
161 tempS = 0x7FFF;
162 } else {
163 tempS = 0x8000;
164 }
165 set_DSPControl_overflow_flag(1, 20, env);
166 }
167
168 return tempS;
169 }
170
171 static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b,
172 CPUMIPSState *env)
173 {
174 int32_t tempI;
175
176 tempI = a + b;
177
178 if (MIPSDSP_OVERFLOW(a, b, tempI, 0x80000000)) {
179 if (a > 0) {
180 tempI = 0x7FFFFFFF;
181 } else {
182 tempI = 0x80000000;
183 }
184 set_DSPControl_overflow_flag(1, 20, env);
185 }
186
187 return tempI;
188 }
189
190 static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
191 {
192 uint16_t temp;
193
194 temp = (uint16_t)a + (uint16_t)b;
195
196 if (temp & 0x0100) {
197 set_DSPControl_overflow_flag(1, 20, env);
198 }
199
200 return temp & 0xFF;
201 }
202
203 static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b,
204 CPUMIPSState *env)
205 {
206 uint32_t temp;
207
208 temp = (uint32_t)a + (uint32_t)b;
209
210 if (temp & 0x00010000) {
211 set_DSPControl_overflow_flag(1, 20, env);
212 }
213
214 return temp & 0xFFFF;
215 }
216
217 static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b,
218 CPUMIPSState *env)
219 {
220 uint8_t result;
221 uint16_t temp;
222
223 temp = (uint16_t)a + (uint16_t)b;
224 result = temp & 0xFF;
225
226 if (0x0100 & temp) {
227 result = 0xFF;
228 set_DSPControl_overflow_flag(1, 20, env);
229 }
230
231 return result;
232 }
233
234 static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b,
235 CPUMIPSState *env)
236 {
237 uint16_t result;
238 uint32_t temp;
239
240 temp = (uint32_t)a + (uint32_t)b;
241 result = temp & 0xFFFF;
242
243 if (0x00010000 & temp) {
244 result = 0xFFFF;
245 set_DSPControl_overflow_flag(1, 20, env);
246 }
247
248 return result;
249 }
250
251 static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
252 CPUMIPSState *env)
253 {
254 int64_t temp;
255 int32_t temp32, temp31, result;
256 int64_t temp_sum;
257
258 #ifndef TARGET_MIPS64
259 temp = ((uint64_t)env->active_tc.HI[acc] << 32) |
260 (uint64_t)env->active_tc.LO[acc];
261 #else
262 temp = (uint64_t)env->active_tc.LO[acc];
263 #endif
264
265 temp_sum = (int64_t)a + temp;
266
267 temp32 = (temp_sum >> 32) & 0x01;
268 temp31 = (temp_sum >> 31) & 0x01;
269 result = temp_sum & 0xFFFFFFFF;
270
271 /* FIXME
272 This sat function may wrong, because user manual wrote:
273 temp127..0 ← temp + ( (signA) || a31..0
274 if ( temp32 ≠ temp31 ) then
275 if ( temp32 = 0 ) then
276 temp31..0 ← 0x80000000
277 else
278 temp31..0 ← 0x7FFFFFFF
279 endif
280 DSPControlouflag:16+acc ← 1
281 endif
282 */
283 if (temp32 != temp31) {
284 if (temp32 == 0) {
285 result = 0x7FFFFFFF;
286 } else {
287 result = 0x80000000;
288 }
289 set_DSPControl_overflow_flag(1, 16 + acc, env);
290 }
291
292 return result;
293 }
294
295 /* a[0] is LO, a[1] is HI. */
296 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
297 int32_t ac,
298 int64_t *a,
299 CPUMIPSState *env)
300 {
301 bool temp64;
302
303 ret[0] = env->active_tc.LO[ac] + a[0];
304 ret[1] = env->active_tc.HI[ac] + a[1];
305
306 if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) &&
307 ((uint64_t)ret[0] < (uint64_t)a[0])) {
308 ret[1] += 1;
309 }
310 temp64 = ret[1] & 1;
311 if (temp64 != ((ret[0] >> 63) & 0x01)) {
312 if (temp64) {
313 ret[0] = (0x01ull << 63);
314 ret[1] = ~0ull;
315 } else {
316 ret[0] = (0x01ull << 63) - 1;
317 ret[1] = 0x00;
318 }
319 set_DSPControl_overflow_flag(1, 16 + ac, env);
320 }
321 }
322
323 static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
324 int32_t ac,
325 int64_t *a,
326 CPUMIPSState *env)
327 {
328 bool temp64;
329
330 ret[0] = env->active_tc.LO[ac] - a[0];
331 ret[1] = env->active_tc.HI[ac] - a[1];
332
333 if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) {
334 ret[1] -= 1;
335 }
336 temp64 = ret[1] & 1;
337 if (temp64 != ((ret[0] >> 63) & 0x01)) {
338 if (temp64) {
339 ret[0] = (0x01ull << 63);
340 ret[1] = ~0ull;
341 } else {
342 ret[0] = (0x01ull << 63) - 1;
343 ret[1] = 0x00;
344 }
345 set_DSPControl_overflow_flag(1, 16 + ac, env);
346 }
347 }
348
349 static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
350 CPUMIPSState *env)
351 {
352 int32_t temp;
353
354 temp = (int32_t)a * (int32_t)b;
355
356 if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) {
357 set_DSPControl_overflow_flag(1, 21, env);
358 }
359 temp &= 0x0000FFFF;
360
361 return temp;
362 }
363
364 static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
365 {
366 return a * b;
367 }
368
369 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
370 {
371 return a * b;
372 }
373
374 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
375 CPUMIPSState *env)
376 {
377 int32_t temp;
378
379 temp = (int32_t)a * (int32_t)b;
380
381 if (temp > (int)0x7FFF) {
382 temp = 0x00007FFF;
383 set_DSPControl_overflow_flag(1, 21, env);
384 } else if (temp < (int)0xffff8000) {
385 temp = 0xFFFF8000;
386 set_DSPControl_overflow_flag(1, 21, env);
387 }
388 temp &= 0x0000FFFF;
389
390 return temp;
391 }
392
393 static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b,
394 CPUMIPSState *env)
395 {
396 int32_t temp;
397
398 if ((a == 0x8000) && (b == 0x8000)) {
399 temp = 0x7FFFFFFF;
400 set_DSPControl_overflow_flag(1, 21, env);
401 } else {
402 temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1;
403 }
404
405 return temp;
406 }
407
408 /* right shift */
409 static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov)
410 {
411 return a >> mov;
412 }
413
414 static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov)
415 {
416 return a >> mov;
417 }
418
419 static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov)
420 {
421 return a >> mov;
422 }
423
424 static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
425 {
426 return a >> mov;
427 }
428
429 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
430 {
431 return a >> mov;
432 }
433
434 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
435 {
436 int32_t temp;
437
438 temp = (int32_t)a + (int32_t)b;
439
440 return (temp >> 1) & 0xFFFF;
441 }
442
443 /* round right shift */
444 static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b)
445 {
446 int32_t temp;
447
448 temp = (int32_t)a + (int32_t)b;
449 temp += 1;
450
451 return (temp >> 1) & 0xFFFF;
452 }
453
454 static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b)
455 {
456 int64_t temp;
457
458 temp = (int64_t)a + (int64_t)b;
459
460 return (temp >> 1) & 0xFFFFFFFF;
461 }
462
463 static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b)
464 {
465 int64_t temp;
466
467 temp = (int64_t)a + (int64_t)b;
468 temp += 1;
469
470 return (temp >> 1) & 0xFFFFFFFF;
471 }
472
473 static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b)
474 {
475 uint16_t temp;
476
477 temp = (uint16_t)a + (uint16_t)b;
478
479 return (temp >> 1) & 0x00FF;
480 }
481
482 static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
483 {
484 uint16_t temp;
485
486 temp = (uint16_t)a + (uint16_t)b + 1;
487
488 return (temp >> 1) & 0x00FF;
489 }
490
491 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
492 {
493 uint16_t temp;
494
495 temp = (uint16_t)a - (uint16_t)b;
496
497 return (temp >> 1) & 0x00FF;
498 }
499
500 static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
501 {
502 uint16_t temp;
503
504 temp = (uint16_t)a - (uint16_t)b + 1;
505
506 return (temp >> 1) & 0x00FF;
507 }
508
509 /* 128 bits long. p[0] is LO, p[1] is HI. */
510 static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
511 int32_t ac,
512 int32_t shift,
513 CPUMIPSState *env)
514 {
515 int64_t acc;
516
517 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
518 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
519 if (shift == 0) {
520 p[0] = acc << 1;
521 p[1] = (acc >> 63) & 0x01;
522 } else {
523 p[0] = acc >> (shift - 1);
524 p[1] = 0;
525 }
526 }
527
528 /* 128 bits long. p[0] is LO, p[1] is HI */
529 static inline void mipsdsp_rashift_acc(uint64_t *p,
530 uint32_t ac,
531 uint32_t shift,
532 CPUMIPSState *env)
533 {
534 uint64_t tempB, tempA;
535
536 tempB = env->active_tc.HI[ac];
537 tempA = env->active_tc.LO[ac];
538 shift = shift & 0x1F;
539
540 if (shift == 0) {
541 p[1] = tempB;
542 p[0] = tempA;
543 } else {
544 p[0] = (tempB << (64 - shift)) | (tempA >> shift);
545 p[1] = (int64_t)tempB >> shift;
546 }
547 }
548
549 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
550 static inline void mipsdsp_rndrashift_acc(uint64_t *p,
551 uint32_t ac,
552 uint32_t shift,
553 CPUMIPSState *env)
554 {
555 int64_t tempB, tempA;
556
557 tempB = env->active_tc.HI[ac];
558 tempA = env->active_tc.LO[ac];
559 shift = shift & 0x3F;
560
561 if (shift == 0) {
562 p[2] = tempB >> 63;
563 p[1] = (tempB << 1) | (tempA >> 63);
564 p[0] = tempA << 1;
565 } else {
566 p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1));
567 p[1] = (int64_t)tempB >> (shift - 1);
568 if (tempB >= 0) {
569 p[2] = 0x0;
570 } else {
571 p[2] = ~0ull;
572 }
573 }
574 }
575
576 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
577 CPUMIPSState *env)
578 {
579 int32_t temp;
580
581 if ((a == 0x8000) && (b == 0x8000)) {
582 temp = 0x7FFFFFFF;
583 set_DSPControl_overflow_flag(1, 16 + ac, env);
584 } else {
585 temp = ((uint32_t)a * (uint32_t)b) << 1;
586 }
587
588 return temp;
589 }
590
591 static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b,
592 CPUMIPSState *env)
593 {
594 uint64_t temp;
595
596 if ((a == 0x80000000) && (b == 0x80000000)) {
597 temp = (0x01ull << 63) - 1;
598 set_DSPControl_overflow_flag(1, 16 + ac, env);
599 } else {
600 temp = ((uint64_t)a * (uint64_t)b) << 1;
601 }
602
603 return temp;
604 }
605
606 static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b)
607 {
608 return (uint16_t)a * (uint16_t)b;
609 }
610
611 static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
612 CPUMIPSState *env)
613 {
614 uint32_t tempI;
615
616 tempI = (uint32_t)a * (uint32_t)b;
617 if (tempI > 0x0000FFFF) {
618 tempI = 0x0000FFFF;
619 set_DSPControl_overflow_flag(1, 21, env);
620 }
621
622 return tempI & 0x0000FFFF;
623 }
624
625 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
626 {
627 return (uint64_t)a * (uint64_t)b;
628 }
629
630 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
631 CPUMIPSState *env)
632 {
633 uint32_t temp;
634
635 if ((a == 0x8000) && (b == 0x8000)) {
636 temp = 0x7FFF0000;
637 set_DSPControl_overflow_flag(1, 21, env);
638 } else {
639 temp = (a * b) << 1;
640 temp = temp + 0x00008000;
641 }
642
643 return (temp & 0xFFFF0000) >> 16;
644 }
645
646 static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
647 CPUMIPSState *env)
648 {
649 int32_t temp;
650
651 if ((a == 0x8000) && (b == 0x8000)) {
652 temp = 0x7FFF0000;
653 set_DSPControl_overflow_flag(1, 21, env);
654 } else {
655 temp = ((uint32_t)a * (uint32_t)b);
656 temp = temp << 1;
657 }
658
659 return (temp >> 16) & 0x0000FFFF;
660 }
661
662 static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
663 CPUMIPSState *env)
664 {
665 int64_t temp;
666
667 temp = (int32_t)a + 0x00008000;
668
669 if (a > (int)0x7fff8000) {
670 temp = 0x7FFFFFFF;
671 set_DSPControl_overflow_flag(1, 22, env);
672 }
673
674 return (temp >> 16) & 0xFFFF;
675 }
676
677 static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
678 CPUMIPSState *env)
679 {
680 uint16_t mag;
681 uint32_t sign;
682
683 sign = (a >> 15) & 0x01;
684 mag = a & 0x7FFF;
685
686 if (sign == 0) {
687 if (mag > 0x7F80) {
688 set_DSPControl_overflow_flag(1, 22, env);
689 return 0xFF;
690 } else {
691 return (mag >> 7) & 0xFFFF;
692 }
693 } else {
694 set_DSPControl_overflow_flag(1, 22, env);
695 return 0x00;
696 }
697 }
698
699 static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env)
700 {
701 uint8_t sign;
702 uint8_t discard;
703
704 if (s == 0) {
705 return a;
706 } else {
707 sign = (a >> 7) & 0x01;
708 if (sign != 0) {
709 discard = (((0x01 << (8 - s)) - 1) << s) |
710 ((a >> (6 - (s - 1))) & ((0x01 << s) - 1));
711 } else {
712 discard = a >> (6 - (s - 1));
713 }
714
715 if (discard != 0x00) {
716 set_DSPControl_overflow_flag(1, 22, env);
717 }
718 return a << s;
719 }
720 }
721
722 static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
723 CPUMIPSState *env)
724 {
725 uint8_t sign;
726 uint16_t discard;
727
728 if (s == 0) {
729 return a;
730 } else {
731 sign = (a >> 15) & 0x01;
732 if (sign != 0) {
733 discard = (((0x01 << (16 - s)) - 1) << s) |
734 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
735 } else {
736 discard = a >> (14 - (s - 1));
737 }
738
739 if ((discard != 0x0000) && (discard != 0xFFFF)) {
740 set_DSPControl_overflow_flag(1, 22, env);
741 }
742 return a << s;
743 }
744 }
745
746
747 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
748 CPUMIPSState *env)
749 {
750 uint32_t discard;
751
752 if (s == 0) {
753 return a;
754 } else {
755 discard = (int32_t)a >> (31 - (s - 1));
756
757 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
758 set_DSPControl_overflow_flag(1, 22, env);
759 }
760 return a << s;
761 }
762 }
763
764 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
765 CPUMIPSState *env)
766 {
767 uint8_t sign;
768 uint16_t discard;
769
770 if (s == 0) {
771 return a;
772 } else {
773 sign = (a >> 15) & 0x01;
774 if (sign != 0) {
775 discard = (((0x01 << (16 - s)) - 1) << s) |
776 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
777 } else {
778 discard = a >> (14 - (s - 1));
779 }
780
781 if ((discard != 0x0000) && (discard != 0xFFFF)) {
782 set_DSPControl_overflow_flag(1, 22, env);
783 return (sign == 0) ? 0x7FFF : 0x8000;
784 } else {
785 return a << s;
786 }
787 }
788 }
789
790 static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s,
791 CPUMIPSState *env)
792 {
793 uint8_t sign;
794 uint32_t discard;
795
796 if (s == 0) {
797 return a;
798 } else {
799 sign = (a >> 31) & 0x01;
800 if (sign != 0) {
801 discard = (((0x01 << (32 - s)) - 1) << s) |
802 ((a >> (30 - (s - 1))) & ((0x01 << s) - 1));
803 } else {
804 discard = a >> (30 - (s - 1));
805 }
806
807 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
808 set_DSPControl_overflow_flag(1, 22, env);
809 return (sign == 0) ? 0x7FFFFFFF : 0x80000000;
810 } else {
811 return a << s;
812 }
813 }
814 }
815
816 static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s)
817 {
818 uint32_t temp;
819
820 if (s == 0) {
821 temp = (uint32_t)a << 1;
822 } else {
823 temp = (int32_t)(int8_t)a >> (s - 1);
824 }
825
826 return (temp + 1) >> 1;
827 }
828
829 static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s)
830 {
831 uint32_t temp;
832
833 if (s == 0) {
834 temp = (uint32_t)a << 1;
835 } else {
836 temp = (int32_t)(int16_t)a >> (s - 1);
837 }
838
839 return (temp + 1) >> 1;
840 }
841
842 static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s)
843 {
844 int64_t temp;
845
846 if (s == 0) {
847 temp = (uint64_t)a << 1;
848 } else {
849 temp = (int64_t)(int32_t)a >> (s - 1);
850 }
851 temp += 1;
852
853 return (temp >> 1) & 0xFFFFFFFFull;
854 }
855
856 static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env)
857 {
858 int16_t temp;
859
860 temp = a - b;
861 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
862 set_DSPControl_overflow_flag(1, 20, env);
863 }
864
865 return temp;
866 }
867
868 static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b,
869 CPUMIPSState *env)
870 {
871 int16_t temp;
872
873 temp = a - b;
874 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
875 if (a > 0) {
876 temp = 0x7FFF;
877 } else {
878 temp = 0x8000;
879 }
880 set_DSPControl_overflow_flag(1, 20, env);
881 }
882
883 return temp;
884 }
885
886 static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b,
887 CPUMIPSState *env)
888 {
889 int32_t temp;
890
891 temp = a - b;
892 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
893 if (a > 0) {
894 temp = 0x7FFFFFFF;
895 } else {
896 temp = 0x80000000;
897 }
898 set_DSPControl_overflow_flag(1, 20, env);
899 }
900
901 return temp & 0xFFFFFFFFull;
902 }
903
904 static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b)
905 {
906 int32_t temp;
907
908 temp = (int32_t)a - (int32_t)b;
909
910 return (temp >> 1) & 0x0000FFFF;
911 }
912
913 static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b)
914 {
915 int32_t temp;
916
917 temp = (int32_t)a - (int32_t)b;
918 temp += 1;
919
920 return (temp >> 1) & 0x0000FFFF;
921 }
922
923 static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b)
924 {
925 int64_t temp;
926
927 temp = (int64_t)a - (int64_t)b;
928
929 return (temp >> 1) & 0xFFFFFFFFull;
930 }
931
932 static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b)
933 {
934 int64_t temp;
935
936 temp = (int64_t)a - (int64_t)b;
937 temp += 1;
938
939 return (temp >> 1) & 0xFFFFFFFFull;
940 }
941
942 static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b,
943 CPUMIPSState *env)
944 {
945 uint8_t temp16;
946 uint32_t temp;
947
948 temp = (uint32_t)a - (uint32_t)b;
949 temp16 = (temp >> 16) & 0x01;
950 if (temp16 == 1) {
951 set_DSPControl_overflow_flag(1, 20, env);
952 }
953 return temp & 0x0000FFFF;
954 }
955
956 static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b,
957 CPUMIPSState *env)
958 {
959 uint8_t temp16;
960 uint32_t temp;
961
962 temp = (uint32_t)a - (uint32_t)b;
963 temp16 = (temp >> 16) & 0x01;
964
965 if (temp16 == 1) {
966 temp = 0x0000;
967 set_DSPControl_overflow_flag(1, 20, env);
968 }
969
970 return temp & 0x0000FFFF;
971 }
972
973 static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
974 {
975 uint8_t temp8;
976 uint16_t temp;
977
978 temp = (uint16_t)a - (uint16_t)b;
979 temp8 = (temp >> 8) & 0x01;
980 if (temp8 == 1) {
981 set_DSPControl_overflow_flag(1, 20, env);
982 }
983
984 return temp & 0x00FF;
985 }
986
987 static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
988 {
989 uint8_t temp8;
990 uint16_t temp;
991
992 temp = (uint16_t)a - (uint16_t)b;
993 temp8 = (temp >> 8) & 0x01;
994 if (temp8 == 1) {
995 temp = 0x00;
996 set_DSPControl_overflow_flag(1, 20, env);
997 }
998
999 return temp & 0x00FF;
1000 }
1001
1002 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
1003 {
1004 int32_t temp;
1005
1006 temp = a - b;
1007 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
1008 set_DSPControl_overflow_flag(1, 20, env);
1009 }
1010
1011 return temp;
1012 }
1013
1014 static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
1015 {
1016 int32_t temp;
1017
1018 temp = a + b;
1019
1020 if (MIPSDSP_OVERFLOW(a, b, temp, 0x80000000)) {
1021 set_DSPControl_overflow_flag(1, 20, env);
1022 }
1023
1024 return temp;
1025 }
1026
1027 static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
1028 {
1029 return a == b;
1030 }
1031
1032 static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b)
1033 {
1034 return a <= b;
1035 }
1036
1037 static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b)
1038 {
1039 return a < b;
1040 }
1041
1042 static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b)
1043 {
1044 return a == b;
1045 }
1046
1047 static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b)
1048 {
1049 return a <= b;
1050 }
1051
1052 static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
1053 {
1054 return a < b;
1055 }
1056 /*** MIPS DSP internal functions end ***/
1057
1058 #define MIPSDSP_LHI 0xFFFFFFFF00000000ull
1059 #define MIPSDSP_LLO 0x00000000FFFFFFFFull
1060 #define MIPSDSP_HI 0xFFFF0000
1061 #define MIPSDSP_LO 0x0000FFFF
1062 #define MIPSDSP_Q3 0xFF000000
1063 #define MIPSDSP_Q2 0x00FF0000
1064 #define MIPSDSP_Q1 0x0000FF00
1065 #define MIPSDSP_Q0 0x000000FF
1066
1067 #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \
1068 do { \
1069 a = (num >> 24) & MIPSDSP_Q0; \
1070 b = (num >> 16) & MIPSDSP_Q0; \
1071 c = (num >> 8) & MIPSDSP_Q0; \
1072 d = num & MIPSDSP_Q0; \
1073 } while (0)
1074
1075 #define MIPSDSP_SPLIT32_16(num, a, b) \
1076 do { \
1077 a = (num >> 16) & MIPSDSP_LO; \
1078 b = num & MIPSDSP_LO; \
1079 } while (0)
1080
1081 #define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a)
1082 #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \
1083 (((uint32_t)a << 24) | \
1084 (((uint32_t)b << 16) | \
1085 (((uint32_t)c << 8) | \
1086 ((uint32_t)d & 0xFF)))))
1087 #define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \
1088 (((uint32_t)a << 16) | \
1089 ((uint32_t)b & 0xFFFF)))
1090
1091 #ifdef TARGET_MIPS64
1092 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \
1093 do { \
1094 a = (num >> 48) & MIPSDSP_LO; \
1095 b = (num >> 32) & MIPSDSP_LO; \
1096 c = (num >> 16) & MIPSDSP_LO; \
1097 d = num & MIPSDSP_LO; \
1098 } while (0)
1099
1100 #define MIPSDSP_SPLIT64_32(num, a, b) \
1101 do { \
1102 a = (num >> 32) & MIPSDSP_LLO; \
1103 b = num & MIPSDSP_LLO; \
1104 } while (0)
1105
1106 #define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
1107 ((uint64_t)b << 32) | \
1108 ((uint64_t)c << 16) | \
1109 (uint64_t)d)
1110 #define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
1111 #endif
1112
1113 /** DSP Arithmetic Sub-class insns **/
1114 #define ARITH_PH(name, func) \
1115 target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \
1116 { \
1117 uint16_t rsh, rsl, rth, rtl, temph, templ; \
1118 \
1119 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
1120 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1121 \
1122 temph = mipsdsp_##func(rsh, rth); \
1123 templ = mipsdsp_##func(rsl, rtl); \
1124 \
1125 return MIPSDSP_RETURN32_16(temph, templ); \
1126 }
1127
1128 #define ARITH_PH_ENV(name, func) \
1129 target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \
1130 CPUMIPSState *env) \
1131 { \
1132 uint16_t rsh, rsl, rth, rtl, temph, templ; \
1133 \
1134 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
1135 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1136 \
1137 temph = mipsdsp_##func(rsh, rth, env); \
1138 templ = mipsdsp_##func(rsl, rtl, env); \
1139 \
1140 return MIPSDSP_RETURN32_16(temph, templ); \
1141 }
1142
1143
1144 ARITH_PH_ENV(addq, add_i16);
1145 ARITH_PH_ENV(addq_s, sat_add_i16);
1146 ARITH_PH_ENV(addu, add_u16);
1147 ARITH_PH_ENV(addu_s, sat_add_u16);
1148
1149 ARITH_PH(addqh, rshift1_add_q16);
1150 ARITH_PH(addqh_r, rrshift1_add_q16);
1151
1152 ARITH_PH_ENV(subq, sub_i16);
1153 ARITH_PH_ENV(subq_s, sat16_sub);
1154 ARITH_PH_ENV(subu, sub_u16_u16);
1155 ARITH_PH_ENV(subu_s, satu16_sub_u16_u16);
1156
1157 ARITH_PH(subqh, rshift1_sub_q16);
1158 ARITH_PH(subqh_r, rrshift1_sub_q16);
1159
1160 #undef ARITH_PH
1161 #undef ARITH_PH_ENV
1162
1163 #ifdef TARGET_MIPS64
1164 #define ARITH_QH_ENV(name, func) \
1165 target_ulong helper_##name##_qh(target_ulong rs, target_ulong rt, \
1166 CPUMIPSState *env) \
1167 { \
1168 uint16_t rs3, rs2, rs1, rs0; \
1169 uint16_t rt3, rt2, rt1, rt0; \
1170 uint16_t tempD, tempC, tempB, tempA; \
1171 \
1172 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1173 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1174 \
1175 tempD = mipsdsp_##func(rs3, rt3, env); \
1176 tempC = mipsdsp_##func(rs2, rt2, env); \
1177 tempB = mipsdsp_##func(rs1, rt1, env); \
1178 tempA = mipsdsp_##func(rs0, rt0, env); \
1179 \
1180 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1181 }
1182
1183 ARITH_QH_ENV(addq, add_i16);
1184 ARITH_QH_ENV(addq_s, sat_add_i16);
1185 ARITH_QH_ENV(addu, add_u16);
1186 ARITH_QH_ENV(addu_s, sat_add_u16);
1187
1188 ARITH_QH_ENV(subq, sub_i16);
1189 ARITH_QH_ENV(subq_s, sat16_sub);
1190 ARITH_QH_ENV(subu, sub_u16_u16);
1191 ARITH_QH_ENV(subu_s, satu16_sub_u16_u16);
1192
1193 #undef ARITH_QH_ENV
1194
1195 #endif
1196
1197 #define ARITH_W(name, func) \
1198 target_ulong helper_##name##_w(target_ulong rs, target_ulong rt) \
1199 { \
1200 uint32_t rd; \
1201 rd = mipsdsp_##func(rs, rt); \
1202 return MIPSDSP_RETURN32(rd); \
1203 }
1204
1205 #define ARITH_W_ENV(name, func) \
1206 target_ulong helper_##name##_w(target_ulong rs, target_ulong rt, \
1207 CPUMIPSState *env) \
1208 { \
1209 uint32_t rd; \
1210 rd = mipsdsp_##func(rs, rt, env); \
1211 return MIPSDSP_RETURN32(rd); \
1212 }
1213
1214 ARITH_W_ENV(addq_s, sat_add_i32);
1215
1216 ARITH_W(addqh, rshift1_add_q32);
1217 ARITH_W(addqh_r, rrshift1_add_q32);
1218
1219 ARITH_W_ENV(subq_s, sat32_sub);
1220
1221 ARITH_W(subqh, rshift1_sub_q32);
1222 ARITH_W(subqh_r, rrshift1_sub_q32);
1223
1224 #undef ARITH_W
1225 #undef ARITH_W_ENV
1226
1227 target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env)
1228 {
1229 uint32_t rd;
1230
1231 rd = mipsdsp_sat_abs32(rt, env);
1232
1233 return (target_ulong)rd;
1234 }
1235
1236
1237 #if defined(TARGET_MIPS64)
1238
1239 #define ARITH_PW_ENV(name, func) \
1240 target_ulong helper_##name##_pw(target_ulong rs, target_ulong rt, \
1241 CPUMIPSState *env) \
1242 { \
1243 uint32_t rs1, rs0; \
1244 uint32_t rt1, rt0; \
1245 uint32_t tempB, tempA; \
1246 \
1247 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
1248 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1249 \
1250 tempB = mipsdsp_##func(rs1, rt1, env); \
1251 tempA = mipsdsp_##func(rs0, rt0, env); \
1252 \
1253 return MIPSDSP_RETURN64_32(tempB, tempA); \
1254 }
1255
1256 ARITH_PW_ENV(addq, add_i32);
1257 ARITH_PW_ENV(addq_s, sat_add_i32);
1258 ARITH_PW_ENV(subq, sub32);
1259 ARITH_PW_ENV(subq_s, sat32_sub);
1260
1261 #undef ARITH_PW_ENV
1262
1263 #endif
1264
1265 #define ARITH_QB(name, func) \
1266 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1267 { \
1268 uint8_t rs0, rs1, rs2, rs3; \
1269 uint8_t rt0, rt1, rt2, rt3; \
1270 uint8_t temp0, temp1, temp2, temp3; \
1271 \
1272 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1273 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1274 \
1275 temp0 = mipsdsp_##func(rs0, rt0); \
1276 temp1 = mipsdsp_##func(rs1, rt1); \
1277 temp2 = mipsdsp_##func(rs2, rt2); \
1278 temp3 = mipsdsp_##func(rs3, rt3); \
1279 \
1280 return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \
1281 }
1282
1283 #define ARITH_QB_ENV(name, func) \
1284 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt, \
1285 CPUMIPSState *env) \
1286 { \
1287 uint8_t rs0, rs1, rs2, rs3; \
1288 uint8_t rt0, rt1, rt2, rt3; \
1289 uint8_t temp0, temp1, temp2, temp3; \
1290 \
1291 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1292 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1293 \
1294 temp0 = mipsdsp_##func(rs0, rt0, env); \
1295 temp1 = mipsdsp_##func(rs1, rt1, env); \
1296 temp2 = mipsdsp_##func(rs2, rt2, env); \
1297 temp3 = mipsdsp_##func(rs3, rt3, env); \
1298 \
1299 return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \
1300 }
1301
1302 ARITH_QB(adduh, rshift1_add_u8);
1303 ARITH_QB(adduh_r, rrshift1_add_u8);
1304
1305 ARITH_QB_ENV(addu, add_u8);
1306 ARITH_QB_ENV(addu_s, sat_add_u8);
1307
1308 #undef ADDU_QB
1309 #undef ADDU_QB_ENV
1310
1311 #if defined(TARGET_MIPS64)
1312 #define ARITH_OB(name, func) \
1313 target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt) \
1314 { \
1315 int i; \
1316 uint8_t rs_t[8], rt_t[8]; \
1317 uint8_t temp[8]; \
1318 uint64_t result; \
1319 \
1320 result = 0; \
1321 \
1322 for (i = 0; i < 8; i++) { \
1323 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \
1324 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1325 temp[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \
1326 result |= (uint64_t)temp[i] << (8 * i); \
1327 } \
1328 \
1329 return result; \
1330 }
1331
1332 #define ARITH_OB_ENV(name, func) \
1333 target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt, \
1334 CPUMIPSState *env) \
1335 { \
1336 int i; \
1337 uint8_t rs_t[8], rt_t[8]; \
1338 uint8_t temp[8]; \
1339 uint64_t result; \
1340 \
1341 result = 0; \
1342 \
1343 for (i = 0; i < 8; i++) { \
1344 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \
1345 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1346 temp[i] = mipsdsp_##func(rs_t[i], rt_t[i], env); \
1347 result |= (uint64_t)temp[i] << (8 * i); \
1348 } \
1349 \
1350 return result; \
1351 }
1352
1353 ARITH_OB_ENV(addu, add_u8);
1354 ARITH_OB_ENV(addu_s, sat_add_u8);
1355
1356 ARITH_OB(adduh, rshift1_add_u8);
1357 ARITH_OB(adduh_r, rrshift1_add_u8);
1358
1359 ARITH_OB_ENV(subu, sub_u8);
1360 ARITH_OB_ENV(subu_s, satu8_sub);
1361
1362 ARITH_OB(subuh, rshift1_sub_u8);
1363 ARITH_OB(subuh_r, rrshift1_sub_u8);
1364
1365 #undef ARITH_OB
1366 #undef ARITH_OB_ENV
1367
1368 #endif
1369
1370 #define SUBU_QB(name, func) \
1371 target_ulong helper_##name##_qb(target_ulong rs, \
1372 target_ulong rt, \
1373 CPUMIPSState *env) \
1374 { \
1375 uint8_t rs3, rs2, rs1, rs0; \
1376 uint8_t rt3, rt2, rt1, rt0; \
1377 uint8_t tempD, tempC, tempB, tempA; \
1378 \
1379 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1380 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1381 \
1382 tempD = mipsdsp_##func(rs3, rt3, env); \
1383 tempC = mipsdsp_##func(rs2, rt2, env); \
1384 tempB = mipsdsp_##func(rs1, rt1, env); \
1385 tempA = mipsdsp_##func(rs0, rt0, env); \
1386 \
1387 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1388 }
1389
1390 SUBU_QB(subu, sub_u8);
1391 SUBU_QB(subu_s, satu8_sub);
1392
1393 #undef SUBU_QB
1394
1395 #define SUBUH_QB(name, var) \
1396 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1397 { \
1398 uint8_t rs3, rs2, rs1, rs0; \
1399 uint8_t rt3, rt2, rt1, rt0; \
1400 uint8_t tempD, tempC, tempB, tempA; \
1401 \
1402 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1403 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1404 \
1405 tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \
1406 tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
1407 tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \
1408 tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
1409 \
1410 return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
1411 ((uint32_t)tempB << 8) | ((uint32_t)tempA); \
1412 }
1413
1414 SUBUH_QB(subuh, 0);
1415 SUBUH_QB(subuh_r, 1);
1416
1417 #undef SUBUH_QB
1418
1419 target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1420 {
1421 uint64_t temp, tempRs, tempRt;
1422 int32_t flag;
1423
1424 tempRs = (uint64_t)rs & MIPSDSP_LLO;
1425 tempRt = (uint64_t)rt & MIPSDSP_LLO;
1426
1427 temp = tempRs + tempRt;
1428 flag = (temp & 0x0100000000ull) >> 32;
1429 set_DSPControl_carryflag(flag, env);
1430
1431 return (target_long)(int32_t)(temp & MIPSDSP_LLO);
1432 }
1433
1434 target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1435 {
1436 uint32_t rd;
1437 int32_t temp32, temp31;
1438 int64_t tempL;
1439
1440 tempL = (int64_t)(int32_t)rs + (int64_t)(int32_t)rt +
1441 get_DSPControl_carryflag(env);
1442 temp31 = (tempL >> 31) & 0x01;
1443 temp32 = (tempL >> 32) & 0x01;
1444
1445 if (temp31 != temp32) {
1446 set_DSPControl_overflow_flag(1, 20, env);
1447 }
1448
1449 rd = tempL & MIPSDSP_LLO;
1450
1451 return (target_long)(int32_t)rd;
1452 }
1453
1454 target_ulong helper_modsub(target_ulong rs, target_ulong rt)
1455 {
1456 int32_t decr;
1457 uint16_t lastindex;
1458 target_ulong rd;
1459
1460 decr = rt & MIPSDSP_Q0;
1461 lastindex = (rt >> 8) & MIPSDSP_LO;
1462
1463 if ((rs & MIPSDSP_LLO) == 0x00000000) {
1464 rd = (target_ulong)lastindex;
1465 } else {
1466 rd = rs - decr;
1467 }
1468
1469 return rd;
1470 }
1471
1472 target_ulong helper_raddu_w_qb(target_ulong rs)
1473 {
1474 uint8_t rs3, rs2, rs1, rs0;
1475 uint16_t temp;
1476
1477 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);
1478
1479 temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
1480
1481 return (target_ulong)temp;
1482 }
1483
1484 #if defined(TARGET_MIPS64)
1485 target_ulong helper_raddu_l_ob(target_ulong rs)
1486 {
1487 int i;
1488 uint16_t rs_t[8];
1489 uint64_t temp;
1490
1491 temp = 0;
1492
1493 for (i = 0; i < 8; i++) {
1494 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0;
1495 temp += (uint64_t)rs_t[i];
1496 }
1497
1498 return temp;
1499 }
1500 #endif
1501
1502 target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env)
1503 {
1504 uint8_t tempD, tempC, tempB, tempA;
1505
1506 MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA);
1507
1508 tempD = mipsdsp_sat_abs8(tempD, env);
1509 tempC = mipsdsp_sat_abs8(tempC, env);
1510 tempB = mipsdsp_sat_abs8(tempB, env);
1511 tempA = mipsdsp_sat_abs8(tempA, env);
1512
1513 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1514 }
1515
1516 target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env)
1517 {
1518 uint16_t tempB, tempA;
1519
1520 MIPSDSP_SPLIT32_16(rt, tempB, tempA);
1521
1522 tempB = mipsdsp_sat_abs16 (tempB, env);
1523 tempA = mipsdsp_sat_abs16 (tempA, env);
1524
1525 return MIPSDSP_RETURN32_16(tempB, tempA);
1526 }
1527
1528 #if defined(TARGET_MIPS64)
1529 target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env)
1530 {
1531 int i;
1532 int8_t temp[8];
1533 uint64_t result;
1534
1535 for (i = 0; i < 8; i++) {
1536 temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0;
1537 temp[i] = mipsdsp_sat_abs8(temp[i], env);
1538 }
1539
1540 for (i = 0; i < 8; i++) {
1541 result = (uint64_t)(uint8_t)temp[i] << (8 * i);
1542 }
1543
1544 return result;
1545 }
1546
1547 target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env)
1548 {
1549 int16_t tempD, tempC, tempB, tempA;
1550
1551 MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA);
1552
1553 tempD = mipsdsp_sat_abs16(tempD, env);
1554 tempC = mipsdsp_sat_abs16(tempC, env);
1555 tempB = mipsdsp_sat_abs16(tempB, env);
1556 tempA = mipsdsp_sat_abs16(tempA, env);
1557
1558 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1559 }
1560
1561 target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env)
1562 {
1563 int32_t tempB, tempA;
1564
1565 MIPSDSP_SPLIT64_32(rt, tempB, tempA);
1566
1567 tempB = mipsdsp_sat_abs32(tempB, env);
1568 tempA = mipsdsp_sat_abs32(tempA, env);
1569
1570 return MIPSDSP_RETURN64_32(tempB, tempA);
1571 }
1572 #endif
1573
1574 #define PRECR_QB_PH(name, a, b)\
1575 target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
1576 { \
1577 uint8_t tempD, tempC, tempB, tempA; \
1578 \
1579 tempD = (rs >> a) & MIPSDSP_Q0; \
1580 tempC = (rs >> b) & MIPSDSP_Q0; \
1581 tempB = (rt >> a) & MIPSDSP_Q0; \
1582 tempA = (rt >> b) & MIPSDSP_Q0; \
1583 \
1584 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1585 }
1586
1587 PRECR_QB_PH(precr, 16, 0);
1588 PRECR_QB_PH(precrq, 24, 8);
1589
1590 #undef PRECR_QB_OH
1591
1592 target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs,
1593 target_ulong rt)
1594 {
1595 uint16_t tempB, tempA;
1596
1597 tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
1598 tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
1599
1600 return MIPSDSP_RETURN32_16(tempB, tempA);
1601 }
1602
1603 target_ulong helper_precr_sra_r_ph_w(uint32_t sa,
1604 target_ulong rs, target_ulong rt)
1605 {
1606 uint64_t tempB, tempA;
1607
1608 /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */
1609 if (sa == 0) {
1610 tempB = (rt & MIPSDSP_LO) << 1;
1611 tempA = (rs & MIPSDSP_LO) << 1;
1612 } else {
1613 tempB = ((int32_t)rt >> (sa - 1)) + 1;
1614 tempA = ((int32_t)rs >> (sa - 1)) + 1;
1615 }
1616 rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
1617
1618 return (target_long)(int32_t)rt;
1619 }
1620
1621 target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt)
1622 {
1623 uint16_t tempB, tempA;
1624
1625 tempB = (rs & MIPSDSP_HI) >> 16;
1626 tempA = (rt & MIPSDSP_HI) >> 16;
1627
1628 return MIPSDSP_RETURN32_16(tempB, tempA);
1629 }
1630
1631 target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt,
1632 CPUMIPSState *env)
1633 {
1634 uint16_t tempB, tempA;
1635
1636 tempB = mipsdsp_trunc16_sat16_round(rs, env);
1637 tempA = mipsdsp_trunc16_sat16_round(rt, env);
1638
1639 return MIPSDSP_RETURN32_16(tempB, tempA);
1640 }
1641
1642 #if defined(TARGET_MIPS64)
1643 target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt)
1644 {
1645 uint8_t rs6, rs4, rs2, rs0;
1646 uint8_t rt6, rt4, rt2, rt0;
1647 uint64_t temp;
1648
1649 rs6 = (rs >> 48) & MIPSDSP_Q0;
1650 rs4 = (rs >> 32) & MIPSDSP_Q0;
1651 rs2 = (rs >> 16) & MIPSDSP_Q0;
1652 rs0 = rs & MIPSDSP_Q0;
1653 rt6 = (rt >> 48) & MIPSDSP_Q0;
1654 rt4 = (rt >> 32) & MIPSDSP_Q0;
1655 rt2 = (rt >> 16) & MIPSDSP_Q0;
1656 rt0 = rt & MIPSDSP_Q0;
1657
1658 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1659 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1660 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1661 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1662
1663 return temp;
1664 }
1665
1666 #define PRECR_QH_PW(name, var) \
1667 target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
1668 uint32_t sa) \
1669 { \
1670 uint16_t rs3, rs2, rs1, rs0; \
1671 uint16_t rt3, rt2, rt1, rt0; \
1672 uint16_t tempD, tempC, tempB, tempA; \
1673 \
1674 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1675 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1676 \
1677 /* When sa = 0, we use rt2, rt0, rs2, rs0; \
1678 * when sa != 0, we use rt3, rt1, rs3, rs1. */ \
1679 if (sa == 0) { \
1680 tempD = rt2 << var; \
1681 tempC = rt0 << var; \
1682 tempB = rs2 << var; \
1683 tempA = rs0 << var; \
1684 } else { \
1685 tempD = (((int16_t)rt3 >> sa) + var) >> var; \
1686 tempC = (((int16_t)rt1 >> sa) + var) >> var; \
1687 tempB = (((int16_t)rs3 >> sa) + var) >> var; \
1688 tempA = (((int16_t)rs1 >> sa) + var) >> var; \
1689 } \
1690 \
1691 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1692 }
1693
1694 PRECR_QH_PW(sra, 0);
1695 PRECR_QH_PW(sra_r, 1);
1696
1697 #undef PRECR_QH_PW
1698
1699 target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt)
1700 {
1701 uint8_t rs6, rs4, rs2, rs0;
1702 uint8_t rt6, rt4, rt2, rt0;
1703 uint64_t temp;
1704
1705 rs6 = (rs >> 56) & MIPSDSP_Q0;
1706 rs4 = (rs >> 40) & MIPSDSP_Q0;
1707 rs2 = (rs >> 24) & MIPSDSP_Q0;
1708 rs0 = (rs >> 8) & MIPSDSP_Q0;
1709 rt6 = (rt >> 56) & MIPSDSP_Q0;
1710 rt4 = (rt >> 40) & MIPSDSP_Q0;
1711 rt2 = (rt >> 24) & MIPSDSP_Q0;
1712 rt0 = (rt >> 8) & MIPSDSP_Q0;
1713
1714 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1715 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1716 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1717 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1718
1719 return temp;
1720 }
1721
1722 target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt)
1723 {
1724 uint16_t tempD, tempC, tempB, tempA;
1725
1726 tempD = (rs >> 48) & MIPSDSP_LO;
1727 tempC = (rs >> 16) & MIPSDSP_LO;
1728 tempB = (rt >> 48) & MIPSDSP_LO;
1729 tempA = (rt >> 16) & MIPSDSP_LO;
1730
1731 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1732 }
1733
1734 target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt,
1735 CPUMIPSState *env)
1736 {
1737 uint32_t rs2, rs0;
1738 uint32_t rt2, rt0;
1739 uint16_t tempD, tempC, tempB, tempA;
1740
1741 rs2 = (rs >> 32) & MIPSDSP_LLO;
1742 rs0 = rs & MIPSDSP_LLO;
1743 rt2 = (rt >> 32) & MIPSDSP_LLO;
1744 rt0 = rt & MIPSDSP_LLO;
1745
1746 tempD = mipsdsp_trunc16_sat16_round(rs2, env);
1747 tempC = mipsdsp_trunc16_sat16_round(rs0, env);
1748 tempB = mipsdsp_trunc16_sat16_round(rt2, env);
1749 tempA = mipsdsp_trunc16_sat16_round(rt0, env);
1750
1751 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1752 }
1753
1754 target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt)
1755 {
1756 uint32_t tempB, tempA;
1757
1758 tempB = (rs >> 32) & MIPSDSP_LLO;
1759 tempA = (rt >> 32) & MIPSDSP_LLO;
1760
1761 return MIPSDSP_RETURN64_32(tempB, tempA);
1762 }
1763 #endif
1764
1765 target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt,
1766 CPUMIPSState *env)
1767 {
1768 uint8_t tempD, tempC, tempB, tempA;
1769 uint16_t rsh, rsl, rth, rtl;
1770
1771 rsh = (rs & MIPSDSP_HI) >> 16;
1772 rsl = rs & MIPSDSP_LO;
1773 rth = (rt & MIPSDSP_HI) >> 16;
1774 rtl = rt & MIPSDSP_LO;
1775
1776 tempD = mipsdsp_sat8_reduce_precision(rsh, env);
1777 tempC = mipsdsp_sat8_reduce_precision(rsl, env);
1778 tempB = mipsdsp_sat8_reduce_precision(rth, env);
1779 tempA = mipsdsp_sat8_reduce_precision(rtl, env);
1780
1781 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1782 }
1783
1784 #if defined(TARGET_MIPS64)
1785 target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt,
1786 CPUMIPSState *env)
1787 {
1788 int i;
1789 uint16_t rs3, rs2, rs1, rs0;
1790 uint16_t rt3, rt2, rt1, rt0;
1791 uint8_t temp[8];
1792 uint64_t result;
1793
1794 result = 0;
1795
1796 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
1797 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
1798
1799 temp[7] = mipsdsp_sat8_reduce_precision(rs3, env);
1800 temp[6] = mipsdsp_sat8_reduce_precision(rs2, env);
1801 temp[5] = mipsdsp_sat8_reduce_precision(rs1, env);
1802 temp[4] = mipsdsp_sat8_reduce_precision(rs0, env);
1803 temp[3] = mipsdsp_sat8_reduce_precision(rt3, env);
1804 temp[2] = mipsdsp_sat8_reduce_precision(rt2, env);
1805 temp[1] = mipsdsp_sat8_reduce_precision(rt1, env);
1806 temp[0] = mipsdsp_sat8_reduce_precision(rt0, env);
1807
1808 for (i = 0; i < 8; i++) {
1809 result |= (uint64_t)temp[i] << (8 * i);
1810 }
1811
1812 return result;
1813 }
1814
1815 #define PRECEQ_PW(name, a, b) \
1816 target_ulong helper_preceq_pw_##name(target_ulong rt) \
1817 { \
1818 uint16_t tempB, tempA; \
1819 uint32_t tempBI, tempAI; \
1820 \
1821 tempB = (rt >> a) & MIPSDSP_LO; \
1822 tempA = (rt >> b) & MIPSDSP_LO; \
1823 \
1824 tempBI = (uint32_t)tempB << 16; \
1825 tempAI = (uint32_t)tempA << 16; \
1826 \
1827 return MIPSDSP_RETURN64_32(tempBI, tempAI); \
1828 }
1829
1830 PRECEQ_PW(qhl, 48, 32);
1831 PRECEQ_PW(qhr, 16, 0);
1832 PRECEQ_PW(qhla, 48, 16);
1833 PRECEQ_PW(qhra, 32, 0);
1834
1835 #undef PRECEQ_PW
1836
1837 #endif
1838
1839 #define PRECEQU_PH(name, a, b) \
1840 target_ulong helper_precequ_ph_##name(target_ulong rt) \
1841 { \
1842 uint16_t tempB, tempA; \
1843 \
1844 tempB = (rt >> a) & MIPSDSP_Q0; \
1845 tempA = (rt >> b) & MIPSDSP_Q0; \
1846 \
1847 tempB = tempB << 7; \
1848 tempA = tempA << 7; \
1849 \
1850 return MIPSDSP_RETURN32_16(tempB, tempA); \
1851 }
1852
1853 PRECEQU_PH(qbl, 24, 16);
1854 PRECEQU_PH(qbr, 8, 0);
1855 PRECEQU_PH(qbla, 24, 8);
1856 PRECEQU_PH(qbra, 16, 0);
1857
1858 #undef PRECEQU_PH
1859
1860 #if defined(TARGET_MIPS64)
1861 #define PRECEQU_QH(name, a, b, c, d) \
1862 target_ulong helper_precequ_qh_##name(target_ulong rt) \
1863 { \
1864 uint16_t tempD, tempC, tempB, tempA; \
1865 \
1866 tempD = (rt >> a) & MIPSDSP_Q0; \
1867 tempC = (rt >> b) & MIPSDSP_Q0; \
1868 tempB = (rt >> c) & MIPSDSP_Q0; \
1869 tempA = (rt >> d) & MIPSDSP_Q0; \
1870 \
1871 tempD = tempD << 7; \
1872 tempC = tempC << 7; \
1873 tempB = tempB << 7; \
1874 tempA = tempA << 7; \
1875 \
1876 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1877 }
1878
1879 PRECEQU_QH(obl, 56, 48, 40, 32);
1880 PRECEQU_QH(obr, 24, 16, 8, 0);
1881 PRECEQU_QH(obla, 56, 40, 24, 8);
1882 PRECEQU_QH(obra, 48, 32, 16, 0);
1883
1884 #undef PRECEQU_QH
1885
1886 #endif
1887
1888 #define PRECEU_PH(name, a, b) \
1889 target_ulong helper_preceu_ph_##name(target_ulong rt) \
1890 { \
1891 uint16_t tempB, tempA; \
1892 \
1893 tempB = (rt >> a) & MIPSDSP_Q0; \
1894 tempA = (rt >> b) & MIPSDSP_Q0; \
1895 \
1896 return MIPSDSP_RETURN32_16(tempB, tempA); \
1897 }
1898
1899 PRECEU_PH(qbl, 24, 16);
1900 PRECEU_PH(qbr, 8, 0);
1901 PRECEU_PH(qbla, 24, 8);
1902 PRECEU_PH(qbra, 16, 0);
1903
1904 #undef PRECEU_PH
1905
1906 #if defined(TARGET_MIPS64)
1907 #define PRECEU_QH(name, a, b, c, d) \
1908 target_ulong helper_preceu_qh_##name(target_ulong rt) \
1909 { \
1910 uint16_t tempD, tempC, tempB, tempA; \
1911 \
1912 tempD = (rt >> a) & MIPSDSP_Q0; \
1913 tempC = (rt >> b) & MIPSDSP_Q0; \
1914 tempB = (rt >> c) & MIPSDSP_Q0; \
1915 tempA = (rt >> d) & MIPSDSP_Q0; \
1916 \
1917 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1918 }
1919
1920 PRECEU_QH(obl, 56, 48, 40, 32);
1921 PRECEU_QH(obr, 24, 16, 8, 0);
1922 PRECEU_QH(obla, 56, 40, 24, 8);
1923 PRECEU_QH(obra, 48, 32, 16, 0);
1924
1925 #undef PRECEU_QH
1926
1927 #endif
1928
1929 /** DSP GPR-Based Shift Sub-class insns **/
1930 #define SHIFT_QB(name, func) \
1931 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \
1932 { \
1933 uint8_t rt3, rt2, rt1, rt0; \
1934 \
1935 sa = sa & 0x07; \
1936 \
1937 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1938 \
1939 rt3 = mipsdsp_##func(rt3, sa); \
1940 rt2 = mipsdsp_##func(rt2, sa); \
1941 rt1 = mipsdsp_##func(rt1, sa); \
1942 rt0 = mipsdsp_##func(rt0, sa); \
1943 \
1944 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1945 }
1946
1947 #define SHIFT_QB_ENV(name, func) \
1948 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\
1949 CPUMIPSState *env) \
1950 { \
1951 uint8_t rt3, rt2, rt1, rt0; \
1952 \
1953 sa = sa & 0x07; \
1954 \
1955 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1956 \
1957 rt3 = mipsdsp_##func(rt3, sa, env); \
1958 rt2 = mipsdsp_##func(rt2, sa, env); \
1959 rt1 = mipsdsp_##func(rt1, sa, env); \
1960 rt0 = mipsdsp_##func(rt0, sa, env); \
1961 \
1962 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1963 }
1964
1965 SHIFT_QB_ENV(shll, lshift8);
1966 SHIFT_QB(shrl, rshift_u8);
1967
1968 SHIFT_QB(shra, rashift8);
1969 SHIFT_QB(shra_r, rnd8_rashift);
1970
1971 #undef SHIFT_QB
1972 #undef SHIFT_QB_ENV
1973
1974 #if defined(TARGET_MIPS64)
1975 #define SHIFT_OB(name, func) \
1976 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \
1977 { \
1978 int i; \
1979 uint8_t rt_t[8]; \
1980 uint64_t temp; \
1981 \
1982 sa = sa & 0x07; \
1983 temp = 0; \
1984 \
1985 for (i = 0; i < 8; i++) { \
1986 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1987 rt_t[i] = mipsdsp_##func(rt_t[i], sa); \
1988 temp |= (uint64_t)rt_t[i] << (8 * i); \
1989 } \
1990 \
1991 return temp; \
1992 }
1993
1994 #define SHIFT_OB_ENV(name, func) \
1995 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \
1996 CPUMIPSState *env) \
1997 { \
1998 int i; \
1999 uint8_t rt_t[8]; \
2000 uint64_t temp; \
2001 \
2002 sa = sa & 0x07; \
2003 temp = 0; \
2004 \
2005 for (i = 0; i < 8; i++) { \
2006 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
2007 rt_t[i] = mipsdsp_##func(rt_t[i], sa, env); \
2008 temp |= (uint64_t)rt_t[i] << (8 * i); \
2009 } \
2010 \
2011 return temp; \
2012 }
2013
2014 SHIFT_OB_ENV(shll, lshift8);
2015 SHIFT_OB(shrl, rshift_u8);
2016
2017 SHIFT_OB(shra, rashift8);
2018 SHIFT_OB(shra_r, rnd8_rashift);
2019
2020 #undef SHIFT_OB
2021 #undef SHIFT_OB_ENV
2022
2023 #endif
2024
2025 #define SHIFT_PH(name, func) \
2026 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \
2027 CPUMIPSState *env) \
2028 { \
2029 uint16_t rth, rtl; \
2030 \
2031 sa = sa & 0x0F; \
2032 \
2033 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2034 \
2035 rth = mipsdsp_##func(rth, sa, env); \
2036 rtl = mipsdsp_##func(rtl, sa, env); \
2037 \
2038 return MIPSDSP_RETURN32_16(rth, rtl); \
2039 }
2040
2041 SHIFT_PH(shll, lshift16);
2042 SHIFT_PH(shll_s, sat16_lshift);
2043
2044 #undef SHIFT_PH
2045
2046 #if defined(TARGET_MIPS64)
2047 #define SHIFT_QH(name, func) \
2048 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \
2049 { \
2050 uint16_t rt3, rt2, rt1, rt0; \
2051 \
2052 sa = sa & 0x0F; \
2053 \
2054 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2055 \
2056 rt3 = mipsdsp_##func(rt3, sa); \
2057 rt2 = mipsdsp_##func(rt2, sa); \
2058 rt1 = mipsdsp_##func(rt1, sa); \
2059 rt0 = mipsdsp_##func(rt0, sa); \
2060 \
2061 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
2062 }
2063
2064 #define SHIFT_QH_ENV(name, func) \
2065 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \
2066 CPUMIPSState *env) \
2067 { \
2068 uint16_t rt3, rt2, rt1, rt0; \
2069 \
2070 sa = sa & 0x0F; \
2071 \
2072 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2073 \
2074 rt3 = mipsdsp_##func(rt3, sa, env); \
2075 rt2 = mipsdsp_##func(rt2, sa, env); \
2076 rt1 = mipsdsp_##func(rt1, sa, env); \
2077 rt0 = mipsdsp_##func(rt0, sa, env); \
2078 \
2079 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
2080 }
2081
2082 SHIFT_QH_ENV(shll, lshift16);
2083 SHIFT_QH_ENV(shll_s, sat16_lshift);
2084
2085 SHIFT_QH(shrl, rshift_u16);
2086 SHIFT_QH(shra, rashift16);
2087 SHIFT_QH(shra_r, rnd16_rashift);
2088
2089 #undef SHIFT_QH
2090 #undef SHIFT_QH_ENV
2091
2092 #endif
2093
2094 #define SHIFT_W(name, func) \
2095 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \
2096 { \
2097 uint32_t temp; \
2098 \
2099 sa = sa & 0x1F; \
2100 temp = mipsdsp_##func(rt, sa); \
2101 \
2102 return (target_long)(int32_t)temp; \
2103 }
2104
2105 #define SHIFT_W_ENV(name, func) \
2106 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \
2107 CPUMIPSState *env) \
2108 { \
2109 uint32_t temp; \
2110 \
2111 sa = sa & 0x1F; \
2112 temp = mipsdsp_##func(rt, sa, env); \
2113 \
2114 return (target_long)(int32_t)temp; \
2115 }
2116
2117 SHIFT_W_ENV(shll_s, sat32_lshift);
2118 SHIFT_W(shra_r, rnd32_rashift);
2119
2120 #undef SHIFT_W
2121 #undef SHIFT_W_ENV
2122
2123 #if defined(TARGET_MIPS64)
2124 #define SHIFT_PW(name, func) \
2125 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \
2126 { \
2127 uint32_t rt1, rt0; \
2128 \
2129 sa = sa & 0x1F; \
2130 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2131 \
2132 rt1 = mipsdsp_##func(rt1, sa); \
2133 rt0 = mipsdsp_##func(rt0, sa); \
2134 \
2135 return MIPSDSP_RETURN64_32(rt1, rt0); \
2136 }
2137
2138 #define SHIFT_PW_ENV(name, func) \
2139 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \
2140 CPUMIPSState *env) \
2141 { \
2142 uint32_t rt1, rt0; \
2143 \
2144 sa = sa & 0x1F; \
2145 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2146 \
2147 rt1 = mipsdsp_##func(rt1, sa, env); \
2148 rt0 = mipsdsp_##func(rt0, sa, env); \
2149 \
2150 return MIPSDSP_RETURN64_32(rt1, rt0); \
2151 }
2152
2153 SHIFT_PW_ENV(shll, lshift32);
2154 SHIFT_PW_ENV(shll_s, sat32_lshift);
2155
2156 SHIFT_PW(shra, rashift32);
2157 SHIFT_PW(shra_r, rnd32_rashift);
2158
2159 #undef SHIFT_PW
2160 #undef SHIFT_PW_ENV
2161
2162 #endif
2163
2164 #define SHIFT_PH(name, func) \
2165 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \
2166 { \
2167 uint16_t rth, rtl; \
2168 \
2169 sa = sa & 0x0F; \
2170 \
2171 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2172 \
2173 rth = mipsdsp_##func(rth, sa); \
2174 rtl = mipsdsp_##func(rtl, sa); \
2175 \
2176 return MIPSDSP_RETURN32_16(rth, rtl); \
2177 }
2178
2179 SHIFT_PH(shrl, rshift_u16);
2180 SHIFT_PH(shra, rashift16);
2181 SHIFT_PH(shra_r, rnd16_rashift);
2182
2183 #undef SHIFT_PH
2184
2185 /** DSP Multiply Sub-class insns **/
2186 /* Return value made up by two 16bits value.
2187 * FIXME give the macro a better name.
2188 */
2189 #define MUL_RETURN32_16_PH(name, func, \
2190 rsmov1, rsmov2, rsfilter, \
2191 rtmov1, rtmov2, rtfilter) \
2192 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2193 CPUMIPSState *env) \
2194 { \
2195 uint16_t rsB, rsA, rtB, rtA; \
2196 \
2197 rsB = (rs >> rsmov1) & rsfilter; \
2198 rsA = (rs >> rsmov2) & rsfilter; \
2199 rtB = (rt >> rtmov1) & rtfilter; \
2200 rtA = (rt >> rtmov2) & rtfilter; \
2201 \
2202 rsB = mipsdsp_##func(rsB, rtB, env); \
2203 rsA = mipsdsp_##func(rsA, rtA, env); \
2204 \
2205 return MIPSDSP_RETURN32_16(rsB, rsA); \
2206 }
2207
2208 MUL_RETURN32_16_PH(muleu_s_ph_qbl, mul_u8_u16, \
2209 24, 16, MIPSDSP_Q0, \
2210 16, 0, MIPSDSP_LO);
2211 MUL_RETURN32_16_PH(muleu_s_ph_qbr, mul_u8_u16, \
2212 8, 0, MIPSDSP_Q0, \
2213 16, 0, MIPSDSP_LO);
2214 MUL_RETURN32_16_PH(mulq_rs_ph, rndq15_mul_q15_q15, \
2215 16, 0, MIPSDSP_LO, \
2216 16, 0, MIPSDSP_LO);
2217 MUL_RETURN32_16_PH(mul_ph, mul_i16_i16, \
2218 16, 0, MIPSDSP_LO, \
2219 16, 0, MIPSDSP_LO);
2220 MUL_RETURN32_16_PH(mul_s_ph, sat16_mul_i16_i16, \
2221 16, 0, MIPSDSP_LO, \
2222 16, 0, MIPSDSP_LO);
2223 MUL_RETURN32_16_PH(mulq_s_ph, sat16_mul_q15_q15, \
2224 16, 0, MIPSDSP_LO, \
2225 16, 0, MIPSDSP_LO);
2226
2227 #undef MUL_RETURN32_16_PH
2228
2229 #define MUL_RETURN32_32_ph(name, func, movbits) \
2230 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2231 CPUMIPSState *env) \
2232 { \
2233 int16_t rsh, rth; \
2234 int32_t temp; \
2235 \
2236 rsh = (rs >> movbits) & MIPSDSP_LO; \
2237 rth = (rt >> movbits) & MIPSDSP_LO; \
2238 temp = mipsdsp_##func(rsh, rth, env); \
2239 \
2240 return (target_long)(int32_t)temp; \
2241 }
2242
2243 MUL_RETURN32_32_ph(muleq_s_w_phl, mul_q15_q15_overflowflag21, 16);
2244 MUL_RETURN32_32_ph(muleq_s_w_phr, mul_q15_q15_overflowflag21, 0);
2245
2246 #undef MUL_RETURN32_32_ph
2247
2248 #define MUL_VOID_PH(name, use_ac_env) \
2249 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2250 CPUMIPSState *env) \
2251 { \
2252 int16_t rsh, rsl, rth, rtl; \
2253 int32_t tempB, tempA; \
2254 int64_t acc, dotp; \
2255 \
2256 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2257 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2258 \
2259 if (use_ac_env == 1) { \
2260 tempB = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2261 tempA = mipsdsp_mul_q15_q15(ac, rsl, rtl, env); \
2262 } else { \
2263 tempB = mipsdsp_mul_u16_u16(rsh, rth); \
2264 tempA = mipsdsp_mul_u16_u16(rsl, rtl); \
2265 } \
2266 \
2267 dotp = (int64_t)tempB - (int64_t)tempA; \
2268 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2269 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2270 dotp = dotp + acc; \
2271 env->active_tc.HI[ac] = (target_long)(int32_t) \
2272 ((dotp & MIPSDSP_LHI) >> 32); \
2273 env->active_tc.LO[ac] = (target_long)(int32_t)(dotp & MIPSDSP_LLO); \
2274 }
2275
2276 MUL_VOID_PH(mulsaq_s_w_ph, 1);
2277 MUL_VOID_PH(mulsa_w_ph, 0);
2278
2279 #undef MUL_VOID_PH
2280
2281 #if defined(TARGET_MIPS64)
2282 #define MUL_RETURN64_16_QH(name, func, \
2283 rsmov1, rsmov2, rsmov3, rsmov4, rsfilter, \
2284 rtmov1, rtmov2, rtmov3, rtmov4, rtfilter) \
2285 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2286 CPUMIPSState *env) \
2287 { \
2288 uint16_t rs3, rs2, rs1, rs0; \
2289 uint16_t rt3, rt2, rt1, rt0; \
2290 uint16_t tempD, tempC, tempB, tempA; \
2291 \
2292 rs3 = (rs >> rsmov1) & rsfilter; \
2293 rs2 = (rs >> rsmov2) & rsfilter; \
2294 rs1 = (rs >> rsmov3) & rsfilter; \
2295 rs0 = (rs >> rsmov4) & rsfilter; \
2296 rt3 = (rt >> rtmov1) & rtfilter; \
2297 rt2 = (rt >> rtmov2) & rtfilter; \
2298 rt1 = (rt >> rtmov3) & rtfilter; \
2299 rt0 = (rt >> rtmov4) & rtfilter; \
2300 \
2301 tempD = mipsdsp_##func(rs3, rt3, env); \
2302 tempC = mipsdsp_##func(rs2, rt2, env); \
2303 tempB = mipsdsp_##func(rs1, rt1, env); \
2304 tempA = mipsdsp_##func(rs0, rt0, env); \
2305 \
2306 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
2307 }
2308
2309 MUL_RETURN64_16_QH(muleu_s_qh_obl, mul_u8_u16, \
2310 56, 48, 40, 32, MIPSDSP_Q0, \
2311 48, 32, 16, 0, MIPSDSP_LO);
2312 MUL_RETURN64_16_QH(muleu_s_qh_obr, mul_u8_u16, \
2313 24, 16, 8, 0, MIPSDSP_Q0, \
2314 48, 32, 16, 0, MIPSDSP_LO);
2315 MUL_RETURN64_16_QH(mulq_rs_qh, rndq15_mul_q15_q15, \
2316 48, 32, 16, 0, MIPSDSP_LO, \
2317 48, 32, 16, 0, MIPSDSP_LO);
2318
2319 #undef MUL_RETURN64_16_QH
2320
2321 #define MUL_RETURN64_32_QH(name, \
2322 rsmov1, rsmov2, \
2323 rtmov1, rtmov2) \
2324 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2325 CPUMIPSState *env) \
2326 { \
2327 uint16_t rsB, rsA; \
2328 uint16_t rtB, rtA; \
2329 uint32_t tempB, tempA; \
2330 \
2331 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2332 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2333 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2334 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2335 \
2336 tempB = mipsdsp_mul_q15_q15(5, rsB, rtB, env); \
2337 tempA = mipsdsp_mul_q15_q15(5, rsA, rtA, env); \
2338 \
2339 return ((uint64_t)tempB << 32) | (uint64_t)tempA; \
2340 }
2341
2342 MUL_RETURN64_32_QH(muleq_s_pw_qhl, 48, 32, 48, 32);
2343 MUL_RETURN64_32_QH(muleq_s_pw_qhr, 16, 0, 16, 0);
2344
2345 #undef MUL_RETURN64_32_QH
2346
2347 void helper_mulsaq_s_w_qh(target_ulong rs, target_ulong rt, uint32_t ac,
2348 CPUMIPSState *env)
2349 {
2350 int16_t rs3, rs2, rs1, rs0;
2351 int16_t rt3, rt2, rt1, rt0;
2352 int32_t tempD, tempC, tempB, tempA;
2353 int64_t acc[2];
2354 int64_t temp[2];
2355 int64_t temp_sum;
2356
2357 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
2358 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
2359
2360 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env);
2361 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env);
2362 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env);
2363 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env);
2364
2365 temp[0] = ((int32_t)tempD - (int32_t)tempC) +
2366 ((int32_t)tempB - (int32_t)tempA);
2367 temp[0] = (int64_t)(temp[0] << 30) >> 30;
2368 if (((temp[0] >> 33) & 0x01) == 0) {
2369 temp[1] = 0x00;
2370 } else {
2371 temp[1] = ~0ull;
2372 }
2373
2374 acc[0] = env->active_tc.LO[ac];
2375 acc[1] = env->active_tc.HI[ac];
2376
2377 temp_sum = acc[0] + temp[0];
2378 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2379 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2380 acc[1] += 1;
2381 }
2382 acc[0] = temp_sum;
2383 acc[1] += temp[1];
2384
2385 env->active_tc.HI[ac] = acc[1];
2386 env->active_tc.LO[ac] = acc[0];
2387 }
2388 #endif
2389
2390 #define DP_QB(name, func, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2391 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2392 CPUMIPSState *env) \
2393 { \
2394 uint8_t rs3, rs2; \
2395 uint8_t rt3, rt2; \
2396 uint16_t tempB, tempA; \
2397 uint64_t tempC, dotp; \
2398 \
2399 rs3 = (rs >> rsmov1) & MIPSDSP_Q0; \
2400 rs2 = (rs >> rsmov2) & MIPSDSP_Q0; \
2401 rt3 = (rt >> rtmov1) & MIPSDSP_Q0; \
2402 rt2 = (rt >> rtmov2) & MIPSDSP_Q0; \
2403 tempB = mipsdsp_##func(rs3, rt3); \
2404 tempA = mipsdsp_##func(rs2, rt2); \
2405 dotp = (int64_t)tempB + (int64_t)tempA; \
2406 if (is_add) { \
2407 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2408 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2409 + dotp; \
2410 } else { \
2411 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2412 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2413 - dotp; \
2414 } \
2415 \
2416 env->active_tc.HI[ac] = (target_long)(int32_t) \
2417 ((tempC & MIPSDSP_LHI) >> 32); \
2418 env->active_tc.LO[ac] = (target_long)(int32_t)(tempC & MIPSDSP_LLO); \
2419 }
2420
2421 DP_QB(dpau_h_qbl, mul_u8_u8, 1, 24, 16, 24, 16);
2422 DP_QB(dpau_h_qbr, mul_u8_u8, 1, 8, 0, 8, 0);
2423 DP_QB(dpsu_h_qbl, mul_u8_u8, 0, 24, 16, 24, 16);
2424 DP_QB(dpsu_h_qbr, mul_u8_u8, 0, 8, 0, 8, 0);
2425
2426 #undef DP_QB
2427
2428 #if defined(TARGET_MIPS64)
2429 #define DP_OB(name, add_sub, \
2430 rsmov1, rsmov2, rsmov3, rsmov4, \
2431 rtmov1, rtmov2, rtmov3, rtmov4) \
2432 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2433 CPUMIPSState *env) \
2434 { \
2435 uint8_t rsD, rsC, rsB, rsA; \
2436 uint8_t rtD, rtC, rtB, rtA; \
2437 uint16_t tempD, tempC, tempB, tempA; \
2438 uint64_t temp[2]; \
2439 uint64_t acc[2]; \
2440 uint64_t temp_sum; \
2441 \
2442 temp[0] = 0; \
2443 temp[1] = 0; \
2444 \
2445 rsD = (rs >> rsmov1) & MIPSDSP_Q0; \
2446 rsC = (rs >> rsmov2) & MIPSDSP_Q0; \
2447 rsB = (rs >> rsmov3) & MIPSDSP_Q0; \
2448 rsA = (rs >> rsmov4) & MIPSDSP_Q0; \
2449 rtD = (rt >> rtmov1) & MIPSDSP_Q0; \
2450 rtC = (rt >> rtmov2) & MIPSDSP_Q0; \
2451 rtB = (rt >> rtmov3) & MIPSDSP_Q0; \
2452 rtA = (rt >> rtmov4) & MIPSDSP_Q0; \
2453 \
2454 tempD = mipsdsp_mul_u8_u8(rsD, rtD); \
2455 tempC = mipsdsp_mul_u8_u8(rsC, rtC); \
2456 tempB = mipsdsp_mul_u8_u8(rsB, rtB); \
2457 tempA = mipsdsp_mul_u8_u8(rsA, rtA); \
2458 \
2459 temp[0] = (uint64_t)tempD + (uint64_t)tempC + \
2460 (uint64_t)tempB + (uint64_t)tempA; \
2461 \
2462 acc[0] = env->active_tc.LO[ac]; \
2463 acc[1] = env->active_tc.HI[ac]; \
2464 \
2465 if (add_sub) { \
2466 temp_sum = acc[0] + temp[0]; \
2467 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2468 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2469 acc[1] += 1; \
2470 } \
2471 temp[0] = temp_sum; \
2472 temp[1] = acc[1] + temp[1]; \
2473 } else { \
2474 temp_sum = acc[0] - temp[0]; \
2475 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2476 acc[1] -= 1; \
2477 } \
2478 temp[0] = temp_sum; \
2479 temp[1] = acc[1] - temp[1]; \
2480 } \
2481 \
2482 env->active_tc.HI[ac] = temp[1]; \
2483 env->active_tc.LO[ac] = temp[0]; \
2484 }
2485
2486 DP_OB(dpau_h_obl, 1, 56, 48, 40, 32, 56, 48, 40, 32);
2487 DP_OB(dpau_h_obr, 1, 24, 16, 8, 0, 24, 16, 8, 0);
2488 DP_OB(dpsu_h_obl, 0, 56, 48, 40, 32, 56, 48, 40, 32);
2489 DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0);
2490
2491 #undef DP_OB
2492 #endif
2493
2494 #define DP_NOFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2495 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2496 CPUMIPSState *env) \
2497 { \
2498 int16_t rsB, rsA, rtB, rtA; \
2499 int32_t tempA, tempB; \
2500 int64_t acc; \
2501 \
2502 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2503 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2504 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2505 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2506 \
2507 tempB = (int32_t)rsB * (int32_t)rtB; \
2508 tempA = (int32_t)rsA * (int32_t)rtA; \
2509 \
2510 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2511 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2512 \
2513 if (is_add) { \
2514 acc = acc + ((int64_t)tempB + (int64_t)tempA); \
2515 } else { \
2516 acc = acc - ((int64_t)tempB + (int64_t)tempA); \
2517 } \
2518 \
2519 env->active_tc.HI[ac] = (target_long)(int32_t)((acc & MIPSDSP_LHI) >> 32); \
2520 env->active_tc.LO[ac] = (target_long)(int32_t)(acc & MIPSDSP_LLO); \
2521 }
2522
2523 DP_NOFUNC_PH(dpa_w_ph, 1, 16, 0, 16, 0);
2524 DP_NOFUNC_PH(dpax_w_ph, 1, 16, 0, 0, 16);
2525 DP_NOFUNC_PH(dps_w_ph, 0, 16, 0, 16, 0);
2526 DP_NOFUNC_PH(dpsx_w_ph, 0, 16, 0, 0, 16);
2527 #undef DP_NOFUNC_PH
2528
2529 #define DP_HASFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2530 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2531 CPUMIPSState *env) \
2532 { \
2533 int16_t rsB, rsA, rtB, rtA; \
2534 int32_t tempB, tempA; \
2535 int64_t acc, dotp; \
2536 \
2537 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2538 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2539 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2540 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2541 \
2542 tempB = mipsdsp_mul_q15_q15(ac, rsB, rtB, env); \
2543 tempA = mipsdsp_mul_q15_q15(ac, rsA, rtA, env); \
2544 \
2545 dotp = (int64_t)tempB + (int64_t)tempA; \
2546 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2547 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2548 \
2549 if (is_add) { \
2550 acc = acc + dotp; \
2551 } else { \
2552 acc = acc - dotp; \
2553 } \
2554 \
2555 env->active_tc.HI[ac] = (target_long)(int32_t) \
2556 ((acc & MIPSDSP_LHI) >> 32); \
2557 env->active_tc.LO[ac] = (target_long)(int32_t) \
2558 (acc & MIPSDSP_LLO); \
2559 }
2560
2561 DP_HASFUNC_PH(dpaq_s_w_ph, 1, 16, 0, 16, 0);
2562 DP_HASFUNC_PH(dpaqx_s_w_ph, 1, 16, 0, 0, 16);
2563 DP_HASFUNC_PH(dpsq_s_w_ph, 0, 16, 0, 16, 0);
2564 DP_HASFUNC_PH(dpsqx_s_w_ph, 0, 16, 0, 0, 16);
2565
2566 #undef DP_HASFUNC_PH
2567
2568 #define DP_128OPERATION_PH(name, is_add) \
2569 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2570 CPUMIPSState *env) \
2571 { \
2572 int16_t rsh, rsl, rth, rtl; \
2573 int32_t tempB, tempA, tempC62_31, tempC63; \
2574 int64_t acc, dotp, tempC; \
2575 \
2576 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2577 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2578 \
2579 tempB = mipsdsp_mul_q15_q15(ac, rsh, rtl, env); \
2580 tempA = mipsdsp_mul_q15_q15(ac, rsl, rth, env); \
2581 \
2582 dotp = (int64_t)tempB + (int64_t)tempA; \
2583 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2584 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2585 if (is_add) { \
2586 tempC = acc + dotp; \
2587 } else { \
2588 tempC = acc - dotp; \
2589 } \
2590 tempC63 = (tempC >> 63) & 0x01; \
2591 tempC62_31 = (tempC >> 31) & 0xFFFFFFFF; \
2592 \
2593 if ((tempC63 == 0) && (tempC62_31 != 0x00000000)) { \
2594 tempC = 0x7FFFFFFF; \
2595 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2596 } \
2597 \
2598 if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) { \
2599 tempC = (int64_t)(int32_t)0x80000000; \
2600 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2601 } \
2602 \
2603 env->active_tc.HI[ac] = (target_long)(int32_t) \
2604 ((tempC & MIPSDSP_LHI) >> 32); \
2605 env->active_tc.LO[ac] = (target_long)(int32_t) \
2606 (tempC & MIPSDSP_LLO); \
2607 }
2608
2609 DP_128OPERATION_PH(dpaqx_sa_w_ph, 1);
2610 DP_128OPERATION_PH(dpsqx_sa_w_ph, 0);
2611
2612 #undef DP_128OPERATION_HP
2613
2614 #if defined(TARGET_MIPS64)
2615 #define DP_QH(name, is_add, use_ac_env) \
2616 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2617 CPUMIPSState *env) \
2618 { \
2619 int32_t rs3, rs2, rs1, rs0; \
2620 int32_t rt3, rt2, rt1, rt0; \
2621 int32_t tempD, tempC, tempB, tempA; \
2622 int64_t acc[2]; \
2623 int64_t temp[2]; \
2624 int64_t temp_sum; \
2625 \
2626 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
2627 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2628 \
2629 if (use_ac_env) { \
2630 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env); \
2631 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env); \
2632 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env); \
2633 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env); \
2634 } else { \
2635 tempD = mipsdsp_mul_u16_u16(rs3, rt3); \
2636 tempC = mipsdsp_mul_u16_u16(rs2, rt2); \
2637 tempB = mipsdsp_mul_u16_u16(rs1, rt1); \
2638 tempA = mipsdsp_mul_u16_u16(rs0, rt0); \
2639 } \
2640 \
2641 temp[0] = (int64_t)tempD + (int64_t)tempC + \
2642 (int64_t)tempB + (int64_t)tempA; \
2643 \
2644 if (temp[0] >= 0) { \
2645 temp[1] = 0; \
2646 } else { \
2647 temp[1] = ~0ull; \
2648 } \
2649 \
2650 acc[1] = env->active_tc.HI[ac]; \
2651 acc[0] = env->active_tc.LO[ac]; \
2652 \
2653 if (is_add) { \
2654 temp_sum = acc[0] + temp[0]; \
2655 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2656 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2657 acc[1] = acc[1] + 1; \
2658 } \
2659 temp[0] = temp_sum; \
2660 temp[1] = acc[1] + temp[1]; \
2661 } else { \
2662 temp_sum = acc[0] - temp[0]; \
2663 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2664 acc[1] = acc[1] - 1; \
2665 } \
2666 temp[0] = temp_sum; \
2667 temp[1] = acc[1] - temp[1]; \
2668 } \
2669 \
2670 env->active_tc.HI[ac] = temp[1]; \
2671 env->active_tc.LO[ac] = temp[0]; \
2672 }
2673
2674 DP_QH(dpa_w_qh, 1, 0);
2675 DP_QH(dpaq_s_w_qh, 1, 1);
2676 DP_QH(dps_w_qh, 0, 0);
2677 DP_QH(dpsq_s_w_qh, 0, 1);
2678
2679 #undef DP_QH
2680
2681 #endif
2682
2683 #define DP_L_W(name, is_add) \
2684 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2685 CPUMIPSState *env) \
2686 { \
2687 int32_t temp63; \
2688 int64_t dotp, acc; \
2689 uint64_t temp; \
2690 \
2691 dotp = mipsdsp_mul_q31_q31(ac, rs, rt, env); \
2692 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2693 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2694 if (!is_add) { \
2695 dotp = -dotp; \
2696 } \
2697 \
2698 temp = acc + dotp; \
2699 if (MIPSDSP_OVERFLOW((uint64_t)acc, (uint64_t)dotp, temp, \
2700 (0x01ull << 63))) { \
2701 temp63 = (temp >> 63) & 0x01; \
2702 if (temp63 == 1) { \
2703 temp = (0x01ull << 63) - 1; \
2704 } else { \
2705 temp = 0x01ull << 63; \
2706 } \
2707 \
2708 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2709 } \
2710 \
2711 env->active_tc.HI[ac] = (target_long)(int32_t) \
2712 ((temp & MIPSDSP_LHI) >> 32); \
2713 env->active_tc.LO[ac] = (target_long)(int32_t) \
2714 (temp & MIPSDSP_LLO); \
2715 }
2716
2717 DP_L_W(dpaq_sa_l_w, 1);
2718 DP_L_W(dpsq_sa_l_w, 0);
2719
2720 #undef DP_L_W
2721
2722 #if defined(TARGET_MIPS64)
2723 #define DP_L_PW(name, func) \
2724 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2725 CPUMIPSState *env) \
2726 { \
2727 int32_t rs1, rs0; \
2728 int32_t rt1, rt0; \
2729 int64_t tempB[2], tempA[2]; \
2730 int64_t temp[2]; \
2731 int64_t acc[2]; \
2732 int64_t temp_sum; \
2733 \
2734 temp[0] = 0; \
2735 temp[1] = 0; \
2736 \
2737 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2738 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2739 \
2740 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env); \
2741 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env); \
2742 \
2743 if (tempB[0] >= 0) { \
2744 tempB[1] = 0x00; \
2745 } else { \
2746 tempB[1] = ~0ull; \
2747 } \
2748 \
2749 if (tempA[0] >= 0) { \
2750 tempA[1] = 0x00; \
2751 } else { \
2752 tempA[1] = ~0ull; \
2753 } \
2754 \
2755 temp_sum = tempB[0] + tempA[0]; \
2756 if (((uint64_t)temp_sum < (uint64_t)tempB[0]) && \
2757 ((uint64_t)temp_sum < (uint64_t)tempA[0])) { \
2758 temp[1] += 1; \
2759 } \
2760 temp[0] = temp_sum; \
2761 temp[1] += tempB[1] + tempA[1]; \
2762 \
2763 mipsdsp_##func(acc, ac, temp, env); \
2764 \
2765 env->active_tc.HI[ac] = acc[1]; \
2766 env->active_tc.LO[ac] = acc[0]; \
2767 }
2768
2769 DP_L_PW(dpaq_sa_l_pw, sat64_acc_add_q63);
2770 DP_L_PW(dpsq_sa_l_pw, sat64_acc_sub_q63);
2771
2772 #undef DP_L_PW
2773
2774 void helper_mulsaq_s_l_pw(target_ulong rs, target_ulong rt, uint32_t ac,
2775 CPUMIPSState *env)
2776 {
2777 int32_t rs1, rs0;
2778 int32_t rt1, rt0;
2779 int64_t tempB[2], tempA[2];
2780 int64_t temp[2];
2781 int64_t acc[2];
2782 int64_t temp_sum;
2783
2784 rs1 = (rs >> 32) & MIPSDSP_LLO;
2785 rs0 = rs & MIPSDSP_LLO;
2786 rt1 = (rt >> 32) & MIPSDSP_LLO;
2787 rt0 = rt & MIPSDSP_LLO;
2788
2789 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env);
2790 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env);
2791
2792 if (tempB[0] >= 0) {
2793 tempB[1] = 0x00;
2794 } else {
2795 tempB[1] = ~0ull;
2796 }
2797
2798 if (tempA[0] >= 0) {
2799 tempA[1] = 0x00;
2800 } else {
2801 tempA[1] = ~0ull;
2802 }
2803
2804 acc[0] = env->active_tc.LO[ac];
2805 acc[1] = env->active_tc.HI[ac];
2806
2807 temp_sum = tempB[0] - tempA[0];
2808 if ((uint64_t)temp_sum > (uint64_t)tempB[0]) {
2809 tempB[1] -= 1;
2810 }
2811 temp[0] = temp_sum;
2812 temp[1] = tempB[1] - tempA[1];
2813
2814 if ((temp[1] & 0x01) == 0) {
2815 temp[1] = 0x00;
2816 } else {
2817 temp[1] = ~0ull;
2818 }
2819
2820 temp_sum = acc[0] + temp[0];
2821 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2822 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2823 acc[1] += 1;
2824 }
2825 acc[0] = temp_sum;
2826 acc[1] += temp[1];
2827
2828 env->active_tc.HI[ac] = acc[1];
2829 env->active_tc.LO[ac] = acc[0];
2830 }
2831 #endif
2832
2833 #define MAQ_S_W(name, mov) \
2834 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2835 CPUMIPSState *env) \
2836 { \
2837 int16_t rsh, rth; \
2838 int32_t tempA; \
2839 int64_t tempL, acc; \
2840 \
2841 rsh = (rs >> mov) & MIPSDSP_LO; \
2842 rth = (rt >> mov) & MIPSDSP_LO; \
2843 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2844 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2845 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2846 tempL = (int64_t)tempA + acc; \
2847 env->active_tc.HI[ac] = (target_long)(int32_t) \
2848 ((tempL & MIPSDSP_LHI) >> 32); \
2849 env->active_tc.LO[ac] = (target_long)(int32_t) \
2850 (tempL & MIPSDSP_LLO); \
2851 }
2852
2853 MAQ_S_W(maq_s_w_phl, 16);
2854 MAQ_S_W(maq_s_w_phr, 0);
2855
2856 #undef MAQ_S_W
2857
2858 #define MAQ_SA_W(name, mov) \
2859 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2860 CPUMIPSState *env) \
2861 { \
2862 int16_t rsh, rth; \
2863 int32_t tempA; \
2864 \
2865 rsh = (rs >> mov) & MIPSDSP_LO; \
2866 rth = (rt >> mov) & MIPSDSP_LO; \
2867 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2868 tempA = mipsdsp_sat32_acc_q31(ac, tempA, env); \
2869 \
2870 env->active_tc.HI[ac] = (target_long)(int32_t)(((int64_t)tempA & \
2871 MIPSDSP_LHI) >> 32); \
2872 env->active_tc.LO[ac] = (target_long)(int32_t)((int64_t)tempA & \
2873 MIPSDSP_LLO); \
2874 }
2875
2876 MAQ_SA_W(maq_sa_w_phl, 16);
2877 MAQ_SA_W(maq_sa_w_phr, 0);
2878
2879 #undef MAQ_SA_W
2880
2881 #define MULQ_W(name, addvar) \
2882 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2883 CPUMIPSState *env) \
2884 { \
2885 uint32_t rs_t, rt_t; \
2886 int32_t tempI; \
2887 int64_t tempL; \
2888 \
2889 rs_t = rs & MIPSDSP_LLO; \
2890 rt_t = rt & MIPSDSP_LLO; \
2891 \
2892 if ((rs_t == 0x80000000) && (rt_t == 0x80000000)) { \
2893 tempL = 0x7FFFFFFF00000000ull; \
2894 set_DSPControl_overflow_flag(1, 21, env); \
2895 } else { \
2896 tempL = ((int64_t)rs_t * (int64_t)rt_t) << 1; \
2897 tempL += addvar; \
2898 } \
2899 tempI = (tempL & MIPSDSP_LHI) >> 32; \
2900 \
2901 return (target_long)(int32_t)tempI; \
2902 }
2903
2904 MULQ_W(mulq_s_w, 0);
2905 MULQ_W(mulq_rs_w, 0x80000000ull);
2906
2907 #undef MULQ_W
2908
2909 #if defined(TARGET_MIPS64)
2910
2911 #define MAQ_S_W_QH(name, mov) \
2912 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2913 CPUMIPSState *env) \
2914 { \
2915 int16_t rs_t, rt_t; \
2916 int32_t temp_mul; \
2917 int64_t temp[2]; \
2918 int64_t acc[2]; \
2919 int64_t temp_sum; \
2920 \
2921 temp[0] = 0; \
2922 temp[1] = 0; \
2923 \
2924 rs_t = (rs >> mov) & MIPSDSP_LO; \
2925 rt_t = (rt >> mov) & MIPSDSP_LO; \
2926 temp_mul = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2927 \
2928 temp[0] = (int64_t)temp_mul; \
2929 if (temp[0] >= 0) { \
2930 temp[1] = 0x00; \
2931 } else { \
2932 temp[1] = ~0ull; \
2933 } \
2934 \
2935 acc[0] = env->active_tc.LO[ac]; \
2936 acc[1] = env->active_tc.HI[ac]; \
2937 \
2938 temp_sum = acc[0] + temp[0]; \
2939 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2940 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2941 acc[1] += 1; \
2942 } \
2943 acc[0] = temp_sum; \
2944 acc[1] += temp[1]; \
2945 \
2946 env->active_tc.HI[ac] = acc[1]; \
2947 env->active_tc.LO[ac] = acc[0]; \
2948 }
2949
2950 MAQ_S_W_QH(maq_s_w_qhll, 48);
2951 MAQ_S_W_QH(maq_s_w_qhlr, 32);
2952 MAQ_S_W_QH(maq_s_w_qhrl, 16);
2953 MAQ_S_W_QH(maq_s_w_qhrr, 0);
2954
2955 #undef MAQ_S_W_QH
2956
2957 #define MAQ_SA_W(name, mov) \
2958 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2959 CPUMIPSState *env) \
2960 { \
2961 int16_t rs_t, rt_t; \
2962 int32_t temp; \
2963 int64_t acc[2]; \
2964 \
2965 rs_t = (rs >> mov) & MIPSDSP_LO; \
2966 rt_t = (rt >> mov) & MIPSDSP_LO; \
2967 temp = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2968 temp = mipsdsp_sat32_acc_q31(ac, temp, env); \
2969 \
2970 acc[0] = (int64_t)(int32_t)temp; \
2971 if (acc[0] >= 0) { \
2972 acc[1] = 0x00; \
2973 } else { \
2974 acc[1] = ~0ull; \
2975 } \
2976 \
2977 env->active_tc.HI[ac] = acc[1]; \
2978 env->active_tc.LO[ac] = acc[0]; \
2979 }
2980
2981 MAQ_SA_W(maq_sa_w_qhll, 48);
2982 MAQ_SA_W(maq_sa_w_qhlr, 32);
2983 MAQ_SA_W(maq_sa_w_qhrl, 16);
2984 MAQ_SA_W(maq_sa_w_qhrr, 0);
2985
2986 #undef MAQ_SA_W
2987
2988 #define MAQ_S_L_PW(name, mov) \
2989 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2990 CPUMIPSState *env) \
2991 { \
2992 int32_t rs_t, rt_t; \
2993 int64_t temp[2]; \
2994 int64_t acc[2]; \
2995 int64_t temp_sum; \
2996 \
2997 temp[0] = 0; \
2998 temp[1] = 0; \
2999 \
3000 rs_t = (rs >> mov) & MIPSDSP_LLO; \
3001 rt_t = (rt >> mov) & MIPSDSP_LLO; \
3002 \
3003 temp[0] = mipsdsp_mul_q31_q31(ac, rs_t, rt_t, env); \
3004 if (temp[0] >= 0) { \
3005 temp[1] = 0x00; \
3006 } else { \
3007 temp[1] = ~0ull; \
3008 } \
3009 \
3010 acc[0] = env->active_tc.LO[ac]; \
3011 acc[1] = env->active_tc.HI[ac]; \
3012 \
3013 temp_sum = acc[0] + temp[0]; \
3014 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
3015 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
3016 acc[1] += 1; \
3017 } \
3018 acc[0] = temp_sum; \
3019 acc[1] += temp[1]; \
3020 \
3021 env->active_tc.HI[ac] = acc[1]; \
3022 env->active_tc.LO[ac] = acc[0]; \
3023 }
3024
3025 MAQ_S_L_PW(maq_s_l_pwl, 32);
3026 MAQ_S_L_PW(maq_s_l_pwr, 0);
3027
3028 #undef MAQ_S_L_PW
3029
3030 #define DM_OPERATE(name, func, is_add, sigext) \
3031 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
3032 CPUMIPSState *env) \
3033 { \
3034 int32_t rs1, rs0; \
3035 int32_t rt1, rt0; \
3036 int64_t tempBL[2], tempAL[2]; \
3037 int64_t acc[2]; \
3038 int64_t temp[2]; \
3039 int64_t temp_sum; \
3040 \
3041 temp[0] = 0x00; \
3042 temp[1] = 0x00; \
3043 \
3044 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
3045 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
3046 \
3047 if (sigext) { \
3048 tempBL[0] = (int64_t)mipsdsp_##func(rs1, rt1); \
3049 tempAL[0] = (int64_t)mipsdsp_##func(rs0, rt0); \
3050 \
3051 if (tempBL[0] >= 0) { \
3052 tempBL[1] = 0x0; \
3053 } else { \
3054 tempBL[1] = ~0ull; \
3055 } \
3056 \
3057 if (tempAL[0] >= 0) { \
3058 tempAL[1] = 0x0; \
3059 } else { \
3060 tempAL[1] = ~0ull; \
3061 } \
3062 } else { \
3063 tempBL[0] = mipsdsp_##func(rs1, rt1); \
3064 tempAL[0] = mipsdsp_##func(rs0, rt0); \
3065 tempBL[1] = 0; \
3066 tempAL[1] = 0; \
3067 } \
3068 \
3069 acc[1] = env->active_tc.HI[ac]; \
3070 acc[0] = env->active_tc.LO[ac]; \
3071 \
3072 temp_sum = tempBL[0] + tempAL[0]; \
3073 if (((uint64_t)temp_sum < (uint64_t)tempBL[0]) && \
3074 ((uint64_t)temp_sum < (uint64_t)tempAL[0])) { \
3075 temp[1] += 1; \
3076 } \
3077 temp[0] = temp_sum; \
3078 temp[1] += tempBL[1] + tempAL[1]; \
3079 \
3080 if (is_add) { \
3081 temp_sum = acc[0] + temp[0]; \
3082 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
3083 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
3084 acc[1] += 1; \
3085 } \
3086 temp[0] = temp_sum; \
3087 temp[1] = acc[1] + temp[1]; \
3088 } else { \
3089 temp_sum = acc[0] - temp[0]; \
3090 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
3091 acc[1] -= 1; \
3092 } \
3093 temp[0] = temp_sum; \
3094 temp[1] = acc[1] - temp[1]; \
3095 } \
3096 \
3097 env->active_tc.HI[ac] = temp[1]; \
3098 env->active_tc.LO[ac] = temp[0]; \
3099 }
3100
3101 DM_OPERATE(dmadd, mul_i32_i32, 1, 1);
3102 DM_OPERATE(dmaddu, mul_u32_u32, 1, 0);
3103 DM_OPERATE(dmsub, mul_i32_i32, 0, 1);
3104 DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
3105 #undef DM_OPERATE
3106 #endif
3107
3108 /** DSP Bit/Manipulation Sub-class insns **/
3109 target_ulong helper_bitrev(target_ulong rt)
3110 {
3111 int32_t temp;
3112 uint32_t rd;
3113 int i;
3114
3115 temp = rt & MIPSDSP_LO;
3116 rd = 0;
3117 for (i = 0; i < 16; i++) {
3118 rd = (rd << 1) | (temp & 1);
3119 temp = temp >> 1;
3120 }
3121
3122 return (target_ulong)rd;
3123 }
3124
3125 #define BIT_INSV(name, posfilter, sizefilter, ret_type) \
3126 target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
3127 target_ulong rt) \
3128 { \
3129 uint32_t pos, size, msb, lsb; \
3130 target_ulong filter; \
3131 target_ulong temp, temprs, temprt; \
3132 target_ulong dspc; \
3133 \
3134 dspc = env->active_tc.DSPControl; \
3135 \
3136 pos = dspc & posfilter; \
3137 size = (dspc >> 7) & sizefilter; \
3138 \
3139 msb = pos + size - 1; \
3140 lsb = pos; \
3141 \
3142 if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
3143 return rt; \
3144 } \
3145 \
3146 filter = ((int32_t)0x01 << size) - 1; \
3147 filter = filter << pos; \
3148 temprs = (rs << pos) & filter; \
3149 temprt = rt & ~filter; \
3150 temp = temprs | temprt; \
3151 \
3152 return (target_long)(ret_type)temp; \
3153 }
3154
3155 BIT_INSV(insv, 0x1F, 0x1F, int32_t);
3156 #ifdef TARGET_MIPS64
3157 BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
3158 #endif
3159
3160 #undef BIT_INSV
3161
3162
3163 /** DSP Compare-Pick Sub-class insns **/
3164 #define CMP_HAS_RET(name, func, split_num, filter, bit_size) \
3165 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
3166 { \
3167 uint32_t rs_t, rt_t; \
3168 uint8_t cc; \
3169 uint32_t temp = 0; \
3170 int i; \
3171 \
3172 for (i = 0; i < split_num; i++) { \
3173 rs_t = (rs >> (bit_size * i)) & filter; \
3174 rt_t = (rt >> (bit_size * i)) & filter; \
3175 cc = mipsdsp_##func(rs_t, rt_t); \
3176 temp |= cc << i; \
3177 } \
3178 \
3179 return (target_ulong)temp; \
3180 }
3181
3182 CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3183 CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3184 CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3185
3186 #ifdef TARGET_MIPS64
3187 CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3188 CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3189 CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3190 #endif
3191
3192 #undef CMP_HAS_RET
3193
3194
3195 #define CMP_NO_RET(name, func, split_num, filter, bit_size) \
3196 void helper_##name(target_ulong rs, target_ulong rt, \
3197 CPUMIPSState *env) \
3198 { \
3199 int##bit_size##_t rs_t, rt_t; \
3200 int##bit_size##_t flag = 0; \
3201 int##bit_size##_t cc; \
3202 int i; \
3203 \
3204 for (i = 0; i < split_num; i++) { \
3205 rs_t = (rs >> (bit_size * i)) & filter; \
3206 rt_t = (rt >> (bit_size * i)) & filter; \
3207 \
3208 cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t); \
3209 flag |= cc << i; \
3210 } \
3211 \
3212 set_DSPControl_24(flag, split_num, env); \
3213 }
3214
3215 CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3216 CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3217 CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3218
3219 CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16);
3220 CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16);
3221 CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16);
3222
3223 #ifdef TARGET_MIPS64
3224 CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3225 CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3226 CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3227
3228 CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16);
3229 CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16);
3230 CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16);
3231
3232 CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32);
3233 CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32);
3234 CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32);
3235 #endif
3236 #undef CMP_NO_RET
3237
3238 #if defined(TARGET_MIPS64)
3239
3240 #define CMPGDU_OB(name) \
3241 target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \
3242 CPUMIPSState *env) \
3243 { \
3244 int i; \
3245 uint8_t rs_t, rt_t; \
3246 uint32_t cond; \
3247 \
3248 cond = 0; \
3249 \
3250 for (i = 0; i < 8; i++) { \
3251 rs_t = (rs >> (8 * i)) & MIPSDSP_Q0; \
3252 rt_t = (rt >> (8 * i)) & MIPSDSP_Q0; \
3253 \
3254 if (mipsdsp_cmpu_##name(rs_t, rt_t)) { \
3255 cond |= 0x01 << i; \
3256 } \
3257 } \
3258 \
3259 set_DSPControl_24(cond, 8, env); \
3260 \
3261 return (uint64_t)cond; \
3262 }
3263
3264 CMPGDU_OB(eq)
3265 CMPGDU_OB(lt)
3266 CMPGDU_OB(le)
3267 #undef CMPGDU_OB
3268 #endif
3269
3270 #define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \
3271 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3272 CPUMIPSState *env) \
3273 { \
3274 uint32_t rs_t, rt_t; \
3275 uint32_t cc; \
3276 target_ulong dsp; \
3277 int i; \
3278 target_ulong result = 0; \
3279 \
3280 dsp = env->active_tc.DSPControl; \
3281 for (i = 0; i < split_num; i++) { \
3282 rs_t = (rs >> (bit_size * i)) & filter; \
3283 rt_t = (rt >> (bit_size * i)) & filter; \
3284 cc = (dsp >> (24 + i)) & 0x01; \
3285 cc = cc == 1 ? rs_t : rt_t; \
3286 \
3287 result |= (target_ulong)cc << (bit_size * i); \
3288 } \
3289 \
3290 if (ret32bit) { \
3291 result = (target_long)(int32_t)(result & MIPSDSP_LLO); \
3292 } \
3293 \
3294 return result; \
3295 }
3296
3297 PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1);
3298 PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1);
3299
3300 #ifdef TARGET_MIPS64
3301 PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0);
3302 PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0);
3303 PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
3304 #endif
3305 #undef PICK_INSN
3306
3307 #define APPEND_INSN(name, ret_32) \
3308 target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \
3309 { \
3310 target_ulong temp; \
3311 \
3312 if (ret_32) { \
3313 temp = ((rt & MIPSDSP_LLO) << sa) | \
3314 ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \
3315 temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \
3316 } else { \
3317 temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \
3318 } \
3319 \
3320 return temp; \
3321 }
3322
3323 APPEND_INSN(append, 1);
3324 #ifdef TARGET_MIPS64
3325 APPEND_INSN(dappend, 0);
3326 #endif
3327 #undef APPEND_INSN
3328
3329 #define PREPEND_INSN(name, or_val, ret_32) \
3330 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3331 uint32_t sa) \
3332 { \
3333 sa |= or_val; \
3334 \
3335 if (1) { \
3336 return (target_long)(int32_t)(uint32_t) \
3337 (((rs & MIPSDSP_LLO) << (32 - sa)) | \
3338 ((rt & MIPSDSP_LLO) >> sa)); \
3339 } else { \
3340 return (rs << (64 - sa)) | (rt >> sa); \
3341 } \
3342 }
3343
3344 PREPEND_INSN(prepend, 0, 1);
3345 #ifdef TARGET_MIPS64
3346 PREPEND_INSN(prependw, 0, 0);
3347 PREPEND_INSN(prependd, 0x20, 0);
3348 #endif
3349 #undef PREPEND_INSN
3350
3351 #define BALIGN_INSN(name, filter, ret32) \
3352 target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \
3353 { \
3354 bp = bp & 0x03; \
3355 \
3356 if ((bp & 1) == 0) { \
3357 return rt; \
3358 } else { \
3359 if (ret32) { \
3360 return (target_long)(int32_t)((rt << (8 * bp)) | \
3361 (rs >> (8 * (4 - bp)))); \
3362 } else { \
3363 return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \
3364 } \
3365 } \
3366 }
3367
3368 BALIGN_INSN(balign, 0x03, 1);
3369 #if defined(TARGET_MIPS64)
3370 BALIGN_INSN(dbalign, 0x07, 0);
3371 #endif
3372 #undef BALIGN_INSN
3373
3374 target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
3375 {
3376 uint32_t rsl, rth;
3377
3378 rsl = rs & MIPSDSP_LO;
3379 rth = (rt & MIPSDSP_HI) >> 16;
3380
3381 return (target_long)(int32_t)((rsl << 16) | rth);
3382 }
3383
3384 #if defined(TARGET_MIPS64)
3385 target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt)
3386 {
3387 uint32_t rs0, rt1;
3388
3389 rs0 = rs & MIPSDSP_LLO;
3390 rt1 = (rt >> 32) & MIPSDSP_LLO;
3391
3392 return ((uint64_t)rs0 << 32) | (uint64_t)rt1;
3393 }
3394 #endif
3395
3396 /** DSP Accumulator and DSPControl Access Sub-class insns **/
3397 target_ulong helper_extr_w(target_ulong ac, target_ulong shift,
3398 CPUMIPSState *env)
3399 {
3400 int32_t tempI;
3401 int64_t tempDL[2];
3402
3403 shift = shift & 0x1F;
3404
3405 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3406 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3407 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3408 set_DSPControl_overflow_flag(1, 23, env);
3409 }
3410
3411 tempI = (tempDL[0] >> 1) & MIPSDSP_LLO;
3412
3413 tempDL[0] += 1;
3414 if (tempDL[0] == 0) {
3415 tempDL[1] += 1;
3416 }
3417
3418 if ((!(tempDL[1] == 0 && (tempDL[0] & MIPSDSP_LHI) == 0x00)) &&
3419 (!(tempDL[1] == 1 && (tempDL[0] & MIPSDSP_LHI) == MIPSDSP_LHI))) {
3420 set_DSPControl_overflow_flag(1, 23, env);
3421 }
3422
3423 return (target_long)tempI;
3424 }
3425
3426 target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift,
3427 CPUMIPSState *env)
3428 {
3429 int64_t tempDL[2];
3430
3431 shift = shift & 0x1F;
3432
3433 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3434 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3435 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3436 set_DSPControl_overflow_flag(1, 23, env);
3437 }
3438
3439 tempDL[0] += 1;
3440 if (tempDL[0] == 0) {
3441 tempDL[1] += 1;
3442 }
3443
3444 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3445 (tempDL[1] != 1 && (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3446 set_DSPControl_overflow_flag(1, 23, env);
3447 }
3448
3449 return (target_long)(int32_t)(tempDL[0] >> 1);
3450 }
3451
3452 target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift,
3453 CPUMIPSState *env)
3454 {
3455 int32_t tempI, temp64;
3456 int64_t tempDL[2];
3457
3458 shift = shift & 0x1F;
3459
3460 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3461 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3462 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3463 set_DSPControl_overflow_flag(1, 23, env);
3464 }
3465 tempDL[0] += 1;
3466 if (tempDL[0] == 0) {
3467 tempDL[1] += 1;
3468 }
3469 tempI = tempDL[0] >> 1;
3470
3471 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3472 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3473 temp64 = tempDL[1];
3474 if (temp64 == 0) {
3475 tempI = 0x7FFFFFFF;
3476 } else {
3477 tempI = 0x80000000;
3478 }
3479 set_DSPControl_overflow_flag(1, 23, env);
3480 }
3481
3482 return (target_long)tempI;
3483 }
3484
3485 #if defined(TARGET_MIPS64)
3486 target_ulong helper_dextr_w(target_ulong ac, target_ulong shift,
3487 CPUMIPSState *env)
3488 {
3489 uint64_t temp[3];
3490
3491 shift = shift & 0x3F;
3492
3493 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3494
3495 return (int64_t)(int32_t)(temp[0] >> 1);
3496 }
3497
3498 target_ulong helper_dextr_r_w(target_ulong ac, target_ulong shift,
3499 CPUMIPSState *env)
3500 {
3501 uint64_t temp[3];
3502 uint32_t temp128;
3503
3504 shift = shift & 0x3F;
3505 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3506
3507 temp[0] += 1;
3508 if (temp[0] == 0) {
3509 temp[1] += 1;
3510 if (temp[1] == 0) {
3511 temp[2] += 1;
3512 }
3513 }
3514
3515 temp128 = temp[2] & 0x01;
3516
3517 if ((temp128 != 0 || temp[1] != 0) &&
3518 (temp128 != 1 || temp[1] != ~0ull)) {
3519 set_DSPControl_overflow_flag(1, 23, env);
3520 }
3521
3522 return (int64_t)(int32_t)(temp[0] >> 1);
3523 }
3524
3525 target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift,
3526 CPUMIPSState *env)
3527 {
3528 uint64_t temp[3];
3529 uint32_t temp128;
3530
3531 shift = shift & 0x3F;
3532 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3533
3534 temp[0] += 1;
3535 if (temp[0] == 0) {
3536 temp[1] += 1;
3537 if (temp[1] == 0) {
3538 temp[2] += 1;
3539 }
3540 }
3541
3542 temp128 = temp[2] & 0x01;
3543
3544 if ((temp128 != 0 || temp[1] != 0) &&
3545 (temp128 != 1 || temp[1] != ~0ull)) {
3546 if (temp128 == 0) {
3547 temp[0] = 0x0FFFFFFFF;
3548 } else {
3549 temp[0] = 0x0100000000ULL;
3550 }
3551 set_DSPControl_overflow_flag(1, 23, env);
3552 }
3553
3554 return (int64_t)(int32_t)(temp[0] >> 1);
3555 }
3556
3557 target_ulong helper_dextr_l(target_ulong ac, target_ulong shift,
3558 CPUMIPSState *env)
3559 {
3560 uint64_t temp[3];
3561 target_ulong result;
3562
3563 shift = shift & 0x3F;
3564
3565 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3566 result = (temp[1] << 63) | (temp[0] >> 1);
3567
3568 return result;
3569 }
3570
3571 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift,
3572 CPUMIPSState *env)
3573 {
3574 uint64_t temp[3];
3575 uint32_t temp128;
3576 target_ulong result;
3577
3578 shift = shift & 0x3F;
3579 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3580
3581 temp[0] += 1;
3582 if (temp[0] == 0) {
3583 temp[1] += 1;
3584 if (temp[1] == 0) {
3585 temp[2] += 1;
3586 }
3587 }
3588
3589 temp128 = temp[2] & 0x01;
3590
3591 if ((temp128 != 0 || temp[1] != 0) &&
3592 (temp128 != 1 || temp[1] != ~0ull)) {
3593 set_DSPControl_overflow_flag(1, 23, env);
3594 }
3595
3596 result = (temp[1] << 63) | (temp[0] >> 1);
3597
3598 return result;
3599 }
3600
3601 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift,
3602 CPUMIPSState *env)
3603 {
3604 uint64_t temp[3];
3605 uint32_t temp128;
3606 target_ulong result;
3607
3608 shift = shift & 0x3F;
3609 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3610
3611 temp[0] += 1;
3612 if (temp[0] == 0) {
3613 temp[1] += 1;
3614 if (temp[1] == 0) {
3615 temp[2] += 1;
3616 }
3617 }
3618
3619 temp128 = temp[2] & 0x01;
3620
3621 if ((temp128 != 0 || temp[1] != 0) &&
3622 (temp128 != 1 || temp[1] != ~0ull)) {
3623 if (temp128 == 0) {
3624 temp[1] &= ~0x00ull - 1;
3625 temp[0] |= ~0x00ull - 1;
3626 } else {
3627 temp[1] |= 0x01;
3628 temp[0] &= 0x01;
3629 }
3630 set_DSPControl_overflow_flag(1, 23, env);
3631 }
3632 result = (temp[1] << 63) | (temp[0] >> 1);
3633
3634 return result;
3635 }
3636 #endif
3637
3638 target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift,
3639 CPUMIPSState *env)
3640 {
3641 int64_t temp, acc;
3642
3643 shift = shift & 0x1F;
3644
3645 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
3646 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
3647
3648 temp = acc >> shift;
3649
3650 if (temp > (int64_t)0x7FFF) {
3651 temp = 0x00007FFF;
3652 set_DSPControl_overflow_flag(1, 23, env);
3653 } else if (temp < (int64_t)0xFFFFFFFFFFFF8000ULL) {
3654 temp = 0xFFFF8000;
3655 set_DSPControl_overflow_flag(1, 23, env);
3656 }
3657
3658 return (target_long)(int32_t)(temp & 0xFFFFFFFF);
3659 }
3660
3661
3662 #if defined(TARGET_MIPS64)
3663 target_ulong helper_dextr_s_h(target_ulong ac, target_ulong shift,
3664 CPUMIPSState *env)
3665 {
3666 int64_t temp[2];
3667 uint32_t temp127;
3668
3669 shift = shift & 0x1F;
3670
3671 mipsdsp_rashift_acc((uint64_t *)temp, ac, shift, env);
3672
3673 temp127 = (temp[1] >> 63) & 0x01;
3674
3675 if ((temp127 == 0) && (temp[1] > 0 || temp[0] > 32767)) {
3676 temp[0] &= 0xFFFF0000;
3677 temp[0] |= 0x00007FFF;
3678 set_DSPControl_overflow_flag(1, 23, env);
3679 } else if ((temp127 == 1) &&
3680 (temp[1] < 0xFFFFFFFFFFFFFFFFll
3681 || temp[0] < 0xFFFFFFFFFFFF1000ll)) {
3682 temp[0] &= 0xFFFF0000;
3683 temp[0] |= 0x00008000;
3684 set_DSPControl_overflow_flag(1, 23, env);
3685 }
3686
3687 return (int64_t)(int16_t)(temp[0] & MIPSDSP_LO);
3688 }
3689
3690 #endif
3691
3692 target_ulong helper_extp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3693 {
3694 int32_t start_pos;
3695 int sub;
3696 uint32_t temp;
3697 uint64_t acc;
3698
3699 size = size & 0x1F;
3700
3701 temp = 0;
3702 start_pos = get_DSPControl_pos(env);
3703 sub = start_pos - (size + 1);
3704 if (sub >= -1) {
3705 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3706 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3707 temp = (acc >> (start_pos - size)) &
3708 (((uint32_t)0x01 << (size + 1)) - 1);
3709 set_DSPControl_efi(0, env);
3710 } else {
3711 set_DSPControl_efi(1, env);
3712 }
3713
3714 return (target_ulong)temp;
3715 }
3716
3717 target_ulong helper_extpdp(target_ulong ac, target_ulong size,
3718 CPUMIPSState *env)
3719 {
3720 int32_t start_pos;
3721 int sub;
3722 uint32_t temp;
3723 uint64_t acc;
3724
3725 size = size & 0x1F;
3726 temp = 0;
3727 start_pos = get_DSPControl_pos(env);
3728 sub = start_pos - (size + 1);
3729 if (sub >= -1) {
3730 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3731 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3732 temp = (acc >> (start_pos - size)) &
3733 (((uint32_t)0x01 << (size + 1)) - 1);
3734
3735 set_DSPControl_pos(start_pos - (size + 1), env);
3736 set_DSPControl_efi(0, env);
3737 } else {
3738 set_DSPControl_efi(1, env);
3739 }
3740
3741 return (target_ulong)temp;
3742 }
3743
3744
3745 #if defined(TARGET_MIPS64)
3746 target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3747 {
3748 int start_pos;
3749 int len;
3750 int sub;
3751 uint64_t tempB, tempA;
3752 uint64_t temp;
3753
3754 temp = 0;
3755
3756 size = size & 0x3F;
3757 start_pos = get_DSPControl_pos(env);
3758 len = start_pos - size;
3759 tempB = env->active_tc.HI[ac];
3760 tempA = env->active_tc.LO[ac];
3761
3762 sub = start_pos - (size + 1);
3763
3764 if (sub >= -1) {
3765 temp = (tempB << (64 - len)) | (tempA >> len);
3766 temp = temp & ((0x01 << (size + 1)) - 1);
3767 set_DSPControl_efi(0, env);
3768 } else {
3769 set_DSPControl_efi(1, env);
3770 }
3771
3772 return temp;
3773 }
3774
3775 target_ulong helper_dextpdp(target_ulong ac, target_ulong size,
3776 CPUMIPSState *env)
3777 {
3778 int start_pos;
3779 int len;
3780 int sub;
3781 uint64_t tempB, tempA;
3782 uint64_t temp;
3783
3784 temp = 0;
3785 size = size & 0x3F;
3786 start_pos = get_DSPControl_pos(env);
3787 len = start_pos - size;
3788 tempB = env->active_tc.HI[ac];
3789 tempA = env->active_tc.LO[ac];
3790
3791 sub = start_pos - (size + 1);
3792
3793 if (sub >= -1) {
3794 temp = (tempB << (64 - len)) | (tempA >> len);
3795 temp = temp & ((0x01 << (size + 1)) - 1);
3796 set_DSPControl_pos(sub, env);
3797 set_DSPControl_efi(0, env);
3798 } else {
3799 set_DSPControl_efi(1, env);
3800 }
3801
3802 return temp;
3803 }
3804
3805 #endif
3806
3807 void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3808 {
3809 int8_t rs5_0;
3810 uint64_t temp, acc;
3811
3812 rs5_0 = rs & 0x3F;
3813 rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
3814
3815 if (unlikely(rs5_0 == 0)) {
3816 return;
3817 }
3818
3819 acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
3820 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3821
3822 if (rs5_0 > 0) {
3823 temp = acc >> rs5_0;
3824 } else {
3825 temp = acc << -rs5_0;
3826 }
3827
3828 env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);
3829 env->active_tc.LO[ac] = (target_ulong)(int32_t)(temp & MIPSDSP_LLO);
3830 }
3831
3832 #if defined(TARGET_MIPS64)
3833 void helper_dshilo(target_ulong shift, target_ulong ac, CPUMIPSState *env)
3834 {
3835 int8_t shift_t;
3836 uint64_t tempB, tempA;
3837
3838 shift_t = (int8_t)(shift << 1) >> 1;
3839
3840 tempB = env->active_tc.HI[ac];
3841 tempA = env->active_tc.LO[ac];
3842
3843 if (shift_t != 0) {
3844 if (shift_t >= 0) {
3845 tempA = (tempB << (64 - shift_t)) | (tempA >> shift_t);
3846 tempB = tempB >> shift_t;
3847 } else {
3848 shift_t = -shift_t;
3849 tempB = (tempB << shift_t) | (tempA >> (64 - shift_t));
3850 tempA = tempA << shift_t;
3851 }
3852 }
3853
3854 env->active_tc.HI[ac] = tempB;
3855 env->active_tc.LO[ac] = tempA;
3856 }
3857
3858 #endif
3859 void helper_mthlip(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3860 {
3861 int32_t tempA, tempB, pos;
3862
3863 tempA = rs;
3864 tempB = env->active_tc.LO[ac];
3865 env->active_tc.HI[ac] = (target_long)tempB;
3866 env->active_tc.LO[ac] = (target_long)tempA;
3867 pos = get_DSPControl_pos(env);
3868
3869 if (pos > 32) {
3870 return;
3871 } else {
3872 set_DSPControl_pos(pos + 32, env);
3873 }
3874 }
3875
3876 #if defined(TARGET_MIPS64)
3877 void helper_dmthlip(target_ulong rs, target_ulong ac, CPUMIPSState *env)
3878 {
3879 uint8_t ac_t;
3880 uint8_t pos;
3881 uint64_t tempB, tempA;
3882
3883 ac_t = ac & 0x3;
3884
3885 tempA = rs;
3886 tempB = env->active_tc.LO[ac_t];
3887
3888 env->active_tc.HI[ac_t] = tempB;
3889 env->active_tc.LO[ac_t] = tempA;
3890
3891 pos = get_DSPControl_pos(env);
3892
3893 if (pos <= 64) {
3894 pos = pos + 64;
3895 set_DSPControl_pos(pos, env);
3896 }
3897 }
3898 #endif
3899
3900 void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
3901 {
3902 uint8_t mask[6];
3903 uint8_t i;
3904 uint32_t newbits, overwrite;
3905 target_ulong dsp;
3906
3907 newbits = 0x00;
3908 overwrite = 0xFFFFFFFF;
3909 dsp = env->active_tc.DSPControl;
3910
3911 for (i = 0; i < 6; i++) {
3912 mask[i] = (mask_num >> i) & 0x01;
3913 }
3914
3915 if (mask[0] == 1) {
3916 #if defined(TARGET_MIPS64)
3917 overwrite &= 0xFFFFFF80;
3918 newbits &= 0xFFFFFF80;
3919 newbits |= 0x0000007F & rs;
3920 #else
3921 overwrite &= 0xFFFFFFC0;
3922 newbits &= 0xFFFFFFC0;
3923 newbits |= 0x0000003F & rs;
3924 #endif
3925 }
3926
3927 if (mask[1] == 1) {
3928 overwrite &= 0xFFFFE07F;
3929 newbits &= 0xFFFFE07F;
3930 newbits |= 0x00001F80 & rs;
3931 }
3932
3933 if (mask[2] == 1) {
3934 overwrite &= 0xFFFFDFFF;
3935 newbits &= 0xFFFFDFFF;
3936 newbits |= 0x00002000 & rs;
3937 }
3938
3939 if (mask[3] == 1) {
3940 overwrite &= 0xFF00FFFF;
3941 newbits &= 0xFF00FFFF;
3942 newbits |= 0x00FF0000 & rs;
3943 }
3944
3945 if (mask[4] == 1) {
3946 overwrite &= 0x00FFFFFF;
3947 newbits &= 0x00FFFFFF;
3948 #if defined(TARGET_MIPS64)
3949 newbits |= 0xFF000000 & rs;
3950 #else
3951 newbits |= 0x0F000000 & rs;
3952 #endif
3953 }
3954
3955 if (mask[5] == 1) {
3956 overwrite &= 0xFFFFBFFF;
3957 newbits &= 0xFFFFBFFF;
3958 newbits |= 0x00004000 & rs;
3959 }
3960
3961 dsp = dsp & overwrite;
3962 dsp = dsp | newbits;
3963 env->active_tc.DSPControl = dsp;
3964 }
3965
3966 target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env)
3967 {
3968 uint8_t mask[6];
3969 uint32_t ruler, i;
3970 target_ulong temp;
3971 target_ulong dsp;
3972
3973 ruler = 0x01;
3974 for (i = 0; i < 6; i++) {
3975 mask[i] = (masknum & ruler) >> i ;
3976 ruler = ruler << 1;
3977 }
3978
3979 temp = 0x00;
3980 dsp = env->active_tc.DSPControl;
3981
3982 if (mask[0] == 1) {
3983 #if defined(TARGET_MIPS64)
3984 temp |= dsp & 0x7F;
3985 #else
3986 temp |= dsp & 0x3F;
3987 #endif
3988 }
3989
3990 if (mask[1] == 1) {
3991 temp |= dsp & 0x1F80;
3992 }
3993
3994 if (mask[2] == 1) {
3995 temp |= dsp & 0x2000;
3996 }
3997
3998 if (mask[3] == 1) {
3999 temp |= dsp & 0x00FF0000;
4000 }
4001
4002 if (mask[4] == 1) {
4003 #if defined(TARGET_MIPS64)
4004 temp |= dsp & 0xFF000000;
4005 #else
4006 temp |= dsp & 0x0F000000;
4007 #endif
4008 }
4009
4010 if (mask[5] == 1) {
4011 temp |= dsp & 0x4000;
4012 }
4013
4014 return temp;
4015 }
4016
4017
4018 #undef MIPSDSP_LHI
4019 #undef MIPSDSP_LLO
4020 #undef MIPSDSP_HI
4021 #undef MIPSDSP_LO
4022 #undef MIPSDSP_Q3
4023 #undef MIPSDSP_Q2
4024 #undef MIPSDSP_Q1
4025 #undef MIPSDSP_Q0
4026
4027 #undef MIPSDSP_SPLIT32_8
4028 #undef MIPSDSP_SPLIT32_16
4029
4030 #undef MIPSDSP_RETURN32
4031 #undef MIPSDSP_RETURN32_8
4032 #undef MIPSDSP_RETURN32_16
4033
4034 #ifdef TARGET_MIPS64
4035 #undef MIPSDSP_SPLIT64_16
4036 #undef MIPSDSP_SPLIT64_32
4037 #undef MIPSDSP_RETURN64_16
4038 #undef MIPSDSP_RETURN64_32
4039 #endif
AR7 emulation for QEMU