2 * Luminary Micro Stellaris Ethernet Controller
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
12 #include "hw/sysbus.h"
13 #include "migration/vmstate.h"
16 #include "qemu/module.h"
19 //#define DEBUG_STELLARIS_ENET 1
21 #ifdef DEBUG_STELLARIS_ENET
22 #define DPRINTF(fmt, ...) \
23 do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
24 #define BADF(fmt, ...) \
25 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
27 #define DPRINTF(fmt, ...) do {} while(0)
28 #define BADF(fmt, ...) \
29 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
32 #define SE_INT_RX 0x01
33 #define SE_INT_TXER 0x02
34 #define SE_INT_TXEMP 0x04
35 #define SE_INT_FOV 0x08
36 #define SE_INT_RXER 0x10
37 #define SE_INT_MD 0x20
38 #define SE_INT_PHY 0x40
40 #define SE_RCTL_RXEN 0x01
41 #define SE_RCTL_AMUL 0x02
42 #define SE_RCTL_PRMS 0x04
43 #define SE_RCTL_BADCRC 0x08
44 #define SE_RCTL_RSTFIFO 0x10
46 #define SE_TCTL_TXEN 0x01
47 #define SE_TCTL_PADEN 0x02
48 #define SE_TCTL_CRC 0x04
49 #define SE_TCTL_DUPLEX 0x08
51 #define TYPE_STELLARIS_ENET "stellaris_enet"
52 #define STELLARIS_ENET(obj) \
53 OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET)
58 } StellarisEnetRxFrame
;
61 SysBusDevice parent_obj
;
74 uint8_t tx_fifo
[2048];
75 /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
76 We implement a full 31 packet fifo. */
77 StellarisEnetRxFrame rx
[31];
78 uint32_t rx_fifo_offset
;
84 } stellaris_enet_state
;
86 static const VMStateDescription vmstate_rx_frame
= {
87 .name
= "stellaris_enet/rx_frame",
89 .minimum_version_id
= 1,
90 .fields
= (VMStateField
[]) {
91 VMSTATE_UINT8_ARRAY(data
, StellarisEnetRxFrame
, 2048),
92 VMSTATE_UINT32(len
, StellarisEnetRxFrame
),
97 static int stellaris_enet_post_load(void *opaque
, int version_id
)
99 stellaris_enet_state
*s
= opaque
;
102 /* Sanitize inbound state. Note that next_packet is an index but
103 * np is a size; hence their valid upper bounds differ.
105 if (s
->next_packet
>= ARRAY_SIZE(s
->rx
)) {
109 if (s
->np
> ARRAY_SIZE(s
->rx
)) {
113 for (i
= 0; i
< ARRAY_SIZE(s
->rx
); i
++) {
114 if (s
->rx
[i
].len
> ARRAY_SIZE(s
->rx
[i
].data
)) {
119 if (s
->rx_fifo_offset
> ARRAY_SIZE(s
->rx
[0].data
) - 4) {
123 if (s
->tx_fifo_len
> ARRAY_SIZE(s
->tx_fifo
)) {
130 static const VMStateDescription vmstate_stellaris_enet
= {
131 .name
= "stellaris_enet",
133 .minimum_version_id
= 2,
134 .post_load
= stellaris_enet_post_load
,
135 .fields
= (VMStateField
[]) {
136 VMSTATE_UINT32(ris
, stellaris_enet_state
),
137 VMSTATE_UINT32(im
, stellaris_enet_state
),
138 VMSTATE_UINT32(rctl
, stellaris_enet_state
),
139 VMSTATE_UINT32(tctl
, stellaris_enet_state
),
140 VMSTATE_UINT32(thr
, stellaris_enet_state
),
141 VMSTATE_UINT32(mctl
, stellaris_enet_state
),
142 VMSTATE_UINT32(mdv
, stellaris_enet_state
),
143 VMSTATE_UINT32(mtxd
, stellaris_enet_state
),
144 VMSTATE_UINT32(mrxd
, stellaris_enet_state
),
145 VMSTATE_UINT32(np
, stellaris_enet_state
),
146 VMSTATE_UINT32(tx_fifo_len
, stellaris_enet_state
),
147 VMSTATE_UINT8_ARRAY(tx_fifo
, stellaris_enet_state
, 2048),
148 VMSTATE_STRUCT_ARRAY(rx
, stellaris_enet_state
, 31, 1,
149 vmstate_rx_frame
, StellarisEnetRxFrame
),
150 VMSTATE_UINT32(rx_fifo_offset
, stellaris_enet_state
),
151 VMSTATE_UINT32(next_packet
, stellaris_enet_state
),
152 VMSTATE_END_OF_LIST()
156 static void stellaris_enet_update(stellaris_enet_state
*s
)
158 qemu_set_irq(s
->irq
, (s
->ris
& s
->im
) != 0);
161 /* Return the data length of the packet currently being assembled
164 static inline int stellaris_txpacket_datalen(stellaris_enet_state
*s
)
166 return s
->tx_fifo
[0] | (s
->tx_fifo
[1] << 8);
169 /* Return true if the packet currently in the TX FIFO is complete,
170 * ie the FIFO holds enough bytes for the data length, ethernet header,
171 * payload and optionally CRC.
173 static inline bool stellaris_txpacket_complete(stellaris_enet_state
*s
)
175 int framelen
= stellaris_txpacket_datalen(s
);
177 if (!(s
->tctl
& SE_TCTL_CRC
)) {
180 /* Cover the corner case of a 2032 byte payload with auto-CRC disabled:
181 * this requires more bytes than will fit in the FIFO. It's not totally
182 * clear how the h/w handles this, but if using threshold-based TX
183 * it will definitely try to transmit something.
185 framelen
= MIN(framelen
, ARRAY_SIZE(s
->tx_fifo
));
186 return s
->tx_fifo_len
>= framelen
;
189 /* Return true if the TX FIFO threshold is enabled and the FIFO
190 * has filled enough to reach it.
192 static inline bool stellaris_tx_thr_reached(stellaris_enet_state
*s
)
194 return (s
->thr
< 0x3f &&
195 (s
->tx_fifo_len
>= 4 * (s
->thr
* 8 + 1)));
198 /* Send the packet currently in the TX FIFO */
199 static void stellaris_enet_send(stellaris_enet_state
*s
)
201 int framelen
= stellaris_txpacket_datalen(s
);
203 /* Ethernet header is in the FIFO but not in the datacount.
204 * We don't implement explicit CRC, so just ignore any
205 * CRC value in the FIFO.
208 if ((s
->tctl
& SE_TCTL_PADEN
) && framelen
< 60) {
209 memset(&s
->tx_fifo
[framelen
+ 2], 0, 60 - framelen
);
212 /* This MIN will have no effect unless the FIFO data is corrupt
213 * (eg bad data from an incoming migration); otherwise the check
214 * on the datalen at the start of writing the data into the FIFO
215 * will have caught this. Silently write a corrupt half-packet,
216 * which is what the hardware does in FIFO underrun situations.
218 framelen
= MIN(framelen
, ARRAY_SIZE(s
->tx_fifo
) - 2);
219 qemu_send_packet(qemu_get_queue(s
->nic
), s
->tx_fifo
+ 2, framelen
);
221 s
->ris
|= SE_INT_TXEMP
;
222 stellaris_enet_update(s
);
223 DPRINTF("Done TX\n");
226 /* TODO: Implement MAC address filtering. */
227 static ssize_t
stellaris_enet_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
229 stellaris_enet_state
*s
= qemu_get_nic_opaque(nc
);
234 if ((s
->rctl
& SE_RCTL_RXEN
) == 0)
240 DPRINTF("Received packet len=%zu\n", size
);
241 n
= s
->next_packet
+ s
->np
;
245 if (size
>= sizeof(s
->rx
[n
].data
) - 6) {
246 /* If the packet won't fit into the
247 * emulated 2K RAM, this is reported
248 * as a FIFO overrun error.
250 s
->ris
|= SE_INT_FOV
;
251 stellaris_enet_update(s
);
256 s
->rx
[n
].len
= size
+ 6;
259 *(p
++) = (size
+ 6) >> 8;
260 memcpy (p
, buf
, size
);
262 crc
= crc32(~0, buf
, size
);
267 /* Clear the remaining bytes in the last word. */
268 if ((size
& 3) != 2) {
269 memset(p
, 0, (6 - size
) & 3);
273 stellaris_enet_update(s
);
278 static int stellaris_enet_can_receive(stellaris_enet_state
*s
)
283 static uint64_t stellaris_enet_read(void *opaque
, hwaddr offset
,
286 stellaris_enet_state
*s
= (stellaris_enet_state
*)opaque
;
291 DPRINTF("IRQ status %02x\n", s
->ris
);
295 case 0x08: /* RCTL */
297 case 0x0c: /* TCTL */
299 case 0x10: /* DATA */
304 BADF("RX underflow\n");
308 rx_fifo
= s
->rx
[s
->next_packet
].data
+ s
->rx_fifo_offset
;
310 val
= rx_fifo
[0] | (rx_fifo
[1] << 8) | (rx_fifo
[2] << 16)
311 | (rx_fifo
[3] << 24);
312 s
->rx_fifo_offset
+= 4;
313 if (s
->rx_fifo_offset
>= s
->rx
[s
->next_packet
].len
) {
314 s
->rx_fifo_offset
= 0;
316 if (s
->next_packet
>= 31)
319 DPRINTF("RX done np=%d\n", s
->np
);
320 if (!s
->np
&& stellaris_enet_can_receive(s
)) {
321 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
327 return s
->conf
.macaddr
.a
[0] | (s
->conf
.macaddr
.a
[1] << 8)
328 | (s
->conf
.macaddr
.a
[2] << 16)
329 | ((uint32_t)s
->conf
.macaddr
.a
[3] << 24);
331 return s
->conf
.macaddr
.a
[4] | (s
->conf
.macaddr
.a
[5] << 8);
334 case 0x20: /* MCTL */
338 case 0x28: /* MADD */
340 case 0x2c: /* MTXD */
342 case 0x30: /* MRXD */
348 case 0x3c: /* Undocumented: Timestamp? */
351 qemu_log_mask(LOG_GUEST_ERROR
, "stellaris_enet_rd%d: Illegal register"
352 " 0x02%" HWADDR_PRIx
"\n",
358 static void stellaris_enet_write(void *opaque
, hwaddr offset
,
359 uint64_t value
, unsigned size
)
361 stellaris_enet_state
*s
= (stellaris_enet_state
*)opaque
;
364 case 0x00: /* IACK */
366 DPRINTF("IRQ ack %02" PRIx64
"/%02x\n", value
, s
->ris
);
367 stellaris_enet_update(s
);
368 /* Clearing TXER also resets the TX fifo. */
369 if (value
& SE_INT_TXER
) {
374 DPRINTF("IRQ mask %02" PRIx64
"/%02x\n", value
, s
->ris
);
376 stellaris_enet_update(s
);
378 case 0x08: /* RCTL */
380 if (value
& SE_RCTL_RSTFIFO
) {
382 s
->rx_fifo_offset
= 0;
383 stellaris_enet_update(s
);
386 case 0x0c: /* TCTL */
389 case 0x10: /* DATA */
390 if (s
->tx_fifo_len
== 0) {
391 /* The first word is special, it contains the data length */
392 int framelen
= value
& 0xffff;
393 if (framelen
> 2032) {
394 DPRINTF("TX frame too long (%d)\n", framelen
);
395 s
->ris
|= SE_INT_TXER
;
396 stellaris_enet_update(s
);
401 if (s
->tx_fifo_len
+ 4 <= ARRAY_SIZE(s
->tx_fifo
)) {
402 s
->tx_fifo
[s
->tx_fifo_len
++] = value
;
403 s
->tx_fifo
[s
->tx_fifo_len
++] = value
>> 8;
404 s
->tx_fifo
[s
->tx_fifo_len
++] = value
>> 16;
405 s
->tx_fifo
[s
->tx_fifo_len
++] = value
>> 24;
408 if (stellaris_tx_thr_reached(s
) && stellaris_txpacket_complete(s
)) {
409 stellaris_enet_send(s
);
413 s
->conf
.macaddr
.a
[0] = value
;
414 s
->conf
.macaddr
.a
[1] = value
>> 8;
415 s
->conf
.macaddr
.a
[2] = value
>> 16;
416 s
->conf
.macaddr
.a
[3] = value
>> 24;
419 s
->conf
.macaddr
.a
[4] = value
;
420 s
->conf
.macaddr
.a
[5] = value
>> 8;
425 case 0x20: /* MCTL */
426 /* TODO: MII registers aren't modelled.
427 * Clear START, indicating that the operation completes immediately.
429 s
->mctl
= value
& ~1;
434 case 0x28: /* MADD */
437 case 0x2c: /* MTXD */
438 s
->mtxd
= value
& 0xff;
442 stellaris_enet_send(s
);
445 case 0x30: /* MRXD */
448 case 0x3c: /* Undocuented: Timestamp? */
452 qemu_log_mask(LOG_GUEST_ERROR
, "stellaris_enet_wr%d: Illegal register "
453 "0x02%" HWADDR_PRIx
" = 0x%" PRIx64
"\n",
454 size
* 8, offset
, value
);
458 static const MemoryRegionOps stellaris_enet_ops
= {
459 .read
= stellaris_enet_read
,
460 .write
= stellaris_enet_write
,
461 .endianness
= DEVICE_NATIVE_ENDIAN
,
464 static void stellaris_enet_reset(DeviceState
*dev
)
466 stellaris_enet_state
*s
= STELLARIS_ENET(dev
);
469 s
->rctl
= SE_RCTL_BADCRC
;
470 s
->im
= SE_INT_PHY
| SE_INT_MD
| SE_INT_RXER
| SE_INT_FOV
| SE_INT_TXEMP
471 | SE_INT_TXER
| SE_INT_RX
;
476 static NetClientInfo net_stellaris_enet_info
= {
477 .type
= NET_CLIENT_DRIVER_NIC
,
478 .size
= sizeof(NICState
),
479 .receive
= stellaris_enet_receive
,
482 static void stellaris_enet_realize(DeviceState
*dev
, Error
**errp
)
484 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
485 stellaris_enet_state
*s
= STELLARIS_ENET(dev
);
487 memory_region_init_io(&s
->mmio
, OBJECT(s
), &stellaris_enet_ops
, s
,
488 "stellaris_enet", 0x1000);
489 sysbus_init_mmio(sbd
, &s
->mmio
);
490 sysbus_init_irq(sbd
, &s
->irq
);
491 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
493 s
->nic
= qemu_new_nic(&net_stellaris_enet_info
, &s
->conf
,
494 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
495 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
498 static Property stellaris_enet_properties
[] = {
499 DEFINE_NIC_PROPERTIES(stellaris_enet_state
, conf
),
500 DEFINE_PROP_END_OF_LIST(),
503 static void stellaris_enet_class_init(ObjectClass
*klass
, void *data
)
505 DeviceClass
*dc
= DEVICE_CLASS(klass
);
507 dc
->realize
= stellaris_enet_realize
;
508 dc
->reset
= stellaris_enet_reset
;
509 dc
->props
= stellaris_enet_properties
;
510 dc
->vmsd
= &vmstate_stellaris_enet
;
513 static const TypeInfo stellaris_enet_info
= {
514 .name
= TYPE_STELLARIS_ENET
,
515 .parent
= TYPE_SYS_BUS_DEVICE
,
516 .instance_size
= sizeof(stellaris_enet_state
),
517 .class_init
= stellaris_enet_class_init
,
520 static void stellaris_enet_register_types(void)
522 type_register_static(&stellaris_enet_info
);
525 type_init(stellaris_enet_register_types
)