hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/ppc/mac.h"
  28 #include "hw/ppc/mac_dbdma.h"
  29 #include "migration/vmstate.h"
  30 #include "qemu/module.h"
  31 #include "hw/misc/macio/macio.h"
  32 #include "sysemu/block-backend.h"
  33 #include "sysemu/dma.h"
  34
  35 #include "hw/ide/internal.h"
  36
  37 /* debug MACIO */
  38 // #define DEBUG_MACIO
  39
  40 #ifdef DEBUG_MACIO
  41 static const int debug_macio = 1;
  42 #else
  43 static const int debug_macio = 0;
  44 #endif
  45
  46 #define MACIO_DPRINTF(fmt, ...) do { \
  47         if (debug_macio) { \
  48             printf(fmt , ## __VA_ARGS__); \
  49         } \
  50     } while (0)
  51
  52
  53 /***********************************************************/
  54 /* MacIO based PowerPC IDE */
  55
  56 #define MACIO_PAGE_SIZE 4096
  57
  58 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
  59 {
  60     DBDMA_io *io = opaque;
  61     MACIOIDEState *m = io->opaque;
  62     IDEState *s = idebus_active_if(&m->bus);
  63     int64_t offset;
  64
  65     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
  66
  67     if (ret < 0) {
  68         MACIO_DPRINTF("DMA error: %d\n", ret);
  69         qemu_sglist_destroy(&s->sg);
  70         ide_atapi_io_error(s, ret);
  71         goto done;
  72     }
  73
  74     if (!m->dma_active) {
  75         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
  76                       s->nsector, io->len, s->status);
  77         /* data not ready yet, wait for the channel to get restarted */
  78         io->processing = false;
  79         return;
  80     }
  81
  82     if (s->io_buffer_size <= 0) {
  83         MACIO_DPRINTF("End of IDE transfer\n");
  84         qemu_sglist_destroy(&s->sg);
  85         ide_atapi_cmd_ok(s);
  86         m->dma_active = false;
  87         goto done;
  88     }
  89
  90     if (io->len == 0) {
  91         MACIO_DPRINTF("End of DMA transfer\n");
  92         goto done;
  93     }
  94
  95     if (s->lba == -1) {
  96         /* Non-block ATAPI transfer - just copy to RAM */
  97         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
  98         dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
  99                          s->io_buffer_size);
 100         io->len = 0;
 101         ide_atapi_cmd_ok(s);
 102         m->dma_active = false;
 103         goto done;
 104     }
 105
 106     /* Calculate current offset */
 107     offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
 108
 109     qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
 110                      &address_space_memory);
 111     qemu_sglist_add(&s->sg, io->addr, io->len);
 112     s->io_buffer_size -= io->len;
 113     s->io_buffer_index += io->len;
 114     io->len = 0;
 115
 116     s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
 117                                       pmac_ide_atapi_transfer_cb, io);
 118     return;
 119
 120 done:
 121     dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
 122                      io->dir, io->dma_len);
 123
 124     if (ret < 0) {
 125         block_acct_failed(blk_get_stats(s->blk), &s->acct);
 126     } else {
 127         block_acct_done(blk_get_stats(s->blk), &s->acct);
 128     }
 129
 130     ide_set_inactive(s, false);
 131     io->dma_end(opaque);
 132 }
 133
 134 static void pmac_ide_transfer_cb(void *opaque, int ret)
 135 {
 136     DBDMA_io *io = opaque;
 137     MACIOIDEState *m = io->opaque;
 138     IDEState *s = idebus_active_if(&m->bus);
 139     int64_t offset;
 140
 141     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
 142
 143     if (ret < 0) {
 144         MACIO_DPRINTF("DMA error: %d\n", ret);
 145         qemu_sglist_destroy(&s->sg);
 146         ide_dma_error(s);
 147         goto done;
 148     }
 149
 150     if (!m->dma_active) {
 151         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 152                       s->nsector, io->len, s->status);
 153         /* data not ready yet, wait for the channel to get restarted */
 154         io->processing = false;
 155         return;
 156     }
 157
 158     if (s->io_buffer_size <= 0) {
 159         MACIO_DPRINTF("End of IDE transfer\n");
 160         qemu_sglist_destroy(&s->sg);
 161         s->status = READY_STAT | SEEK_STAT;
 162         ide_set_irq(s->bus);
 163         m->dma_active = false;
 164         goto done;
 165     }
 166
 167     if (io->len == 0) {
 168         MACIO_DPRINTF("End of DMA transfer\n");
 169         goto done;
 170     }
 171
 172     /* Calculate number of sectors */
 173     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
 174
 175     qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
 176                      &address_space_memory);
 177     qemu_sglist_add(&s->sg, io->addr, io->len);
 178     s->io_buffer_size -= io->len;
 179     s->io_buffer_index += io->len;
 180     io->len = 0;
 181
 182     switch (s->dma_cmd) {
 183     case IDE_DMA_READ:
 184         s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
 185                                           pmac_ide_atapi_transfer_cb, io);
 186         break;
 187     case IDE_DMA_WRITE:
 188         s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
 189                                            pmac_ide_transfer_cb, io);
 190         break;
 191     case IDE_DMA_TRIM:
 192         s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
 193                                         offset, 0x1, ide_issue_trim, s,
 194                                         pmac_ide_transfer_cb, io,
 195                                         DMA_DIRECTION_TO_DEVICE);
 196         break;
 197     default:
 198         abort();
 199     }
 200
 201     return;
 202
 203 done:
 204     dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
 205                      io->dir, io->dma_len);
 206
 207     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 208         if (ret < 0) {
 209             block_acct_failed(blk_get_stats(s->blk), &s->acct);
 210         } else {
 211             block_acct_done(blk_get_stats(s->blk), &s->acct);
 212         }
 213     }
 214
 215     ide_set_inactive(s, false);
 216     io->dma_end(opaque);
 217 }
 218
 219 static void pmac_ide_transfer(DBDMA_io *io)
 220 {
 221     MACIOIDEState *m = io->opaque;
 222     IDEState *s = idebus_active_if(&m->bus);
 223
 224     MACIO_DPRINTF("\n");
 225
 226     if (s->drive_kind == IDE_CD) {
 227         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 228                          BLOCK_ACCT_READ);
 229
 230         pmac_ide_atapi_transfer_cb(io, 0);
 231         return;
 232     }
 233
 234     switch (s->dma_cmd) {
 235     case IDE_DMA_READ:
 236         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 237                          BLOCK_ACCT_READ);
 238         break;
 239     case IDE_DMA_WRITE:
 240         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 241                          BLOCK_ACCT_WRITE);
 242         break;
 243     default:
 244         break;
 245     }
 246
 247     pmac_ide_transfer_cb(io, 0);
 248 }
 249
 250 static void pmac_ide_flush(DBDMA_io *io)
 251 {
 252     MACIOIDEState *m = io->opaque;
 253     IDEState *s = idebus_active_if(&m->bus);
 254
 255     if (s->bus->dma->aiocb) {
 256         blk_drain(s->blk);
 257     }
 258 }
 259
 260 /* PowerMac IDE memory IO */
 261 static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
 262 {
 263     MACIOIDEState *d = opaque;
 264     uint64_t retval = 0xffffffff;
 265     int reg = addr >> 4;
 266
 267     switch (reg) {
 268     case 0x0:
 269         if (size == 2) {
 270             retval = ide_data_readw(&d->bus, 0);
 271         } else if (size == 4) {
 272             retval = ide_data_readl(&d->bus, 0);
 273         }
 274         break;
 275     case 0x1 ... 0x7:
 276         if (size == 1) {
 277             retval = ide_ioport_read(&d->bus, reg);
 278         }
 279         break;
 280     case 0x8:
 281     case 0x16:
 282         if (size == 1) {
 283             retval = ide_status_read(&d->bus, 0);
 284         }
 285         break;
 286     case 0x20:
 287         if (size == 4) {
 288             retval = d->timing_reg;
 289         }
 290         break;
 291     case 0x30:
 292         /* This is an interrupt state register that only exists
 293          * in the KeyLargo and later variants. Bit 0x8000_0000
 294          * latches the DMA interrupt and has to be written to
 295          * clear. Bit 0x4000_0000 is an image of the disk
 296          * interrupt. MacOS X relies on this and will hang if
 297          * we don't provide at least the disk interrupt
 298          */
 299         if (size == 4) {
 300             retval = d->irq_reg;
 301         }
 302         break;
 303     }
 304
 305     return retval;
 306 }
 307
 308
 309 static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
 310                            unsigned size)
 311 {
 312     MACIOIDEState *d = opaque;
 313     int reg = addr >> 4;
 314
 315     switch (reg) {
 316     case 0x0:
 317         if (size == 2) {
 318             ide_data_writew(&d->bus, 0, val);
 319         } else if (size == 4) {
 320             ide_data_writel(&d->bus, 0, val);
 321         }
 322         break;
 323     case 0x1 ... 0x7:
 324         if (size == 1) {
 325             ide_ioport_write(&d->bus, reg, val);
 326         }
 327         break;
 328     case 0x8:
 329     case 0x16:
 330         if (size == 1) {
 331             ide_cmd_write(&d->bus, 0, val);
 332         }
 333         break;
 334     case 0x20:
 335         if (size == 4) {
 336             d->timing_reg = val;
 337         }
 338         break;
 339     case 0x30:
 340         if (size == 4) {
 341             if (val & 0x80000000u) {
 342                 d->irq_reg &= 0x7fffffff;
 343             }
 344         }
 345         break;
 346     }
 347 }
 348
 349 static const MemoryRegionOps pmac_ide_ops = {
 350     .read = pmac_ide_read,
 351     .write = pmac_ide_write,
 352     .valid.min_access_size = 1,
 353     .valid.max_access_size = 4,
 354     .endianness = DEVICE_LITTLE_ENDIAN,
 355 };
 356
 357 static const VMStateDescription vmstate_pmac = {
 358     .name = "ide",
 359     .version_id = 5,
 360     .minimum_version_id = 0,
 361     .fields = (VMStateField[]) {
 362         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 363         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 364         VMSTATE_BOOL(dma_active, MACIOIDEState),
 365         VMSTATE_UINT32(timing_reg, MACIOIDEState),
 366         VMSTATE_UINT32(irq_reg, MACIOIDEState),
 367         VMSTATE_END_OF_LIST()
 368     }
 369 };
 370
 371 static void macio_ide_reset(DeviceState *dev)
 372 {
 373     MACIOIDEState *d = MACIO_IDE(dev);
 374
 375     ide_bus_reset(&d->bus);
 376 }
 377
 378 static int ide_nop_int(IDEDMA *dma, int x)
 379 {
 380     return 0;
 381 }
 382
 383 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
 384 {
 385     return 0;
 386 }
 387
 388 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
 389                             BlockCompletionFunc *cb)
 390 {
 391     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
 392
 393     s->io_buffer_index = 0;
 394     if (s->drive_kind == IDE_CD) {
 395         s->io_buffer_size = s->packet_transfer_size;
 396     } else {
 397         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
 398     }
 399
 400     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
 401     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
 402                   s->io_buffer_size, s->io_buffer_index);
 403     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
 404     MACIO_DPRINTF("-------------------------\n");
 405
 406     m->dma_active = true;
 407     DBDMA_kick(m->dbdma);
 408 }
 409
 410 static const IDEDMAOps dbdma_ops = {
 411     .start_dma      = ide_dbdma_start,
 412     .prepare_buf    = ide_nop_int32,
 413     .rw_buf         = ide_nop_int,
 414 };
 415
 416 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
 417 {
 418     MACIOIDEState *s = MACIO_IDE(dev);
 419
 420     ide_init2(&s->bus, s->ide_irq);
 421
 422     /* Register DMA callbacks */
 423     s->dma.ops = &dbdma_ops;
 424     s->bus.dma = &s->dma;
 425 }
 426
 427 static void pmac_ide_irq(void *opaque, int n, int level)
 428 {
 429     MACIOIDEState *s = opaque;
 430     uint32_t mask = 0x80000000u >> n;
 431
 432     /* We need to reflect the IRQ state in the irq register */
 433     if (level) {
 434         s->irq_reg |= mask;
 435     } else {
 436         s->irq_reg &= ~mask;
 437     }
 438
 439     if (n) {
 440         qemu_set_irq(s->real_ide_irq, level);
 441     } else {
 442         qemu_set_irq(s->real_dma_irq, level);
 443     }
 444 }
 445
 446 static void macio_ide_initfn(Object *obj)
 447 {
 448     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 449     MACIOIDEState *s = MACIO_IDE(obj);
 450
 451     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
 452     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
 453     sysbus_init_mmio(d, &s->mem);
 454     sysbus_init_irq(d, &s->real_ide_irq);
 455     sysbus_init_irq(d, &s->real_dma_irq);
 456     s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0);
 457     s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1);
 458
 459     object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
 460                              (Object **) &s->dbdma,
 461                              qdev_prop_allow_set_link_before_realize, 0, NULL);
 462 }
 463
 464 static Property macio_ide_properties[] = {
 465     DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
 466     DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1),
 467     DEFINE_PROP_END_OF_LIST(),
 468 };
 469
 470 static void macio_ide_class_init(ObjectClass *oc, void *data)
 471 {
 472     DeviceClass *dc = DEVICE_CLASS(oc);
 473
 474     dc->realize = macio_ide_realizefn;
 475     dc->reset = macio_ide_reset;
 476     dc->props = macio_ide_properties;
 477     dc->vmsd = &vmstate_pmac;
 478     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 479 }
 480
 481 static const TypeInfo macio_ide_type_info = {
 482     .name = TYPE_MACIO_IDE,
 483     .parent = TYPE_SYS_BUS_DEVICE,
 484     .instance_size = sizeof(MACIOIDEState),
 485     .instance_init = macio_ide_initfn,
 486     .class_init = macio_ide_class_init,
 487 };
 488
 489 static void macio_ide_register_types(void)
 490 {
 491     type_register_static(&macio_ide_type_info);
 492 }
 493
 494 /* hd_table must contain 2 block drivers */
 495 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
 496 {
 497     int i;
 498
 499     for (i = 0; i < 2; i++) {
 500         if (hd_table[i]) {
 501             ide_create_drive(&s->bus, i, hd_table[i]);
 502         }
 503     }
 504 }
 505
 506 void macio_ide_register_dma(MACIOIDEState *s)
 507 {
 508     DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq,
 509                            pmac_ide_transfer, pmac_ide_flush, s);
 510 }
 511
 512 type_init(macio_ide_register_types)