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hw/i386: De-duplicate gsi_handler() to remove kvm_pc_gsi_handler()
[qemu/ar7.git] / hw / i386 / pc.c
blobea7320b91b993efa0b697bbc13e13c2b7c91c6a0
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/intc/i8259.h"
48 #include "hw/dma/i8257.h"
49 #include "hw/timer/i8254.h"
50 #include "hw/input/i8042.h"
51 #include "hw/irq.h"
52 #include "hw/audio/pcspk.h"
53 #include "hw/pci/msi.h"
54 #include "hw/sysbus.h"
55 #include "sysemu/sysemu.h"
56 #include "sysemu/tcg.h"
57 #include "sysemu/numa.h"
58 #include "sysemu/kvm.h"
59 #include "sysemu/qtest.h"
60 #include "sysemu/reset.h"
61 #include "sysemu/runstate.h"
62 #include "kvm_i386.h"
63 #include "hw/xen/xen.h"
64 #include "hw/xen/start_info.h"
65 #include "ui/qemu-spice.h"
66 #include "exec/memory.h"
67 #include "exec/address-spaces.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "hw/boards.h"
77 #include "acpi-build.h"
78 #include "hw/mem/pc-dimm.h"
79 #include "qapi/error.h"
80 #include "qapi/qapi-visit-common.h"
81 #include "qapi/visitor.h"
82 #include "hw/core/cpu.h"
83 #include "hw/usb.h"
84 #include "hw/i386/intel_iommu.h"
85 #include "hw/net/ne2000-isa.h"
86 #include "standard-headers/asm-x86/bootparam.h"
87 #include "hw/virtio/virtio-pmem-pci.h"
88 #include "hw/mem/memory-device.h"
89 #include "sysemu/replay.h"
90 #include "qapi/qmp/qerror.h"
91 #include "config-devices.h"
92 #include "e820_memory_layout.h"
93 #include "fw_cfg.h"
94 #include "trace.h"
95
96 GlobalProperty pc_compat_4_2[] = {};
97 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
98
99 GlobalProperty pc_compat_4_1[] = {};
100 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
101
102 GlobalProperty pc_compat_4_0[] = {};
103 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
104
105 GlobalProperty pc_compat_3_1[] = {
106 { "intel-iommu", "dma-drain", "off" },
107 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
108 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
109 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
110 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
111 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
112 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
113 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
114 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
115 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
116 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
117 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
118 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
119 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
120 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
121 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
122 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
123 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
124 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
125 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
126 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
127 };
128 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
129
130 GlobalProperty pc_compat_3_0[] = {
131 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
132 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
133 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
134 };
135 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
136
137 GlobalProperty pc_compat_2_12[] = {
138 { TYPE_X86_CPU, "legacy-cache", "on" },
139 { TYPE_X86_CPU, "topoext", "off" },
140 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
141 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
142 };
143 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
144
145 GlobalProperty pc_compat_2_11[] = {
146 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
147 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
148 };
149 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
150
151 GlobalProperty pc_compat_2_10[] = {
152 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
153 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
154 { "q35-pcihost", "x-pci-hole64-fix", "off" },
155 };
156 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
157
158 GlobalProperty pc_compat_2_9[] = {
159 { "mch", "extended-tseg-mbytes", "0" },
160 };
161 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
162
163 GlobalProperty pc_compat_2_8[] = {
164 { TYPE_X86_CPU, "tcg-cpuid", "off" },
165 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
166 { "ICH9-LPC", "x-smi-broadcast", "off" },
167 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
168 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
169 };
170 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
171
172 GlobalProperty pc_compat_2_7[] = {
173 { TYPE_X86_CPU, "l3-cache", "off" },
174 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
175 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
176 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
177 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
178 { "isa-pcspk", "migrate", "off" },
179 };
180 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
181
182 GlobalProperty pc_compat_2_6[] = {
183 { TYPE_X86_CPU, "cpuid-0xb", "off" },
184 { "vmxnet3", "romfile", "" },
185 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
186 { "apic-common", "legacy-instance-id", "on", }
187 };
188 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
189
190 GlobalProperty pc_compat_2_5[] = {};
191 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
192
193 GlobalProperty pc_compat_2_4[] = {
194 PC_CPU_MODEL_IDS("2.4.0")
195 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
196 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
197 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
198 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
199 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
200 { TYPE_X86_CPU, "check", "off" },
201 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
202 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
203 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
204 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
205 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
206 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
207 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
208 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
209 };
210 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
211
212 GlobalProperty pc_compat_2_3[] = {
213 PC_CPU_MODEL_IDS("2.3.0")
214 { TYPE_X86_CPU, "arat", "off" },
215 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
216 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
217 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
218 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
219 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
220 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
221 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
222 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
223 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
224 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
225 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
226 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
227 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
228 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
229 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
234 };
235 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
236
237 GlobalProperty pc_compat_2_2[] = {
238 PC_CPU_MODEL_IDS("2.2.0")
239 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
240 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
241 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
242 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
243 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
244 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
245 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
246 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
247 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
254 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
255 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
256 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
257 };
258 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
259
260 GlobalProperty pc_compat_2_1[] = {
261 PC_CPU_MODEL_IDS("2.1.0")
262 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
263 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
264 };
265 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
266
267 GlobalProperty pc_compat_2_0[] = {
268 PC_CPU_MODEL_IDS("2.0.0")
269 { "virtio-scsi-pci", "any_layout", "off" },
270 { "PIIX4_PM", "memory-hotplug-support", "off" },
271 { "apic", "version", "0x11" },
272 { "nec-usb-xhci", "superspeed-ports-first", "off" },
273 { "nec-usb-xhci", "force-pcie-endcap", "on" },
274 { "pci-serial", "prog_if", "0" },
275 { "pci-serial-2x", "prog_if", "0" },
276 { "pci-serial-4x", "prog_if", "0" },
277 { "virtio-net-pci", "guest_announce", "off" },
278 { "ICH9-LPC", "memory-hotplug-support", "off" },
279 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
280 { "ioh3420", COMPAT_PROP_PCP, "off" },
281 };
282 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
283
284 GlobalProperty pc_compat_1_7[] = {
285 PC_CPU_MODEL_IDS("1.7.0")
286 { TYPE_USB_DEVICE, "msos-desc", "no" },
287 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
288 { "hpet", HPET_INTCAP, "4" },
289 };
290 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
291
292 GlobalProperty pc_compat_1_6[] = {
293 PC_CPU_MODEL_IDS("1.6.0")
294 { "e1000", "mitigation", "off" },
295 { "qemu64-" TYPE_X86_CPU, "model", "2" },
296 { "qemu32-" TYPE_X86_CPU, "model", "3" },
297 { "i440FX-pcihost", "short_root_bus", "1" },
298 { "q35-pcihost", "short_root_bus", "1" },
299 };
300 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
301
302 GlobalProperty pc_compat_1_5[] = {
303 PC_CPU_MODEL_IDS("1.5.0")
304 { "Conroe-" TYPE_X86_CPU, "model", "2" },
305 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
306 { "Penryn-" TYPE_X86_CPU, "model", "2" },
307 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
308 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
309 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
310 { "virtio-net-pci", "any_layout", "off" },
311 { TYPE_X86_CPU, "pmu", "on" },
312 { "i440FX-pcihost", "short_root_bus", "0" },
313 { "q35-pcihost", "short_root_bus", "0" },
314 };
315 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
316
317 GlobalProperty pc_compat_1_4[] = {
318 PC_CPU_MODEL_IDS("1.4.0")
319 { "scsi-hd", "discard_granularity", "0" },
320 { "scsi-cd", "discard_granularity", "0" },
321 { "scsi-disk", "discard_granularity", "0" },
322 { "ide-hd", "discard_granularity", "0" },
323 { "ide-cd", "discard_granularity", "0" },
324 { "ide-drive", "discard_granularity", "0" },
325 { "virtio-blk-pci", "discard_granularity", "0" },
326 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
327 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
328 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
329 { "e1000", "romfile", "pxe-e1000.rom" },
330 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
331 { "pcnet", "romfile", "pxe-pcnet.rom" },
332 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
333 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
334 { "486-" TYPE_X86_CPU, "model", "0" },
335 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
336 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
337 };
338 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
339
340 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
341 {
342 GSIState *s;
343
344 s = g_new0(GSIState, 1);
345 if (kvm_ioapic_in_kernel()) {
346 kvm_pc_setup_irq_routing(pci_enabled);
347 }
348 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
349
350 return s;
351 }
352
353 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
354 unsigned size)
355 {
356 }
357
358 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
359 {
360 return 0xffffffffffffffffULL;
361 }
362
363 /* MSDOS compatibility mode FPU exception support */
364 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
365 unsigned size)
366 {
367 if (tcg_enabled()) {
368 cpu_set_ignne();
369 }
370 }
371
372 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
373 {
374 return 0xffffffffffffffffULL;
375 }
376
377 /* PC cmos mappings */
378
379 #define REG_EQUIPMENT_BYTE 0x14
380
381 int cmos_get_fd_drive_type(FloppyDriveType fd0)
382 {
383 int val;
384
385 switch (fd0) {
386 case FLOPPY_DRIVE_TYPE_144:
387 /* 1.44 Mb 3"5 drive */
388 val = 4;
389 break;
390 case FLOPPY_DRIVE_TYPE_288:
391 /* 2.88 Mb 3"5 drive */
392 val = 5;
393 break;
394 case FLOPPY_DRIVE_TYPE_120:
395 /* 1.2 Mb 5"5 drive */
396 val = 2;
397 break;
398 case FLOPPY_DRIVE_TYPE_NONE:
399 default:
400 val = 0;
401 break;
402 }
403 return val;
404 }
405
406 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
407 int16_t cylinders, int8_t heads, int8_t sectors)
408 {
409 rtc_set_memory(s, type_ofs, 47);
410 rtc_set_memory(s, info_ofs, cylinders);
411 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
412 rtc_set_memory(s, info_ofs + 2, heads);
413 rtc_set_memory(s, info_ofs + 3, 0xff);
414 rtc_set_memory(s, info_ofs + 4, 0xff);
415 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
416 rtc_set_memory(s, info_ofs + 6, cylinders);
417 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
418 rtc_set_memory(s, info_ofs + 8, sectors);
419 }
420
421 /* convert boot_device letter to something recognizable by the bios */
422 static int boot_device2nibble(char boot_device)
423 {
424 switch(boot_device) {
425 case 'a':
426 case 'b':
427 return 0x01; /* floppy boot */
428 case 'c':
429 return 0x02; /* hard drive boot */
430 case 'd':
431 return 0x03; /* CD-ROM boot */
432 case 'n':
433 return 0x04; /* Network boot */
434 }
435 return 0;
436 }
437
438 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
439 {
440 #define PC_MAX_BOOT_DEVICES 3
441 int nbds, bds[3] = { 0, };
442 int i;
443
444 nbds = strlen(boot_device);
445 if (nbds > PC_MAX_BOOT_DEVICES) {
446 error_setg(errp, "Too many boot devices for PC");
447 return;
448 }
449 for (i = 0; i < nbds; i++) {
450 bds[i] = boot_device2nibble(boot_device[i]);
451 if (bds[i] == 0) {
452 error_setg(errp, "Invalid boot device for PC: '%c'",
453 boot_device[i]);
454 return;
455 }
456 }
457 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
458 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
459 }
460
461 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
462 {
463 set_boot_dev(opaque, boot_device, errp);
464 }
465
466 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
467 {
468 int val, nb, i;
469 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
470 FLOPPY_DRIVE_TYPE_NONE };
471
472 /* floppy type */
473 if (floppy) {
474 for (i = 0; i < 2; i++) {
475 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
476 }
477 }
478 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
479 cmos_get_fd_drive_type(fd_type[1]);
480 rtc_set_memory(rtc_state, 0x10, val);
481
482 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
483 nb = 0;
484 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
485 nb++;
486 }
487 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
488 nb++;
489 }
490 switch (nb) {
491 case 0:
492 break;
493 case 1:
494 val |= 0x01; /* 1 drive, ready for boot */
495 break;
496 case 2:
497 val |= 0x41; /* 2 drives, ready for boot */
498 break;
499 }
500 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
501 }
502
503 typedef struct pc_cmos_init_late_arg {
504 ISADevice *rtc_state;
505 BusState *idebus[2];
506 } pc_cmos_init_late_arg;
507
508 typedef struct check_fdc_state {
509 ISADevice *floppy;
510 bool multiple;
511 } CheckFdcState;
512
513 static int check_fdc(Object *obj, void *opaque)
514 {
515 CheckFdcState *state = opaque;
516 Object *fdc;
517 uint32_t iobase;
518 Error *local_err = NULL;
519
520 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
521 if (!fdc) {
522 return 0;
523 }
524
525 iobase = object_property_get_uint(obj, "iobase", &local_err);
526 if (local_err || iobase != 0x3f0) {
527 error_free(local_err);
528 return 0;
529 }
530
531 if (state->floppy) {
532 state->multiple = true;
533 } else {
534 state->floppy = ISA_DEVICE(obj);
535 }
536 return 0;
537 }
538
539 static const char * const fdc_container_path[] = {
540 "/unattached", "/peripheral", "/peripheral-anon"
541 };
542
543 /*
544 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
545 * and ACPI objects.
546 */
547 ISADevice *pc_find_fdc0(void)
548 {
549 int i;
550 Object *container;
551 CheckFdcState state = { 0 };
552
553 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
554 container = container_get(qdev_get_machine(), fdc_container_path[i]);
555 object_child_foreach(container, check_fdc, &state);
556 }
557
558 if (state.multiple) {
559 warn_report("multiple floppy disk controllers with "
560 "iobase=0x3f0 have been found");
561 error_printf("the one being picked for CMOS setup might not reflect "
562 "your intent");
563 }
564
565 return state.floppy;
566 }
567
568 static void pc_cmos_init_late(void *opaque)
569 {
570 pc_cmos_init_late_arg *arg = opaque;
571 ISADevice *s = arg->rtc_state;
572 int16_t cylinders;
573 int8_t heads, sectors;
574 int val;
575 int i, trans;
576
577 val = 0;
578 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
579 &cylinders, &heads, &sectors) >= 0) {
580 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
581 val |= 0xf0;
582 }
583 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
584 &cylinders, &heads, &sectors) >= 0) {
585 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
586 val |= 0x0f;
587 }
588 rtc_set_memory(s, 0x12, val);
589
590 val = 0;
591 for (i = 0; i < 4; i++) {
592 /* NOTE: ide_get_geometry() returns the physical
593 geometry. It is always such that: 1 <= sects <= 63, 1
594 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
595 geometry can be different if a translation is done. */
596 if (arg->idebus[i / 2] &&
597 ide_get_geometry(arg->idebus[i / 2], i % 2,
598 &cylinders, &heads, &sectors) >= 0) {
599 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
600 assert((trans & ~3) == 0);
601 val |= trans << (i * 2);
602 }
603 }
604 rtc_set_memory(s, 0x39, val);
605
606 pc_cmos_init_floppy(s, pc_find_fdc0());
607
608 qemu_unregister_reset(pc_cmos_init_late, opaque);
609 }
610
611 void pc_cmos_init(PCMachineState *pcms,
612 BusState *idebus0, BusState *idebus1,
613 ISADevice *s)
614 {
615 int val;
616 static pc_cmos_init_late_arg arg;
617 X86MachineState *x86ms = X86_MACHINE(pcms);
618
619 /* various important CMOS locations needed by PC/Bochs bios */
620
621 /* memory size */
622 /* base memory (first MiB) */
623 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
624 rtc_set_memory(s, 0x15, val);
625 rtc_set_memory(s, 0x16, val >> 8);
626 /* extended memory (next 64MiB) */
627 if (x86ms->below_4g_mem_size > 1 * MiB) {
628 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
629 } else {
630 val = 0;
631 }
632 if (val > 65535)
633 val = 65535;
634 rtc_set_memory(s, 0x17, val);
635 rtc_set_memory(s, 0x18, val >> 8);
636 rtc_set_memory(s, 0x30, val);
637 rtc_set_memory(s, 0x31, val >> 8);
638 /* memory between 16MiB and 4GiB */
639 if (x86ms->below_4g_mem_size > 16 * MiB) {
640 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
641 } else {
642 val = 0;
643 }
644 if (val > 65535)
645 val = 65535;
646 rtc_set_memory(s, 0x34, val);
647 rtc_set_memory(s, 0x35, val >> 8);
648 /* memory above 4GiB */
649 val = x86ms->above_4g_mem_size / 65536;
650 rtc_set_memory(s, 0x5b, val);
651 rtc_set_memory(s, 0x5c, val >> 8);
652 rtc_set_memory(s, 0x5d, val >> 16);
653
654 object_property_add_link(OBJECT(pcms), "rtc_state",
655 TYPE_ISA_DEVICE,
656 (Object **)&x86ms->rtc,
657 object_property_allow_set_link,
658 OBJ_PROP_LINK_STRONG, &error_abort);
659 object_property_set_link(OBJECT(pcms), OBJECT(s),
660 "rtc_state", &error_abort);
661
662 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
663
664 val = 0;
665 val |= 0x02; /* FPU is there */
666 val |= 0x04; /* PS/2 mouse installed */
667 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
668
669 /* hard drives and FDC */
670 arg.rtc_state = s;
671 arg.idebus[0] = idebus0;
672 arg.idebus[1] = idebus1;
673 qemu_register_reset(pc_cmos_init_late, &arg);
674 }
675
676 #define TYPE_PORT92 "port92"
677 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
678
679 /* port 92 stuff: could be split off */
680 typedef struct Port92State {
681 ISADevice parent_obj;
682
683 MemoryRegion io;
684 uint8_t outport;
685 qemu_irq a20_out;
686 } Port92State;
687
688 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
689 unsigned size)
690 {
691 Port92State *s = opaque;
692 int oldval = s->outport;
693
694 trace_port92_write(val);
695 s->outport = val;
696 qemu_set_irq(s->a20_out, (val >> 1) & 1);
697 if ((val & 1) && !(oldval & 1)) {
698 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
699 }
700 }
701
702 static uint64_t port92_read(void *opaque, hwaddr addr,
703 unsigned size)
704 {
705 Port92State *s = opaque;
706 uint32_t ret;
707
708 ret = s->outport;
709 trace_port92_read(ret);
710 return ret;
711 }
712
713 static void port92_init(ISADevice *dev, qemu_irq a20_out)
714 {
715 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
716 }
717
718 static const VMStateDescription vmstate_port92_isa = {
719 .name = "port92",
720 .version_id = 1,
721 .minimum_version_id = 1,
722 .fields = (VMStateField[]) {
723 VMSTATE_UINT8(outport, Port92State),
724 VMSTATE_END_OF_LIST()
725 }
726 };
727
728 static void port92_reset(DeviceState *d)
729 {
730 Port92State *s = PORT92(d);
731
732 s->outport &= ~1;
733 }
734
735 static const MemoryRegionOps port92_ops = {
736 .read = port92_read,
737 .write = port92_write,
738 .impl = {
739 .min_access_size = 1,
740 .max_access_size = 1,
741 },
742 .endianness = DEVICE_LITTLE_ENDIAN,
743 };
744
745 static void port92_initfn(Object *obj)
746 {
747 Port92State *s = PORT92(obj);
748
749 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
750
751 s->outport = 0;
752
753 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
754 }
755
756 static void port92_realizefn(DeviceState *dev, Error **errp)
757 {
758 ISADevice *isadev = ISA_DEVICE(dev);
759 Port92State *s = PORT92(dev);
760
761 isa_register_ioport(isadev, &s->io, 0x92);
762 }
763
764 static void port92_class_initfn(ObjectClass *klass, void *data)
765 {
766 DeviceClass *dc = DEVICE_CLASS(klass);
767
768 dc->realize = port92_realizefn;
769 dc->reset = port92_reset;
770 dc->vmsd = &vmstate_port92_isa;
771 /*
772 * Reason: unlike ordinary ISA devices, this one needs additional
773 * wiring: its A20 output line needs to be wired up by
774 * port92_init().
775 */
776 dc->user_creatable = false;
777 }
778
779 static const TypeInfo port92_info = {
780 .name = TYPE_PORT92,
781 .parent = TYPE_ISA_DEVICE,
782 .instance_size = sizeof(Port92State),
783 .instance_init = port92_initfn,
784 .class_init = port92_class_initfn,
785 };
786
787 static void port92_register_types(void)
788 {
789 type_register_static(&port92_info);
790 }
791
792 type_init(port92_register_types)
793
794 static void handle_a20_line_change(void *opaque, int irq, int level)
795 {
796 X86CPU *cpu = opaque;
797
798 /* XXX: send to all CPUs ? */
799 /* XXX: add logic to handle multiple A20 line sources */
800 x86_cpu_set_a20(cpu, level);
801 }
802
803 #define NE2000_NB_MAX 6
804
805 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
806 0x280, 0x380 };
807 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
808
809 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
810 {
811 static int nb_ne2k = 0;
812
813 if (nb_ne2k == NE2000_NB_MAX)
814 return;
815 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
816 ne2000_irq[nb_ne2k], nd);
817 nb_ne2k++;
818 }
819
820 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
821 {
822 X86CPU *cpu = opaque;
823
824 if (level) {
825 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
826 }
827 }
828
829 /*
830 * This function is very similar to smp_parse()
831 * in hw/core/machine.c but includes CPU die support.
832 */
833 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
834 {
835 X86MachineState *x86ms = X86_MACHINE(ms);
836
837 if (opts) {
838 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
839 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
840 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
841 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
842 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
843
844 /* compute missing values, prefer sockets over cores over threads */
845 if (cpus == 0 || sockets == 0) {
846 cores = cores > 0 ? cores : 1;
847 threads = threads > 0 ? threads : 1;
848 if (cpus == 0) {
849 sockets = sockets > 0 ? sockets : 1;
850 cpus = cores * threads * dies * sockets;
851 } else {
852 ms->smp.max_cpus =
853 qemu_opt_get_number(opts, "maxcpus", cpus);
854 sockets = ms->smp.max_cpus / (cores * threads * dies);
855 }
856 } else if (cores == 0) {
857 threads = threads > 0 ? threads : 1;
858 cores = cpus / (sockets * dies * threads);
859 cores = cores > 0 ? cores : 1;
860 } else if (threads == 0) {
861 threads = cpus / (cores * dies * sockets);
862 threads = threads > 0 ? threads : 1;
863 } else if (sockets * dies * cores * threads < cpus) {
864 error_report("cpu topology: "
865 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
866 "smp_cpus (%u)",
867 sockets, dies, cores, threads, cpus);
868 exit(1);
869 }
870
871 ms->smp.max_cpus =
872 qemu_opt_get_number(opts, "maxcpus", cpus);
873
874 if (ms->smp.max_cpus < cpus) {
875 error_report("maxcpus must be equal to or greater than smp");
876 exit(1);
877 }
878
879 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
880 error_report("cpu topology: "
881 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
882 "maxcpus (%u)",
883 sockets, dies, cores, threads,
884 ms->smp.max_cpus);
885 exit(1);
886 }
887
888 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
889 warn_report("Invalid CPU topology deprecated: "
890 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
891 "!= maxcpus (%u)",
892 sockets, dies, cores, threads,
893 ms->smp.max_cpus);
894 }
895
896 ms->smp.cpus = cpus;
897 ms->smp.cores = cores;
898 ms->smp.threads = threads;
899 x86ms->smp_dies = dies;
900 }
901
902 if (ms->smp.cpus > 1) {
903 Error *blocker = NULL;
904 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
905 replay_add_blocker(blocker);
906 }
907 }
908
909 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
910 {
911 X86MachineState *x86ms = X86_MACHINE(ms);
912 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
913 Error *local_err = NULL;
914
915 if (id < 0) {
916 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
917 return;
918 }
919
920 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
921 error_setg(errp, "Unable to add CPU: %" PRIi64
922 ", resulting APIC ID (%" PRIi64 ") is too large",
923 id, apic_id);
924 return;
925 }
926
927
928 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
929 if (local_err) {
930 error_propagate(errp, local_err);
931 return;
932 }
933 }
934
935 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
936 {
937 if (cpus_count > 0xff) {
938 /* If the number of CPUs can't be represented in 8 bits, the
939 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
940 * to make old BIOSes fail more predictably.
941 */
942 rtc_set_memory(rtc, 0x5f, 0);
943 } else {
944 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
945 }
946 }
947
948 static
949 void pc_machine_done(Notifier *notifier, void *data)
950 {
951 PCMachineState *pcms = container_of(notifier,
952 PCMachineState, machine_done);
953 X86MachineState *x86ms = X86_MACHINE(pcms);
954 PCIBus *bus = pcms->bus;
955
956 /* set the number of CPUs */
957 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
958
959 if (bus) {
960 int extra_hosts = 0;
961
962 QLIST_FOREACH(bus, &bus->child, sibling) {
963 /* look for expander root buses */
964 if (pci_bus_is_root(bus)) {
965 extra_hosts++;
966 }
967 }
968 if (extra_hosts && x86ms->fw_cfg) {
969 uint64_t *val = g_malloc(sizeof(*val));
970 *val = cpu_to_le64(extra_hosts);
971 fw_cfg_add_file(x86ms->fw_cfg,
972 "etc/extra-pci-roots", val, sizeof(*val));
973 }
974 }
975
976 acpi_setup();
977 if (x86ms->fw_cfg) {
978 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
979 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
980 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
981 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
982 }
983
984 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
985 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
986
987 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
988 iommu->intr_eim != ON_OFF_AUTO_ON) {
989 error_report("current -smp configuration requires "
990 "Extended Interrupt Mode enabled. "
991 "You can add an IOMMU using: "
992 "-device intel-iommu,intremap=on,eim=on");
993 exit(EXIT_FAILURE);
994 }
995 }
996 }
997
998 void pc_guest_info_init(PCMachineState *pcms)
999 {
1000 int i;
1001 MachineState *ms = MACHINE(pcms);
1002 X86MachineState *x86ms = X86_MACHINE(pcms);
1003
1004 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
1005 pcms->numa_nodes = ms->numa_state->num_nodes;
1006 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1007 sizeof *pcms->node_mem);
1008 for (i = 0; i < ms->numa_state->num_nodes; i++) {
1009 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
1010 }
1011
1012 pcms->machine_done.notify = pc_machine_done;
1013 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1014 }
1015
1016 /* setup pci memory address space mapping into system address space */
1017 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1018 MemoryRegion *pci_address_space)
1019 {
1020 /* Set to lower priority than RAM */
1021 memory_region_add_subregion_overlap(system_memory, 0x0,
1022 pci_address_space, -1);
1023 }
1024
1025 void xen_load_linux(PCMachineState *pcms)
1026 {
1027 int i;
1028 FWCfgState *fw_cfg;
1029 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1030 X86MachineState *x86ms = X86_MACHINE(pcms);
1031
1032 assert(MACHINE(pcms)->kernel_filename != NULL);
1033
1034 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1035 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1036 rom_set_fw(fw_cfg);
1037
1038 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1039 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1040 for (i = 0; i < nb_option_roms; i++) {
1041 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1042 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1043 !strcmp(option_rom[i].name, "pvh.bin") ||
1044 !strcmp(option_rom[i].name, "multiboot.bin"));
1045 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1046 }
1047 x86ms->fw_cfg = fw_cfg;
1048 }
1049
1050 void pc_memory_init(PCMachineState *pcms,
1051 MemoryRegion *system_memory,
1052 MemoryRegion *rom_memory,
1053 MemoryRegion **ram_memory)
1054 {
1055 int linux_boot, i;
1056 MemoryRegion *ram, *option_rom_mr;
1057 MemoryRegion *ram_below_4g, *ram_above_4g;
1058 FWCfgState *fw_cfg;
1059 MachineState *machine = MACHINE(pcms);
1060 MachineClass *mc = MACHINE_GET_CLASS(machine);
1061 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1062 X86MachineState *x86ms = X86_MACHINE(pcms);
1063
1064 assert(machine->ram_size == x86ms->below_4g_mem_size +
1065 x86ms->above_4g_mem_size);
1066
1067 linux_boot = (machine->kernel_filename != NULL);
1068
1069 /* Allocate RAM. We allocate it as a single memory region and use
1070 * aliases to address portions of it, mostly for backwards compatibility
1071 * with older qemus that used qemu_ram_alloc().
1072 */
1073 ram = g_malloc(sizeof(*ram));
1074 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1075 machine->ram_size);
1076 *ram_memory = ram;
1077 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1078 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1079 0, x86ms->below_4g_mem_size);
1080 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1081 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1082 if (x86ms->above_4g_mem_size > 0) {
1083 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1084 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1085 x86ms->below_4g_mem_size,
1086 x86ms->above_4g_mem_size);
1087 memory_region_add_subregion(system_memory, 0x100000000ULL,
1088 ram_above_4g);
1089 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
1090 }
1091
1092 if (!pcmc->has_reserved_memory &&
1093 (machine->ram_slots ||
1094 (machine->maxram_size > machine->ram_size))) {
1095
1096 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1097 mc->name);
1098 exit(EXIT_FAILURE);
1099 }
1100
1101 /* always allocate the device memory information */
1102 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1103
1104 /* initialize device memory address space */
1105 if (pcmc->has_reserved_memory &&
1106 (machine->ram_size < machine->maxram_size)) {
1107 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1108
1109 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1110 error_report("unsupported amount of memory slots: %"PRIu64,
1111 machine->ram_slots);
1112 exit(EXIT_FAILURE);
1113 }
1114
1115 if (QEMU_ALIGN_UP(machine->maxram_size,
1116 TARGET_PAGE_SIZE) != machine->maxram_size) {
1117 error_report("maximum memory size must by aligned to multiple of "
1118 "%d bytes", TARGET_PAGE_SIZE);
1119 exit(EXIT_FAILURE);
1120 }
1121
1122 machine->device_memory->base =
1123 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1124
1125 if (pcmc->enforce_aligned_dimm) {
1126 /* size device region assuming 1G page max alignment per slot */
1127 device_mem_size += (1 * GiB) * machine->ram_slots;
1128 }
1129
1130 if ((machine->device_memory->base + device_mem_size) <
1131 device_mem_size) {
1132 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1133 machine->maxram_size);
1134 exit(EXIT_FAILURE);
1135 }
1136
1137 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1138 "device-memory", device_mem_size);
1139 memory_region_add_subregion(system_memory, machine->device_memory->base,
1140 &machine->device_memory->mr);
1141 }
1142
1143 /* Initialize PC system firmware */
1144 pc_system_firmware_init(pcms, rom_memory);
1145
1146 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1147 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1148 &error_fatal);
1149 if (pcmc->pci_enabled) {
1150 memory_region_set_readonly(option_rom_mr, true);
1151 }
1152 memory_region_add_subregion_overlap(rom_memory,
1153 PC_ROM_MIN_VGA,
1154 option_rom_mr,
1155 1);
1156
1157 fw_cfg = fw_cfg_arch_create(machine,
1158 x86ms->boot_cpus, x86ms->apic_id_limit);
1159
1160 rom_set_fw(fw_cfg);
1161
1162 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1163 uint64_t *val = g_malloc(sizeof(*val));
1164 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1165 uint64_t res_mem_end = machine->device_memory->base;
1166
1167 if (!pcmc->broken_reserved_end) {
1168 res_mem_end += memory_region_size(&machine->device_memory->mr);
1169 }
1170 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1171 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1172 }
1173
1174 if (linux_boot) {
1175 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1176 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1177 }
1178
1179 for (i = 0; i < nb_option_roms; i++) {
1180 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1181 }
1182 x86ms->fw_cfg = fw_cfg;
1183
1184 /* Init default IOAPIC address space */
1185 x86ms->ioapic_as = &address_space_memory;
1186
1187 /* Init ACPI memory hotplug IO base address */
1188 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1189 }
1190
1191 /*
1192 * The 64bit pci hole starts after "above 4G RAM" and
1193 * potentially the space reserved for memory hotplug.
1194 */
1195 uint64_t pc_pci_hole64_start(void)
1196 {
1197 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1198 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1199 MachineState *ms = MACHINE(pcms);
1200 X86MachineState *x86ms = X86_MACHINE(pcms);
1201 uint64_t hole64_start = 0;
1202
1203 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1204 hole64_start = ms->device_memory->base;
1205 if (!pcmc->broken_reserved_end) {
1206 hole64_start += memory_region_size(&ms->device_memory->mr);
1207 }
1208 } else {
1209 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1210 }
1211
1212 return ROUND_UP(hole64_start, 1 * GiB);
1213 }
1214
1215 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1216 {
1217 DeviceState *dev = NULL;
1218
1219 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1220 if (pci_bus) {
1221 PCIDevice *pcidev = pci_vga_init(pci_bus);
1222 dev = pcidev ? &pcidev->qdev : NULL;
1223 } else if (isa_bus) {
1224 ISADevice *isadev = isa_vga_init(isa_bus);
1225 dev = isadev ? DEVICE(isadev) : NULL;
1226 }
1227 rom_reset_order_override();
1228 return dev;
1229 }
1230
1231 static const MemoryRegionOps ioport80_io_ops = {
1232 .write = ioport80_write,
1233 .read = ioport80_read,
1234 .endianness = DEVICE_NATIVE_ENDIAN,
1235 .impl = {
1236 .min_access_size = 1,
1237 .max_access_size = 1,
1238 },
1239 };
1240
1241 static const MemoryRegionOps ioportF0_io_ops = {
1242 .write = ioportF0_write,
1243 .read = ioportF0_read,
1244 .endianness = DEVICE_NATIVE_ENDIAN,
1245 .impl = {
1246 .min_access_size = 1,
1247 .max_access_size = 1,
1248 },
1249 };
1250
1251 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1252 {
1253 int i;
1254 DriveInfo *fd[MAX_FD];
1255 qemu_irq *a20_line;
1256 ISADevice *i8042, *port92, *vmmouse;
1257
1258 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1259 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1260
1261 for (i = 0; i < MAX_FD; i++) {
1262 fd[i] = drive_get(IF_FLOPPY, 0, i);
1263 create_fdctrl |= !!fd[i];
1264 }
1265 if (create_fdctrl) {
1266 fdctrl_init_isa(isa_bus, fd);
1267 }
1268
1269 i8042 = isa_create_simple(isa_bus, "i8042");
1270 if (!no_vmport) {
1271 vmport_init(isa_bus);
1272 vmmouse = isa_try_create(isa_bus, "vmmouse");
1273 } else {
1274 vmmouse = NULL;
1275 }
1276 if (vmmouse) {
1277 DeviceState *dev = DEVICE(vmmouse);
1278 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1279 qdev_init_nofail(dev);
1280 }
1281 port92 = isa_create_simple(isa_bus, "port92");
1282
1283 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1284 i8042_setup_a20_line(i8042, a20_line[0]);
1285 port92_init(port92, a20_line[1]);
1286 g_free(a20_line);
1287 }
1288
1289 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1290 ISADevice **rtc_state,
1291 bool create_fdctrl,
1292 bool no_vmport,
1293 bool has_pit,
1294 uint32_t hpet_irqs)
1295 {
1296 int i;
1297 DeviceState *hpet = NULL;
1298 int pit_isa_irq = 0;
1299 qemu_irq pit_alt_irq = NULL;
1300 qemu_irq rtc_irq = NULL;
1301 ISADevice *pit = NULL;
1302 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1303 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1304
1305 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1306 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1307
1308 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1309 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1310
1311 /*
1312 * Check if an HPET shall be created.
1313 *
1314 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1315 * when the HPET wants to take over. Thus we have to disable the latter.
1316 */
1317 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1318 /* In order to set property, here not using sysbus_try_create_simple */
1319 hpet = qdev_try_create(NULL, TYPE_HPET);
1320 if (hpet) {
1321 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1322 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1323 * IRQ8 and IRQ2.
1324 */
1325 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1326 HPET_INTCAP, NULL);
1327 if (!compat) {
1328 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1329 }
1330 qdev_init_nofail(hpet);
1331 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1332
1333 for (i = 0; i < GSI_NUM_PINS; i++) {
1334 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1335 }
1336 pit_isa_irq = -1;
1337 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1338 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1339 }
1340 }
1341 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1342
1343 qemu_register_boot_set(pc_boot_set, *rtc_state);
1344
1345 if (!xen_enabled() && has_pit) {
1346 if (kvm_pit_in_kernel()) {
1347 pit = kvm_pit_init(isa_bus, 0x40);
1348 } else {
1349 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1350 }
1351 if (hpet) {
1352 /* connect PIT to output control line of the HPET */
1353 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1354 }
1355 pcspk_init(isa_bus, pit);
1356 }
1357
1358 i8257_dma_init(isa_bus, 0);
1359
1360 /* Super I/O */
1361 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1362 }
1363
1364 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1365 {
1366 int i;
1367
1368 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1369 for (i = 0; i < nb_nics; i++) {
1370 NICInfo *nd = &nd_table[i];
1371 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1372
1373 if (g_str_equal(model, "ne2k_isa")) {
1374 pc_init_ne2k_isa(isa_bus, nd);
1375 } else {
1376 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1377 }
1378 }
1379 rom_reset_order_override();
1380 }
1381
1382 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1383 {
1384 qemu_irq *i8259;
1385
1386 if (kvm_pic_in_kernel()) {
1387 i8259 = kvm_i8259_init(isa_bus);
1388 } else if (xen_enabled()) {
1389 i8259 = xen_interrupt_controller_init();
1390 } else {
1391 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1392 }
1393
1394 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1395 i8259_irqs[i] = i8259[i];
1396 }
1397
1398 g_free(i8259);
1399 }
1400
1401 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1402 Error **errp)
1403 {
1404 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1405 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1406 const MachineState *ms = MACHINE(hotplug_dev);
1407 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1408 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1409 Error *local_err = NULL;
1410
1411 /*
1412 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1413 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1414 * addition to cover this case.
1415 */
1416 if (!pcms->acpi_dev || !acpi_enabled) {
1417 error_setg(errp,
1418 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1419 return;
1420 }
1421
1422 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1423 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1424 return;
1425 }
1426
1427 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1428 if (local_err) {
1429 error_propagate(errp, local_err);
1430 return;
1431 }
1432
1433 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1434 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1435 }
1436
1437 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1438 DeviceState *dev, Error **errp)
1439 {
1440 Error *local_err = NULL;
1441 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1442 MachineState *ms = MACHINE(hotplug_dev);
1443 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1444
1445 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1446 if (local_err) {
1447 goto out;
1448 }
1449
1450 if (is_nvdimm) {
1451 nvdimm_plug(ms->nvdimms_state);
1452 }
1453
1454 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1455 out:
1456 error_propagate(errp, local_err);
1457 }
1458
1459 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1460 DeviceState *dev, Error **errp)
1461 {
1462 Error *local_err = NULL;
1463 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1464
1465 /*
1466 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1467 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1468 * addition to cover this case.
1469 */
1470 if (!pcms->acpi_dev || !acpi_enabled) {
1471 error_setg(&local_err,
1472 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1473 goto out;
1474 }
1475
1476 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1477 error_setg(&local_err,
1478 "nvdimm device hot unplug is not supported yet.");
1479 goto out;
1480 }
1481
1482 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1483 &local_err);
1484 out:
1485 error_propagate(errp, local_err);
1486 }
1487
1488 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1489 DeviceState *dev, Error **errp)
1490 {
1491 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1492 Error *local_err = NULL;
1493
1494 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1495 if (local_err) {
1496 goto out;
1497 }
1498
1499 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1500 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1501 out:
1502 error_propagate(errp, local_err);
1503 }
1504
1505 static int pc_apic_cmp(const void *a, const void *b)
1506 {
1507 CPUArchId *apic_a = (CPUArchId *)a;
1508 CPUArchId *apic_b = (CPUArchId *)b;
1509
1510 return apic_a->arch_id - apic_b->arch_id;
1511 }
1512
1513 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1514 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1515 * entry corresponding to CPU's apic_id returns NULL.
1516 */
1517 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1518 {
1519 CPUArchId apic_id, *found_cpu;
1520
1521 apic_id.arch_id = id;
1522 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1523 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1524 pc_apic_cmp);
1525 if (found_cpu && idx) {
1526 *idx = found_cpu - ms->possible_cpus->cpus;
1527 }
1528 return found_cpu;
1529 }
1530
1531 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1532 DeviceState *dev, Error **errp)
1533 {
1534 CPUArchId *found_cpu;
1535 Error *local_err = NULL;
1536 X86CPU *cpu = X86_CPU(dev);
1537 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1538 X86MachineState *x86ms = X86_MACHINE(pcms);
1539
1540 if (pcms->acpi_dev) {
1541 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1542 if (local_err) {
1543 goto out;
1544 }
1545 }
1546
1547 /* increment the number of CPUs */
1548 x86ms->boot_cpus++;
1549 if (x86ms->rtc) {
1550 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1551 }
1552 if (x86ms->fw_cfg) {
1553 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1554 }
1555
1556 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1557 found_cpu->cpu = OBJECT(dev);
1558 out:
1559 error_propagate(errp, local_err);
1560 }
1561 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1562 DeviceState *dev, Error **errp)
1563 {
1564 int idx = -1;
1565 Error *local_err = NULL;
1566 X86CPU *cpu = X86_CPU(dev);
1567 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1568
1569 if (!pcms->acpi_dev) {
1570 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1571 goto out;
1572 }
1573
1574 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1575 assert(idx != -1);
1576 if (idx == 0) {
1577 error_setg(&local_err, "Boot CPU is unpluggable");
1578 goto out;
1579 }
1580
1581 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1582 &local_err);
1583 if (local_err) {
1584 goto out;
1585 }
1586
1587 out:
1588 error_propagate(errp, local_err);
1589
1590 }
1591
1592 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1593 DeviceState *dev, Error **errp)
1594 {
1595 CPUArchId *found_cpu;
1596 Error *local_err = NULL;
1597 X86CPU *cpu = X86_CPU(dev);
1598 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1599 X86MachineState *x86ms = X86_MACHINE(pcms);
1600
1601 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1602 if (local_err) {
1603 goto out;
1604 }
1605
1606 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1607 found_cpu->cpu = NULL;
1608 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1609
1610 /* decrement the number of CPUs */
1611 x86ms->boot_cpus--;
1612 /* Update the number of CPUs in CMOS */
1613 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1614 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1615 out:
1616 error_propagate(errp, local_err);
1617 }
1618
1619 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1620 DeviceState *dev, Error **errp)
1621 {
1622 int idx;
1623 CPUState *cs;
1624 CPUArchId *cpu_slot;
1625 X86CPUTopoInfo topo;
1626 X86CPU *cpu = X86_CPU(dev);
1627 CPUX86State *env = &cpu->env;
1628 MachineState *ms = MACHINE(hotplug_dev);
1629 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1630 X86MachineState *x86ms = X86_MACHINE(pcms);
1631 unsigned int smp_cores = ms->smp.cores;
1632 unsigned int smp_threads = ms->smp.threads;
1633
1634 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1635 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1636 ms->cpu_type);
1637 return;
1638 }
1639
1640 env->nr_dies = x86ms->smp_dies;
1641
1642 /*
1643 * If APIC ID is not set,
1644 * set it based on socket/die/core/thread properties.
1645 */
1646 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1647 int max_socket = (ms->smp.max_cpus - 1) /
1648 smp_threads / smp_cores / x86ms->smp_dies;
1649
1650 /*
1651 * die-id was optional in QEMU 4.0 and older, so keep it optional
1652 * if there's only one die per socket.
1653 */
1654 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1655 cpu->die_id = 0;
1656 }
1657
1658 if (cpu->socket_id < 0) {
1659 error_setg(errp, "CPU socket-id is not set");
1660 return;
1661 } else if (cpu->socket_id > max_socket) {
1662 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1663 cpu->socket_id, max_socket);
1664 return;
1665 }
1666 if (cpu->die_id < 0) {
1667 error_setg(errp, "CPU die-id is not set");
1668 return;
1669 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1670 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1671 cpu->die_id, x86ms->smp_dies - 1);
1672 return;
1673 }
1674 if (cpu->core_id < 0) {
1675 error_setg(errp, "CPU core-id is not set");
1676 return;
1677 } else if (cpu->core_id > (smp_cores - 1)) {
1678 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1679 cpu->core_id, smp_cores - 1);
1680 return;
1681 }
1682 if (cpu->thread_id < 0) {
1683 error_setg(errp, "CPU thread-id is not set");
1684 return;
1685 } else if (cpu->thread_id > (smp_threads - 1)) {
1686 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1687 cpu->thread_id, smp_threads - 1);
1688 return;
1689 }
1690
1691 topo.pkg_id = cpu->socket_id;
1692 topo.die_id = cpu->die_id;
1693 topo.core_id = cpu->core_id;
1694 topo.smt_id = cpu->thread_id;
1695 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
1696 smp_threads, &topo);
1697 }
1698
1699 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1700 if (!cpu_slot) {
1701 MachineState *ms = MACHINE(pcms);
1702
1703 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1704 smp_cores, smp_threads, &topo);
1705 error_setg(errp,
1706 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1707 " APIC ID %" PRIu32 ", valid index range 0:%d",
1708 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
1709 cpu->apic_id, ms->possible_cpus->len - 1);
1710 return;
1711 }
1712
1713 if (cpu_slot->cpu) {
1714 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1715 idx, cpu->apic_id);
1716 return;
1717 }
1718
1719 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1720 * so that machine_query_hotpluggable_cpus would show correct values
1721 */
1722 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1723 * once -smp refactoring is complete and there will be CPU private
1724 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1725 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1726 smp_cores, smp_threads, &topo);
1727 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1728 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1729 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1730 return;
1731 }
1732 cpu->socket_id = topo.pkg_id;
1733
1734 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
1735 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1736 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
1737 return;
1738 }
1739 cpu->die_id = topo.die_id;
1740
1741 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1742 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1743 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1744 return;
1745 }
1746 cpu->core_id = topo.core_id;
1747
1748 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1749 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1750 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1751 return;
1752 }
1753 cpu->thread_id = topo.smt_id;
1754
1755 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1756 !kvm_hv_vpindex_settable()) {
1757 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1758 return;
1759 }
1760
1761 cs = CPU(cpu);
1762 cs->cpu_index = idx;
1763
1764 numa_cpu_pre_plug(cpu_slot, dev, errp);
1765 }
1766
1767 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1768 DeviceState *dev, Error **errp)
1769 {
1770 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1771 Error *local_err = NULL;
1772
1773 if (!hotplug_dev2) {
1774 /*
1775 * Without a bus hotplug handler, we cannot control the plug/unplug
1776 * order. This should never be the case on x86, however better add
1777 * a safety net.
1778 */
1779 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1780 return;
1781 }
1782 /*
1783 * First, see if we can plug this memory device at all. If that
1784 * succeeds, branch of to the actual hotplug handler.
1785 */
1786 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1787 &local_err);
1788 if (!local_err) {
1789 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1790 }
1791 error_propagate(errp, local_err);
1792 }
1793
1794 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1795 DeviceState *dev, Error **errp)
1796 {
1797 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1798 Error *local_err = NULL;
1799
1800 /*
1801 * Plug the memory device first and then branch off to the actual
1802 * hotplug handler. If that one fails, we can easily undo the memory
1803 * device bits.
1804 */
1805 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1806 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1807 if (local_err) {
1808 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1809 }
1810 error_propagate(errp, local_err);
1811 }
1812
1813 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1814 DeviceState *dev, Error **errp)
1815 {
1816 /* We don't support virtio pmem hot unplug */
1817 error_setg(errp, "virtio pmem device unplug not supported.");
1818 }
1819
1820 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1821 DeviceState *dev, Error **errp)
1822 {
1823 /* We don't support virtio pmem hot unplug */
1824 }
1825
1826 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1827 DeviceState *dev, Error **errp)
1828 {
1829 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1830 pc_memory_pre_plug(hotplug_dev, dev, errp);
1831 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1832 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1833 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1834 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1835 }
1836 }
1837
1838 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1839 DeviceState *dev, Error **errp)
1840 {
1841 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1842 pc_memory_plug(hotplug_dev, dev, errp);
1843 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1844 pc_cpu_plug(hotplug_dev, dev, errp);
1845 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1846 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1847 }
1848 }
1849
1850 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1851 DeviceState *dev, Error **errp)
1852 {
1853 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1854 pc_memory_unplug_request(hotplug_dev, dev, errp);
1855 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1856 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1857 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1858 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1859 } else {
1860 error_setg(errp, "acpi: device unplug request for not supported device"
1861 " type: %s", object_get_typename(OBJECT(dev)));
1862 }
1863 }
1864
1865 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1866 DeviceState *dev, Error **errp)
1867 {
1868 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1869 pc_memory_unplug(hotplug_dev, dev, errp);
1870 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1871 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1872 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1873 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1874 } else {
1875 error_setg(errp, "acpi: device unplug for not supported device"
1876 " type: %s", object_get_typename(OBJECT(dev)));
1877 }
1878 }
1879
1880 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1881 DeviceState *dev)
1882 {
1883 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1884 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1885 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1886 return HOTPLUG_HANDLER(machine);
1887 }
1888
1889 return NULL;
1890 }
1891
1892 static void
1893 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1894 const char *name, void *opaque,
1895 Error **errp)
1896 {
1897 MachineState *ms = MACHINE(obj);
1898 int64_t value = 0;
1899
1900 if (ms->device_memory) {
1901 value = memory_region_size(&ms->device_memory->mr);
1902 }
1903
1904 visit_type_int(v, name, &value, errp);
1905 }
1906
1907 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1908 void *opaque, Error **errp)
1909 {
1910 PCMachineState *pcms = PC_MACHINE(obj);
1911 OnOffAuto vmport = pcms->vmport;
1912
1913 visit_type_OnOffAuto(v, name, &vmport, errp);
1914 }
1915
1916 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1917 void *opaque, Error **errp)
1918 {
1919 PCMachineState *pcms = PC_MACHINE(obj);
1920
1921 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1922 }
1923
1924 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1925 {
1926 PCMachineState *pcms = PC_MACHINE(obj);
1927
1928 return pcms->smbus_enabled;
1929 }
1930
1931 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1932 {
1933 PCMachineState *pcms = PC_MACHINE(obj);
1934
1935 pcms->smbus_enabled = value;
1936 }
1937
1938 static bool pc_machine_get_sata(Object *obj, Error **errp)
1939 {
1940 PCMachineState *pcms = PC_MACHINE(obj);
1941
1942 return pcms->sata_enabled;
1943 }
1944
1945 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1946 {
1947 PCMachineState *pcms = PC_MACHINE(obj);
1948
1949 pcms->sata_enabled = value;
1950 }
1951
1952 static bool pc_machine_get_pit(Object *obj, Error **errp)
1953 {
1954 PCMachineState *pcms = PC_MACHINE(obj);
1955
1956 return pcms->pit_enabled;
1957 }
1958
1959 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1960 {
1961 PCMachineState *pcms = PC_MACHINE(obj);
1962
1963 pcms->pit_enabled = value;
1964 }
1965
1966 static void pc_machine_initfn(Object *obj)
1967 {
1968 PCMachineState *pcms = PC_MACHINE(obj);
1969
1970 #ifdef CONFIG_VMPORT
1971 pcms->vmport = ON_OFF_AUTO_AUTO;
1972 #else
1973 pcms->vmport = ON_OFF_AUTO_OFF;
1974 #endif /* CONFIG_VMPORT */
1975 /* acpi build is enabled by default if machine supports it */
1976 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1977 pcms->smbus_enabled = true;
1978 pcms->sata_enabled = true;
1979 pcms->pit_enabled = true;
1980
1981 pc_system_flash_create(pcms);
1982 }
1983
1984 static void pc_machine_reset(MachineState *machine)
1985 {
1986 CPUState *cs;
1987 X86CPU *cpu;
1988
1989 qemu_devices_reset();
1990
1991 /* Reset APIC after devices have been reset to cancel
1992 * any changes that qemu_devices_reset() might have done.
1993 */
1994 CPU_FOREACH(cs) {
1995 cpu = X86_CPU(cs);
1996
1997 if (cpu->apic_state) {
1998 device_reset(cpu->apic_state);
1999 }
2000 }
2001 }
2002
2003 static void pc_machine_wakeup(MachineState *machine)
2004 {
2005 cpu_synchronize_all_states();
2006 pc_machine_reset(machine);
2007 cpu_synchronize_all_post_reset();
2008 }
2009
2010 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
2011 {
2012 X86IOMMUState *iommu = x86_iommu_get_default();
2013 IntelIOMMUState *intel_iommu;
2014
2015 if (iommu &&
2016 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
2017 object_dynamic_cast((Object *)dev, "vfio-pci")) {
2018 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2019 if (!intel_iommu->caching_mode) {
2020 error_setg(errp, "Device assignment is not allowed without "
2021 "enabling caching-mode=on for Intel IOMMU.");
2022 return false;
2023 }
2024 }
2025
2026 return true;
2027 }
2028
2029 static void pc_machine_class_init(ObjectClass *oc, void *data)
2030 {
2031 MachineClass *mc = MACHINE_CLASS(oc);
2032 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2033 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2034
2035 pcmc->pci_enabled = true;
2036 pcmc->has_acpi_build = true;
2037 pcmc->rsdp_in_ram = true;
2038 pcmc->smbios_defaults = true;
2039 pcmc->smbios_uuid_encoded = true;
2040 pcmc->gigabyte_align = true;
2041 pcmc->has_reserved_memory = true;
2042 pcmc->kvmclock_enabled = true;
2043 pcmc->enforce_aligned_dimm = true;
2044 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2045 * to be used at the moment, 32K should be enough for a while. */
2046 pcmc->acpi_data_size = 0x20000 + 0x8000;
2047 pcmc->linuxboot_dma_enabled = true;
2048 pcmc->pvh_enabled = true;
2049 assert(!mc->get_hotplug_handler);
2050 mc->get_hotplug_handler = pc_get_hotplug_handler;
2051 mc->hotplug_allowed = pc_hotplug_allowed;
2052 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
2053 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
2054 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
2055 mc->auto_enable_numa_with_memhp = true;
2056 mc->has_hotpluggable_cpus = true;
2057 mc->default_boot_order = "cad";
2058 mc->hot_add_cpu = pc_hot_add_cpu;
2059 mc->smp_parse = pc_smp_parse;
2060 mc->block_default_type = IF_IDE;
2061 mc->max_cpus = 255;
2062 mc->reset = pc_machine_reset;
2063 mc->wakeup = pc_machine_wakeup;
2064 hc->pre_plug = pc_machine_device_pre_plug_cb;
2065 hc->plug = pc_machine_device_plug_cb;
2066 hc->unplug_request = pc_machine_device_unplug_request_cb;
2067 hc->unplug = pc_machine_device_unplug_cb;
2068 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2069 mc->nvdimm_supported = true;
2070 mc->numa_mem_supported = true;
2071
2072 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2073 pc_machine_get_device_memory_region_size, NULL,
2074 NULL, NULL, &error_abort);
2075
2076 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2077 pc_machine_get_vmport, pc_machine_set_vmport,
2078 NULL, NULL, &error_abort);
2079 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2080 "Enable vmport (pc & q35)", &error_abort);
2081
2082 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2083 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2084
2085 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2086 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2087
2088 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2089 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2090 }
2091
2092 static const TypeInfo pc_machine_info = {
2093 .name = TYPE_PC_MACHINE,
2094 .parent = TYPE_X86_MACHINE,
2095 .abstract = true,
2096 .instance_size = sizeof(PCMachineState),
2097 .instance_init = pc_machine_initfn,
2098 .class_size = sizeof(PCMachineClass),
2099 .class_init = pc_machine_class_init,
2100 .interfaces = (InterfaceInfo[]) {
2101 { TYPE_HOTPLUG_HANDLER },
2102 { }
2103 },
2104 };
2105
2106 static void pc_machine_register_types(void)
2107 {
2108 type_register_static(&pc_machine_info);
2109 }
2110
2111 type_init(pc_machine_register_types)
AR7 emulation for QEMU