?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'v2.10.0-rc0'
[qemu/ar7.git] / target / m68k / translate.c
blobc386008202d87b8290cead8f5cad2bce73401816
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35 //#define DEBUG_DISPATCH 1
36
37 #define DEFO32(name, offset) static TCGv QREG_##name;
38 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
39 #include "qregs.def"
40 #undef DEFO32
41 #undef DEFO64
42
43 static TCGv_i32 cpu_halted;
44 static TCGv_i32 cpu_exception_index;
45
46 static TCGv_env cpu_env;
47
48 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
49 static TCGv cpu_dregs[8];
50 static TCGv cpu_aregs[8];
51 static TCGv_i64 cpu_macc[4];
52
53 #define REG(insn, pos) (((insn) >> (pos)) & 7)
54 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
55 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
56 #define MACREG(acc) cpu_macc[acc]
57 #define QREG_SP get_areg(s, 7)
58
59 static TCGv NULL_QREG;
60 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
61 /* Used to distinguish stores from bad addressing modes. */
62 static TCGv store_dummy;
63
64 #include "exec/gen-icount.h"
65
66 void m68k_tcg_init(void)
67 {
68 char *p;
69 int i;
70
71 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
72 tcg_ctx.tcg_env = cpu_env;
73
74 #define DEFO32(name, offset) \
75 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
76 offsetof(CPUM68KState, offset), #name);
77 #define DEFO64(name, offset) \
78 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
79 offsetof(CPUM68KState, offset), #name);
80 #include "qregs.def"
81 #undef DEFO32
82 #undef DEFO64
83
84 cpu_halted = tcg_global_mem_new_i32(cpu_env,
85 -offsetof(M68kCPU, env) +
86 offsetof(CPUState, halted), "HALTED");
87 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
88 -offsetof(M68kCPU, env) +
89 offsetof(CPUState, exception_index),
90 "EXCEPTION");
91
92 p = cpu_reg_names;
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "D%d", i);
95 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
96 offsetof(CPUM68KState, dregs[i]), p);
97 p += 3;
98 sprintf(p, "A%d", i);
99 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
100 offsetof(CPUM68KState, aregs[i]), p);
101 p += 3;
102 }
103 for (i = 0; i < 4; i++) {
104 sprintf(p, "ACC%d", i);
105 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
106 offsetof(CPUM68KState, macc[i]), p);
107 p += 5;
108 }
109
110 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
111 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
112 }
113
114 /* internal defines */
115 typedef struct DisasContext {
116 CPUM68KState *env;
117 target_ulong insn_pc; /* Start of the current instruction. */
118 target_ulong pc;
119 int is_jmp;
120 CCOp cc_op; /* Current CC operation */
121 int cc_op_synced;
122 int user;
123 struct TranslationBlock *tb;
124 int singlestep_enabled;
125 TCGv_i64 mactmp;
126 int done_mac;
127 int writeback_mask;
128 TCGv writeback[8];
129 } DisasContext;
130
131 static TCGv get_areg(DisasContext *s, unsigned regno)
132 {
133 if (s->writeback_mask & (1 << regno)) {
134 return s->writeback[regno];
135 } else {
136 return cpu_aregs[regno];
137 }
138 }
139
140 static void delay_set_areg(DisasContext *s, unsigned regno,
141 TCGv val, bool give_temp)
142 {
143 if (s->writeback_mask & (1 << regno)) {
144 if (give_temp) {
145 tcg_temp_free(s->writeback[regno]);
146 s->writeback[regno] = val;
147 } else {
148 tcg_gen_mov_i32(s->writeback[regno], val);
149 }
150 } else {
151 s->writeback_mask |= 1 << regno;
152 if (give_temp) {
153 s->writeback[regno] = val;
154 } else {
155 TCGv tmp = tcg_temp_new();
156 s->writeback[regno] = tmp;
157 tcg_gen_mov_i32(tmp, val);
158 }
159 }
160 }
161
162 static void do_writebacks(DisasContext *s)
163 {
164 unsigned mask = s->writeback_mask;
165 if (mask) {
166 s->writeback_mask = 0;
167 do {
168 unsigned regno = ctz32(mask);
169 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
170 tcg_temp_free(s->writeback[regno]);
171 mask &= mask - 1;
172 } while (mask);
173 }
174 }
175
176 #define DISAS_JUMP_NEXT 4
177
178 #if defined(CONFIG_USER_ONLY)
179 #define IS_USER(s) 1
180 #else
181 #define IS_USER(s) s->user
182 #endif
183
184 /* XXX: move that elsewhere */
185 /* ??? Fix exceptions. */
186 static void *gen_throws_exception;
187 #define gen_last_qop NULL
188
189 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
190
191 #ifdef DEBUG_DISPATCH
192 #define DISAS_INSN(name) \
193 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
194 uint16_t insn); \
195 static void disas_##name(CPUM68KState *env, DisasContext *s, \
196 uint16_t insn) \
197 { \
198 qemu_log("Dispatch " #name "\n"); \
199 real_disas_##name(env, s, insn); \
200 } \
201 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
202 uint16_t insn)
203 #else
204 #define DISAS_INSN(name) \
205 static void disas_##name(CPUM68KState *env, DisasContext *s, \
206 uint16_t insn)
207 #endif
208
209 static const uint8_t cc_op_live[CC_OP_NB] = {
210 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
211 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
212 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
213 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
214 [CC_OP_LOGIC] = CCF_X | CCF_N
215 };
216
217 static void set_cc_op(DisasContext *s, CCOp op)
218 {
219 CCOp old_op = s->cc_op;
220 int dead;
221
222 if (old_op == op) {
223 return;
224 }
225 s->cc_op = op;
226 s->cc_op_synced = 0;
227
228 /* Discard CC computation that will no longer be used.
229 Note that X and N are never dead. */
230 dead = cc_op_live[old_op] & ~cc_op_live[op];
231 if (dead & CCF_C) {
232 tcg_gen_discard_i32(QREG_CC_C);
233 }
234 if (dead & CCF_Z) {
235 tcg_gen_discard_i32(QREG_CC_Z);
236 }
237 if (dead & CCF_V) {
238 tcg_gen_discard_i32(QREG_CC_V);
239 }
240 }
241
242 /* Update the CPU env CC_OP state. */
243 static void update_cc_op(DisasContext *s)
244 {
245 if (!s->cc_op_synced) {
246 s->cc_op_synced = 1;
247 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
248 }
249 }
250
251 /* Generate a jump to an immediate address. */
252 static void gen_jmp_im(DisasContext *s, uint32_t dest)
253 {
254 update_cc_op(s);
255 tcg_gen_movi_i32(QREG_PC, dest);
256 s->is_jmp = DISAS_JUMP;
257 }
258
259 /* Generate a jump to the address in qreg DEST. */
260 static void gen_jmp(DisasContext *s, TCGv dest)
261 {
262 update_cc_op(s);
263 tcg_gen_mov_i32(QREG_PC, dest);
264 s->is_jmp = DISAS_JUMP;
265 }
266
267 static void gen_raise_exception(int nr)
268 {
269 TCGv_i32 tmp = tcg_const_i32(nr);
270
271 gen_helper_raise_exception(cpu_env, tmp);
272 tcg_temp_free_i32(tmp);
273 }
274
275 static void gen_exception(DisasContext *s, uint32_t where, int nr)
276 {
277 update_cc_op(s);
278 gen_jmp_im(s, where);
279 gen_raise_exception(nr);
280 }
281
282 static inline void gen_addr_fault(DisasContext *s)
283 {
284 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
285 }
286
287 /* Generate a load from the specified address. Narrow values are
288 sign extended to full register width. */
289 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
290 {
291 TCGv tmp;
292 int index = IS_USER(s);
293 tmp = tcg_temp_new_i32();
294 switch(opsize) {
295 case OS_BYTE:
296 if (sign)
297 tcg_gen_qemu_ld8s(tmp, addr, index);
298 else
299 tcg_gen_qemu_ld8u(tmp, addr, index);
300 break;
301 case OS_WORD:
302 if (sign)
303 tcg_gen_qemu_ld16s(tmp, addr, index);
304 else
305 tcg_gen_qemu_ld16u(tmp, addr, index);
306 break;
307 case OS_LONG:
308 tcg_gen_qemu_ld32u(tmp, addr, index);
309 break;
310 default:
311 g_assert_not_reached();
312 }
313 gen_throws_exception = gen_last_qop;
314 return tmp;
315 }
316
317 /* Generate a store. */
318 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
319 {
320 int index = IS_USER(s);
321 switch(opsize) {
322 case OS_BYTE:
323 tcg_gen_qemu_st8(val, addr, index);
324 break;
325 case OS_WORD:
326 tcg_gen_qemu_st16(val, addr, index);
327 break;
328 case OS_LONG:
329 tcg_gen_qemu_st32(val, addr, index);
330 break;
331 default:
332 g_assert_not_reached();
333 }
334 gen_throws_exception = gen_last_qop;
335 }
336
337 typedef enum {
338 EA_STORE,
339 EA_LOADU,
340 EA_LOADS
341 } ea_what;
342
343 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
344 otherwise generate a store. */
345 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
346 ea_what what)
347 {
348 if (what == EA_STORE) {
349 gen_store(s, opsize, addr, val);
350 return store_dummy;
351 } else {
352 return gen_load(s, opsize, addr, what == EA_LOADS);
353 }
354 }
355
356 /* Read a 16-bit immediate constant */
357 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
358 {
359 uint16_t im;
360 im = cpu_lduw_code(env, s->pc);
361 s->pc += 2;
362 return im;
363 }
364
365 /* Read an 8-bit immediate constant */
366 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
367 {
368 return read_im16(env, s);
369 }
370
371 /* Read a 32-bit immediate constant. */
372 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
373 {
374 uint32_t im;
375 im = read_im16(env, s) << 16;
376 im |= 0xffff & read_im16(env, s);
377 return im;
378 }
379
380 /* Read a 64-bit immediate constant. */
381 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
382 {
383 uint64_t im;
384 im = (uint64_t)read_im32(env, s) << 32;
385 im |= (uint64_t)read_im32(env, s);
386 return im;
387 }
388
389 /* Calculate and address index. */
390 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
391 {
392 TCGv add;
393 int scale;
394
395 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
396 if ((ext & 0x800) == 0) {
397 tcg_gen_ext16s_i32(tmp, add);
398 add = tmp;
399 }
400 scale = (ext >> 9) & 3;
401 if (scale != 0) {
402 tcg_gen_shli_i32(tmp, add, scale);
403 add = tmp;
404 }
405 return add;
406 }
407
408 /* Handle a base + index + displacement effective addresss.
409 A NULL_QREG base means pc-relative. */
410 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
411 {
412 uint32_t offset;
413 uint16_t ext;
414 TCGv add;
415 TCGv tmp;
416 uint32_t bd, od;
417
418 offset = s->pc;
419 ext = read_im16(env, s);
420
421 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
422 return NULL_QREG;
423
424 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
425 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
426 ext &= ~(3 << 9);
427 }
428
429 if (ext & 0x100) {
430 /* full extension word format */
431 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
432 return NULL_QREG;
433
434 if ((ext & 0x30) > 0x10) {
435 /* base displacement */
436 if ((ext & 0x30) == 0x20) {
437 bd = (int16_t)read_im16(env, s);
438 } else {
439 bd = read_im32(env, s);
440 }
441 } else {
442 bd = 0;
443 }
444 tmp = tcg_temp_new();
445 if ((ext & 0x44) == 0) {
446 /* pre-index */
447 add = gen_addr_index(s, ext, tmp);
448 } else {
449 add = NULL_QREG;
450 }
451 if ((ext & 0x80) == 0) {
452 /* base not suppressed */
453 if (IS_NULL_QREG(base)) {
454 base = tcg_const_i32(offset + bd);
455 bd = 0;
456 }
457 if (!IS_NULL_QREG(add)) {
458 tcg_gen_add_i32(tmp, add, base);
459 add = tmp;
460 } else {
461 add = base;
462 }
463 }
464 if (!IS_NULL_QREG(add)) {
465 if (bd != 0) {
466 tcg_gen_addi_i32(tmp, add, bd);
467 add = tmp;
468 }
469 } else {
470 add = tcg_const_i32(bd);
471 }
472 if ((ext & 3) != 0) {
473 /* memory indirect */
474 base = gen_load(s, OS_LONG, add, 0);
475 if ((ext & 0x44) == 4) {
476 add = gen_addr_index(s, ext, tmp);
477 tcg_gen_add_i32(tmp, add, base);
478 add = tmp;
479 } else {
480 add = base;
481 }
482 if ((ext & 3) > 1) {
483 /* outer displacement */
484 if ((ext & 3) == 2) {
485 od = (int16_t)read_im16(env, s);
486 } else {
487 od = read_im32(env, s);
488 }
489 } else {
490 od = 0;
491 }
492 if (od != 0) {
493 tcg_gen_addi_i32(tmp, add, od);
494 add = tmp;
495 }
496 }
497 } else {
498 /* brief extension word format */
499 tmp = tcg_temp_new();
500 add = gen_addr_index(s, ext, tmp);
501 if (!IS_NULL_QREG(base)) {
502 tcg_gen_add_i32(tmp, add, base);
503 if ((int8_t)ext)
504 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
505 } else {
506 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
507 }
508 add = tmp;
509 }
510 return add;
511 }
512
513 /* Sign or zero extend a value. */
514
515 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
516 {
517 switch (opsize) {
518 case OS_BYTE:
519 if (sign) {
520 tcg_gen_ext8s_i32(res, val);
521 } else {
522 tcg_gen_ext8u_i32(res, val);
523 }
524 break;
525 case OS_WORD:
526 if (sign) {
527 tcg_gen_ext16s_i32(res, val);
528 } else {
529 tcg_gen_ext16u_i32(res, val);
530 }
531 break;
532 case OS_LONG:
533 tcg_gen_mov_i32(res, val);
534 break;
535 default:
536 g_assert_not_reached();
537 }
538 }
539
540 /* Evaluate all the CC flags. */
541
542 static void gen_flush_flags(DisasContext *s)
543 {
544 TCGv t0, t1;
545
546 switch (s->cc_op) {
547 case CC_OP_FLAGS:
548 return;
549
550 case CC_OP_ADDB:
551 case CC_OP_ADDW:
552 case CC_OP_ADDL:
553 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
554 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
555 /* Compute signed overflow for addition. */
556 t0 = tcg_temp_new();
557 t1 = tcg_temp_new();
558 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
559 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
560 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
561 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
562 tcg_temp_free(t0);
563 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
564 tcg_temp_free(t1);
565 break;
566
567 case CC_OP_SUBB:
568 case CC_OP_SUBW:
569 case CC_OP_SUBL:
570 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
571 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
572 /* Compute signed overflow for subtraction. */
573 t0 = tcg_temp_new();
574 t1 = tcg_temp_new();
575 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
576 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
577 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
578 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
579 tcg_temp_free(t0);
580 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
581 tcg_temp_free(t1);
582 break;
583
584 case CC_OP_CMPB:
585 case CC_OP_CMPW:
586 case CC_OP_CMPL:
587 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
588 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
589 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
590 /* Compute signed overflow for subtraction. */
591 t0 = tcg_temp_new();
592 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
593 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
594 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
595 tcg_temp_free(t0);
596 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
597 break;
598
599 case CC_OP_LOGIC:
600 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
601 tcg_gen_movi_i32(QREG_CC_C, 0);
602 tcg_gen_movi_i32(QREG_CC_V, 0);
603 break;
604
605 case CC_OP_DYNAMIC:
606 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
607 s->cc_op_synced = 1;
608 break;
609
610 default:
611 t0 = tcg_const_i32(s->cc_op);
612 gen_helper_flush_flags(cpu_env, t0);
613 tcg_temp_free(t0);
614 s->cc_op_synced = 1;
615 break;
616 }
617
618 /* Note that flush_flags also assigned to env->cc_op. */
619 s->cc_op = CC_OP_FLAGS;
620 }
621
622 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
623 {
624 TCGv tmp;
625
626 if (opsize == OS_LONG) {
627 tmp = val;
628 } else {
629 tmp = tcg_temp_new();
630 gen_ext(tmp, val, opsize, sign);
631 }
632
633 return tmp;
634 }
635
636 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
637 {
638 gen_ext(QREG_CC_N, val, opsize, 1);
639 set_cc_op(s, CC_OP_LOGIC);
640 }
641
642 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
643 {
644 tcg_gen_mov_i32(QREG_CC_N, dest);
645 tcg_gen_mov_i32(QREG_CC_V, src);
646 set_cc_op(s, CC_OP_CMPB + opsize);
647 }
648
649 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
650 {
651 gen_ext(QREG_CC_N, dest, opsize, 1);
652 tcg_gen_mov_i32(QREG_CC_V, src);
653 }
654
655 static inline int opsize_bytes(int opsize)
656 {
657 switch (opsize) {
658 case OS_BYTE: return 1;
659 case OS_WORD: return 2;
660 case OS_LONG: return 4;
661 case OS_SINGLE: return 4;
662 case OS_DOUBLE: return 8;
663 case OS_EXTENDED: return 12;
664 case OS_PACKED: return 12;
665 default:
666 g_assert_not_reached();
667 }
668 }
669
670 static inline int insn_opsize(int insn)
671 {
672 switch ((insn >> 6) & 3) {
673 case 0: return OS_BYTE;
674 case 1: return OS_WORD;
675 case 2: return OS_LONG;
676 default:
677 g_assert_not_reached();
678 }
679 /* Should never happen. */
680 return -1;
681 }
682
683 static inline int ext_opsize(int ext, int pos)
684 {
685 switch ((ext >> pos) & 7) {
686 case 0: return OS_LONG;
687 case 1: return OS_SINGLE;
688 case 2: return OS_EXTENDED;
689 case 3: return OS_PACKED;
690 case 4: return OS_WORD;
691 case 5: return OS_DOUBLE;
692 case 6: return OS_BYTE;
693 default:
694 g_assert_not_reached();
695 }
696 }
697
698 /* Assign value to a register. If the width is less than the register width
699 only the low part of the register is set. */
700 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
701 {
702 TCGv tmp;
703 switch (opsize) {
704 case OS_BYTE:
705 tcg_gen_andi_i32(reg, reg, 0xffffff00);
706 tmp = tcg_temp_new();
707 tcg_gen_ext8u_i32(tmp, val);
708 tcg_gen_or_i32(reg, reg, tmp);
709 tcg_temp_free(tmp);
710 break;
711 case OS_WORD:
712 tcg_gen_andi_i32(reg, reg, 0xffff0000);
713 tmp = tcg_temp_new();
714 tcg_gen_ext16u_i32(tmp, val);
715 tcg_gen_or_i32(reg, reg, tmp);
716 tcg_temp_free(tmp);
717 break;
718 case OS_LONG:
719 case OS_SINGLE:
720 tcg_gen_mov_i32(reg, val);
721 break;
722 default:
723 g_assert_not_reached();
724 }
725 }
726
727 /* Generate code for an "effective address". Does not adjust the base
728 register for autoincrement addressing modes. */
729 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
730 int mode, int reg0, int opsize)
731 {
732 TCGv reg;
733 TCGv tmp;
734 uint16_t ext;
735 uint32_t offset;
736
737 switch (mode) {
738 case 0: /* Data register direct. */
739 case 1: /* Address register direct. */
740 return NULL_QREG;
741 case 3: /* Indirect postincrement. */
742 if (opsize == OS_UNSIZED) {
743 return NULL_QREG;
744 }
745 /* fallthru */
746 case 2: /* Indirect register */
747 return get_areg(s, reg0);
748 case 4: /* Indirect predecrememnt. */
749 if (opsize == OS_UNSIZED) {
750 return NULL_QREG;
751 }
752 reg = get_areg(s, reg0);
753 tmp = tcg_temp_new();
754 if (reg0 == 7 && opsize == OS_BYTE &&
755 m68k_feature(s->env, M68K_FEATURE_M68000)) {
756 tcg_gen_subi_i32(tmp, reg, 2);
757 } else {
758 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
759 }
760 return tmp;
761 case 5: /* Indirect displacement. */
762 reg = get_areg(s, reg0);
763 tmp = tcg_temp_new();
764 ext = read_im16(env, s);
765 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
766 return tmp;
767 case 6: /* Indirect index + displacement. */
768 reg = get_areg(s, reg0);
769 return gen_lea_indexed(env, s, reg);
770 case 7: /* Other */
771 switch (reg0) {
772 case 0: /* Absolute short. */
773 offset = (int16_t)read_im16(env, s);
774 return tcg_const_i32(offset);
775 case 1: /* Absolute long. */
776 offset = read_im32(env, s);
777 return tcg_const_i32(offset);
778 case 2: /* pc displacement */
779 offset = s->pc;
780 offset += (int16_t)read_im16(env, s);
781 return tcg_const_i32(offset);
782 case 3: /* pc index+displacement. */
783 return gen_lea_indexed(env, s, NULL_QREG);
784 case 4: /* Immediate. */
785 default:
786 return NULL_QREG;
787 }
788 }
789 /* Should never happen. */
790 return NULL_QREG;
791 }
792
793 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
794 int opsize)
795 {
796 int mode = extract32(insn, 3, 3);
797 int reg0 = REG(insn, 0);
798 return gen_lea_mode(env, s, mode, reg0, opsize);
799 }
800
801 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
802 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
803 ADDRP is non-null for readwrite operands. */
804 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
805 int opsize, TCGv val, TCGv *addrp, ea_what what)
806 {
807 TCGv reg, tmp, result;
808 int32_t offset;
809
810 switch (mode) {
811 case 0: /* Data register direct. */
812 reg = cpu_dregs[reg0];
813 if (what == EA_STORE) {
814 gen_partset_reg(opsize, reg, val);
815 return store_dummy;
816 } else {
817 return gen_extend(reg, opsize, what == EA_LOADS);
818 }
819 case 1: /* Address register direct. */
820 reg = get_areg(s, reg0);
821 if (what == EA_STORE) {
822 tcg_gen_mov_i32(reg, val);
823 return store_dummy;
824 } else {
825 return gen_extend(reg, opsize, what == EA_LOADS);
826 }
827 case 2: /* Indirect register */
828 reg = get_areg(s, reg0);
829 return gen_ldst(s, opsize, reg, val, what);
830 case 3: /* Indirect postincrement. */
831 reg = get_areg(s, reg0);
832 result = gen_ldst(s, opsize, reg, val, what);
833 if (what == EA_STORE || !addrp) {
834 TCGv tmp = tcg_temp_new();
835 if (reg0 == 7 && opsize == OS_BYTE &&
836 m68k_feature(s->env, M68K_FEATURE_M68000)) {
837 tcg_gen_addi_i32(tmp, reg, 2);
838 } else {
839 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
840 }
841 delay_set_areg(s, reg0, tmp, true);
842 }
843 return result;
844 case 4: /* Indirect predecrememnt. */
845 if (addrp && what == EA_STORE) {
846 tmp = *addrp;
847 } else {
848 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
849 if (IS_NULL_QREG(tmp)) {
850 return tmp;
851 }
852 if (addrp) {
853 *addrp = tmp;
854 }
855 }
856 result = gen_ldst(s, opsize, tmp, val, what);
857 if (what == EA_STORE || !addrp) {
858 delay_set_areg(s, reg0, tmp, false);
859 }
860 return result;
861 case 5: /* Indirect displacement. */
862 case 6: /* Indirect index + displacement. */
863 do_indirect:
864 if (addrp && what == EA_STORE) {
865 tmp = *addrp;
866 } else {
867 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
868 if (IS_NULL_QREG(tmp)) {
869 return tmp;
870 }
871 if (addrp) {
872 *addrp = tmp;
873 }
874 }
875 return gen_ldst(s, opsize, tmp, val, what);
876 case 7: /* Other */
877 switch (reg0) {
878 case 0: /* Absolute short. */
879 case 1: /* Absolute long. */
880 case 2: /* pc displacement */
881 case 3: /* pc index+displacement. */
882 goto do_indirect;
883 case 4: /* Immediate. */
884 /* Sign extend values for consistency. */
885 switch (opsize) {
886 case OS_BYTE:
887 if (what == EA_LOADS) {
888 offset = (int8_t)read_im8(env, s);
889 } else {
890 offset = read_im8(env, s);
891 }
892 break;
893 case OS_WORD:
894 if (what == EA_LOADS) {
895 offset = (int16_t)read_im16(env, s);
896 } else {
897 offset = read_im16(env, s);
898 }
899 break;
900 case OS_LONG:
901 offset = read_im32(env, s);
902 break;
903 default:
904 g_assert_not_reached();
905 }
906 return tcg_const_i32(offset);
907 default:
908 return NULL_QREG;
909 }
910 }
911 /* Should never happen. */
912 return NULL_QREG;
913 }
914
915 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
916 int opsize, TCGv val, TCGv *addrp, ea_what what)
917 {
918 int mode = extract32(insn, 3, 3);
919 int reg0 = REG(insn, 0);
920 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
921 }
922
923 static TCGv_ptr gen_fp_ptr(int freg)
924 {
925 TCGv_ptr fp = tcg_temp_new_ptr();
926 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
927 return fp;
928 }
929
930 static TCGv_ptr gen_fp_result_ptr(void)
931 {
932 TCGv_ptr fp = tcg_temp_new_ptr();
933 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
934 return fp;
935 }
936
937 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
938 {
939 TCGv t32;
940 TCGv_i64 t64;
941
942 t32 = tcg_temp_new();
943 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
944 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
945 tcg_temp_free(t32);
946
947 t64 = tcg_temp_new_i64();
948 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
949 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
950 tcg_temp_free_i64(t64);
951 }
952
953 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
954 {
955 TCGv tmp;
956 TCGv_i64 t64;
957 int index = IS_USER(s);
958
959 t64 = tcg_temp_new_i64();
960 tmp = tcg_temp_new();
961 switch (opsize) {
962 case OS_BYTE:
963 tcg_gen_qemu_ld8s(tmp, addr, index);
964 gen_helper_exts32(cpu_env, fp, tmp);
965 break;
966 case OS_WORD:
967 tcg_gen_qemu_ld16s(tmp, addr, index);
968 gen_helper_exts32(cpu_env, fp, tmp);
969 break;
970 case OS_LONG:
971 tcg_gen_qemu_ld32u(tmp, addr, index);
972 gen_helper_exts32(cpu_env, fp, tmp);
973 break;
974 case OS_SINGLE:
975 tcg_gen_qemu_ld32u(tmp, addr, index);
976 gen_helper_extf32(cpu_env, fp, tmp);
977 break;
978 case OS_DOUBLE:
979 tcg_gen_qemu_ld64(t64, addr, index);
980 gen_helper_extf64(cpu_env, fp, t64);
981 tcg_temp_free_i64(t64);
982 break;
983 case OS_EXTENDED:
984 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
985 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
986 break;
987 }
988 tcg_gen_qemu_ld32u(tmp, addr, index);
989 tcg_gen_shri_i32(tmp, tmp, 16);
990 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
991 tcg_gen_addi_i32(tmp, addr, 4);
992 tcg_gen_qemu_ld64(t64, tmp, index);
993 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
994 break;
995 case OS_PACKED:
996 /* unimplemented data type on 68040/ColdFire
997 * FIXME if needed for another FPU
998 */
999 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1000 break;
1001 default:
1002 g_assert_not_reached();
1003 }
1004 tcg_temp_free(tmp);
1005 tcg_temp_free_i64(t64);
1006 gen_throws_exception = gen_last_qop;
1007 }
1008
1009 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
1010 {
1011 TCGv tmp;
1012 TCGv_i64 t64;
1013 int index = IS_USER(s);
1014
1015 t64 = tcg_temp_new_i64();
1016 tmp = tcg_temp_new();
1017 switch (opsize) {
1018 case OS_BYTE:
1019 gen_helper_reds32(tmp, cpu_env, fp);
1020 tcg_gen_qemu_st8(tmp, addr, index);
1021 break;
1022 case OS_WORD:
1023 gen_helper_reds32(tmp, cpu_env, fp);
1024 tcg_gen_qemu_st16(tmp, addr, index);
1025 break;
1026 case OS_LONG:
1027 gen_helper_reds32(tmp, cpu_env, fp);
1028 tcg_gen_qemu_st32(tmp, addr, index);
1029 break;
1030 case OS_SINGLE:
1031 gen_helper_redf32(tmp, cpu_env, fp);
1032 tcg_gen_qemu_st32(tmp, addr, index);
1033 break;
1034 case OS_DOUBLE:
1035 gen_helper_redf64(t64, cpu_env, fp);
1036 tcg_gen_qemu_st64(t64, addr, index);
1037 break;
1038 case OS_EXTENDED:
1039 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1040 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1041 break;
1042 }
1043 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1044 tcg_gen_shli_i32(tmp, tmp, 16);
1045 tcg_gen_qemu_st32(tmp, addr, index);
1046 tcg_gen_addi_i32(tmp, addr, 4);
1047 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1048 tcg_gen_qemu_st64(t64, tmp, index);
1049 break;
1050 case OS_PACKED:
1051 /* unimplemented data type on 68040/ColdFire
1052 * FIXME if needed for another FPU
1053 */
1054 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1055 break;
1056 default:
1057 g_assert_not_reached();
1058 }
1059 tcg_temp_free(tmp);
1060 tcg_temp_free_i64(t64);
1061 gen_throws_exception = gen_last_qop;
1062 }
1063
1064 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1065 TCGv_ptr fp, ea_what what)
1066 {
1067 if (what == EA_STORE) {
1068 gen_store_fp(s, opsize, addr, fp);
1069 } else {
1070 gen_load_fp(s, opsize, addr, fp);
1071 }
1072 }
1073
1074 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1075 int reg0, int opsize, TCGv_ptr fp, ea_what what)
1076 {
1077 TCGv reg, addr, tmp;
1078 TCGv_i64 t64;
1079
1080 switch (mode) {
1081 case 0: /* Data register direct. */
1082 reg = cpu_dregs[reg0];
1083 if (what == EA_STORE) {
1084 switch (opsize) {
1085 case OS_BYTE:
1086 case OS_WORD:
1087 case OS_LONG:
1088 gen_helper_reds32(reg, cpu_env, fp);
1089 break;
1090 case OS_SINGLE:
1091 gen_helper_redf32(reg, cpu_env, fp);
1092 break;
1093 default:
1094 g_assert_not_reached();
1095 }
1096 } else {
1097 tmp = tcg_temp_new();
1098 switch (opsize) {
1099 case OS_BYTE:
1100 tcg_gen_ext8s_i32(tmp, reg);
1101 gen_helper_exts32(cpu_env, fp, tmp);
1102 break;
1103 case OS_WORD:
1104 tcg_gen_ext16s_i32(tmp, reg);
1105 gen_helper_exts32(cpu_env, fp, tmp);
1106 break;
1107 case OS_LONG:
1108 gen_helper_exts32(cpu_env, fp, reg);
1109 break;
1110 case OS_SINGLE:
1111 gen_helper_extf32(cpu_env, fp, reg);
1112 break;
1113 default:
1114 g_assert_not_reached();
1115 }
1116 tcg_temp_free(tmp);
1117 }
1118 return 0;
1119 case 1: /* Address register direct. */
1120 return -1;
1121 case 2: /* Indirect register */
1122 addr = get_areg(s, reg0);
1123 gen_ldst_fp(s, opsize, addr, fp, what);
1124 return 0;
1125 case 3: /* Indirect postincrement. */
1126 addr = cpu_aregs[reg0];
1127 gen_ldst_fp(s, opsize, addr, fp, what);
1128 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1129 return 0;
1130 case 4: /* Indirect predecrememnt. */
1131 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1132 if (IS_NULL_QREG(addr)) {
1133 return -1;
1134 }
1135 gen_ldst_fp(s, opsize, addr, fp, what);
1136 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1137 return 0;
1138 case 5: /* Indirect displacement. */
1139 case 6: /* Indirect index + displacement. */
1140 do_indirect:
1141 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1142 if (IS_NULL_QREG(addr)) {
1143 return -1;
1144 }
1145 gen_ldst_fp(s, opsize, addr, fp, what);
1146 return 0;
1147 case 7: /* Other */
1148 switch (reg0) {
1149 case 0: /* Absolute short. */
1150 case 1: /* Absolute long. */
1151 case 2: /* pc displacement */
1152 case 3: /* pc index+displacement. */
1153 goto do_indirect;
1154 case 4: /* Immediate. */
1155 if (what == EA_STORE) {
1156 return -1;
1157 }
1158 switch (opsize) {
1159 case OS_BYTE:
1160 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1161 gen_helper_exts32(cpu_env, fp, tmp);
1162 tcg_temp_free(tmp);
1163 break;
1164 case OS_WORD:
1165 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1166 gen_helper_exts32(cpu_env, fp, tmp);
1167 tcg_temp_free(tmp);
1168 break;
1169 case OS_LONG:
1170 tmp = tcg_const_i32(read_im32(env, s));
1171 gen_helper_exts32(cpu_env, fp, tmp);
1172 tcg_temp_free(tmp);
1173 break;
1174 case OS_SINGLE:
1175 tmp = tcg_const_i32(read_im32(env, s));
1176 gen_helper_extf32(cpu_env, fp, tmp);
1177 tcg_temp_free(tmp);
1178 break;
1179 case OS_DOUBLE:
1180 t64 = tcg_const_i64(read_im64(env, s));
1181 gen_helper_extf64(cpu_env, fp, t64);
1182 tcg_temp_free_i64(t64);
1183 break;
1184 case OS_EXTENDED:
1185 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1186 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1187 break;
1188 }
1189 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1190 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1191 tcg_temp_free(tmp);
1192 t64 = tcg_const_i64(read_im64(env, s));
1193 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1194 tcg_temp_free_i64(t64);
1195 break;
1196 case OS_PACKED:
1197 /* unimplemented data type on 68040/ColdFire
1198 * FIXME if needed for another FPU
1199 */
1200 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1201 break;
1202 default:
1203 g_assert_not_reached();
1204 }
1205 return 0;
1206 default:
1207 return -1;
1208 }
1209 }
1210 return -1;
1211 }
1212
1213 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1214 int opsize, TCGv_ptr fp, ea_what what)
1215 {
1216 int mode = extract32(insn, 3, 3);
1217 int reg0 = REG(insn, 0);
1218 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what);
1219 }
1220
1221 typedef struct {
1222 TCGCond tcond;
1223 bool g1;
1224 bool g2;
1225 TCGv v1;
1226 TCGv v2;
1227 } DisasCompare;
1228
1229 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1230 {
1231 TCGv tmp, tmp2;
1232 TCGCond tcond;
1233 CCOp op = s->cc_op;
1234
1235 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1236 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1237 c->g1 = c->g2 = 1;
1238 c->v1 = QREG_CC_N;
1239 c->v2 = QREG_CC_V;
1240 switch (cond) {
1241 case 2: /* HI */
1242 case 3: /* LS */
1243 tcond = TCG_COND_LEU;
1244 goto done;
1245 case 4: /* CC */
1246 case 5: /* CS */
1247 tcond = TCG_COND_LTU;
1248 goto done;
1249 case 6: /* NE */
1250 case 7: /* EQ */
1251 tcond = TCG_COND_EQ;
1252 goto done;
1253 case 10: /* PL */
1254 case 11: /* MI */
1255 c->g1 = c->g2 = 0;
1256 c->v2 = tcg_const_i32(0);
1257 c->v1 = tmp = tcg_temp_new();
1258 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1259 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1260 /* fallthru */
1261 case 12: /* GE */
1262 case 13: /* LT */
1263 tcond = TCG_COND_LT;
1264 goto done;
1265 case 14: /* GT */
1266 case 15: /* LE */
1267 tcond = TCG_COND_LE;
1268 goto done;
1269 }
1270 }
1271
1272 c->g1 = 1;
1273 c->g2 = 0;
1274 c->v2 = tcg_const_i32(0);
1275
1276 switch (cond) {
1277 case 0: /* T */
1278 case 1: /* F */
1279 c->v1 = c->v2;
1280 tcond = TCG_COND_NEVER;
1281 goto done;
1282 case 14: /* GT (!(Z || (N ^ V))) */
1283 case 15: /* LE (Z || (N ^ V)) */
1284 /* Logic operations clear V, which simplifies LE to (Z || N),
1285 and since Z and N are co-located, this becomes a normal
1286 comparison vs N. */
1287 if (op == CC_OP_LOGIC) {
1288 c->v1 = QREG_CC_N;
1289 tcond = TCG_COND_LE;
1290 goto done;
1291 }
1292 break;
1293 case 12: /* GE (!(N ^ V)) */
1294 case 13: /* LT (N ^ V) */
1295 /* Logic operations clear V, which simplifies this to N. */
1296 if (op != CC_OP_LOGIC) {
1297 break;
1298 }
1299 /* fallthru */
1300 case 10: /* PL (!N) */
1301 case 11: /* MI (N) */
1302 /* Several cases represent N normally. */
1303 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1304 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1305 op == CC_OP_LOGIC) {
1306 c->v1 = QREG_CC_N;
1307 tcond = TCG_COND_LT;
1308 goto done;
1309 }
1310 break;
1311 case 6: /* NE (!Z) */
1312 case 7: /* EQ (Z) */
1313 /* Some cases fold Z into N. */
1314 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1315 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1316 op == CC_OP_LOGIC) {
1317 tcond = TCG_COND_EQ;
1318 c->v1 = QREG_CC_N;
1319 goto done;
1320 }
1321 break;
1322 case 4: /* CC (!C) */
1323 case 5: /* CS (C) */
1324 /* Some cases fold C into X. */
1325 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1326 op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) {
1327 tcond = TCG_COND_NE;
1328 c->v1 = QREG_CC_X;
1329 goto done;
1330 }
1331 /* fallthru */
1332 case 8: /* VC (!V) */
1333 case 9: /* VS (V) */
1334 /* Logic operations clear V and C. */
1335 if (op == CC_OP_LOGIC) {
1336 tcond = TCG_COND_NEVER;
1337 c->v1 = c->v2;
1338 goto done;
1339 }
1340 break;
1341 }
1342
1343 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1344 gen_flush_flags(s);
1345
1346 switch (cond) {
1347 case 0: /* T */
1348 case 1: /* F */
1349 default:
1350 /* Invalid, or handled above. */
1351 abort();
1352 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1353 case 3: /* LS (C || Z) */
1354 c->v1 = tmp = tcg_temp_new();
1355 c->g1 = 0;
1356 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1357 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1358 tcond = TCG_COND_NE;
1359 break;
1360 case 4: /* CC (!C) */
1361 case 5: /* CS (C) */
1362 c->v1 = QREG_CC_C;
1363 tcond = TCG_COND_NE;
1364 break;
1365 case 6: /* NE (!Z) */
1366 case 7: /* EQ (Z) */
1367 c->v1 = QREG_CC_Z;
1368 tcond = TCG_COND_EQ;
1369 break;
1370 case 8: /* VC (!V) */
1371 case 9: /* VS (V) */
1372 c->v1 = QREG_CC_V;
1373 tcond = TCG_COND_LT;
1374 break;
1375 case 10: /* PL (!N) */
1376 case 11: /* MI (N) */
1377 c->v1 = QREG_CC_N;
1378 tcond = TCG_COND_LT;
1379 break;
1380 case 12: /* GE (!(N ^ V)) */
1381 case 13: /* LT (N ^ V) */
1382 c->v1 = tmp = tcg_temp_new();
1383 c->g1 = 0;
1384 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1385 tcond = TCG_COND_LT;
1386 break;
1387 case 14: /* GT (!(Z || (N ^ V))) */
1388 case 15: /* LE (Z || (N ^ V)) */
1389 c->v1 = tmp = tcg_temp_new();
1390 c->g1 = 0;
1391 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1392 tcg_gen_neg_i32(tmp, tmp);
1393 tmp2 = tcg_temp_new();
1394 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1395 tcg_gen_or_i32(tmp, tmp, tmp2);
1396 tcg_temp_free(tmp2);
1397 tcond = TCG_COND_LT;
1398 break;
1399 }
1400
1401 done:
1402 if ((cond & 1) == 0) {
1403 tcond = tcg_invert_cond(tcond);
1404 }
1405 c->tcond = tcond;
1406 }
1407
1408 static void free_cond(DisasCompare *c)
1409 {
1410 if (!c->g1) {
1411 tcg_temp_free(c->v1);
1412 }
1413 if (!c->g2) {
1414 tcg_temp_free(c->v2);
1415 }
1416 }
1417
1418 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1419 {
1420 DisasCompare c;
1421
1422 gen_cc_cond(&c, s, cond);
1423 update_cc_op(s);
1424 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1425 free_cond(&c);
1426 }
1427
1428 /* Force a TB lookup after an instruction that changes the CPU state. */
1429 static void gen_lookup_tb(DisasContext *s)
1430 {
1431 update_cc_op(s);
1432 tcg_gen_movi_i32(QREG_PC, s->pc);
1433 s->is_jmp = DISAS_UPDATE;
1434 }
1435
1436 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1437 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1438 op_sign ? EA_LOADS : EA_LOADU); \
1439 if (IS_NULL_QREG(result)) { \
1440 gen_addr_fault(s); \
1441 return; \
1442 } \
1443 } while (0)
1444
1445 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1446 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1447 if (IS_NULL_QREG(ea_result)) { \
1448 gen_addr_fault(s); \
1449 return; \
1450 } \
1451 } while (0)
1452
1453 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1454 {
1455 #ifndef CONFIG_USER_ONLY
1456 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1457 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1458 #else
1459 return true;
1460 #endif
1461 }
1462
1463 /* Generate a jump to an immediate address. */
1464 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1465 {
1466 if (unlikely(s->singlestep_enabled)) {
1467 gen_exception(s, dest, EXCP_DEBUG);
1468 } else if (use_goto_tb(s, dest)) {
1469 tcg_gen_goto_tb(n);
1470 tcg_gen_movi_i32(QREG_PC, dest);
1471 tcg_gen_exit_tb((uintptr_t)s->tb + n);
1472 } else {
1473 gen_jmp_im(s, dest);
1474 tcg_gen_exit_tb(0);
1475 }
1476 s->is_jmp = DISAS_TB_JUMP;
1477 }
1478
1479 DISAS_INSN(scc)
1480 {
1481 DisasCompare c;
1482 int cond;
1483 TCGv tmp;
1484
1485 cond = (insn >> 8) & 0xf;
1486 gen_cc_cond(&c, s, cond);
1487
1488 tmp = tcg_temp_new();
1489 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1490 free_cond(&c);
1491
1492 tcg_gen_neg_i32(tmp, tmp);
1493 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1494 tcg_temp_free(tmp);
1495 }
1496
1497 DISAS_INSN(dbcc)
1498 {
1499 TCGLabel *l1;
1500 TCGv reg;
1501 TCGv tmp;
1502 int16_t offset;
1503 uint32_t base;
1504
1505 reg = DREG(insn, 0);
1506 base = s->pc;
1507 offset = (int16_t)read_im16(env, s);
1508 l1 = gen_new_label();
1509 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1510
1511 tmp = tcg_temp_new();
1512 tcg_gen_ext16s_i32(tmp, reg);
1513 tcg_gen_addi_i32(tmp, tmp, -1);
1514 gen_partset_reg(OS_WORD, reg, tmp);
1515 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1516 gen_jmp_tb(s, 1, base + offset);
1517 gen_set_label(l1);
1518 gen_jmp_tb(s, 0, s->pc);
1519 }
1520
1521 DISAS_INSN(undef_mac)
1522 {
1523 gen_exception(s, s->pc - 2, EXCP_LINEA);
1524 }
1525
1526 DISAS_INSN(undef_fpu)
1527 {
1528 gen_exception(s, s->pc - 2, EXCP_LINEF);
1529 }
1530
1531 DISAS_INSN(undef)
1532 {
1533 /* ??? This is both instructions that are as yet unimplemented
1534 for the 680x0 series, as well as those that are implemented
1535 but actually illegal for CPU32 or pre-68020. */
1536 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
1537 insn, s->pc - 2);
1538 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
1539 }
1540
1541 DISAS_INSN(mulw)
1542 {
1543 TCGv reg;
1544 TCGv tmp;
1545 TCGv src;
1546 int sign;
1547
1548 sign = (insn & 0x100) != 0;
1549 reg = DREG(insn, 9);
1550 tmp = tcg_temp_new();
1551 if (sign)
1552 tcg_gen_ext16s_i32(tmp, reg);
1553 else
1554 tcg_gen_ext16u_i32(tmp, reg);
1555 SRC_EA(env, src, OS_WORD, sign, NULL);
1556 tcg_gen_mul_i32(tmp, tmp, src);
1557 tcg_gen_mov_i32(reg, tmp);
1558 gen_logic_cc(s, tmp, OS_LONG);
1559 tcg_temp_free(tmp);
1560 }
1561
1562 DISAS_INSN(divw)
1563 {
1564 int sign;
1565 TCGv src;
1566 TCGv destr;
1567
1568 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1569
1570 sign = (insn & 0x100) != 0;
1571
1572 /* dest.l / src.w */
1573
1574 SRC_EA(env, src, OS_WORD, sign, NULL);
1575 destr = tcg_const_i32(REG(insn, 9));
1576 if (sign) {
1577 gen_helper_divsw(cpu_env, destr, src);
1578 } else {
1579 gen_helper_divuw(cpu_env, destr, src);
1580 }
1581 tcg_temp_free(destr);
1582
1583 set_cc_op(s, CC_OP_FLAGS);
1584 }
1585
1586 DISAS_INSN(divl)
1587 {
1588 TCGv num, reg, den;
1589 int sign;
1590 uint16_t ext;
1591
1592 ext = read_im16(env, s);
1593
1594 sign = (ext & 0x0800) != 0;
1595
1596 if (ext & 0x400) {
1597 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1598 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
1599 return;
1600 }
1601
1602 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1603
1604 SRC_EA(env, den, OS_LONG, 0, NULL);
1605 num = tcg_const_i32(REG(ext, 12));
1606 reg = tcg_const_i32(REG(ext, 0));
1607 if (sign) {
1608 gen_helper_divsll(cpu_env, num, reg, den);
1609 } else {
1610 gen_helper_divull(cpu_env, num, reg, den);
1611 }
1612 tcg_temp_free(reg);
1613 tcg_temp_free(num);
1614 set_cc_op(s, CC_OP_FLAGS);
1615 return;
1616 }
1617
1618 /* divX.l <EA>, Dq 32/32 -> 32q */
1619 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1620
1621 SRC_EA(env, den, OS_LONG, 0, NULL);
1622 num = tcg_const_i32(REG(ext, 12));
1623 reg = tcg_const_i32(REG(ext, 0));
1624 if (sign) {
1625 gen_helper_divsl(cpu_env, num, reg, den);
1626 } else {
1627 gen_helper_divul(cpu_env, num, reg, den);
1628 }
1629 tcg_temp_free(reg);
1630 tcg_temp_free(num);
1631
1632 set_cc_op(s, CC_OP_FLAGS);
1633 }
1634
1635 static void bcd_add(TCGv dest, TCGv src)
1636 {
1637 TCGv t0, t1;
1638
1639 /* dest10 = dest10 + src10 + X
1640 *
1641 * t1 = src
1642 * t2 = t1 + 0x066
1643 * t3 = t2 + dest + X
1644 * t4 = t2 ^ dest
1645 * t5 = t3 ^ t4
1646 * t6 = ~t5 & 0x110
1647 * t7 = (t6 >> 2) | (t6 >> 3)
1648 * return t3 - t7
1649 */
1650
1651 /* t1 = (src + 0x066) + dest + X
1652 * = result with some possible exceding 0x6
1653 */
1654
1655 t0 = tcg_const_i32(0x066);
1656 tcg_gen_add_i32(t0, t0, src);
1657
1658 t1 = tcg_temp_new();
1659 tcg_gen_add_i32(t1, t0, dest);
1660 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1661
1662 /* we will remove exceding 0x6 where there is no carry */
1663
1664 /* t0 = (src + 0x0066) ^ dest
1665 * = t1 without carries
1666 */
1667
1668 tcg_gen_xor_i32(t0, t0, dest);
1669
1670 /* extract the carries
1671 * t0 = t0 ^ t1
1672 * = only the carries
1673 */
1674
1675 tcg_gen_xor_i32(t0, t0, t1);
1676
1677 /* generate 0x1 where there is no carry
1678 * and for each 0x10, generate a 0x6
1679 */
1680
1681 tcg_gen_shri_i32(t0, t0, 3);
1682 tcg_gen_not_i32(t0, t0);
1683 tcg_gen_andi_i32(t0, t0, 0x22);
1684 tcg_gen_add_i32(dest, t0, t0);
1685 tcg_gen_add_i32(dest, dest, t0);
1686 tcg_temp_free(t0);
1687
1688 /* remove the exceding 0x6
1689 * for digits that have not generated a carry
1690 */
1691
1692 tcg_gen_sub_i32(dest, t1, dest);
1693 tcg_temp_free(t1);
1694 }
1695
1696 static void bcd_sub(TCGv dest, TCGv src)
1697 {
1698 TCGv t0, t1, t2;
1699
1700 /* dest10 = dest10 - src10 - X
1701 * = bcd_add(dest + 1 - X, 0x199 - src)
1702 */
1703
1704 /* t0 = 0x066 + (0x199 - src) */
1705
1706 t0 = tcg_temp_new();
1707 tcg_gen_subfi_i32(t0, 0x1ff, src);
1708
1709 /* t1 = t0 + dest + 1 - X*/
1710
1711 t1 = tcg_temp_new();
1712 tcg_gen_add_i32(t1, t0, dest);
1713 tcg_gen_addi_i32(t1, t1, 1);
1714 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1715
1716 /* t2 = t0 ^ dest */
1717
1718 t2 = tcg_temp_new();
1719 tcg_gen_xor_i32(t2, t0, dest);
1720
1721 /* t0 = t1 ^ t2 */
1722
1723 tcg_gen_xor_i32(t0, t1, t2);
1724
1725 /* t2 = ~t0 & 0x110
1726 * t0 = (t2 >> 2) | (t2 >> 3)
1727 *
1728 * to fit on 8bit operands, changed in:
1729 *
1730 * t2 = ~(t0 >> 3) & 0x22
1731 * t0 = t2 + t2
1732 * t0 = t0 + t2
1733 */
1734
1735 tcg_gen_shri_i32(t2, t0, 3);
1736 tcg_gen_not_i32(t2, t2);
1737 tcg_gen_andi_i32(t2, t2, 0x22);
1738 tcg_gen_add_i32(t0, t2, t2);
1739 tcg_gen_add_i32(t0, t0, t2);
1740 tcg_temp_free(t2);
1741
1742 /* return t1 - t0 */
1743
1744 tcg_gen_sub_i32(dest, t1, t0);
1745 tcg_temp_free(t0);
1746 tcg_temp_free(t1);
1747 }
1748
1749 static void bcd_flags(TCGv val)
1750 {
1751 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1752 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1753
1754 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1755
1756 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1757 }
1758
1759 DISAS_INSN(abcd_reg)
1760 {
1761 TCGv src;
1762 TCGv dest;
1763
1764 gen_flush_flags(s); /* !Z is sticky */
1765
1766 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1767 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1768 bcd_add(dest, src);
1769 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1770
1771 bcd_flags(dest);
1772 }
1773
1774 DISAS_INSN(abcd_mem)
1775 {
1776 TCGv src, dest, addr;
1777
1778 gen_flush_flags(s); /* !Z is sticky */
1779
1780 /* Indirect pre-decrement load (mode 4) */
1781
1782 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1783 NULL_QREG, NULL, EA_LOADU);
1784 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1785 NULL_QREG, &addr, EA_LOADU);
1786
1787 bcd_add(dest, src);
1788
1789 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1790
1791 bcd_flags(dest);
1792 }
1793
1794 DISAS_INSN(sbcd_reg)
1795 {
1796 TCGv src, dest;
1797
1798 gen_flush_flags(s); /* !Z is sticky */
1799
1800 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1801 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1802
1803 bcd_sub(dest, src);
1804
1805 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1806
1807 bcd_flags(dest);
1808 }
1809
1810 DISAS_INSN(sbcd_mem)
1811 {
1812 TCGv src, dest, addr;
1813
1814 gen_flush_flags(s); /* !Z is sticky */
1815
1816 /* Indirect pre-decrement load (mode 4) */
1817
1818 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1819 NULL_QREG, NULL, EA_LOADU);
1820 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1821 NULL_QREG, &addr, EA_LOADU);
1822
1823 bcd_sub(dest, src);
1824
1825 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1826
1827 bcd_flags(dest);
1828 }
1829
1830 DISAS_INSN(nbcd)
1831 {
1832 TCGv src, dest;
1833 TCGv addr;
1834
1835 gen_flush_flags(s); /* !Z is sticky */
1836
1837 SRC_EA(env, src, OS_BYTE, 0, &addr);
1838
1839 dest = tcg_const_i32(0);
1840 bcd_sub(dest, src);
1841
1842 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1843
1844 bcd_flags(dest);
1845
1846 tcg_temp_free(dest);
1847 }
1848
1849 DISAS_INSN(addsub)
1850 {
1851 TCGv reg;
1852 TCGv dest;
1853 TCGv src;
1854 TCGv tmp;
1855 TCGv addr;
1856 int add;
1857 int opsize;
1858
1859 add = (insn & 0x4000) != 0;
1860 opsize = insn_opsize(insn);
1861 reg = gen_extend(DREG(insn, 9), opsize, 1);
1862 dest = tcg_temp_new();
1863 if (insn & 0x100) {
1864 SRC_EA(env, tmp, opsize, 1, &addr);
1865 src = reg;
1866 } else {
1867 tmp = reg;
1868 SRC_EA(env, src, opsize, 1, NULL);
1869 }
1870 if (add) {
1871 tcg_gen_add_i32(dest, tmp, src);
1872 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1873 set_cc_op(s, CC_OP_ADDB + opsize);
1874 } else {
1875 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1876 tcg_gen_sub_i32(dest, tmp, src);
1877 set_cc_op(s, CC_OP_SUBB + opsize);
1878 }
1879 gen_update_cc_add(dest, src, opsize);
1880 if (insn & 0x100) {
1881 DEST_EA(env, insn, opsize, dest, &addr);
1882 } else {
1883 gen_partset_reg(opsize, DREG(insn, 9), dest);
1884 }
1885 tcg_temp_free(dest);
1886 }
1887
1888 /* Reverse the order of the bits in REG. */
1889 DISAS_INSN(bitrev)
1890 {
1891 TCGv reg;
1892 reg = DREG(insn, 0);
1893 gen_helper_bitrev(reg, reg);
1894 }
1895
1896 DISAS_INSN(bitop_reg)
1897 {
1898 int opsize;
1899 int op;
1900 TCGv src1;
1901 TCGv src2;
1902 TCGv tmp;
1903 TCGv addr;
1904 TCGv dest;
1905
1906 if ((insn & 0x38) != 0)
1907 opsize = OS_BYTE;
1908 else
1909 opsize = OS_LONG;
1910 op = (insn >> 6) & 3;
1911 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1912
1913 gen_flush_flags(s);
1914 src2 = tcg_temp_new();
1915 if (opsize == OS_BYTE)
1916 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1917 else
1918 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1919
1920 tmp = tcg_const_i32(1);
1921 tcg_gen_shl_i32(tmp, tmp, src2);
1922 tcg_temp_free(src2);
1923
1924 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
1925
1926 dest = tcg_temp_new();
1927 switch (op) {
1928 case 1: /* bchg */
1929 tcg_gen_xor_i32(dest, src1, tmp);
1930 break;
1931 case 2: /* bclr */
1932 tcg_gen_andc_i32(dest, src1, tmp);
1933 break;
1934 case 3: /* bset */
1935 tcg_gen_or_i32(dest, src1, tmp);
1936 break;
1937 default: /* btst */
1938 break;
1939 }
1940 tcg_temp_free(tmp);
1941 if (op) {
1942 DEST_EA(env, insn, opsize, dest, &addr);
1943 }
1944 tcg_temp_free(dest);
1945 }
1946
1947 DISAS_INSN(sats)
1948 {
1949 TCGv reg;
1950 reg = DREG(insn, 0);
1951 gen_flush_flags(s);
1952 gen_helper_sats(reg, reg, QREG_CC_V);
1953 gen_logic_cc(s, reg, OS_LONG);
1954 }
1955
1956 static void gen_push(DisasContext *s, TCGv val)
1957 {
1958 TCGv tmp;
1959
1960 tmp = tcg_temp_new();
1961 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1962 gen_store(s, OS_LONG, tmp, val);
1963 tcg_gen_mov_i32(QREG_SP, tmp);
1964 tcg_temp_free(tmp);
1965 }
1966
1967 static TCGv mreg(int reg)
1968 {
1969 if (reg < 8) {
1970 /* Dx */
1971 return cpu_dregs[reg];
1972 }
1973 /* Ax */
1974 return cpu_aregs[reg & 7];
1975 }
1976
1977 DISAS_INSN(movem)
1978 {
1979 TCGv addr, incr, tmp, r[16];
1980 int is_load = (insn & 0x0400) != 0;
1981 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
1982 uint16_t mask = read_im16(env, s);
1983 int mode = extract32(insn, 3, 3);
1984 int reg0 = REG(insn, 0);
1985 int i;
1986
1987 tmp = cpu_aregs[reg0];
1988
1989 switch (mode) {
1990 case 0: /* data register direct */
1991 case 1: /* addr register direct */
1992 do_addr_fault:
1993 gen_addr_fault(s);
1994 return;
1995
1996 case 2: /* indirect */
1997 break;
1998
1999 case 3: /* indirect post-increment */
2000 if (!is_load) {
2001 /* post-increment is not allowed */
2002 goto do_addr_fault;
2003 }
2004 break;
2005
2006 case 4: /* indirect pre-decrement */
2007 if (is_load) {
2008 /* pre-decrement is not allowed */
2009 goto do_addr_fault;
2010 }
2011 /* We want a bare copy of the address reg, without any pre-decrement
2012 adjustment, as gen_lea would provide. */
2013 break;
2014
2015 default:
2016 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2017 if (IS_NULL_QREG(tmp)) {
2018 goto do_addr_fault;
2019 }
2020 break;
2021 }
2022
2023 addr = tcg_temp_new();
2024 tcg_gen_mov_i32(addr, tmp);
2025 incr = tcg_const_i32(opsize_bytes(opsize));
2026
2027 if (is_load) {
2028 /* memory to register */
2029 for (i = 0; i < 16; i++) {
2030 if (mask & (1 << i)) {
2031 r[i] = gen_load(s, opsize, addr, 1);
2032 tcg_gen_add_i32(addr, addr, incr);
2033 }
2034 }
2035 for (i = 0; i < 16; i++) {
2036 if (mask & (1 << i)) {
2037 tcg_gen_mov_i32(mreg(i), r[i]);
2038 tcg_temp_free(r[i]);
2039 }
2040 }
2041 if (mode == 3) {
2042 /* post-increment: movem (An)+,X */
2043 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2044 }
2045 } else {
2046 /* register to memory */
2047 if (mode == 4) {
2048 /* pre-decrement: movem X,-(An) */
2049 for (i = 15; i >= 0; i--) {
2050 if ((mask << i) & 0x8000) {
2051 tcg_gen_sub_i32(addr, addr, incr);
2052 if (reg0 + 8 == i &&
2053 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2054 /* M68020+: if the addressing register is the
2055 * register moved to memory, the value written
2056 * is the initial value decremented by the size of
2057 * the operation, regardless of how many actual
2058 * stores have been performed until this point.
2059 * M68000/M68010: the value is the initial value.
2060 */
2061 tmp = tcg_temp_new();
2062 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2063 gen_store(s, opsize, addr, tmp);
2064 tcg_temp_free(tmp);
2065 } else {
2066 gen_store(s, opsize, addr, mreg(i));
2067 }
2068 }
2069 }
2070 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2071 } else {
2072 for (i = 0; i < 16; i++) {
2073 if (mask & (1 << i)) {
2074 gen_store(s, opsize, addr, mreg(i));
2075 tcg_gen_add_i32(addr, addr, incr);
2076 }
2077 }
2078 }
2079 }
2080
2081 tcg_temp_free(incr);
2082 tcg_temp_free(addr);
2083 }
2084
2085 DISAS_INSN(bitop_im)
2086 {
2087 int opsize;
2088 int op;
2089 TCGv src1;
2090 uint32_t mask;
2091 int bitnum;
2092 TCGv tmp;
2093 TCGv addr;
2094
2095 if ((insn & 0x38) != 0)
2096 opsize = OS_BYTE;
2097 else
2098 opsize = OS_LONG;
2099 op = (insn >> 6) & 3;
2100
2101 bitnum = read_im16(env, s);
2102 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2103 if (bitnum & 0xfe00) {
2104 disas_undef(env, s, insn);
2105 return;
2106 }
2107 } else {
2108 if (bitnum & 0xff00) {
2109 disas_undef(env, s, insn);
2110 return;
2111 }
2112 }
2113
2114 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2115
2116 gen_flush_flags(s);
2117 if (opsize == OS_BYTE)
2118 bitnum &= 7;
2119 else
2120 bitnum &= 31;
2121 mask = 1 << bitnum;
2122
2123 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2124
2125 if (op) {
2126 tmp = tcg_temp_new();
2127 switch (op) {
2128 case 1: /* bchg */
2129 tcg_gen_xori_i32(tmp, src1, mask);
2130 break;
2131 case 2: /* bclr */
2132 tcg_gen_andi_i32(tmp, src1, ~mask);
2133 break;
2134 case 3: /* bset */
2135 tcg_gen_ori_i32(tmp, src1, mask);
2136 break;
2137 default: /* btst */
2138 break;
2139 }
2140 DEST_EA(env, insn, opsize, tmp, &addr);
2141 tcg_temp_free(tmp);
2142 }
2143 }
2144
2145 DISAS_INSN(arith_im)
2146 {
2147 int op;
2148 TCGv im;
2149 TCGv src1;
2150 TCGv dest;
2151 TCGv addr;
2152 int opsize;
2153
2154 op = (insn >> 9) & 7;
2155 opsize = insn_opsize(insn);
2156 switch (opsize) {
2157 case OS_BYTE:
2158 im = tcg_const_i32((int8_t)read_im8(env, s));
2159 break;
2160 case OS_WORD:
2161 im = tcg_const_i32((int16_t)read_im16(env, s));
2162 break;
2163 case OS_LONG:
2164 im = tcg_const_i32(read_im32(env, s));
2165 break;
2166 default:
2167 abort();
2168 }
2169 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2170 dest = tcg_temp_new();
2171 switch (op) {
2172 case 0: /* ori */
2173 tcg_gen_or_i32(dest, src1, im);
2174 gen_logic_cc(s, dest, opsize);
2175 break;
2176 case 1: /* andi */
2177 tcg_gen_and_i32(dest, src1, im);
2178 gen_logic_cc(s, dest, opsize);
2179 break;
2180 case 2: /* subi */
2181 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2182 tcg_gen_sub_i32(dest, src1, im);
2183 gen_update_cc_add(dest, im, opsize);
2184 set_cc_op(s, CC_OP_SUBB + opsize);
2185 break;
2186 case 3: /* addi */
2187 tcg_gen_add_i32(dest, src1, im);
2188 gen_update_cc_add(dest, im, opsize);
2189 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2190 set_cc_op(s, CC_OP_ADDB + opsize);
2191 break;
2192 case 5: /* eori */
2193 tcg_gen_xor_i32(dest, src1, im);
2194 gen_logic_cc(s, dest, opsize);
2195 break;
2196 case 6: /* cmpi */
2197 gen_update_cc_cmp(s, src1, im, opsize);
2198 break;
2199 default:
2200 abort();
2201 }
2202 tcg_temp_free(im);
2203 if (op != 6) {
2204 DEST_EA(env, insn, opsize, dest, &addr);
2205 }
2206 tcg_temp_free(dest);
2207 }
2208
2209 DISAS_INSN(cas)
2210 {
2211 int opsize;
2212 TCGv addr;
2213 uint16_t ext;
2214 TCGv load;
2215 TCGv cmp;
2216 TCGMemOp opc;
2217
2218 switch ((insn >> 9) & 3) {
2219 case 1:
2220 opsize = OS_BYTE;
2221 opc = MO_SB;
2222 break;
2223 case 2:
2224 opsize = OS_WORD;
2225 opc = MO_TESW;
2226 break;
2227 case 3:
2228 opsize = OS_LONG;
2229 opc = MO_TESL;
2230 break;
2231 default:
2232 g_assert_not_reached();
2233 }
2234
2235 ext = read_im16(env, s);
2236
2237 /* cas Dc,Du,<EA> */
2238
2239 addr = gen_lea(env, s, insn, opsize);
2240 if (IS_NULL_QREG(addr)) {
2241 gen_addr_fault(s);
2242 return;
2243 }
2244
2245 cmp = gen_extend(DREG(ext, 0), opsize, 1);
2246
2247 /* if <EA> == Dc then
2248 * <EA> = Du
2249 * Dc = <EA> (because <EA> == Dc)
2250 * else
2251 * Dc = <EA>
2252 */
2253
2254 load = tcg_temp_new();
2255 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2256 IS_USER(s), opc);
2257 /* update flags before setting cmp to load */
2258 gen_update_cc_cmp(s, load, cmp, opsize);
2259 gen_partset_reg(opsize, DREG(ext, 0), load);
2260
2261 tcg_temp_free(load);
2262
2263 switch (extract32(insn, 3, 3)) {
2264 case 3: /* Indirect postincrement. */
2265 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2266 break;
2267 case 4: /* Indirect predecrememnt. */
2268 tcg_gen_mov_i32(AREG(insn, 0), addr);
2269 break;
2270 }
2271 }
2272
2273 DISAS_INSN(cas2w)
2274 {
2275 uint16_t ext1, ext2;
2276 TCGv addr1, addr2;
2277 TCGv regs;
2278
2279 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2280
2281 ext1 = read_im16(env, s);
2282
2283 if (ext1 & 0x8000) {
2284 /* Address Register */
2285 addr1 = AREG(ext1, 12);
2286 } else {
2287 /* Data Register */
2288 addr1 = DREG(ext1, 12);
2289 }
2290
2291 ext2 = read_im16(env, s);
2292 if (ext2 & 0x8000) {
2293 /* Address Register */
2294 addr2 = AREG(ext2, 12);
2295 } else {
2296 /* Data Register */
2297 addr2 = DREG(ext2, 12);
2298 }
2299
2300 /* if (R1) == Dc1 && (R2) == Dc2 then
2301 * (R1) = Du1
2302 * (R2) = Du2
2303 * else
2304 * Dc1 = (R1)
2305 * Dc2 = (R2)
2306 */
2307
2308 regs = tcg_const_i32(REG(ext2, 6) |
2309 (REG(ext1, 6) << 3) |
2310 (REG(ext2, 0) << 6) |
2311 (REG(ext1, 0) << 9));
2312 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2313 tcg_temp_free(regs);
2314
2315 /* Note that cas2w also assigned to env->cc_op. */
2316 s->cc_op = CC_OP_CMPW;
2317 s->cc_op_synced = 1;
2318 }
2319
2320 DISAS_INSN(cas2l)
2321 {
2322 uint16_t ext1, ext2;
2323 TCGv addr1, addr2, regs;
2324
2325 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2326
2327 ext1 = read_im16(env, s);
2328
2329 if (ext1 & 0x8000) {
2330 /* Address Register */
2331 addr1 = AREG(ext1, 12);
2332 } else {
2333 /* Data Register */
2334 addr1 = DREG(ext1, 12);
2335 }
2336
2337 ext2 = read_im16(env, s);
2338 if (ext2 & 0x8000) {
2339 /* Address Register */
2340 addr2 = AREG(ext2, 12);
2341 } else {
2342 /* Data Register */
2343 addr2 = DREG(ext2, 12);
2344 }
2345
2346 /* if (R1) == Dc1 && (R2) == Dc2 then
2347 * (R1) = Du1
2348 * (R2) = Du2
2349 * else
2350 * Dc1 = (R1)
2351 * Dc2 = (R2)
2352 */
2353
2354 regs = tcg_const_i32(REG(ext2, 6) |
2355 (REG(ext1, 6) << 3) |
2356 (REG(ext2, 0) << 6) |
2357 (REG(ext1, 0) << 9));
2358 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2359 tcg_temp_free(regs);
2360
2361 /* Note that cas2l also assigned to env->cc_op. */
2362 s->cc_op = CC_OP_CMPL;
2363 s->cc_op_synced = 1;
2364 }
2365
2366 DISAS_INSN(byterev)
2367 {
2368 TCGv reg;
2369
2370 reg = DREG(insn, 0);
2371 tcg_gen_bswap32_i32(reg, reg);
2372 }
2373
2374 DISAS_INSN(move)
2375 {
2376 TCGv src;
2377 TCGv dest;
2378 int op;
2379 int opsize;
2380
2381 switch (insn >> 12) {
2382 case 1: /* move.b */
2383 opsize = OS_BYTE;
2384 break;
2385 case 2: /* move.l */
2386 opsize = OS_LONG;
2387 break;
2388 case 3: /* move.w */
2389 opsize = OS_WORD;
2390 break;
2391 default:
2392 abort();
2393 }
2394 SRC_EA(env, src, opsize, 1, NULL);
2395 op = (insn >> 6) & 7;
2396 if (op == 1) {
2397 /* movea */
2398 /* The value will already have been sign extended. */
2399 dest = AREG(insn, 9);
2400 tcg_gen_mov_i32(dest, src);
2401 } else {
2402 /* normal move */
2403 uint16_t dest_ea;
2404 dest_ea = ((insn >> 9) & 7) | (op << 3);
2405 DEST_EA(env, dest_ea, opsize, src, NULL);
2406 /* This will be correct because loads sign extend. */
2407 gen_logic_cc(s, src, opsize);
2408 }
2409 }
2410
2411 DISAS_INSN(negx)
2412 {
2413 TCGv z;
2414 TCGv src;
2415 TCGv addr;
2416 int opsize;
2417
2418 opsize = insn_opsize(insn);
2419 SRC_EA(env, src, opsize, 1, &addr);
2420
2421 gen_flush_flags(s); /* compute old Z */
2422
2423 /* Perform substract with borrow.
2424 * (X, N) = -(src + X);
2425 */
2426
2427 z = tcg_const_i32(0);
2428 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2429 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2430 tcg_temp_free(z);
2431 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2432
2433 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2434
2435 /* Compute signed-overflow for negation. The normal formula for
2436 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2437 * this simplies to res & src.
2438 */
2439
2440 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2441
2442 /* Copy the rest of the results into place. */
2443 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2444 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2445
2446 set_cc_op(s, CC_OP_FLAGS);
2447
2448 /* result is in QREG_CC_N */
2449
2450 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2451 }
2452
2453 DISAS_INSN(lea)
2454 {
2455 TCGv reg;
2456 TCGv tmp;
2457
2458 reg = AREG(insn, 9);
2459 tmp = gen_lea(env, s, insn, OS_LONG);
2460 if (IS_NULL_QREG(tmp)) {
2461 gen_addr_fault(s);
2462 return;
2463 }
2464 tcg_gen_mov_i32(reg, tmp);
2465 }
2466
2467 DISAS_INSN(clr)
2468 {
2469 int opsize;
2470 TCGv zero;
2471
2472 zero = tcg_const_i32(0);
2473
2474 opsize = insn_opsize(insn);
2475 DEST_EA(env, insn, opsize, zero, NULL);
2476 gen_logic_cc(s, zero, opsize);
2477 tcg_temp_free(zero);
2478 }
2479
2480 static TCGv gen_get_ccr(DisasContext *s)
2481 {
2482 TCGv dest;
2483
2484 gen_flush_flags(s);
2485 update_cc_op(s);
2486 dest = tcg_temp_new();
2487 gen_helper_get_ccr(dest, cpu_env);
2488 return dest;
2489 }
2490
2491 DISAS_INSN(move_from_ccr)
2492 {
2493 TCGv ccr;
2494
2495 ccr = gen_get_ccr(s);
2496 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2497 }
2498
2499 DISAS_INSN(neg)
2500 {
2501 TCGv src1;
2502 TCGv dest;
2503 TCGv addr;
2504 int opsize;
2505
2506 opsize = insn_opsize(insn);
2507 SRC_EA(env, src1, opsize, 1, &addr);
2508 dest = tcg_temp_new();
2509 tcg_gen_neg_i32(dest, src1);
2510 set_cc_op(s, CC_OP_SUBB + opsize);
2511 gen_update_cc_add(dest, src1, opsize);
2512 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2513 DEST_EA(env, insn, opsize, dest, &addr);
2514 tcg_temp_free(dest);
2515 }
2516
2517 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2518 {
2519 if (ccr_only) {
2520 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2521 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2522 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2523 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2524 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2525 } else {
2526 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
2527 }
2528 set_cc_op(s, CC_OP_FLAGS);
2529 }
2530
2531 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2532 int ccr_only)
2533 {
2534 if ((insn & 0x38) == 0) {
2535 if (ccr_only) {
2536 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
2537 } else {
2538 gen_helper_set_sr(cpu_env, DREG(insn, 0));
2539 }
2540 set_cc_op(s, CC_OP_FLAGS);
2541 } else if ((insn & 0x3f) == 0x3c) {
2542 uint16_t val;
2543 val = read_im16(env, s);
2544 gen_set_sr_im(s, val, ccr_only);
2545 } else {
2546 disas_undef(env, s, insn);
2547 }
2548 }
2549
2550
2551 DISAS_INSN(move_to_ccr)
2552 {
2553 gen_set_sr(env, s, insn, 1);
2554 }
2555
2556 DISAS_INSN(not)
2557 {
2558 TCGv src1;
2559 TCGv dest;
2560 TCGv addr;
2561 int opsize;
2562
2563 opsize = insn_opsize(insn);
2564 SRC_EA(env, src1, opsize, 1, &addr);
2565 dest = tcg_temp_new();
2566 tcg_gen_not_i32(dest, src1);
2567 DEST_EA(env, insn, opsize, dest, &addr);
2568 gen_logic_cc(s, dest, opsize);
2569 }
2570
2571 DISAS_INSN(swap)
2572 {
2573 TCGv src1;
2574 TCGv src2;
2575 TCGv reg;
2576
2577 src1 = tcg_temp_new();
2578 src2 = tcg_temp_new();
2579 reg = DREG(insn, 0);
2580 tcg_gen_shli_i32(src1, reg, 16);
2581 tcg_gen_shri_i32(src2, reg, 16);
2582 tcg_gen_or_i32(reg, src1, src2);
2583 tcg_temp_free(src2);
2584 tcg_temp_free(src1);
2585 gen_logic_cc(s, reg, OS_LONG);
2586 }
2587
2588 DISAS_INSN(bkpt)
2589 {
2590 gen_exception(s, s->pc - 2, EXCP_DEBUG);
2591 }
2592
2593 DISAS_INSN(pea)
2594 {
2595 TCGv tmp;
2596
2597 tmp = gen_lea(env, s, insn, OS_LONG);
2598 if (IS_NULL_QREG(tmp)) {
2599 gen_addr_fault(s);
2600 return;
2601 }
2602 gen_push(s, tmp);
2603 }
2604
2605 DISAS_INSN(ext)
2606 {
2607 int op;
2608 TCGv reg;
2609 TCGv tmp;
2610
2611 reg = DREG(insn, 0);
2612 op = (insn >> 6) & 7;
2613 tmp = tcg_temp_new();
2614 if (op == 3)
2615 tcg_gen_ext16s_i32(tmp, reg);
2616 else
2617 tcg_gen_ext8s_i32(tmp, reg);
2618 if (op == 2)
2619 gen_partset_reg(OS_WORD, reg, tmp);
2620 else
2621 tcg_gen_mov_i32(reg, tmp);
2622 gen_logic_cc(s, tmp, OS_LONG);
2623 tcg_temp_free(tmp);
2624 }
2625
2626 DISAS_INSN(tst)
2627 {
2628 int opsize;
2629 TCGv tmp;
2630
2631 opsize = insn_opsize(insn);
2632 SRC_EA(env, tmp, opsize, 1, NULL);
2633 gen_logic_cc(s, tmp, opsize);
2634 }
2635
2636 DISAS_INSN(pulse)
2637 {
2638 /* Implemented as a NOP. */
2639 }
2640
2641 DISAS_INSN(illegal)
2642 {
2643 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2644 }
2645
2646 /* ??? This should be atomic. */
2647 DISAS_INSN(tas)
2648 {
2649 TCGv dest;
2650 TCGv src1;
2651 TCGv addr;
2652
2653 dest = tcg_temp_new();
2654 SRC_EA(env, src1, OS_BYTE, 1, &addr);
2655 gen_logic_cc(s, src1, OS_BYTE);
2656 tcg_gen_ori_i32(dest, src1, 0x80);
2657 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2658 tcg_temp_free(dest);
2659 }
2660
2661 DISAS_INSN(mull)
2662 {
2663 uint16_t ext;
2664 TCGv src1;
2665 int sign;
2666
2667 ext = read_im16(env, s);
2668
2669 sign = ext & 0x800;
2670
2671 if (ext & 0x400) {
2672 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2673 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
2674 return;
2675 }
2676
2677 SRC_EA(env, src1, OS_LONG, 0, NULL);
2678
2679 if (sign) {
2680 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2681 } else {
2682 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2683 }
2684 /* if Dl == Dh, 68040 returns low word */
2685 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2686 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2687 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2688
2689 tcg_gen_movi_i32(QREG_CC_V, 0);
2690 tcg_gen_movi_i32(QREG_CC_C, 0);
2691
2692 set_cc_op(s, CC_OP_FLAGS);
2693 return;
2694 }
2695 SRC_EA(env, src1, OS_LONG, 0, NULL);
2696 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2697 tcg_gen_movi_i32(QREG_CC_C, 0);
2698 if (sign) {
2699 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2700 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2701 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2702 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2703 } else {
2704 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2705 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2706 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2707 }
2708 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2709 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2710
2711 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2712
2713 set_cc_op(s, CC_OP_FLAGS);
2714 } else {
2715 /* The upper 32 bits of the product are discarded, so
2716 muls.l and mulu.l are functionally equivalent. */
2717 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2718 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2719 }
2720 }
2721
2722 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2723 {
2724 TCGv reg;
2725 TCGv tmp;
2726
2727 reg = AREG(insn, 0);
2728 tmp = tcg_temp_new();
2729 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2730 gen_store(s, OS_LONG, tmp, reg);
2731 if ((insn & 7) != 7) {
2732 tcg_gen_mov_i32(reg, tmp);
2733 }
2734 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2735 tcg_temp_free(tmp);
2736 }
2737
2738 DISAS_INSN(link)
2739 {
2740 int16_t offset;
2741
2742 offset = read_im16(env, s);
2743 gen_link(s, insn, offset);
2744 }
2745
2746 DISAS_INSN(linkl)
2747 {
2748 int32_t offset;
2749
2750 offset = read_im32(env, s);
2751 gen_link(s, insn, offset);
2752 }
2753
2754 DISAS_INSN(unlk)
2755 {
2756 TCGv src;
2757 TCGv reg;
2758 TCGv tmp;
2759
2760 src = tcg_temp_new();
2761 reg = AREG(insn, 0);
2762 tcg_gen_mov_i32(src, reg);
2763 tmp = gen_load(s, OS_LONG, src, 0);
2764 tcg_gen_mov_i32(reg, tmp);
2765 tcg_gen_addi_i32(QREG_SP, src, 4);
2766 tcg_temp_free(src);
2767 }
2768
2769 DISAS_INSN(nop)
2770 {
2771 }
2772
2773 DISAS_INSN(rtd)
2774 {
2775 TCGv tmp;
2776 int16_t offset = read_im16(env, s);
2777
2778 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
2779 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2780 gen_jmp(s, tmp);
2781 }
2782
2783 DISAS_INSN(rts)
2784 {
2785 TCGv tmp;
2786
2787 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
2788 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
2789 gen_jmp(s, tmp);
2790 }
2791
2792 DISAS_INSN(jump)
2793 {
2794 TCGv tmp;
2795
2796 /* Load the target address first to ensure correct exception
2797 behavior. */
2798 tmp = gen_lea(env, s, insn, OS_LONG);
2799 if (IS_NULL_QREG(tmp)) {
2800 gen_addr_fault(s);
2801 return;
2802 }
2803 if ((insn & 0x40) == 0) {
2804 /* jsr */
2805 gen_push(s, tcg_const_i32(s->pc));
2806 }
2807 gen_jmp(s, tmp);
2808 }
2809
2810 DISAS_INSN(addsubq)
2811 {
2812 TCGv src;
2813 TCGv dest;
2814 TCGv val;
2815 int imm;
2816 TCGv addr;
2817 int opsize;
2818
2819 if ((insn & 070) == 010) {
2820 /* Operation on address register is always long. */
2821 opsize = OS_LONG;
2822 } else {
2823 opsize = insn_opsize(insn);
2824 }
2825 SRC_EA(env, src, opsize, 1, &addr);
2826 imm = (insn >> 9) & 7;
2827 if (imm == 0) {
2828 imm = 8;
2829 }
2830 val = tcg_const_i32(imm);
2831 dest = tcg_temp_new();
2832 tcg_gen_mov_i32(dest, src);
2833 if ((insn & 0x38) == 0x08) {
2834 /* Don't update condition codes if the destination is an
2835 address register. */
2836 if (insn & 0x0100) {
2837 tcg_gen_sub_i32(dest, dest, val);
2838 } else {
2839 tcg_gen_add_i32(dest, dest, val);
2840 }
2841 } else {
2842 if (insn & 0x0100) {
2843 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2844 tcg_gen_sub_i32(dest, dest, val);
2845 set_cc_op(s, CC_OP_SUBB + opsize);
2846 } else {
2847 tcg_gen_add_i32(dest, dest, val);
2848 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2849 set_cc_op(s, CC_OP_ADDB + opsize);
2850 }
2851 gen_update_cc_add(dest, val, opsize);
2852 }
2853 tcg_temp_free(val);
2854 DEST_EA(env, insn, opsize, dest, &addr);
2855 tcg_temp_free(dest);
2856 }
2857
2858 DISAS_INSN(tpf)
2859 {
2860 switch (insn & 7) {
2861 case 2: /* One extension word. */
2862 s->pc += 2;
2863 break;
2864 case 3: /* Two extension words. */
2865 s->pc += 4;
2866 break;
2867 case 4: /* No extension words. */
2868 break;
2869 default:
2870 disas_undef(env, s, insn);
2871 }
2872 }
2873
2874 DISAS_INSN(branch)
2875 {
2876 int32_t offset;
2877 uint32_t base;
2878 int op;
2879 TCGLabel *l1;
2880
2881 base = s->pc;
2882 op = (insn >> 8) & 0xf;
2883 offset = (int8_t)insn;
2884 if (offset == 0) {
2885 offset = (int16_t)read_im16(env, s);
2886 } else if (offset == -1) {
2887 offset = read_im32(env, s);
2888 }
2889 if (op == 1) {
2890 /* bsr */
2891 gen_push(s, tcg_const_i32(s->pc));
2892 }
2893 if (op > 1) {
2894 /* Bcc */
2895 l1 = gen_new_label();
2896 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
2897 gen_jmp_tb(s, 1, base + offset);
2898 gen_set_label(l1);
2899 gen_jmp_tb(s, 0, s->pc);
2900 } else {
2901 /* Unconditional branch. */
2902 gen_jmp_tb(s, 0, base + offset);
2903 }
2904 }
2905
2906 DISAS_INSN(moveq)
2907 {
2908 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
2909 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
2910 }
2911
2912 DISAS_INSN(mvzs)
2913 {
2914 int opsize;
2915 TCGv src;
2916 TCGv reg;
2917
2918 if (insn & 0x40)
2919 opsize = OS_WORD;
2920 else
2921 opsize = OS_BYTE;
2922 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
2923 reg = DREG(insn, 9);
2924 tcg_gen_mov_i32(reg, src);
2925 gen_logic_cc(s, src, opsize);
2926 }
2927
2928 DISAS_INSN(or)
2929 {
2930 TCGv reg;
2931 TCGv dest;
2932 TCGv src;
2933 TCGv addr;
2934 int opsize;
2935
2936 opsize = insn_opsize(insn);
2937 reg = gen_extend(DREG(insn, 9), opsize, 0);
2938 dest = tcg_temp_new();
2939 if (insn & 0x100) {
2940 SRC_EA(env, src, opsize, 0, &addr);
2941 tcg_gen_or_i32(dest, src, reg);
2942 DEST_EA(env, insn, opsize, dest, &addr);
2943 } else {
2944 SRC_EA(env, src, opsize, 0, NULL);
2945 tcg_gen_or_i32(dest, src, reg);
2946 gen_partset_reg(opsize, DREG(insn, 9), dest);
2947 }
2948 gen_logic_cc(s, dest, opsize);
2949 tcg_temp_free(dest);
2950 }
2951
2952 DISAS_INSN(suba)
2953 {
2954 TCGv src;
2955 TCGv reg;
2956
2957 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
2958 reg = AREG(insn, 9);
2959 tcg_gen_sub_i32(reg, reg, src);
2960 }
2961
2962 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
2963 {
2964 TCGv tmp;
2965
2966 gen_flush_flags(s); /* compute old Z */
2967
2968 /* Perform substract with borrow.
2969 * (X, N) = dest - (src + X);
2970 */
2971
2972 tmp = tcg_const_i32(0);
2973 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
2974 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
2975 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2976 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2977
2978 /* Compute signed-overflow for substract. */
2979
2980 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
2981 tcg_gen_xor_i32(tmp, dest, src);
2982 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
2983 tcg_temp_free(tmp);
2984
2985 /* Copy the rest of the results into place. */
2986 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2987 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2988
2989 set_cc_op(s, CC_OP_FLAGS);
2990
2991 /* result is in QREG_CC_N */
2992 }
2993
2994 DISAS_INSN(subx_reg)
2995 {
2996 TCGv dest;
2997 TCGv src;
2998 int opsize;
2999
3000 opsize = insn_opsize(insn);
3001
3002 src = gen_extend(DREG(insn, 0), opsize, 1);
3003 dest = gen_extend(DREG(insn, 9), opsize, 1);
3004
3005 gen_subx(s, src, dest, opsize);
3006
3007 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3008 }
3009
3010 DISAS_INSN(subx_mem)
3011 {
3012 TCGv src;
3013 TCGv addr_src;
3014 TCGv dest;
3015 TCGv addr_dest;
3016 int opsize;
3017
3018 opsize = insn_opsize(insn);
3019
3020 addr_src = AREG(insn, 0);
3021 tcg_gen_subi_i32(addr_src, addr_src, opsize);
3022 src = gen_load(s, opsize, addr_src, 1);
3023
3024 addr_dest = AREG(insn, 9);
3025 tcg_gen_subi_i32(addr_dest, addr_dest, opsize);
3026 dest = gen_load(s, opsize, addr_dest, 1);
3027
3028 gen_subx(s, src, dest, opsize);
3029
3030 gen_store(s, opsize, addr_dest, QREG_CC_N);
3031 }
3032
3033 DISAS_INSN(mov3q)
3034 {
3035 TCGv src;
3036 int val;
3037
3038 val = (insn >> 9) & 7;
3039 if (val == 0)
3040 val = -1;
3041 src = tcg_const_i32(val);
3042 gen_logic_cc(s, src, OS_LONG);
3043 DEST_EA(env, insn, OS_LONG, src, NULL);
3044 tcg_temp_free(src);
3045 }
3046
3047 DISAS_INSN(cmp)
3048 {
3049 TCGv src;
3050 TCGv reg;
3051 int opsize;
3052
3053 opsize = insn_opsize(insn);
3054 SRC_EA(env, src, opsize, 1, NULL);
3055 reg = gen_extend(DREG(insn, 9), opsize, 1);
3056 gen_update_cc_cmp(s, reg, src, opsize);
3057 }
3058
3059 DISAS_INSN(cmpa)
3060 {
3061 int opsize;
3062 TCGv src;
3063 TCGv reg;
3064
3065 if (insn & 0x100) {
3066 opsize = OS_LONG;
3067 } else {
3068 opsize = OS_WORD;
3069 }
3070 SRC_EA(env, src, opsize, 1, NULL);
3071 reg = AREG(insn, 9);
3072 gen_update_cc_cmp(s, reg, src, OS_LONG);
3073 }
3074
3075 DISAS_INSN(cmpm)
3076 {
3077 int opsize = insn_opsize(insn);
3078 TCGv src, dst;
3079
3080 /* Post-increment load (mode 3) from Ay. */
3081 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3082 NULL_QREG, NULL, EA_LOADS);
3083 /* Post-increment load (mode 3) from Ax. */
3084 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3085 NULL_QREG, NULL, EA_LOADS);
3086
3087 gen_update_cc_cmp(s, dst, src, opsize);
3088 }
3089
3090 DISAS_INSN(eor)
3091 {
3092 TCGv src;
3093 TCGv dest;
3094 TCGv addr;
3095 int opsize;
3096
3097 opsize = insn_opsize(insn);
3098
3099 SRC_EA(env, src, opsize, 0, &addr);
3100 dest = tcg_temp_new();
3101 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3102 gen_logic_cc(s, dest, opsize);
3103 DEST_EA(env, insn, opsize, dest, &addr);
3104 tcg_temp_free(dest);
3105 }
3106
3107 static void do_exg(TCGv reg1, TCGv reg2)
3108 {
3109 TCGv temp = tcg_temp_new();
3110 tcg_gen_mov_i32(temp, reg1);
3111 tcg_gen_mov_i32(reg1, reg2);
3112 tcg_gen_mov_i32(reg2, temp);
3113 tcg_temp_free(temp);
3114 }
3115
3116 DISAS_INSN(exg_dd)
3117 {
3118 /* exchange Dx and Dy */
3119 do_exg(DREG(insn, 9), DREG(insn, 0));
3120 }
3121
3122 DISAS_INSN(exg_aa)
3123 {
3124 /* exchange Ax and Ay */
3125 do_exg(AREG(insn, 9), AREG(insn, 0));
3126 }
3127
3128 DISAS_INSN(exg_da)
3129 {
3130 /* exchange Dx and Ay */
3131 do_exg(DREG(insn, 9), AREG(insn, 0));
3132 }
3133
3134 DISAS_INSN(and)
3135 {
3136 TCGv src;
3137 TCGv reg;
3138 TCGv dest;
3139 TCGv addr;
3140 int opsize;
3141
3142 dest = tcg_temp_new();
3143
3144 opsize = insn_opsize(insn);
3145 reg = DREG(insn, 9);
3146 if (insn & 0x100) {
3147 SRC_EA(env, src, opsize, 0, &addr);
3148 tcg_gen_and_i32(dest, src, reg);
3149 DEST_EA(env, insn, opsize, dest, &addr);
3150 } else {
3151 SRC_EA(env, src, opsize, 0, NULL);
3152 tcg_gen_and_i32(dest, src, reg);
3153 gen_partset_reg(opsize, reg, dest);
3154 }
3155 gen_logic_cc(s, dest, opsize);
3156 tcg_temp_free(dest);
3157 }
3158
3159 DISAS_INSN(adda)
3160 {
3161 TCGv src;
3162 TCGv reg;
3163
3164 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3165 reg = AREG(insn, 9);
3166 tcg_gen_add_i32(reg, reg, src);
3167 }
3168
3169 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3170 {
3171 TCGv tmp;
3172
3173 gen_flush_flags(s); /* compute old Z */
3174
3175 /* Perform addition with carry.
3176 * (X, N) = src + dest + X;
3177 */
3178
3179 tmp = tcg_const_i32(0);
3180 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3181 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3182 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3183
3184 /* Compute signed-overflow for addition. */
3185
3186 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3187 tcg_gen_xor_i32(tmp, dest, src);
3188 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3189 tcg_temp_free(tmp);
3190
3191 /* Copy the rest of the results into place. */
3192 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3193 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3194
3195 set_cc_op(s, CC_OP_FLAGS);
3196
3197 /* result is in QREG_CC_N */
3198 }
3199
3200 DISAS_INSN(addx_reg)
3201 {
3202 TCGv dest;
3203 TCGv src;
3204 int opsize;
3205
3206 opsize = insn_opsize(insn);
3207
3208 dest = gen_extend(DREG(insn, 9), opsize, 1);
3209 src = gen_extend(DREG(insn, 0), opsize, 1);
3210
3211 gen_addx(s, src, dest, opsize);
3212
3213 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3214 }
3215
3216 DISAS_INSN(addx_mem)
3217 {
3218 TCGv src;
3219 TCGv addr_src;
3220 TCGv dest;
3221 TCGv addr_dest;
3222 int opsize;
3223
3224 opsize = insn_opsize(insn);
3225
3226 addr_src = AREG(insn, 0);
3227 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3228 src = gen_load(s, opsize, addr_src, 1);
3229
3230 addr_dest = AREG(insn, 9);
3231 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3232 dest = gen_load(s, opsize, addr_dest, 1);
3233
3234 gen_addx(s, src, dest, opsize);
3235
3236 gen_store(s, opsize, addr_dest, QREG_CC_N);
3237 }
3238
3239 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3240 {
3241 int count = (insn >> 9) & 7;
3242 int logical = insn & 8;
3243 int left = insn & 0x100;
3244 int bits = opsize_bytes(opsize) * 8;
3245 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3246
3247 if (count == 0) {
3248 count = 8;
3249 }
3250
3251 tcg_gen_movi_i32(QREG_CC_V, 0);
3252 if (left) {
3253 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3254 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3255
3256 /* Note that ColdFire always clears V (done above),
3257 while M68000 sets if the most significant bit is changed at
3258 any time during the shift operation */
3259 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3260 /* if shift count >= bits, V is (reg != 0) */
3261 if (count >= bits) {
3262 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3263 } else {
3264 TCGv t0 = tcg_temp_new();
3265 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3266 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3267 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3268 tcg_temp_free(t0);
3269 }
3270 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3271 }
3272 } else {
3273 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3274 if (logical) {
3275 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3276 } else {
3277 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3278 }
3279 }
3280
3281 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3282 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3283 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3284 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3285
3286 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3287 set_cc_op(s, CC_OP_FLAGS);
3288 }
3289
3290 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3291 {
3292 int logical = insn & 8;
3293 int left = insn & 0x100;
3294 int bits = opsize_bytes(opsize) * 8;
3295 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3296 TCGv s32;
3297 TCGv_i64 t64, s64;
3298
3299 t64 = tcg_temp_new_i64();
3300 s64 = tcg_temp_new_i64();
3301 s32 = tcg_temp_new();
3302
3303 /* Note that m68k truncates the shift count modulo 64, not 32.
3304 In addition, a 64-bit shift makes it easy to find "the last
3305 bit shifted out", for the carry flag. */
3306 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3307 tcg_gen_extu_i32_i64(s64, s32);
3308 tcg_gen_extu_i32_i64(t64, reg);
3309
3310 /* Optimistically set V=0. Also used as a zero source below. */
3311 tcg_gen_movi_i32(QREG_CC_V, 0);
3312 if (left) {
3313 tcg_gen_shl_i64(t64, t64, s64);
3314
3315 if (opsize == OS_LONG) {
3316 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3317 /* Note that C=0 if shift count is 0, and we get that for free. */
3318 } else {
3319 TCGv zero = tcg_const_i32(0);
3320 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3321 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3322 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3323 s32, zero, zero, QREG_CC_C);
3324 tcg_temp_free(zero);
3325 }
3326 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3327
3328 /* X = C, but only if the shift count was non-zero. */
3329 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3330 QREG_CC_C, QREG_CC_X);
3331
3332 /* M68000 sets V if the most significant bit is changed at
3333 * any time during the shift operation. Do this via creating
3334 * an extension of the sign bit, comparing, and discarding
3335 * the bits below the sign bit. I.e.
3336 * int64_t s = (intN_t)reg;
3337 * int64_t t = (int64_t)(intN_t)reg << count;
3338 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3339 */
3340 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3341 TCGv_i64 tt = tcg_const_i64(32);
3342 /* if shift is greater than 32, use 32 */
3343 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3344 tcg_temp_free_i64(tt);
3345 /* Sign extend the input to 64 bits; re-do the shift. */
3346 tcg_gen_ext_i32_i64(t64, reg);
3347 tcg_gen_shl_i64(s64, t64, s64);
3348 /* Clear all bits that are unchanged. */
3349 tcg_gen_xor_i64(t64, t64, s64);
3350 /* Ignore the bits below the sign bit. */
3351 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3352 /* If any bits remain set, we have overflow. */
3353 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3354 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3355 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3356 }
3357 } else {
3358 tcg_gen_shli_i64(t64, t64, 32);
3359 if (logical) {
3360 tcg_gen_shr_i64(t64, t64, s64);
3361 } else {
3362 tcg_gen_sar_i64(t64, t64, s64);
3363 }
3364 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3365
3366 /* Note that C=0 if shift count is 0, and we get that for free. */
3367 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3368
3369 /* X = C, but only if the shift count was non-zero. */
3370 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3371 QREG_CC_C, QREG_CC_X);
3372 }
3373 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3374 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3375
3376 tcg_temp_free(s32);
3377 tcg_temp_free_i64(s64);
3378 tcg_temp_free_i64(t64);
3379
3380 /* Write back the result. */
3381 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3382 set_cc_op(s, CC_OP_FLAGS);
3383 }
3384
3385 DISAS_INSN(shift8_im)
3386 {
3387 shift_im(s, insn, OS_BYTE);
3388 }
3389
3390 DISAS_INSN(shift16_im)
3391 {
3392 shift_im(s, insn, OS_WORD);
3393 }
3394
3395 DISAS_INSN(shift_im)
3396 {
3397 shift_im(s, insn, OS_LONG);
3398 }
3399
3400 DISAS_INSN(shift8_reg)
3401 {
3402 shift_reg(s, insn, OS_BYTE);
3403 }
3404
3405 DISAS_INSN(shift16_reg)
3406 {
3407 shift_reg(s, insn, OS_WORD);
3408 }
3409
3410 DISAS_INSN(shift_reg)
3411 {
3412 shift_reg(s, insn, OS_LONG);
3413 }
3414
3415 DISAS_INSN(shift_mem)
3416 {
3417 int logical = insn & 8;
3418 int left = insn & 0x100;
3419 TCGv src;
3420 TCGv addr;
3421
3422 SRC_EA(env, src, OS_WORD, !logical, &addr);
3423 tcg_gen_movi_i32(QREG_CC_V, 0);
3424 if (left) {
3425 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3426 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3427
3428 /* Note that ColdFire always clears V,
3429 while M68000 sets if the most significant bit is changed at
3430 any time during the shift operation */
3431 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3432 src = gen_extend(src, OS_WORD, 1);
3433 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3434 }
3435 } else {
3436 tcg_gen_mov_i32(QREG_CC_C, src);
3437 if (logical) {
3438 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3439 } else {
3440 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3441 }
3442 }
3443
3444 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3445 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3446 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3447 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3448
3449 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3450 set_cc_op(s, CC_OP_FLAGS);
3451 }
3452
3453 static void rotate(TCGv reg, TCGv shift, int left, int size)
3454 {
3455 switch (size) {
3456 case 8:
3457 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3458 tcg_gen_ext8u_i32(reg, reg);
3459 tcg_gen_muli_i32(reg, reg, 0x01010101);
3460 goto do_long;
3461 case 16:
3462 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3463 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3464 goto do_long;
3465 do_long:
3466 default:
3467 if (left) {
3468 tcg_gen_rotl_i32(reg, reg, shift);
3469 } else {
3470 tcg_gen_rotr_i32(reg, reg, shift);
3471 }
3472 }
3473
3474 /* compute flags */
3475
3476 switch (size) {
3477 case 8:
3478 tcg_gen_ext8s_i32(reg, reg);
3479 break;
3480 case 16:
3481 tcg_gen_ext16s_i32(reg, reg);
3482 break;
3483 default:
3484 break;
3485 }
3486
3487 /* QREG_CC_X is not affected */
3488
3489 tcg_gen_mov_i32(QREG_CC_N, reg);
3490 tcg_gen_mov_i32(QREG_CC_Z, reg);
3491
3492 if (left) {
3493 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3494 } else {
3495 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3496 }
3497
3498 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3499 }
3500
3501 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3502 {
3503 switch (size) {
3504 case 8:
3505 tcg_gen_ext8s_i32(reg, reg);
3506 break;
3507 case 16:
3508 tcg_gen_ext16s_i32(reg, reg);
3509 break;
3510 default:
3511 break;
3512 }
3513 tcg_gen_mov_i32(QREG_CC_N, reg);
3514 tcg_gen_mov_i32(QREG_CC_Z, reg);
3515 tcg_gen_mov_i32(QREG_CC_X, X);
3516 tcg_gen_mov_i32(QREG_CC_C, X);
3517 tcg_gen_movi_i32(QREG_CC_V, 0);
3518 }
3519
3520 /* Result of rotate_x() is valid if 0 <= shift <= size */
3521 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3522 {
3523 TCGv X, shl, shr, shx, sz, zero;
3524
3525 sz = tcg_const_i32(size);
3526
3527 shr = tcg_temp_new();
3528 shl = tcg_temp_new();
3529 shx = tcg_temp_new();
3530 if (left) {
3531 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3532 tcg_gen_movi_i32(shr, size + 1);
3533 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3534 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3535 /* shx = shx < 0 ? size : shx; */
3536 zero = tcg_const_i32(0);
3537 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3538 tcg_temp_free(zero);
3539 } else {
3540 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3541 tcg_gen_movi_i32(shl, size + 1);
3542 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3543 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3544 }
3545
3546 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3547
3548 tcg_gen_shl_i32(shl, reg, shl);
3549 tcg_gen_shr_i32(shr, reg, shr);
3550 tcg_gen_or_i32(reg, shl, shr);
3551 tcg_temp_free(shl);
3552 tcg_temp_free(shr);
3553 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3554 tcg_gen_or_i32(reg, reg, shx);
3555 tcg_temp_free(shx);
3556
3557 /* X = (reg >> size) & 1 */
3558
3559 X = tcg_temp_new();
3560 tcg_gen_shr_i32(X, reg, sz);
3561 tcg_gen_andi_i32(X, X, 1);
3562 tcg_temp_free(sz);
3563
3564 return X;
3565 }
3566
3567 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3568 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3569 {
3570 TCGv_i64 t0, shift64;
3571 TCGv X, lo, hi, zero;
3572
3573 shift64 = tcg_temp_new_i64();
3574 tcg_gen_extu_i32_i64(shift64, shift);
3575
3576 t0 = tcg_temp_new_i64();
3577
3578 X = tcg_temp_new();
3579 lo = tcg_temp_new();
3580 hi = tcg_temp_new();
3581
3582 if (left) {
3583 /* create [reg:X:..] */
3584
3585 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3586 tcg_gen_concat_i32_i64(t0, lo, reg);
3587
3588 /* rotate */
3589
3590 tcg_gen_rotl_i64(t0, t0, shift64);
3591 tcg_temp_free_i64(shift64);
3592
3593 /* result is [reg:..:reg:X] */
3594
3595 tcg_gen_extr_i64_i32(lo, hi, t0);
3596 tcg_gen_andi_i32(X, lo, 1);
3597
3598 tcg_gen_shri_i32(lo, lo, 1);
3599 } else {
3600 /* create [..:X:reg] */
3601
3602 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3603
3604 tcg_gen_rotr_i64(t0, t0, shift64);
3605 tcg_temp_free_i64(shift64);
3606
3607 /* result is value: [X:reg:..:reg] */
3608
3609 tcg_gen_extr_i64_i32(lo, hi, t0);
3610
3611 /* extract X */
3612
3613 tcg_gen_shri_i32(X, hi, 31);
3614
3615 /* extract result */
3616
3617 tcg_gen_shli_i32(hi, hi, 1);
3618 }
3619 tcg_temp_free_i64(t0);
3620 tcg_gen_or_i32(lo, lo, hi);
3621 tcg_temp_free(hi);
3622
3623 /* if shift == 0, register and X are not affected */
3624
3625 zero = tcg_const_i32(0);
3626 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3627 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3628 tcg_temp_free(zero);
3629 tcg_temp_free(lo);
3630
3631 return X;
3632 }
3633
3634 DISAS_INSN(rotate_im)
3635 {
3636 TCGv shift;
3637 int tmp;
3638 int left = (insn & 0x100);
3639
3640 tmp = (insn >> 9) & 7;
3641 if (tmp == 0) {
3642 tmp = 8;
3643 }
3644
3645 shift = tcg_const_i32(tmp);
3646 if (insn & 8) {
3647 rotate(DREG(insn, 0), shift, left, 32);
3648 } else {
3649 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3650 rotate_x_flags(DREG(insn, 0), X, 32);
3651 tcg_temp_free(X);
3652 }
3653 tcg_temp_free(shift);
3654
3655 set_cc_op(s, CC_OP_FLAGS);
3656 }
3657
3658 DISAS_INSN(rotate8_im)
3659 {
3660 int left = (insn & 0x100);
3661 TCGv reg;
3662 TCGv shift;
3663 int tmp;
3664
3665 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3666
3667 tmp = (insn >> 9) & 7;
3668 if (tmp == 0) {
3669 tmp = 8;
3670 }
3671
3672 shift = tcg_const_i32(tmp);
3673 if (insn & 8) {
3674 rotate(reg, shift, left, 8);
3675 } else {
3676 TCGv X = rotate_x(reg, shift, left, 8);
3677 rotate_x_flags(reg, X, 8);
3678 tcg_temp_free(X);
3679 }
3680 tcg_temp_free(shift);
3681 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3682 set_cc_op(s, CC_OP_FLAGS);
3683 }
3684
3685 DISAS_INSN(rotate16_im)
3686 {
3687 int left = (insn & 0x100);
3688 TCGv reg;
3689 TCGv shift;
3690 int tmp;
3691
3692 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3693 tmp = (insn >> 9) & 7;
3694 if (tmp == 0) {
3695 tmp = 8;
3696 }
3697
3698 shift = tcg_const_i32(tmp);
3699 if (insn & 8) {
3700 rotate(reg, shift, left, 16);
3701 } else {
3702 TCGv X = rotate_x(reg, shift, left, 16);
3703 rotate_x_flags(reg, X, 16);
3704 tcg_temp_free(X);
3705 }
3706 tcg_temp_free(shift);
3707 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3708 set_cc_op(s, CC_OP_FLAGS);
3709 }
3710
3711 DISAS_INSN(rotate_reg)
3712 {
3713 TCGv reg;
3714 TCGv src;
3715 TCGv t0, t1;
3716 int left = (insn & 0x100);
3717
3718 reg = DREG(insn, 0);
3719 src = DREG(insn, 9);
3720 /* shift in [0..63] */
3721 t0 = tcg_temp_new();
3722 tcg_gen_andi_i32(t0, src, 63);
3723 t1 = tcg_temp_new_i32();
3724 if (insn & 8) {
3725 tcg_gen_andi_i32(t1, src, 31);
3726 rotate(reg, t1, left, 32);
3727 /* if shift == 0, clear C */
3728 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3729 t0, QREG_CC_V /* 0 */,
3730 QREG_CC_V /* 0 */, QREG_CC_C);
3731 } else {
3732 TCGv X;
3733 /* modulo 33 */
3734 tcg_gen_movi_i32(t1, 33);
3735 tcg_gen_remu_i32(t1, t0, t1);
3736 X = rotate32_x(DREG(insn, 0), t1, left);
3737 rotate_x_flags(DREG(insn, 0), X, 32);
3738 tcg_temp_free(X);
3739 }
3740 tcg_temp_free(t1);
3741 tcg_temp_free(t0);
3742 set_cc_op(s, CC_OP_FLAGS);
3743 }
3744
3745 DISAS_INSN(rotate8_reg)
3746 {
3747 TCGv reg;
3748 TCGv src;
3749 TCGv t0, t1;
3750 int left = (insn & 0x100);
3751
3752 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3753 src = DREG(insn, 9);
3754 /* shift in [0..63] */
3755 t0 = tcg_temp_new_i32();
3756 tcg_gen_andi_i32(t0, src, 63);
3757 t1 = tcg_temp_new_i32();
3758 if (insn & 8) {
3759 tcg_gen_andi_i32(t1, src, 7);
3760 rotate(reg, t1, left, 8);
3761 /* if shift == 0, clear C */
3762 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3763 t0, QREG_CC_V /* 0 */,
3764 QREG_CC_V /* 0 */, QREG_CC_C);
3765 } else {
3766 TCGv X;
3767 /* modulo 9 */
3768 tcg_gen_movi_i32(t1, 9);
3769 tcg_gen_remu_i32(t1, t0, t1);
3770 X = rotate_x(reg, t1, left, 8);
3771 rotate_x_flags(reg, X, 8);
3772 tcg_temp_free(X);
3773 }
3774 tcg_temp_free(t1);
3775 tcg_temp_free(t0);
3776 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3777 set_cc_op(s, CC_OP_FLAGS);
3778 }
3779
3780 DISAS_INSN(rotate16_reg)
3781 {
3782 TCGv reg;
3783 TCGv src;
3784 TCGv t0, t1;
3785 int left = (insn & 0x100);
3786
3787 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3788 src = DREG(insn, 9);
3789 /* shift in [0..63] */
3790 t0 = tcg_temp_new_i32();
3791 tcg_gen_andi_i32(t0, src, 63);
3792 t1 = tcg_temp_new_i32();
3793 if (insn & 8) {
3794 tcg_gen_andi_i32(t1, src, 15);
3795 rotate(reg, t1, left, 16);
3796 /* if shift == 0, clear C */
3797 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3798 t0, QREG_CC_V /* 0 */,
3799 QREG_CC_V /* 0 */, QREG_CC_C);
3800 } else {
3801 TCGv X;
3802 /* modulo 17 */
3803 tcg_gen_movi_i32(t1, 17);
3804 tcg_gen_remu_i32(t1, t0, t1);
3805 X = rotate_x(reg, t1, left, 16);
3806 rotate_x_flags(reg, X, 16);
3807 tcg_temp_free(X);
3808 }
3809 tcg_temp_free(t1);
3810 tcg_temp_free(t0);
3811 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3812 set_cc_op(s, CC_OP_FLAGS);
3813 }
3814
3815 DISAS_INSN(rotate_mem)
3816 {
3817 TCGv src;
3818 TCGv addr;
3819 TCGv shift;
3820 int left = (insn & 0x100);
3821
3822 SRC_EA(env, src, OS_WORD, 0, &addr);
3823
3824 shift = tcg_const_i32(1);
3825 if (insn & 0x0200) {
3826 rotate(src, shift, left, 16);
3827 } else {
3828 TCGv X = rotate_x(src, shift, left, 16);
3829 rotate_x_flags(src, X, 16);
3830 tcg_temp_free(X);
3831 }
3832 tcg_temp_free(shift);
3833 DEST_EA(env, insn, OS_WORD, src, &addr);
3834 set_cc_op(s, CC_OP_FLAGS);
3835 }
3836
3837 DISAS_INSN(bfext_reg)
3838 {
3839 int ext = read_im16(env, s);
3840 int is_sign = insn & 0x200;
3841 TCGv src = DREG(insn, 0);
3842 TCGv dst = DREG(ext, 12);
3843 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3844 int ofs = extract32(ext, 6, 5); /* big bit-endian */
3845 int pos = 32 - ofs - len; /* little bit-endian */
3846 TCGv tmp = tcg_temp_new();
3847 TCGv shift;
3848
3849 /* In general, we're going to rotate the field so that it's at the
3850 top of the word and then right-shift by the compliment of the
3851 width to extend the field. */
3852 if (ext & 0x20) {
3853 /* Variable width. */
3854 if (ext & 0x800) {
3855 /* Variable offset. */
3856 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3857 tcg_gen_rotl_i32(tmp, src, tmp);
3858 } else {
3859 tcg_gen_rotli_i32(tmp, src, ofs);
3860 }
3861
3862 shift = tcg_temp_new();
3863 tcg_gen_neg_i32(shift, DREG(ext, 0));
3864 tcg_gen_andi_i32(shift, shift, 31);
3865 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
3866 if (is_sign) {
3867 tcg_gen_mov_i32(dst, QREG_CC_N);
3868 } else {
3869 tcg_gen_shr_i32(dst, tmp, shift);
3870 }
3871 tcg_temp_free(shift);
3872 } else {
3873 /* Immediate width. */
3874 if (ext & 0x800) {
3875 /* Variable offset */
3876 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3877 tcg_gen_rotl_i32(tmp, src, tmp);
3878 src = tmp;
3879 pos = 32 - len;
3880 } else {
3881 /* Immediate offset. If the field doesn't wrap around the
3882 end of the word, rely on (s)extract completely. */
3883 if (pos < 0) {
3884 tcg_gen_rotli_i32(tmp, src, ofs);
3885 src = tmp;
3886 pos = 32 - len;
3887 }
3888 }
3889
3890 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
3891 if (is_sign) {
3892 tcg_gen_mov_i32(dst, QREG_CC_N);
3893 } else {
3894 tcg_gen_extract_i32(dst, src, pos, len);
3895 }
3896 }
3897
3898 tcg_temp_free(tmp);
3899 set_cc_op(s, CC_OP_LOGIC);
3900 }
3901
3902 DISAS_INSN(bfext_mem)
3903 {
3904 int ext = read_im16(env, s);
3905 int is_sign = insn & 0x200;
3906 TCGv dest = DREG(ext, 12);
3907 TCGv addr, len, ofs;
3908
3909 addr = gen_lea(env, s, insn, OS_UNSIZED);
3910 if (IS_NULL_QREG(addr)) {
3911 gen_addr_fault(s);
3912 return;
3913 }
3914
3915 if (ext & 0x20) {
3916 len = DREG(ext, 0);
3917 } else {
3918 len = tcg_const_i32(extract32(ext, 0, 5));
3919 }
3920 if (ext & 0x800) {
3921 ofs = DREG(ext, 6);
3922 } else {
3923 ofs = tcg_const_i32(extract32(ext, 6, 5));
3924 }
3925
3926 if (is_sign) {
3927 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
3928 tcg_gen_mov_i32(QREG_CC_N, dest);
3929 } else {
3930 TCGv_i64 tmp = tcg_temp_new_i64();
3931 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
3932 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
3933 tcg_temp_free_i64(tmp);
3934 }
3935 set_cc_op(s, CC_OP_LOGIC);
3936
3937 if (!(ext & 0x20)) {
3938 tcg_temp_free(len);
3939 }
3940 if (!(ext & 0x800)) {
3941 tcg_temp_free(ofs);
3942 }
3943 }
3944
3945 DISAS_INSN(bfop_reg)
3946 {
3947 int ext = read_im16(env, s);
3948 TCGv src = DREG(insn, 0);
3949 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3950 int ofs = extract32(ext, 6, 5); /* big bit-endian */
3951 TCGv mask, tofs, tlen;
3952
3953 TCGV_UNUSED(tofs);
3954 TCGV_UNUSED(tlen);
3955 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
3956 tofs = tcg_temp_new();
3957 tlen = tcg_temp_new();
3958 }
3959
3960 if ((ext & 0x820) == 0) {
3961 /* Immediate width and offset. */
3962 uint32_t maski = 0x7fffffffu >> (len - 1);
3963 if (ofs + len <= 32) {
3964 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
3965 } else {
3966 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
3967 }
3968 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
3969 mask = tcg_const_i32(ror32(maski, ofs));
3970 if (!TCGV_IS_UNUSED(tofs)) {
3971 tcg_gen_movi_i32(tofs, ofs);
3972 tcg_gen_movi_i32(tlen, len);
3973 }
3974 } else {
3975 TCGv tmp = tcg_temp_new();
3976 if (ext & 0x20) {
3977 /* Variable width */
3978 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
3979 tcg_gen_andi_i32(tmp, tmp, 31);
3980 mask = tcg_const_i32(0x7fffffffu);
3981 tcg_gen_shr_i32(mask, mask, tmp);
3982 if (!TCGV_IS_UNUSED(tlen)) {
3983 tcg_gen_addi_i32(tlen, tmp, 1);
3984 }
3985 } else {
3986 /* Immediate width */
3987 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
3988 if (!TCGV_IS_UNUSED(tlen)) {
3989 tcg_gen_movi_i32(tlen, len);
3990 }
3991 }
3992 if (ext & 0x800) {
3993 /* Variable offset */
3994 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3995 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
3996 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
3997 tcg_gen_rotr_i32(mask, mask, tmp);
3998 if (!TCGV_IS_UNUSED(tofs)) {
3999 tcg_gen_mov_i32(tofs, tmp);
4000 }
4001 } else {
4002 /* Immediate offset (and variable width) */
4003 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4004 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4005 tcg_gen_rotri_i32(mask, mask, ofs);
4006 if (!TCGV_IS_UNUSED(tofs)) {
4007 tcg_gen_movi_i32(tofs, ofs);
4008 }
4009 }
4010 tcg_temp_free(tmp);
4011 }
4012 set_cc_op(s, CC_OP_LOGIC);
4013
4014 switch (insn & 0x0f00) {
4015 case 0x0a00: /* bfchg */
4016 tcg_gen_eqv_i32(src, src, mask);
4017 break;
4018 case 0x0c00: /* bfclr */
4019 tcg_gen_and_i32(src, src, mask);
4020 break;
4021 case 0x0d00: /* bfffo */
4022 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4023 tcg_temp_free(tlen);
4024 tcg_temp_free(tofs);
4025 break;
4026 case 0x0e00: /* bfset */
4027 tcg_gen_orc_i32(src, src, mask);
4028 break;
4029 case 0x0800: /* bftst */
4030 /* flags already set; no other work to do. */
4031 break;
4032 default:
4033 g_assert_not_reached();
4034 }
4035 tcg_temp_free(mask);
4036 }
4037
4038 DISAS_INSN(bfop_mem)
4039 {
4040 int ext = read_im16(env, s);
4041 TCGv addr, len, ofs;
4042 TCGv_i64 t64;
4043
4044 addr = gen_lea(env, s, insn, OS_UNSIZED);
4045 if (IS_NULL_QREG(addr)) {
4046 gen_addr_fault(s);
4047 return;
4048 }
4049
4050 if (ext & 0x20) {
4051 len = DREG(ext, 0);
4052 } else {
4053 len = tcg_const_i32(extract32(ext, 0, 5));
4054 }
4055 if (ext & 0x800) {
4056 ofs = DREG(ext, 6);
4057 } else {
4058 ofs = tcg_const_i32(extract32(ext, 6, 5));
4059 }
4060
4061 switch (insn & 0x0f00) {
4062 case 0x0a00: /* bfchg */
4063 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4064 break;
4065 case 0x0c00: /* bfclr */
4066 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4067 break;
4068 case 0x0d00: /* bfffo */
4069 t64 = tcg_temp_new_i64();
4070 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4071 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4072 tcg_temp_free_i64(t64);
4073 break;
4074 case 0x0e00: /* bfset */
4075 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4076 break;
4077 case 0x0800: /* bftst */
4078 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4079 break;
4080 default:
4081 g_assert_not_reached();
4082 }
4083 set_cc_op(s, CC_OP_LOGIC);
4084
4085 if (!(ext & 0x20)) {
4086 tcg_temp_free(len);
4087 }
4088 if (!(ext & 0x800)) {
4089 tcg_temp_free(ofs);
4090 }
4091 }
4092
4093 DISAS_INSN(bfins_reg)
4094 {
4095 int ext = read_im16(env, s);
4096 TCGv dst = DREG(insn, 0);
4097 TCGv src = DREG(ext, 12);
4098 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4099 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4100 int pos = 32 - ofs - len; /* little bit-endian */
4101 TCGv tmp;
4102
4103 tmp = tcg_temp_new();
4104
4105 if (ext & 0x20) {
4106 /* Variable width */
4107 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4108 tcg_gen_andi_i32(tmp, tmp, 31);
4109 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4110 } else {
4111 /* Immediate width */
4112 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4113 }
4114 set_cc_op(s, CC_OP_LOGIC);
4115
4116 /* Immediate width and offset */
4117 if ((ext & 0x820) == 0) {
4118 /* Check for suitability for deposit. */
4119 if (pos >= 0) {
4120 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4121 } else {
4122 uint32_t maski = -2U << (len - 1);
4123 uint32_t roti = (ofs + len) & 31;
4124 tcg_gen_andi_i32(tmp, src, ~maski);
4125 tcg_gen_rotri_i32(tmp, tmp, roti);
4126 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4127 tcg_gen_or_i32(dst, dst, tmp);
4128 }
4129 } else {
4130 TCGv mask = tcg_temp_new();
4131 TCGv rot = tcg_temp_new();
4132
4133 if (ext & 0x20) {
4134 /* Variable width */
4135 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4136 tcg_gen_andi_i32(rot, rot, 31);
4137 tcg_gen_movi_i32(mask, -2);
4138 tcg_gen_shl_i32(mask, mask, rot);
4139 tcg_gen_mov_i32(rot, DREG(ext, 0));
4140 tcg_gen_andc_i32(tmp, src, mask);
4141 } else {
4142 /* Immediate width (variable offset) */
4143 uint32_t maski = -2U << (len - 1);
4144 tcg_gen_andi_i32(tmp, src, ~maski);
4145 tcg_gen_movi_i32(mask, maski);
4146 tcg_gen_movi_i32(rot, len & 31);
4147 }
4148 if (ext & 0x800) {
4149 /* Variable offset */
4150 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4151 } else {
4152 /* Immediate offset (variable width) */
4153 tcg_gen_addi_i32(rot, rot, ofs);
4154 }
4155 tcg_gen_andi_i32(rot, rot, 31);
4156 tcg_gen_rotr_i32(mask, mask, rot);
4157 tcg_gen_rotr_i32(tmp, tmp, rot);
4158 tcg_gen_and_i32(dst, dst, mask);
4159 tcg_gen_or_i32(dst, dst, tmp);
4160
4161 tcg_temp_free(rot);
4162 tcg_temp_free(mask);
4163 }
4164 tcg_temp_free(tmp);
4165 }
4166
4167 DISAS_INSN(bfins_mem)
4168 {
4169 int ext = read_im16(env, s);
4170 TCGv src = DREG(ext, 12);
4171 TCGv addr, len, ofs;
4172
4173 addr = gen_lea(env, s, insn, OS_UNSIZED);
4174 if (IS_NULL_QREG(addr)) {
4175 gen_addr_fault(s);
4176 return;
4177 }
4178
4179 if (ext & 0x20) {
4180 len = DREG(ext, 0);
4181 } else {
4182 len = tcg_const_i32(extract32(ext, 0, 5));
4183 }
4184 if (ext & 0x800) {
4185 ofs = DREG(ext, 6);
4186 } else {
4187 ofs = tcg_const_i32(extract32(ext, 6, 5));
4188 }
4189
4190 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4191 set_cc_op(s, CC_OP_LOGIC);
4192
4193 if (!(ext & 0x20)) {
4194 tcg_temp_free(len);
4195 }
4196 if (!(ext & 0x800)) {
4197 tcg_temp_free(ofs);
4198 }
4199 }
4200
4201 DISAS_INSN(ff1)
4202 {
4203 TCGv reg;
4204 reg = DREG(insn, 0);
4205 gen_logic_cc(s, reg, OS_LONG);
4206 gen_helper_ff1(reg, reg);
4207 }
4208
4209 static TCGv gen_get_sr(DisasContext *s)
4210 {
4211 TCGv ccr;
4212 TCGv sr;
4213
4214 ccr = gen_get_ccr(s);
4215 sr = tcg_temp_new();
4216 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
4217 tcg_gen_or_i32(sr, sr, ccr);
4218 return sr;
4219 }
4220
4221 DISAS_INSN(strldsr)
4222 {
4223 uint16_t ext;
4224 uint32_t addr;
4225
4226 addr = s->pc - 2;
4227 ext = read_im16(env, s);
4228 if (ext != 0x46FC) {
4229 gen_exception(s, addr, EXCP_UNSUPPORTED);
4230 return;
4231 }
4232 ext = read_im16(env, s);
4233 if (IS_USER(s) || (ext & SR_S) == 0) {
4234 gen_exception(s, addr, EXCP_PRIVILEGE);
4235 return;
4236 }
4237 gen_push(s, gen_get_sr(s));
4238 gen_set_sr_im(s, ext, 0);
4239 }
4240
4241 DISAS_INSN(move_from_sr)
4242 {
4243 TCGv sr;
4244
4245 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
4246 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4247 return;
4248 }
4249 sr = gen_get_sr(s);
4250 DEST_EA(env, insn, OS_WORD, sr, NULL);
4251 }
4252
4253 DISAS_INSN(move_to_sr)
4254 {
4255 if (IS_USER(s)) {
4256 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4257 return;
4258 }
4259 gen_set_sr(env, s, insn, 0);
4260 gen_lookup_tb(s);
4261 }
4262
4263 DISAS_INSN(move_from_usp)
4264 {
4265 if (IS_USER(s)) {
4266 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4267 return;
4268 }
4269 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4270 offsetof(CPUM68KState, sp[M68K_USP]));
4271 }
4272
4273 DISAS_INSN(move_to_usp)
4274 {
4275 if (IS_USER(s)) {
4276 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4277 return;
4278 }
4279 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4280 offsetof(CPUM68KState, sp[M68K_USP]));
4281 }
4282
4283 DISAS_INSN(halt)
4284 {
4285 gen_exception(s, s->pc, EXCP_HALT_INSN);
4286 }
4287
4288 DISAS_INSN(stop)
4289 {
4290 uint16_t ext;
4291
4292 if (IS_USER(s)) {
4293 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4294 return;
4295 }
4296
4297 ext = read_im16(env, s);
4298
4299 gen_set_sr_im(s, ext, 0);
4300 tcg_gen_movi_i32(cpu_halted, 1);
4301 gen_exception(s, s->pc, EXCP_HLT);
4302 }
4303
4304 DISAS_INSN(rte)
4305 {
4306 if (IS_USER(s)) {
4307 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4308 return;
4309 }
4310 gen_exception(s, s->pc - 2, EXCP_RTE);
4311 }
4312
4313 DISAS_INSN(movec)
4314 {
4315 uint16_t ext;
4316 TCGv reg;
4317
4318 if (IS_USER(s)) {
4319 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4320 return;
4321 }
4322
4323 ext = read_im16(env, s);
4324
4325 if (ext & 0x8000) {
4326 reg = AREG(ext, 12);
4327 } else {
4328 reg = DREG(ext, 12);
4329 }
4330 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4331 gen_lookup_tb(s);
4332 }
4333
4334 DISAS_INSN(intouch)
4335 {
4336 if (IS_USER(s)) {
4337 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4338 return;
4339 }
4340 /* ICache fetch. Implement as no-op. */
4341 }
4342
4343 DISAS_INSN(cpushl)
4344 {
4345 if (IS_USER(s)) {
4346 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4347 return;
4348 }
4349 /* Cache push/invalidate. Implement as no-op. */
4350 }
4351
4352 DISAS_INSN(wddata)
4353 {
4354 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4355 }
4356
4357 DISAS_INSN(wdebug)
4358 {
4359 M68kCPU *cpu = m68k_env_get_cpu(env);
4360
4361 if (IS_USER(s)) {
4362 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4363 return;
4364 }
4365 /* TODO: Implement wdebug. */
4366 cpu_abort(CPU(cpu), "WDEBUG not implemented");
4367 }
4368
4369 DISAS_INSN(trap)
4370 {
4371 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
4372 }
4373
4374 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4375 {
4376 switch (reg) {
4377 case M68K_FPIAR:
4378 tcg_gen_movi_i32(res, 0);
4379 break;
4380 case M68K_FPSR:
4381 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4382 break;
4383 case M68K_FPCR:
4384 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4385 break;
4386 }
4387 }
4388
4389 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4390 {
4391 switch (reg) {
4392 case M68K_FPIAR:
4393 break;
4394 case M68K_FPSR:
4395 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4396 break;
4397 case M68K_FPCR:
4398 gen_helper_set_fpcr(cpu_env, val);
4399 break;
4400 }
4401 }
4402
4403 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4404 {
4405 int index = IS_USER(s);
4406 TCGv tmp;
4407
4408 tmp = tcg_temp_new();
4409 gen_load_fcr(s, tmp, reg);
4410 tcg_gen_qemu_st32(tmp, addr, index);
4411 tcg_temp_free(tmp);
4412 }
4413
4414 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4415 {
4416 int index = IS_USER(s);
4417 TCGv tmp;
4418
4419 tmp = tcg_temp_new();
4420 tcg_gen_qemu_ld32u(tmp, addr, index);
4421 gen_store_fcr(s, tmp, reg);
4422 tcg_temp_free(tmp);
4423 }
4424
4425
4426 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4427 uint32_t insn, uint32_t ext)
4428 {
4429 int mask = (ext >> 10) & 7;
4430 int is_write = (ext >> 13) & 1;
4431 int mode = extract32(insn, 3, 3);
4432 int i;
4433 TCGv addr, tmp;
4434
4435 switch (mode) {
4436 case 0: /* Dn */
4437 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4438 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4439 return;
4440 }
4441 if (is_write) {
4442 gen_load_fcr(s, DREG(insn, 0), mask);
4443 } else {
4444 gen_store_fcr(s, DREG(insn, 0), mask);
4445 }
4446 return;
4447 case 1: /* An, only with FPIAR */
4448 if (mask != M68K_FPIAR) {
4449 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4450 return;
4451 }
4452 if (is_write) {
4453 gen_load_fcr(s, AREG(insn, 0), mask);
4454 } else {
4455 gen_store_fcr(s, AREG(insn, 0), mask);
4456 }
4457 return;
4458 default:
4459 break;
4460 }
4461
4462 tmp = gen_lea(env, s, insn, OS_LONG);
4463 if (IS_NULL_QREG(tmp)) {
4464 gen_addr_fault(s);
4465 return;
4466 }
4467
4468 addr = tcg_temp_new();
4469 tcg_gen_mov_i32(addr, tmp);
4470
4471 /* mask:
4472 *
4473 * 0b100 Floating-Point Control Register
4474 * 0b010 Floating-Point Status Register
4475 * 0b001 Floating-Point Instruction Address Register
4476 *
4477 */
4478
4479 if (is_write && mode == 4) {
4480 for (i = 2; i >= 0; i--, mask >>= 1) {
4481 if (mask & 1) {
4482 gen_qemu_store_fcr(s, addr, 1 << i);
4483 if (mask != 1) {
4484 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
4485 }
4486 }
4487 }
4488 tcg_gen_mov_i32(AREG(insn, 0), addr);
4489 } else {
4490 for (i = 0; i < 3; i++, mask >>= 1) {
4491 if (mask & 1) {
4492 if (is_write) {
4493 gen_qemu_store_fcr(s, addr, 1 << i);
4494 } else {
4495 gen_qemu_load_fcr(s, addr, 1 << i);
4496 }
4497 if (mask != 1 || mode == 3) {
4498 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
4499 }
4500 }
4501 }
4502 if (mode == 3) {
4503 tcg_gen_mov_i32(AREG(insn, 0), addr);
4504 }
4505 }
4506 tcg_temp_free_i32(addr);
4507 }
4508
4509 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
4510 uint32_t insn, uint32_t ext)
4511 {
4512 int opsize;
4513 TCGv addr, tmp;
4514 int mode = (ext >> 11) & 0x3;
4515 int is_load = ((ext & 0x2000) == 0);
4516
4517 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
4518 opsize = OS_EXTENDED;
4519 } else {
4520 opsize = OS_DOUBLE; /* FIXME */
4521 }
4522
4523 addr = gen_lea(env, s, insn, opsize);
4524 if (IS_NULL_QREG(addr)) {
4525 gen_addr_fault(s);
4526 return;
4527 }
4528
4529 tmp = tcg_temp_new();
4530 if (mode & 0x1) {
4531 /* Dynamic register list */
4532 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
4533 } else {
4534 /* Static register list */
4535 tcg_gen_movi_i32(tmp, ext & 0xff);
4536 }
4537
4538 if (!is_load && (mode & 2) == 0) {
4539 /* predecrement addressing mode
4540 * only available to store register to memory
4541 */
4542 if (opsize == OS_EXTENDED) {
4543 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
4544 } else {
4545 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
4546 }
4547 } else {
4548 /* postincrement addressing mode */
4549 if (opsize == OS_EXTENDED) {
4550 if (is_load) {
4551 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
4552 } else {
4553 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
4554 }
4555 } else {
4556 if (is_load) {
4557 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
4558 } else {
4559 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
4560 }
4561 }
4562 }
4563 if ((insn & 070) == 030 || (insn & 070) == 040) {
4564 tcg_gen_mov_i32(AREG(insn, 0), tmp);
4565 }
4566 tcg_temp_free(tmp);
4567 }
4568
4569 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4570 immediately before the next FP instruction is executed. */
4571 DISAS_INSN(fpu)
4572 {
4573 uint16_t ext;
4574 int opmode;
4575 int opsize;
4576 TCGv_ptr cpu_src, cpu_dest;
4577
4578 ext = read_im16(env, s);
4579 opmode = ext & 0x7f;
4580 switch ((ext >> 13) & 7) {
4581 case 0:
4582 break;
4583 case 1:
4584 goto undef;
4585 case 2:
4586 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
4587 /* fmovecr */
4588 TCGv rom_offset = tcg_const_i32(opmode);
4589 cpu_dest = gen_fp_ptr(REG(ext, 7));
4590 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
4591 tcg_temp_free_ptr(cpu_dest);
4592 tcg_temp_free(rom_offset);
4593 return;
4594 }
4595 break;
4596 case 3: /* fmove out */
4597 cpu_src = gen_fp_ptr(REG(ext, 7));
4598 opsize = ext_opsize(ext, 10);
4599 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) == -1) {
4600 gen_addr_fault(s);
4601 }
4602 gen_helper_ftst(cpu_env, cpu_src);
4603 tcg_temp_free_ptr(cpu_src);
4604 return;
4605 case 4: /* fmove to control register. */
4606 case 5: /* fmove from control register. */
4607 gen_op_fmove_fcr(env, s, insn, ext);
4608 return;
4609 case 6: /* fmovem */
4610 case 7:
4611 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
4612 goto undef;
4613 }
4614 gen_op_fmovem(env, s, insn, ext);
4615 return;
4616 }
4617 if (ext & (1 << 14)) {
4618 /* Source effective address. */
4619 opsize = ext_opsize(ext, 10);
4620 cpu_src = gen_fp_result_ptr();
4621 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) == -1) {
4622 gen_addr_fault(s);
4623 return;
4624 }
4625 } else {
4626 /* Source register. */
4627 opsize = OS_EXTENDED;
4628 cpu_src = gen_fp_ptr(REG(ext, 10));
4629 }
4630 cpu_dest = gen_fp_ptr(REG(ext, 7));
4631 switch (opmode) {
4632 case 0: /* fmove */
4633 gen_fp_move(cpu_dest, cpu_src);
4634 break;
4635 case 0x40: /* fsmove */
4636 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
4637 break;
4638 case 0x44: /* fdmove */
4639 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
4640 break;
4641 case 1: /* fint */
4642 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
4643 break;
4644 case 3: /* fintrz */
4645 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
4646 break;
4647 case 4: /* fsqrt */
4648 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
4649 break;
4650 case 0x41: /* fssqrt */
4651 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
4652 break;
4653 case 0x45: /* fdsqrt */
4654 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
4655 break;
4656 case 0x18: /* fabs */
4657 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
4658 break;
4659 case 0x58: /* fsabs */
4660 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
4661 break;
4662 case 0x5c: /* fdabs */
4663 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
4664 break;
4665 case 0x1a: /* fneg */
4666 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
4667 break;
4668 case 0x5a: /* fsneg */
4669 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
4670 break;
4671 case 0x5e: /* fdneg */
4672 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
4673 break;
4674 case 0x20: /* fdiv */
4675 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4676 break;
4677 case 0x60: /* fsdiv */
4678 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4679 break;
4680 case 0x64: /* fddiv */
4681 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4682 break;
4683 case 0x22: /* fadd */
4684 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4685 break;
4686 case 0x62: /* fsadd */
4687 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4688 break;
4689 case 0x66: /* fdadd */
4690 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4691 break;
4692 case 0x23: /* fmul */
4693 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4694 break;
4695 case 0x63: /* fsmul */
4696 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4697 break;
4698 case 0x67: /* fdmul */
4699 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4700 break;
4701 case 0x24: /* fsgldiv */
4702 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4703 break;
4704 case 0x27: /* fsglmul */
4705 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4706 break;
4707 case 0x28: /* fsub */
4708 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4709 break;
4710 case 0x68: /* fssub */
4711 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4712 break;
4713 case 0x6c: /* fdsub */
4714 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4715 break;
4716 case 0x38: /* fcmp */
4717 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
4718 return;
4719 case 0x3a: /* ftst */
4720 gen_helper_ftst(cpu_env, cpu_src);
4721 return;
4722 default:
4723 goto undef;
4724 }
4725 tcg_temp_free_ptr(cpu_src);
4726 gen_helper_ftst(cpu_env, cpu_dest);
4727 tcg_temp_free_ptr(cpu_dest);
4728 return;
4729 undef:
4730 /* FIXME: Is this right for offset addressing modes? */
4731 s->pc -= 2;
4732 disas_undef_fpu(env, s, insn);
4733 }
4734
4735 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
4736 {
4737 TCGv fpsr;
4738
4739 c->g1 = 1;
4740 c->v2 = tcg_const_i32(0);
4741 c->g2 = 0;
4742 /* TODO: Raise BSUN exception. */
4743 fpsr = tcg_temp_new();
4744 gen_load_fcr(s, fpsr, M68K_FPSR);
4745 switch (cond) {
4746 case 0: /* False */
4747 case 16: /* Signaling False */
4748 c->v1 = c->v2;
4749 c->tcond = TCG_COND_NEVER;
4750 break;
4751 case 1: /* EQual Z */
4752 case 17: /* Signaling EQual Z */
4753 c->v1 = tcg_temp_new();
4754 c->g1 = 0;
4755 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4756 c->tcond = TCG_COND_NE;
4757 break;
4758 case 2: /* Ordered Greater Than !(A || Z || N) */
4759 case 18: /* Greater Than !(A || Z || N) */
4760 c->v1 = tcg_temp_new();
4761 c->g1 = 0;
4762 tcg_gen_andi_i32(c->v1, fpsr,
4763 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4764 c->tcond = TCG_COND_EQ;
4765 break;
4766 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
4767 case 19: /* Greater than or Equal Z || !(A || N) */
4768 c->v1 = tcg_temp_new();
4769 c->g1 = 0;
4770 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4771 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4772 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
4773 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4774 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4775 c->tcond = TCG_COND_NE;
4776 break;
4777 case 4: /* Ordered Less Than !(!N || A || Z); */
4778 case 20: /* Less Than !(!N || A || Z); */
4779 c->v1 = tcg_temp_new();
4780 c->g1 = 0;
4781 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
4782 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
4783 c->tcond = TCG_COND_EQ;
4784 break;
4785 case 5: /* Ordered Less than or Equal Z || (N && !A) */
4786 case 21: /* Less than or Equal Z || (N && !A) */
4787 c->v1 = tcg_temp_new();
4788 c->g1 = 0;
4789 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4790 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4791 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4792 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
4793 c->tcond = TCG_COND_NE;
4794 break;
4795 case 6: /* Ordered Greater or Less than !(A || Z) */
4796 case 22: /* Greater or Less than !(A || Z) */
4797 c->v1 = tcg_temp_new();
4798 c->g1 = 0;
4799 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4800 c->tcond = TCG_COND_EQ;
4801 break;
4802 case 7: /* Ordered !A */
4803 case 23: /* Greater, Less or Equal !A */
4804 c->v1 = tcg_temp_new();
4805 c->g1 = 0;
4806 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4807 c->tcond = TCG_COND_EQ;
4808 break;
4809 case 8: /* Unordered A */
4810 case 24: /* Not Greater, Less or Equal A */
4811 c->v1 = tcg_temp_new();
4812 c->g1 = 0;
4813 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4814 c->tcond = TCG_COND_NE;
4815 break;
4816 case 9: /* Unordered or Equal A || Z */
4817 case 25: /* Not Greater or Less then A || Z */
4818 c->v1 = tcg_temp_new();
4819 c->g1 = 0;
4820 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4821 c->tcond = TCG_COND_NE;
4822 break;
4823 case 10: /* Unordered or Greater Than A || !(N || Z)) */
4824 case 26: /* Not Less or Equal A || !(N || Z)) */
4825 c->v1 = tcg_temp_new();
4826 c->g1 = 0;
4827 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4828 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4829 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
4830 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4831 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4832 c->tcond = TCG_COND_NE;
4833 break;
4834 case 11: /* Unordered or Greater or Equal A || Z || !N */
4835 case 27: /* Not Less Than A || Z || !N */
4836 c->v1 = tcg_temp_new();
4837 c->g1 = 0;
4838 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4839 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4840 c->tcond = TCG_COND_NE;
4841 break;
4842 case 12: /* Unordered or Less Than A || (N && !Z) */
4843 case 28: /* Not Greater than or Equal A || (N && !Z) */
4844 c->v1 = tcg_temp_new();
4845 c->g1 = 0;
4846 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4847 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4848 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4849 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
4850 c->tcond = TCG_COND_NE;
4851 break;
4852 case 13: /* Unordered or Less or Equal A || Z || N */
4853 case 29: /* Not Greater Than A || Z || N */
4854 c->v1 = tcg_temp_new();
4855 c->g1 = 0;
4856 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4857 c->tcond = TCG_COND_NE;
4858 break;
4859 case 14: /* Not Equal !Z */
4860 case 30: /* Signaling Not Equal !Z */
4861 c->v1 = tcg_temp_new();
4862 c->g1 = 0;
4863 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4864 c->tcond = TCG_COND_EQ;
4865 break;
4866 case 15: /* True */
4867 case 31: /* Signaling True */
4868 c->v1 = c->v2;
4869 c->tcond = TCG_COND_ALWAYS;
4870 break;
4871 }
4872 tcg_temp_free(fpsr);
4873 }
4874
4875 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
4876 {
4877 DisasCompare c;
4878
4879 gen_fcc_cond(&c, s, cond);
4880 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
4881 free_cond(&c);
4882 }
4883
4884 DISAS_INSN(fbcc)
4885 {
4886 uint32_t offset;
4887 uint32_t base;
4888 TCGLabel *l1;
4889
4890 base = s->pc;
4891 offset = (int16_t)read_im16(env, s);
4892 if (insn & (1 << 6)) {
4893 offset = (offset << 16) | read_im16(env, s);
4894 }
4895
4896 l1 = gen_new_label();
4897 update_cc_op(s);
4898 gen_fjmpcc(s, insn & 0x3f, l1);
4899 gen_jmp_tb(s, 0, s->pc);
4900 gen_set_label(l1);
4901 gen_jmp_tb(s, 1, base + offset);
4902 }
4903
4904 DISAS_INSN(fscc)
4905 {
4906 DisasCompare c;
4907 int cond;
4908 TCGv tmp;
4909 uint16_t ext;
4910
4911 ext = read_im16(env, s);
4912 cond = ext & 0x3f;
4913 gen_fcc_cond(&c, s, cond);
4914
4915 tmp = tcg_temp_new();
4916 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
4917 free_cond(&c);
4918
4919 tcg_gen_neg_i32(tmp, tmp);
4920 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
4921 tcg_temp_free(tmp);
4922 }
4923
4924 static void QEMU_NORETURN disas_frestore(CPUM68KState *env,
4925 DisasContext *s, uint16_t insn);
4926 DISAS_INSN(frestore)
4927 {
4928 M68kCPU *cpu = m68k_env_get_cpu(env);
4929
4930 /* TODO: Implement frestore. */
4931 cpu_abort(CPU(cpu), "FRESTORE not implemented");
4932 }
4933
4934 static void QEMU_NORETURN disas_fsave(CPUM68KState *env,
4935 DisasContext *s, uint16_t insn);
4936 DISAS_INSN(fsave)
4937 {
4938 M68kCPU *cpu = m68k_env_get_cpu(env);
4939
4940 /* TODO: Implement fsave. */
4941 cpu_abort(CPU(cpu), "FSAVE not implemented");
4942 }
4943
4944 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
4945 {
4946 TCGv tmp = tcg_temp_new();
4947 if (s->env->macsr & MACSR_FI) {
4948 if (upper)
4949 tcg_gen_andi_i32(tmp, val, 0xffff0000);
4950 else
4951 tcg_gen_shli_i32(tmp, val, 16);
4952 } else if (s->env->macsr & MACSR_SU) {
4953 if (upper)
4954 tcg_gen_sari_i32(tmp, val, 16);
4955 else
4956 tcg_gen_ext16s_i32(tmp, val);
4957 } else {
4958 if (upper)
4959 tcg_gen_shri_i32(tmp, val, 16);
4960 else
4961 tcg_gen_ext16u_i32(tmp, val);
4962 }
4963 return tmp;
4964 }
4965
4966 static void gen_mac_clear_flags(void)
4967 {
4968 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
4969 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
4970 }
4971
4972 DISAS_INSN(mac)
4973 {
4974 TCGv rx;
4975 TCGv ry;
4976 uint16_t ext;
4977 int acc;
4978 TCGv tmp;
4979 TCGv addr;
4980 TCGv loadval;
4981 int dual;
4982 TCGv saved_flags;
4983
4984 if (!s->done_mac) {
4985 s->mactmp = tcg_temp_new_i64();
4986 s->done_mac = 1;
4987 }
4988
4989 ext = read_im16(env, s);
4990
4991 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
4992 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
4993 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
4994 disas_undef(env, s, insn);
4995 return;
4996 }
4997 if (insn & 0x30) {
4998 /* MAC with load. */
4999 tmp = gen_lea(env, s, insn, OS_LONG);
5000 addr = tcg_temp_new();
5001 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5002 /* Load the value now to ensure correct exception behavior.
5003 Perform writeback after reading the MAC inputs. */
5004 loadval = gen_load(s, OS_LONG, addr, 0);
5005
5006 acc ^= 1;
5007 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5008 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5009 } else {
5010 loadval = addr = NULL_QREG;
5011 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5012 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5013 }
5014
5015 gen_mac_clear_flags();
5016 #if 0
5017 l1 = -1;
5018 /* Disabled because conditional branches clobber temporary vars. */
5019 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5020 /* Skip the multiply if we know we will ignore it. */
5021 l1 = gen_new_label();
5022 tmp = tcg_temp_new();
5023 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5024 gen_op_jmp_nz32(tmp, l1);
5025 }
5026 #endif
5027
5028 if ((ext & 0x0800) == 0) {
5029 /* Word. */
5030 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5031 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5032 }
5033 if (s->env->macsr & MACSR_FI) {
5034 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5035 } else {
5036 if (s->env->macsr & MACSR_SU)
5037 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5038 else
5039 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5040 switch ((ext >> 9) & 3) {
5041 case 1:
5042 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5043 break;
5044 case 3:
5045 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5046 break;
5047 }
5048 }
5049
5050 if (dual) {
5051 /* Save the overflow flag from the multiply. */
5052 saved_flags = tcg_temp_new();
5053 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5054 } else {
5055 saved_flags = NULL_QREG;
5056 }
5057
5058 #if 0
5059 /* Disabled because conditional branches clobber temporary vars. */
5060 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5061 /* Skip the accumulate if the value is already saturated. */
5062 l1 = gen_new_label();
5063 tmp = tcg_temp_new();
5064 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5065 gen_op_jmp_nz32(tmp, l1);
5066 }
5067 #endif
5068
5069 if (insn & 0x100)
5070 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5071 else
5072 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5073
5074 if (s->env->macsr & MACSR_FI)
5075 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5076 else if (s->env->macsr & MACSR_SU)
5077 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5078 else
5079 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5080
5081 #if 0
5082 /* Disabled because conditional branches clobber temporary vars. */
5083 if (l1 != -1)
5084 gen_set_label(l1);
5085 #endif
5086
5087 if (dual) {
5088 /* Dual accumulate variant. */
5089 acc = (ext >> 2) & 3;
5090 /* Restore the overflow flag from the multiplier. */
5091 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5092 #if 0
5093 /* Disabled because conditional branches clobber temporary vars. */
5094 if ((s->env->macsr & MACSR_OMC) != 0) {
5095 /* Skip the accumulate if the value is already saturated. */
5096 l1 = gen_new_label();
5097 tmp = tcg_temp_new();
5098 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5099 gen_op_jmp_nz32(tmp, l1);
5100 }
5101 #endif
5102 if (ext & 2)
5103 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5104 else
5105 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5106 if (s->env->macsr & MACSR_FI)
5107 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5108 else if (s->env->macsr & MACSR_SU)
5109 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5110 else
5111 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5112 #if 0
5113 /* Disabled because conditional branches clobber temporary vars. */
5114 if (l1 != -1)
5115 gen_set_label(l1);
5116 #endif
5117 }
5118 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5119
5120 if (insn & 0x30) {
5121 TCGv rw;
5122 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5123 tcg_gen_mov_i32(rw, loadval);
5124 /* FIXME: Should address writeback happen with the masked or
5125 unmasked value? */
5126 switch ((insn >> 3) & 7) {
5127 case 3: /* Post-increment. */
5128 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5129 break;
5130 case 4: /* Pre-decrement. */
5131 tcg_gen_mov_i32(AREG(insn, 0), addr);
5132 }
5133 }
5134 }
5135
5136 DISAS_INSN(from_mac)
5137 {
5138 TCGv rx;
5139 TCGv_i64 acc;
5140 int accnum;
5141
5142 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5143 accnum = (insn >> 9) & 3;
5144 acc = MACREG(accnum);
5145 if (s->env->macsr & MACSR_FI) {
5146 gen_helper_get_macf(rx, cpu_env, acc);
5147 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5148 tcg_gen_extrl_i64_i32(rx, acc);
5149 } else if (s->env->macsr & MACSR_SU) {
5150 gen_helper_get_macs(rx, acc);
5151 } else {
5152 gen_helper_get_macu(rx, acc);
5153 }
5154 if (insn & 0x40) {
5155 tcg_gen_movi_i64(acc, 0);
5156 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5157 }
5158 }
5159
5160 DISAS_INSN(move_mac)
5161 {
5162 /* FIXME: This can be done without a helper. */
5163 int src;
5164 TCGv dest;
5165 src = insn & 3;
5166 dest = tcg_const_i32((insn >> 9) & 3);
5167 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5168 gen_mac_clear_flags();
5169 gen_helper_mac_set_flags(cpu_env, dest);
5170 }
5171
5172 DISAS_INSN(from_macsr)
5173 {
5174 TCGv reg;
5175
5176 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5177 tcg_gen_mov_i32(reg, QREG_MACSR);
5178 }
5179
5180 DISAS_INSN(from_mask)
5181 {
5182 TCGv reg;
5183 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5184 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5185 }
5186
5187 DISAS_INSN(from_mext)
5188 {
5189 TCGv reg;
5190 TCGv acc;
5191 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5192 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5193 if (s->env->macsr & MACSR_FI)
5194 gen_helper_get_mac_extf(reg, cpu_env, acc);
5195 else
5196 gen_helper_get_mac_exti(reg, cpu_env, acc);
5197 }
5198
5199 DISAS_INSN(macsr_to_ccr)
5200 {
5201 TCGv tmp = tcg_temp_new();
5202 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5203 gen_helper_set_sr(cpu_env, tmp);
5204 tcg_temp_free(tmp);
5205 set_cc_op(s, CC_OP_FLAGS);
5206 }
5207
5208 DISAS_INSN(to_mac)
5209 {
5210 TCGv_i64 acc;
5211 TCGv val;
5212 int accnum;
5213 accnum = (insn >> 9) & 3;
5214 acc = MACREG(accnum);
5215 SRC_EA(env, val, OS_LONG, 0, NULL);
5216 if (s->env->macsr & MACSR_FI) {
5217 tcg_gen_ext_i32_i64(acc, val);
5218 tcg_gen_shli_i64(acc, acc, 8);
5219 } else if (s->env->macsr & MACSR_SU) {
5220 tcg_gen_ext_i32_i64(acc, val);
5221 } else {
5222 tcg_gen_extu_i32_i64(acc, val);
5223 }
5224 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5225 gen_mac_clear_flags();
5226 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5227 }
5228
5229 DISAS_INSN(to_macsr)
5230 {
5231 TCGv val;
5232 SRC_EA(env, val, OS_LONG, 0, NULL);
5233 gen_helper_set_macsr(cpu_env, val);
5234 gen_lookup_tb(s);
5235 }
5236
5237 DISAS_INSN(to_mask)
5238 {
5239 TCGv val;
5240 SRC_EA(env, val, OS_LONG, 0, NULL);
5241 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5242 }
5243
5244 DISAS_INSN(to_mext)
5245 {
5246 TCGv val;
5247 TCGv acc;
5248 SRC_EA(env, val, OS_LONG, 0, NULL);
5249 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5250 if (s->env->macsr & MACSR_FI)
5251 gen_helper_set_mac_extf(cpu_env, val, acc);
5252 else if (s->env->macsr & MACSR_SU)
5253 gen_helper_set_mac_exts(cpu_env, val, acc);
5254 else
5255 gen_helper_set_mac_extu(cpu_env, val, acc);
5256 }
5257
5258 static disas_proc opcode_table[65536];
5259
5260 static void
5261 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5262 {
5263 int i;
5264 int from;
5265 int to;
5266
5267 /* Sanity check. All set bits must be included in the mask. */
5268 if (opcode & ~mask) {
5269 fprintf(stderr,
5270 "qemu internal error: bogus opcode definition %04x/%04x\n",
5271 opcode, mask);
5272 abort();
5273 }
5274 /* This could probably be cleverer. For now just optimize the case where
5275 the top bits are known. */
5276 /* Find the first zero bit in the mask. */
5277 i = 0x8000;
5278 while ((i & mask) != 0)
5279 i >>= 1;
5280 /* Iterate over all combinations of this and lower bits. */
5281 if (i == 0)
5282 i = 1;
5283 else
5284 i <<= 1;
5285 from = opcode & ~(i - 1);
5286 to = from + i;
5287 for (i = from; i < to; i++) {
5288 if ((i & mask) == opcode)
5289 opcode_table[i] = proc;
5290 }
5291 }
5292
5293 /* Register m68k opcode handlers. Order is important.
5294 Later insn override earlier ones. */
5295 void register_m68k_insns (CPUM68KState *env)
5296 {
5297 /* Build the opcode table only once to avoid
5298 multithreading issues. */
5299 if (opcode_table[0] != NULL) {
5300 return;
5301 }
5302
5303 /* use BASE() for instruction available
5304 * for CF_ISA_A and M68000.
5305 */
5306 #define BASE(name, opcode, mask) \
5307 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5308 #define INSN(name, opcode, mask, feature) do { \
5309 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5310 BASE(name, opcode, mask); \
5311 } while(0)
5312 BASE(undef, 0000, 0000);
5313 INSN(arith_im, 0080, fff8, CF_ISA_A);
5314 INSN(arith_im, 0000, ff00, M68000);
5315 INSN(undef, 00c0, ffc0, M68000);
5316 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
5317 BASE(bitop_reg, 0100, f1c0);
5318 BASE(bitop_reg, 0140, f1c0);
5319 BASE(bitop_reg, 0180, f1c0);
5320 BASE(bitop_reg, 01c0, f1c0);
5321 INSN(arith_im, 0280, fff8, CF_ISA_A);
5322 INSN(arith_im, 0200, ff00, M68000);
5323 INSN(undef, 02c0, ffc0, M68000);
5324 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
5325 INSN(arith_im, 0480, fff8, CF_ISA_A);
5326 INSN(arith_im, 0400, ff00, M68000);
5327 INSN(undef, 04c0, ffc0, M68000);
5328 INSN(arith_im, 0600, ff00, M68000);
5329 INSN(undef, 06c0, ffc0, M68000);
5330 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
5331 INSN(arith_im, 0680, fff8, CF_ISA_A);
5332 INSN(arith_im, 0c00, ff38, CF_ISA_A);
5333 INSN(arith_im, 0c00, ff00, M68000);
5334 BASE(bitop_im, 0800, ffc0);
5335 BASE(bitop_im, 0840, ffc0);
5336 BASE(bitop_im, 0880, ffc0);
5337 BASE(bitop_im, 08c0, ffc0);
5338 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5339 INSN(arith_im, 0a00, ff00, M68000);
5340 INSN(cas, 0ac0, ffc0, CAS);
5341 INSN(cas, 0cc0, ffc0, CAS);
5342 INSN(cas, 0ec0, ffc0, CAS);
5343 INSN(cas2w, 0cfc, ffff, CAS);
5344 INSN(cas2l, 0efc, ffff, CAS);
5345 BASE(move, 1000, f000);
5346 BASE(move, 2000, f000);
5347 BASE(move, 3000, f000);
5348 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
5349 INSN(negx, 4080, fff8, CF_ISA_A);
5350 INSN(negx, 4000, ff00, M68000);
5351 INSN(undef, 40c0, ffc0, M68000);
5352 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
5353 INSN(move_from_sr, 40c0, ffc0, M68000);
5354 BASE(lea, 41c0, f1c0);
5355 BASE(clr, 4200, ff00);
5356 BASE(undef, 42c0, ffc0);
5357 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
5358 INSN(move_from_ccr, 42c0, ffc0, M68000);
5359 INSN(neg, 4480, fff8, CF_ISA_A);
5360 INSN(neg, 4400, ff00, M68000);
5361 INSN(undef, 44c0, ffc0, M68000);
5362 BASE(move_to_ccr, 44c0, ffc0);
5363 INSN(not, 4680, fff8, CF_ISA_A);
5364 INSN(not, 4600, ff00, M68000);
5365 INSN(undef, 46c0, ffc0, M68000);
5366 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
5367 INSN(nbcd, 4800, ffc0, M68000);
5368 INSN(linkl, 4808, fff8, M68000);
5369 BASE(pea, 4840, ffc0);
5370 BASE(swap, 4840, fff8);
5371 INSN(bkpt, 4848, fff8, BKPT);
5372 INSN(movem, 48d0, fbf8, CF_ISA_A);
5373 INSN(movem, 48e8, fbf8, CF_ISA_A);
5374 INSN(movem, 4880, fb80, M68000);
5375 BASE(ext, 4880, fff8);
5376 BASE(ext, 48c0, fff8);
5377 BASE(ext, 49c0, fff8);
5378 BASE(tst, 4a00, ff00);
5379 INSN(tas, 4ac0, ffc0, CF_ISA_B);
5380 INSN(tas, 4ac0, ffc0, M68000);
5381 INSN(halt, 4ac8, ffff, CF_ISA_A);
5382 INSN(pulse, 4acc, ffff, CF_ISA_A);
5383 BASE(illegal, 4afc, ffff);
5384 INSN(mull, 4c00, ffc0, CF_ISA_A);
5385 INSN(mull, 4c00, ffc0, LONG_MULDIV);
5386 INSN(divl, 4c40, ffc0, CF_ISA_A);
5387 INSN(divl, 4c40, ffc0, LONG_MULDIV);
5388 INSN(sats, 4c80, fff8, CF_ISA_B);
5389 BASE(trap, 4e40, fff0);
5390 BASE(link, 4e50, fff8);
5391 BASE(unlk, 4e58, fff8);
5392 INSN(move_to_usp, 4e60, fff8, USP);
5393 INSN(move_from_usp, 4e68, fff8, USP);
5394 BASE(nop, 4e71, ffff);
5395 BASE(stop, 4e72, ffff);
5396 BASE(rte, 4e73, ffff);
5397 INSN(rtd, 4e74, ffff, RTD);
5398 BASE(rts, 4e75, ffff);
5399 INSN(movec, 4e7b, ffff, CF_ISA_A);
5400 BASE(jump, 4e80, ffc0);
5401 BASE(jump, 4ec0, ffc0);
5402 INSN(addsubq, 5000, f080, M68000);
5403 BASE(addsubq, 5080, f0c0);
5404 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
5405 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
5406 INSN(dbcc, 50c8, f0f8, M68000);
5407 INSN(tpf, 51f8, fff8, CF_ISA_A);
5408
5409 /* Branch instructions. */
5410 BASE(branch, 6000, f000);
5411 /* Disable long branch instructions, then add back the ones we want. */
5412 BASE(undef, 60ff, f0ff); /* All long branches. */
5413 INSN(branch, 60ff, f0ff, CF_ISA_B);
5414 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
5415 INSN(branch, 60ff, ffff, BRAL);
5416 INSN(branch, 60ff, f0ff, BCCL);
5417
5418 BASE(moveq, 7000, f100);
5419 INSN(mvzs, 7100, f100, CF_ISA_B);
5420 BASE(or, 8000, f000);
5421 BASE(divw, 80c0, f0c0);
5422 INSN(sbcd_reg, 8100, f1f8, M68000);
5423 INSN(sbcd_mem, 8108, f1f8, M68000);
5424 BASE(addsub, 9000, f000);
5425 INSN(undef, 90c0, f0c0, CF_ISA_A);
5426 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
5427 INSN(subx_reg, 9100, f138, M68000);
5428 INSN(subx_mem, 9108, f138, M68000);
5429 INSN(suba, 91c0, f1c0, CF_ISA_A);
5430 INSN(suba, 90c0, f0c0, M68000);
5431
5432 BASE(undef_mac, a000, f000);
5433 INSN(mac, a000, f100, CF_EMAC);
5434 INSN(from_mac, a180, f9b0, CF_EMAC);
5435 INSN(move_mac, a110, f9fc, CF_EMAC);
5436 INSN(from_macsr,a980, f9f0, CF_EMAC);
5437 INSN(from_mask, ad80, fff0, CF_EMAC);
5438 INSN(from_mext, ab80, fbf0, CF_EMAC);
5439 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
5440 INSN(to_mac, a100, f9c0, CF_EMAC);
5441 INSN(to_macsr, a900, ffc0, CF_EMAC);
5442 INSN(to_mext, ab00, fbc0, CF_EMAC);
5443 INSN(to_mask, ad00, ffc0, CF_EMAC);
5444
5445 INSN(mov3q, a140, f1c0, CF_ISA_B);
5446 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
5447 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
5448 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
5449 INSN(cmp, b080, f1c0, CF_ISA_A);
5450 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
5451 INSN(cmp, b000, f100, M68000);
5452 INSN(eor, b100, f100, M68000);
5453 INSN(cmpm, b108, f138, M68000);
5454 INSN(cmpa, b0c0, f0c0, M68000);
5455 INSN(eor, b180, f1c0, CF_ISA_A);
5456 BASE(and, c000, f000);
5457 INSN(exg_dd, c140, f1f8, M68000);
5458 INSN(exg_aa, c148, f1f8, M68000);
5459 INSN(exg_da, c188, f1f8, M68000);
5460 BASE(mulw, c0c0, f0c0);
5461 INSN(abcd_reg, c100, f1f8, M68000);
5462 INSN(abcd_mem, c108, f1f8, M68000);
5463 BASE(addsub, d000, f000);
5464 INSN(undef, d0c0, f0c0, CF_ISA_A);
5465 INSN(addx_reg, d180, f1f8, CF_ISA_A);
5466 INSN(addx_reg, d100, f138, M68000);
5467 INSN(addx_mem, d108, f138, M68000);
5468 INSN(adda, d1c0, f1c0, CF_ISA_A);
5469 INSN(adda, d0c0, f0c0, M68000);
5470 INSN(shift_im, e080, f0f0, CF_ISA_A);
5471 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
5472 INSN(shift8_im, e000, f0f0, M68000);
5473 INSN(shift16_im, e040, f0f0, M68000);
5474 INSN(shift_im, e080, f0f0, M68000);
5475 INSN(shift8_reg, e020, f0f0, M68000);
5476 INSN(shift16_reg, e060, f0f0, M68000);
5477 INSN(shift_reg, e0a0, f0f0, M68000);
5478 INSN(shift_mem, e0c0, fcc0, M68000);
5479 INSN(rotate_im, e090, f0f0, M68000);
5480 INSN(rotate8_im, e010, f0f0, M68000);
5481 INSN(rotate16_im, e050, f0f0, M68000);
5482 INSN(rotate_reg, e0b0, f0f0, M68000);
5483 INSN(rotate8_reg, e030, f0f0, M68000);
5484 INSN(rotate16_reg, e070, f0f0, M68000);
5485 INSN(rotate_mem, e4c0, fcc0, M68000);
5486 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
5487 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
5488 INSN(bfins_mem, efc0, ffc0, BITFIELD);
5489 INSN(bfins_reg, efc0, fff8, BITFIELD);
5490 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
5491 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
5492 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
5493 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
5494 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
5495 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
5496 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
5497 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
5498 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
5499 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
5500 BASE(undef_fpu, f000, f000);
5501 INSN(fpu, f200, ffc0, CF_FPU);
5502 INSN(fbcc, f280, ffc0, CF_FPU);
5503 INSN(frestore, f340, ffc0, CF_FPU);
5504 INSN(fsave, f300, ffc0, CF_FPU);
5505 INSN(fpu, f200, ffc0, FPU);
5506 INSN(fscc, f240, ffc0, FPU);
5507 INSN(fbcc, f280, ff80, FPU);
5508 INSN(frestore, f340, ffc0, FPU);
5509 INSN(fsave, f300, ffc0, FPU);
5510 INSN(intouch, f340, ffc0, CF_ISA_A);
5511 INSN(cpushl, f428, ff38, CF_ISA_A);
5512 INSN(wddata, fb00, ff00, CF_ISA_A);
5513 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
5514 #undef INSN
5515 }
5516
5517 /* ??? Some of this implementation is not exception safe. We should always
5518 write back the result to memory before setting the condition codes. */
5519 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
5520 {
5521 uint16_t insn = read_im16(env, s);
5522 opcode_table[insn](env, s, insn);
5523 do_writebacks(s);
5524 }
5525
5526 /* generate intermediate code for basic block 'tb'. */
5527 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
5528 {
5529 CPUM68KState *env = cs->env_ptr;
5530 DisasContext dc1, *dc = &dc1;
5531 target_ulong pc_start;
5532 int pc_offset;
5533 int num_insns;
5534 int max_insns;
5535
5536 /* generate intermediate code */
5537 pc_start = tb->pc;
5538
5539 dc->tb = tb;
5540
5541 dc->env = env;
5542 dc->is_jmp = DISAS_NEXT;
5543 dc->pc = pc_start;
5544 dc->cc_op = CC_OP_DYNAMIC;
5545 dc->cc_op_synced = 1;
5546 dc->singlestep_enabled = cs->singlestep_enabled;
5547 dc->user = (env->sr & SR_S) == 0;
5548 dc->done_mac = 0;
5549 dc->writeback_mask = 0;
5550 num_insns = 0;
5551 max_insns = tb->cflags & CF_COUNT_MASK;
5552 if (max_insns == 0) {
5553 max_insns = CF_COUNT_MASK;
5554 }
5555 if (max_insns > TCG_MAX_INSNS) {
5556 max_insns = TCG_MAX_INSNS;
5557 }
5558
5559 gen_tb_start(tb);
5560 do {
5561 pc_offset = dc->pc - pc_start;
5562 gen_throws_exception = NULL;
5563 tcg_gen_insn_start(dc->pc, dc->cc_op);
5564 num_insns++;
5565
5566 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5567 gen_exception(dc, dc->pc, EXCP_DEBUG);
5568 dc->is_jmp = DISAS_JUMP;
5569 /* The address covered by the breakpoint must be included in
5570 [tb->pc, tb->pc + tb->size) in order to for it to be
5571 properly cleared -- thus we increment the PC here so that
5572 the logic setting tb->size below does the right thing. */
5573 dc->pc += 2;
5574 break;
5575 }
5576
5577 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
5578 gen_io_start();
5579 }
5580
5581 dc->insn_pc = dc->pc;
5582 disas_m68k_insn(env, dc);
5583 } while (!dc->is_jmp && !tcg_op_buf_full() &&
5584 !cs->singlestep_enabled &&
5585 !singlestep &&
5586 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
5587 num_insns < max_insns);
5588
5589 if (tb->cflags & CF_LAST_IO)
5590 gen_io_end();
5591 if (unlikely(cs->singlestep_enabled)) {
5592 /* Make sure the pc is updated, and raise a debug exception. */
5593 if (!dc->is_jmp) {
5594 update_cc_op(dc);
5595 tcg_gen_movi_i32(QREG_PC, dc->pc);
5596 }
5597 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
5598 } else {
5599 switch(dc->is_jmp) {
5600 case DISAS_NEXT:
5601 update_cc_op(dc);
5602 gen_jmp_tb(dc, 0, dc->pc);
5603 break;
5604 default:
5605 case DISAS_JUMP:
5606 case DISAS_UPDATE:
5607 update_cc_op(dc);
5608 /* indicate that the hash table must be used to find the next TB */
5609 tcg_gen_exit_tb(0);
5610 break;
5611 case DISAS_TB_JUMP:
5612 /* nothing more to generate */
5613 break;
5614 }
5615 }
5616 gen_tb_end(tb, num_insns);
5617
5618 #ifdef DEBUG_DISAS
5619 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5620 && qemu_log_in_addr_range(pc_start)) {
5621 qemu_log_lock();
5622 qemu_log("----------------\n");
5623 qemu_log("IN: %s\n", lookup_symbol(pc_start));
5624 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
5625 qemu_log("\n");
5626 qemu_log_unlock();
5627 }
5628 #endif
5629 tb->size = dc->pc - pc_start;
5630 tb->icount = num_insns;
5631 }
5632
5633 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
5634 {
5635 floatx80 a = { .high = high, .low = low };
5636 union {
5637 float64 f64;
5638 double d;
5639 } u;
5640
5641 u.f64 = floatx80_to_float64(a, &env->fp_status);
5642 return u.d;
5643 }
5644
5645 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
5646 int flags)
5647 {
5648 M68kCPU *cpu = M68K_CPU(cs);
5649 CPUM68KState *env = &cpu->env;
5650 int i;
5651 uint16_t sr;
5652 for (i = 0; i < 8; i++) {
5653 cpu_fprintf(f, "D%d = %08x A%d = %08x "
5654 "F%d = %04x %016"PRIx64" (%12g)\n",
5655 i, env->dregs[i], i, env->aregs[i],
5656 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
5657 floatx80_to_double(env, env->fregs[i].l.upper,
5658 env->fregs[i].l.lower));
5659 }
5660 cpu_fprintf (f, "PC = %08x ", env->pc);
5661 sr = env->sr | cpu_m68k_get_ccr(env);
5662 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
5663 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
5664 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
5665 cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
5666 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
5667 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
5668 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
5669 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
5670 cpu_fprintf(f, "\n "
5671 "FPCR = %04x ", env->fpcr);
5672 switch (env->fpcr & FPCR_PREC_MASK) {
5673 case FPCR_PREC_X:
5674 cpu_fprintf(f, "X ");
5675 break;
5676 case FPCR_PREC_S:
5677 cpu_fprintf(f, "S ");
5678 break;
5679 case FPCR_PREC_D:
5680 cpu_fprintf(f, "D ");
5681 break;
5682 }
5683 switch (env->fpcr & FPCR_RND_MASK) {
5684 case FPCR_RND_N:
5685 cpu_fprintf(f, "RN ");
5686 break;
5687 case FPCR_RND_Z:
5688 cpu_fprintf(f, "RZ ");
5689 break;
5690 case FPCR_RND_M:
5691 cpu_fprintf(f, "RM ");
5692 break;
5693 case FPCR_RND_P:
5694 cpu_fprintf(f, "RP ");
5695 break;
5696 }
5697 }
5698
5699 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
5700 target_ulong *data)
5701 {
5702 int cc_op = data[1];
5703 env->pc = data[0];
5704 if (cc_op != CC_OP_DYNAMIC) {
5705 env->cc_op = cc_op;
5706 }
5707 }
AR7 emulation for QEMU