hw/char/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/char/serial.h"
  28 #include "chardev/char-serial.h"
  29 #include "qapi/error.h"
  30 #include "qemu/timer.h"
  31 #include "exec/address-spaces.h"
  32 #include "qemu/error-report.h"
  33
  34 //#define DEBUG_SERIAL
  35
  36 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  37
  38 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  39 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  40 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  41 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  42
  43 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  44 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  45
  46 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  47 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  48 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  49 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  50 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  51
  52 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  53 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  54
  55 /*
  56  * These are the definitions for the Modem Control Register
  57  */
  58 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  59 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  60 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  61 #define UART_MCR_RTS    0x02    /* RTS complement */
  62 #define UART_MCR_DTR    0x01    /* DTR complement */
  63
  64 /*
  65  * These are the definitions for the Modem Status Register
  66  */
  67 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  68 #define UART_MSR_RI     0x40    /* Ring Indicator */
  69 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  70 #define UART_MSR_CTS    0x10    /* Clear to Send */
  71 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  72 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  73 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  74 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  75 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  76
  77 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  78 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  79 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  80 #define UART_LSR_FE     0x08    /* Frame error indicator */
  81 #define UART_LSR_PE     0x04    /* Parity error indicator */
  82 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  83 #define UART_LSR_DR     0x01    /* Receiver data ready */
  84 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  85
  86 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  87
  88 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  89 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  90 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  91 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  92
  93 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  94 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  95 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  96 #define UART_FCR_FE         0x01    /* FIFO Enable */
  97
  98 #define MAX_XMIT_RETRY      4
  99
 100 #ifdef DEBUG_SERIAL
 101 #define DPRINTF(fmt, ...) \
 102 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 103 #else
 104 #define DPRINTF(fmt, ...) \
 105 do {} while (0)
 106 #endif
 107
 108 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 109 static void serial_xmit(SerialState *s);
 110
 111 static inline void recv_fifo_put(SerialState *s, uint8_t chr)
 112 {
 113     /* Receive overruns do not overwrite FIFO contents. */
 114     if (!fifo8_is_full(&s->recv_fifo)) {
 115         fifo8_push(&s->recv_fifo, chr);
 116     } else {
 117         s->lsr |= UART_LSR_OE;
 118     }
 119 }
 120
 121 static void serial_update_irq(SerialState *s)
 122 {
 123     uint8_t tmp_iir = UART_IIR_NO_INT;
 124
 125     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 126         tmp_iir = UART_IIR_RLSI;
 127     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 128         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 129          * this is not in the specification but is observed on existing
 130          * hardware.  */
 131         tmp_iir = UART_IIR_CTI;
 132     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 133                (!(s->fcr & UART_FCR_FE) ||
 134                 s->recv_fifo.num >= s->recv_fifo_itl)) {
 135         tmp_iir = UART_IIR_RDI;
 136     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 137         tmp_iir = UART_IIR_THRI;
 138     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 139         tmp_iir = UART_IIR_MSI;
 140     }
 141
 142     s->iir = tmp_iir | (s->iir & 0xF0);
 143
 144     if (tmp_iir != UART_IIR_NO_INT) {
 145         qemu_irq_raise(s->irq);
 146     } else {
 147         qemu_irq_lower(s->irq);
 148     }
 149 }
 150
 151 static void serial_update_parameters(SerialState *s)
 152 {
 153     int speed, parity, data_bits, stop_bits, frame_size;
 154     QEMUSerialSetParams ssp;
 155
 156     if (s->divider == 0 || s->divider > s->baudbase) {
 157         return;
 158     }
 159
 160     /* Start bit. */
 161     frame_size = 1;
 162     if (s->lcr & 0x08) {
 163         /* Parity bit. */
 164         frame_size++;
 165         if (s->lcr & 0x10)
 166             parity = 'E';
 167         else
 168             parity = 'O';
 169     } else {
 170             parity = 'N';
 171     }
 172     if (s->lcr & 0x04)
 173         stop_bits = 2;
 174     else
 175         stop_bits = 1;
 176
 177     data_bits = (s->lcr & 0x03) + 5;
 178     frame_size += data_bits + stop_bits;
 179     speed = s->baudbase / s->divider;
 180     ssp.speed = speed;
 181     ssp.parity = parity;
 182     ssp.data_bits = data_bits;
 183     ssp.stop_bits = stop_bits;
 184     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
 185     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 186
 187     DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 188            speed, parity, data_bits, stop_bits);
 189 }
 190
 191 static void serial_update_msl(SerialState *s)
 192 {
 193     uint8_t omsr;
 194     int flags;
 195
 196     timer_del(s->modem_status_poll);
 197
 198     if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM,
 199                           &flags) == -ENOTSUP) {
 200         s->poll_msl = -1;
 201         return;
 202     }
 203
 204     omsr = s->msr;
 205
 206     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 207     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 208     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 209     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 210
 211     if (s->msr != omsr) {
 212          /* Set delta bits */
 213          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 214          /* UART_MSR_TERI only if change was from 1 -> 0 */
 215          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 216              s->msr &= ~UART_MSR_TERI;
 217          serial_update_irq(s);
 218     }
 219
 220     /* The real 16550A apparently has a 250ns response latency to line status changes.
 221        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 222
 223     if (s->poll_msl) {
 224         timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 225                   NANOSECONDS_PER_SECOND / 100);
 226     }
 227 }
 228
 229 static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond,
 230                                 void *opaque)
 231 {
 232     SerialState *s = opaque;
 233     s->watch_tag = 0;
 234     serial_xmit(s);
 235     return FALSE;
 236 }
 237
 238 static void serial_xmit(SerialState *s)
 239 {
 240     do {
 241         assert(!(s->lsr & UART_LSR_TEMT));
 242         if (s->tsr_retry == 0) {
 243             assert(!(s->lsr & UART_LSR_THRE));
 244
 245             if (s->fcr & UART_FCR_FE) {
 246                 assert(!fifo8_is_empty(&s->xmit_fifo));
 247                 s->tsr = fifo8_pop(&s->xmit_fifo);
 248                 if (!s->xmit_fifo.num) {
 249                     s->lsr |= UART_LSR_THRE;
 250                 }
 251             } else {
 252                 s->tsr = s->thr;
 253                 s->lsr |= UART_LSR_THRE;
 254             }
 255             if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
 256                 s->thr_ipending = 1;
 257                 serial_update_irq(s);
 258             }
 259         }
 260
 261         if (s->mcr & UART_MCR_LOOP) {
 262             /* in loopback mode, say that we just received a char */
 263             serial_receive1(s, &s->tsr, 1);
 264         } else if (qemu_chr_fe_write(&s->chr, &s->tsr, 1) != 1 &&
 265                    s->tsr_retry < MAX_XMIT_RETRY) {
 266             assert(s->watch_tag == 0);
 267             s->watch_tag =
 268                 qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 269                                       serial_watch_cb, s);
 270             if (s->watch_tag > 0) {
 271                 s->tsr_retry++;
 272                 return;
 273             }
 274         }
 275         s->tsr_retry = 0;
 276
 277         /* Transmit another byte if it is already available. It is only
 278            possible when FIFO is enabled and not empty. */
 279     } while (!(s->lsr & UART_LSR_THRE));
 280
 281     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 282     s->lsr |= UART_LSR_TEMT;
 283 }
 284
 285 /* Setter for FCR.
 286    is_load flag means, that value is set while loading VM state
 287    and interrupt should not be invoked */
 288 static void serial_write_fcr(SerialState *s, uint8_t val)
 289 {
 290     /* Set fcr - val only has the bits that are supposed to "stick" */
 291     s->fcr = val;
 292
 293     if (val & UART_FCR_FE) {
 294         s->iir |= UART_IIR_FE;
 295         /* Set recv_fifo trigger Level */
 296         switch (val & 0xC0) {
 297         case UART_FCR_ITL_1:
 298             s->recv_fifo_itl = 1;
 299             break;
 300         case UART_FCR_ITL_2:
 301             s->recv_fifo_itl = 4;
 302             break;
 303         case UART_FCR_ITL_3:
 304             s->recv_fifo_itl = 8;
 305             break;
 306         case UART_FCR_ITL_4:
 307             s->recv_fifo_itl = 14;
 308             break;
 309         }
 310     } else {
 311         s->iir &= ~UART_IIR_FE;
 312     }
 313 }
 314
 315 static void serial_update_tiocm(SerialState *s)
 316 {
 317     int flags;
 318
 319     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 320
 321     flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 322
 323     if (s->mcr & UART_MCR_RTS) {
 324         flags |= CHR_TIOCM_RTS;
 325     }
 326     if (s->mcr & UART_MCR_DTR) {
 327         flags |= CHR_TIOCM_DTR;
 328     }
 329
 330     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 331 }
 332
 333 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 334                                 unsigned size)
 335 {
 336     SerialState *s = opaque;
 337
 338     addr &= 7;
 339     assert(addr < 8);
 340
 341     //~ fprintf(stderr, "%s(%p,0x%08x)\n", __func__, opaque, addr);
 342
 343     DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
 344     switch(addr) {
 345     default:
 346     case 0:
 347         if (s->lcr & UART_LCR_DLAB) {
 348             s->divider = (s->divider & 0xff00) | val;
 349             serial_update_parameters(s);
 350         } else {
 351             s->thr = (uint8_t) val;
 352             if(s->fcr & UART_FCR_FE) {
 353                 /* xmit overruns overwrite data, so make space if needed */
 354                 if (fifo8_is_full(&s->xmit_fifo)) {
 355                     fifo8_pop(&s->xmit_fifo);
 356                 }
 357                 fifo8_push(&s->xmit_fifo, s->thr);
 358             }
 359             s->thr_ipending = 0;
 360             s->lsr &= ~UART_LSR_THRE;
 361             s->lsr &= ~UART_LSR_TEMT;
 362             serial_update_irq(s);
 363             if (s->tsr_retry == 0) {
 364                 serial_xmit(s);
 365             }
 366         }
 367         break;
 368     case 1:
 369         if (s->lcr & UART_LCR_DLAB) {
 370             s->divider = (s->divider & 0x00ff) | (val << 8);
 371             serial_update_parameters(s);
 372         } else {
 373             uint8_t changed = (s->ier ^ val) & 0x0f;
 374             s->ier = val & 0x0f;
 375             /* If the backend device is a real serial port, turn polling of the modem
 376              * status lines on physical port on or off depending on UART_IER_MSI state.
 377              */
 378             if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
 379                 if (s->ier & UART_IER_MSI) {
 380                      s->poll_msl = 1;
 381                      serial_update_msl(s);
 382                 } else {
 383                      timer_del(s->modem_status_poll);
 384                      s->poll_msl = 0;
 385                 }
 386             }
 387
 388             /* Turning on the THRE interrupt on IER can trigger the interrupt
 389              * if LSR.THRE=1, even if it had been masked before by reading IIR.
 390              * This is not in the datasheet, but Windows relies on it.  It is
 391              * unclear if THRE has to be resampled every time THRI becomes
 392              * 1, or only on the rising edge.  Bochs does the latter, and Windows
 393              * always toggles IER to all zeroes and back to all ones, so do the
 394              * same.
 395              *
 396              * If IER.THRI is zero, thr_ipending is not used.  Set it to zero
 397              * so that the thr_ipending subsection is not migrated.
 398              */
 399             if (changed & UART_IER_THRI) {
 400                 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
 401                     s->thr_ipending = 1;
 402                 } else {
 403                     s->thr_ipending = 0;
 404                 }
 405             }
 406
 407             if (changed) {
 408                 serial_update_irq(s);
 409             }
 410         }
 411         break;
 412     case 2:
 413         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 414         if ((val ^ s->fcr) & UART_FCR_FE) {
 415             val |= UART_FCR_XFR | UART_FCR_RFR;
 416         }
 417
 418         /* FIFO clear */
 419
 420         if (val & UART_FCR_RFR) {
 421             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 422             timer_del(s->fifo_timeout_timer);
 423             s->timeout_ipending = 0;
 424             fifo8_reset(&s->recv_fifo);
 425         }
 426
 427         if (val & UART_FCR_XFR) {
 428             s->lsr |= UART_LSR_THRE;
 429             s->thr_ipending = 1;
 430             fifo8_reset(&s->xmit_fifo);
 431         }
 432
 433         serial_write_fcr(s, val & 0xC9);
 434         serial_update_irq(s);
 435         break;
 436     case 3:
 437         {
 438             int break_enable;
 439             s->lcr = val;
 440             serial_update_parameters(s);
 441             break_enable = (val >> 6) & 1;
 442             if (break_enable != s->last_break_enable) {
 443                 s->last_break_enable = break_enable;
 444                 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 445                                   &break_enable);
 446             }
 447         }
 448         break;
 449     case 4:
 450         {
 451             int old_mcr = s->mcr;
 452             s->mcr = val & 0x1f;
 453             if (val & UART_MCR_LOOP)
 454                 break;
 455
 456             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 457                 serial_update_tiocm(s);
 458                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 459                    from the device/computer at the other end of the serial line */
 460                 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
 461             }
 462         }
 463         break;
 464     case 5:
 465         break;
 466     case 6:
 467         break;
 468     case 7:
 469         s->scr = val;
 470         break;
 471     }
 472 }
 473
 474 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
 475 {
 476     SerialState *s = opaque;
 477     uint32_t ret;
 478
 479     addr &= 7;
 480     assert(addr < 8);
 481
 482   //~ fprintf(stderr, "%s(%p,0x%08x)\n", __func__, opaque, addr);
 483
 484     switch(addr) {
 485     default:
 486     case 0:
 487         if (s->lcr & UART_LCR_DLAB) {
 488             ret = s->divider & 0xff;
 489         } else {
 490             if(s->fcr & UART_FCR_FE) {
 491                 ret = fifo8_is_empty(&s->recv_fifo) ?
 492                             0 : fifo8_pop(&s->recv_fifo);
 493                 if (s->recv_fifo.num == 0) {
 494                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 495                 } else {
 496                     timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 497                 }
 498                 s->timeout_ipending = 0;
 499             } else {
 500                 ret = s->rbr;
 501                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 502             }
 503             serial_update_irq(s);
 504             if (!(s->mcr & UART_MCR_LOOP)) {
 505                 /* in loopback mode, don't receive any data */
 506                 qemu_chr_fe_accept_input(&s->chr);
 507             }
 508         }
 509         break;
 510     case 1:
 511         if (s->lcr & UART_LCR_DLAB) {
 512             ret = (s->divider >> 8) & 0xff;
 513         } else {
 514             ret = s->ier;
 515         }
 516         break;
 517     case 2:
 518         ret = s->iir;
 519         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 520             s->thr_ipending = 0;
 521             serial_update_irq(s);
 522         }
 523         break;
 524     case 3:
 525         ret = s->lcr;
 526         break;
 527     case 4:
 528         ret = s->mcr;
 529         break;
 530     case 5:
 531         ret = s->lsr;
 532         /* Clear break and overrun interrupts */
 533         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 534             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 535             serial_update_irq(s);
 536         }
 537         break;
 538     case 6:
 539         if (s->mcr & UART_MCR_LOOP) {
 540             /* in loopback, the modem output pins are connected to the
 541                inputs */
 542             ret = (s->mcr & 0x0c) << 4;
 543             ret |= (s->mcr & 0x02) << 3;
 544             ret |= (s->mcr & 0x01) << 5;
 545         } else {
 546             if (s->poll_msl >= 0)
 547                 serial_update_msl(s);
 548             ret = s->msr;
 549             /* Clear delta bits & msr int after read, if they were set */
 550             if (s->msr & UART_MSR_ANY_DELTA) {
 551                 s->msr &= 0xF0;
 552                 serial_update_irq(s);
 553             }
 554         }
 555         break;
 556     case 7:
 557         ret = s->scr;
 558         break;
 559     }
 560     DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
 561     return ret;
 562 }
 563
 564 static int serial_can_receive(SerialState *s)
 565 {
 566     //~ fprintf(stderr, "%s:%u\n", __FILE__, __LINE__);
 567     if(s->fcr & UART_FCR_FE) {
 568         if (s->recv_fifo.num < UART_FIFO_LENGTH) {
 569             /*
 570              * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
 571              * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
 572              * effect will be to almost always fill the fifo completely before
 573              * the guest has a chance to respond, effectively overriding the ITL
 574              * that the guest has set.
 575              */
 576             return (s->recv_fifo.num <= s->recv_fifo_itl) ?
 577                         s->recv_fifo_itl - s->recv_fifo.num : 1;
 578         } else {
 579             return 0;
 580         }
 581     } else {
 582         return !(s->lsr & UART_LSR_DR);
 583     }
 584 }
 585
 586 static void serial_receive_break(SerialState *s)
 587 {
 588     s->rbr = 0;
 589     /* When the LSR_DR is set a null byte is pushed into the fifo */
 590     recv_fifo_put(s, '\0');
 591     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 592     serial_update_irq(s);
 593 }
 594
 595 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 596 static void fifo_timeout_int (void *opaque) {
 597     SerialState *s = opaque;
 598     if (s->recv_fifo.num) {
 599         s->timeout_ipending = 1;
 600         serial_update_irq(s);
 601     }
 602 }
 603
 604 static int serial_can_receive1(void *opaque)
 605 {
 606     SerialState *s = opaque;
 607     return serial_can_receive(s);
 608 }
 609
 610 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 611 {
 612     SerialState *s = opaque;
 613
 614     if (s->wakeup) {
 615         qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
 616     }
 617     if(s->fcr & UART_FCR_FE) {
 618         int i;
 619         for (i = 0; i < size; i++) {
 620             recv_fifo_put(s, buf[i]);
 621         }
 622         s->lsr |= UART_LSR_DR;
 623         /* call the timeout receive callback in 4 char transmit time */
 624         timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 625     } else {
 626         if (s->lsr & UART_LSR_DR)
 627             s->lsr |= UART_LSR_OE;
 628         s->rbr = buf[0];
 629         s->lsr |= UART_LSR_DR;
 630     }
 631     serial_update_irq(s);
 632 }
 633
 634 static void serial_event(void *opaque, int event)
 635 {
 636     SerialState *s = opaque;
 637     DPRINTF("event %x\n", event);
 638     if (event == CHR_EVENT_BREAK)
 639         serial_receive_break(s);
 640 }
 641
 642 static void serial_pre_save(void *opaque)
 643 {
 644     SerialState *s = opaque;
 645     s->fcr_vmstate = s->fcr;
 646 }
 647
 648 static int serial_pre_load(void *opaque)
 649 {
 650     SerialState *s = opaque;
 651     s->thr_ipending = -1;
 652     s->poll_msl = -1;
 653     return 0;
 654 }
 655
 656 static int serial_post_load(void *opaque, int version_id)
 657 {
 658     SerialState *s = opaque;
 659
 660     if (version_id < 3) {
 661         s->fcr_vmstate = 0;
 662     }
 663     if (s->thr_ipending == -1) {
 664         s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 665     }
 666
 667     if (s->tsr_retry > 0) {
 668         /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty).  */
 669         if (s->lsr & UART_LSR_TEMT) {
 670             error_report("inconsistent state in serial device "
 671                          "(tsr empty, tsr_retry=%d", s->tsr_retry);
 672             return -1;
 673         }
 674
 675         if (s->tsr_retry > MAX_XMIT_RETRY) {
 676             s->tsr_retry = MAX_XMIT_RETRY;
 677         }
 678
 679         assert(s->watch_tag == 0);
 680         s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 681                                              serial_watch_cb, s);
 682     } else {
 683         /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty).  */
 684         if (!(s->lsr & UART_LSR_TEMT)) {
 685             error_report("inconsistent state in serial device "
 686                          "(tsr not empty, tsr_retry=0");
 687             return -1;
 688         }
 689     }
 690
 691     s->last_break_enable = (s->lcr >> 6) & 1;
 692     /* Initialize fcr via setter to perform essential side-effects */
 693     serial_write_fcr(s, s->fcr_vmstate);
 694     serial_update_parameters(s);
 695     return 0;
 696 }
 697
 698 static bool serial_thr_ipending_needed(void *opaque)
 699 {
 700     SerialState *s = opaque;
 701
 702     if (s->ier & UART_IER_THRI) {
 703         bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 704         return s->thr_ipending != expected_value;
 705     } else {
 706         /* LSR.THRE will be sampled again when the interrupt is
 707          * enabled.  thr_ipending is not used in this case, do
 708          * not migrate it.
 709          */
 710         return false;
 711     }
 712 }
 713
 714 static const VMStateDescription vmstate_serial_thr_ipending = {
 715     .name = "serial/thr_ipending",
 716     .version_id = 1,
 717     .minimum_version_id = 1,
 718     .needed = serial_thr_ipending_needed,
 719     .fields = (VMStateField[]) {
 720         VMSTATE_INT32(thr_ipending, SerialState),
 721         VMSTATE_END_OF_LIST()
 722     }
 723 };
 724
 725 static bool serial_tsr_needed(void *opaque)
 726 {
 727     SerialState *s = (SerialState *)opaque;
 728     return s->tsr_retry != 0;
 729 }
 730
 731 static const VMStateDescription vmstate_serial_tsr = {
 732     .name = "serial/tsr",
 733     .version_id = 1,
 734     .minimum_version_id = 1,
 735     .needed = serial_tsr_needed,
 736     .fields = (VMStateField[]) {
 737         VMSTATE_UINT32(tsr_retry, SerialState),
 738         VMSTATE_UINT8(thr, SerialState),
 739         VMSTATE_UINT8(tsr, SerialState),
 740         VMSTATE_END_OF_LIST()
 741     }
 742 };
 743
 744 static bool serial_recv_fifo_needed(void *opaque)
 745 {
 746     SerialState *s = (SerialState *)opaque;
 747     return !fifo8_is_empty(&s->recv_fifo);
 748
 749 }
 750
 751 static const VMStateDescription vmstate_serial_recv_fifo = {
 752     .name = "serial/recv_fifo",
 753     .version_id = 1,
 754     .minimum_version_id = 1,
 755     .needed = serial_recv_fifo_needed,
 756     .fields = (VMStateField[]) {
 757         VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 758         VMSTATE_END_OF_LIST()
 759     }
 760 };
 761
 762 static bool serial_xmit_fifo_needed(void *opaque)
 763 {
 764     SerialState *s = (SerialState *)opaque;
 765     return !fifo8_is_empty(&s->xmit_fifo);
 766 }
 767
 768 static const VMStateDescription vmstate_serial_xmit_fifo = {
 769     .name = "serial/xmit_fifo",
 770     .version_id = 1,
 771     .minimum_version_id = 1,
 772     .needed = serial_xmit_fifo_needed,
 773     .fields = (VMStateField[]) {
 774         VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 775         VMSTATE_END_OF_LIST()
 776     }
 777 };
 778
 779 static bool serial_fifo_timeout_timer_needed(void *opaque)
 780 {
 781     SerialState *s = (SerialState *)opaque;
 782     return timer_pending(s->fifo_timeout_timer);
 783 }
 784
 785 static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
 786     .name = "serial/fifo_timeout_timer",
 787     .version_id = 1,
 788     .minimum_version_id = 1,
 789     .needed = serial_fifo_timeout_timer_needed,
 790     .fields = (VMStateField[]) {
 791         VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
 792         VMSTATE_END_OF_LIST()
 793     }
 794 };
 795
 796 static bool serial_timeout_ipending_needed(void *opaque)
 797 {
 798     SerialState *s = (SerialState *)opaque;
 799     return s->timeout_ipending != 0;
 800 }
 801
 802 static const VMStateDescription vmstate_serial_timeout_ipending = {
 803     .name = "serial/timeout_ipending",
 804     .version_id = 1,
 805     .minimum_version_id = 1,
 806     .needed = serial_timeout_ipending_needed,
 807     .fields = (VMStateField[]) {
 808         VMSTATE_INT32(timeout_ipending, SerialState),
 809         VMSTATE_END_OF_LIST()
 810     }
 811 };
 812
 813 static bool serial_poll_needed(void *opaque)
 814 {
 815     SerialState *s = (SerialState *)opaque;
 816     return s->poll_msl >= 0;
 817 }
 818
 819 static const VMStateDescription vmstate_serial_poll = {
 820     .name = "serial/poll",
 821     .version_id = 1,
 822     .needed = serial_poll_needed,
 823     .minimum_version_id = 1,
 824     .fields = (VMStateField[]) {
 825         VMSTATE_INT32(poll_msl, SerialState),
 826         VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
 827         VMSTATE_END_OF_LIST()
 828     }
 829 };
 830
 831 const VMStateDescription vmstate_serial = {
 832     .name = "serial",
 833     .version_id = 3,
 834     .minimum_version_id = 2,
 835     .pre_save = serial_pre_save,
 836     .pre_load = serial_pre_load,
 837     .post_load = serial_post_load,
 838     .fields = (VMStateField[]) {
 839         VMSTATE_UINT16_V(divider, SerialState, 2),
 840         VMSTATE_UINT8(rbr, SerialState),
 841         VMSTATE_UINT8(ier, SerialState),
 842         VMSTATE_UINT8(iir, SerialState),
 843         VMSTATE_UINT8(lcr, SerialState),
 844         VMSTATE_UINT8(mcr, SerialState),
 845         VMSTATE_UINT8(lsr, SerialState),
 846         VMSTATE_UINT8(msr, SerialState),
 847         VMSTATE_UINT8(scr, SerialState),
 848         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 849         VMSTATE_END_OF_LIST()
 850     },
 851     .subsections = (const VMStateDescription*[]) {
 852         &vmstate_serial_thr_ipending,
 853         &vmstate_serial_tsr,
 854         &vmstate_serial_recv_fifo,
 855         &vmstate_serial_xmit_fifo,
 856         &vmstate_serial_fifo_timeout_timer,
 857         &vmstate_serial_timeout_ipending,
 858         &vmstate_serial_poll,
 859         NULL
 860     }
 861 };
 862
 863 static void serial_reset(void *opaque)
 864 {
 865     SerialState *s = opaque;
 866
 867     if (s->watch_tag > 0) {
 868         g_source_remove(s->watch_tag);
 869         s->watch_tag = 0;
 870     }
 871
 872     s->rbr = 0;
 873     s->ier = 0;
 874     s->iir = UART_IIR_NO_INT;
 875     s->lcr = 0;
 876     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 877     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 878     s->divider = 0x0C;
 879     s->mcr = UART_MCR_OUT2;
 880     s->scr = 0;
 881     s->tsr_retry = 0;
 882     s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 883     s->poll_msl = 0;
 884     serial_update_parameters(s);
 885
 886     s->timeout_ipending = 0;
 887     timer_del(s->fifo_timeout_timer);
 888     timer_del(s->modem_status_poll);
 889
 890     fifo8_reset(&s->recv_fifo);
 891     fifo8_reset(&s->xmit_fifo);
 892
 893     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 894
 895     s->thr_ipending = 0;
 896     s->last_break_enable = 0;
 897     qemu_irq_lower(s->irq);
 898
 899     serial_update_msl(s);
 900     s->msr &= ~UART_MSR_ANY_DELTA;
 901 }
 902
 903 static int serial_be_change(void *opaque)
 904 {
 905     SerialState *s = opaque;
 906
 907     qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
 908                              serial_event, serial_be_change, s, NULL, true);
 909
 910     serial_update_parameters(s);
 911
 912     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 913                       &s->last_break_enable);
 914
 915     s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0;
 916     serial_update_msl(s);
 917
 918     if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) {
 919         serial_update_tiocm(s);
 920     }
 921
 922     if (s->watch_tag > 0) {
 923         g_source_remove(s->watch_tag);
 924         s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 925                                              serial_watch_cb, s);
 926     }
 927
 928     return 0;
 929 }
 930
 931 void serial_realize_core(SerialState *s, Error **errp)
 932 {
 933     if (!qemu_chr_fe_backend_connected(&s->chr)) {
 934         error_setg(errp, "Can't create serial device, empty char device");
 935         return;
 936     }
 937
 938     s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
 939
 940     s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
 941     qemu_register_reset(serial_reset, s);
 942
 943     qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
 944                              serial_event, serial_be_change, s, NULL, true);
 945     fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
 946     fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
 947     serial_reset(s);
 948 }
 949
 950 void serial_exit_core(SerialState *s)
 951 {
 952     qemu_chr_fe_deinit(&s->chr, false);
 953
 954     timer_del(s->modem_status_poll);
 955     timer_free(s->modem_status_poll);
 956
 957     timer_del(s->fifo_timeout_timer);
 958     timer_free(s->fifo_timeout_timer);
 959
 960     fifo8_destroy(&s->recv_fifo);
 961     fifo8_destroy(&s->xmit_fifo);
 962
 963     qemu_unregister_reset(serial_reset, s);
 964 }
 965
 966 /* Change the main reference oscillator frequency. */
 967 void serial_set_frequency(SerialState *s, uint32_t frequency)
 968 {
 969     s->baudbase = frequency;
 970     serial_update_parameters(s);
 971 }
 972
 973 const MemoryRegionOps serial_io_ops = {
 974     .read = serial_ioport_read,
 975     .write = serial_ioport_write,
 976     .impl = {
 977         .min_access_size = 1,
 978         .max_access_size = 1,
 979     },
 980     .endianness = DEVICE_LITTLE_ENDIAN,
 981 };
 982
 983 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 984                          Chardev *chr, MemoryRegion *system_io)
 985 {
 986     SerialState *s;
 987
 988     s = g_malloc0(sizeof(SerialState));
 989
 990     s->base = base;
 991     s->it_shift = 0;
 992     s->irq = irq;
 993     s->baudbase = baudbase;
 994     qemu_chr_fe_init(&s->chr, chr, &error_abort);
 995     serial_realize_core(s, &error_fatal);
 996
 997     vmstate_register(NULL, base, &vmstate_serial, s);
 998
 999     memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
1000     memory_region_add_subregion(system_io, base, &s->io);
1001
1002     return s;
1003 }
1004
1005 /* Memory mapped interface */
1006 uint64_t serial_mm_read(void *opaque, hwaddr addr,
1007                         unsigned size)
1008 {
1009     SerialState *s = opaque;
1010     return serial_ioport_read(s, (addr - s->base) >> s->it_shift, 1);
1011 }
1012
1013 void serial_mm_write(void *opaque, hwaddr addr,
1014                      uint64_t value, unsigned size)
1015 {
1016     SerialState *s = opaque;
1017     value &= ~0u >> (32 - (size * 8));
1018     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value, 1);
1019 }
1020
1021 static const MemoryRegionOps serial_mm_ops[3] = {
1022     [DEVICE_NATIVE_ENDIAN] = {
1023         .read = serial_mm_read,
1024         .write = serial_mm_write,
1025         .endianness = DEVICE_NATIVE_ENDIAN,
1026     },
1027     [DEVICE_LITTLE_ENDIAN] = {
1028         .read = serial_mm_read,
1029         .write = serial_mm_write,
1030         .endianness = DEVICE_LITTLE_ENDIAN,
1031     },
1032     [DEVICE_BIG_ENDIAN] = {
1033         .read = serial_mm_read,
1034         .write = serial_mm_write,
1035         .endianness = DEVICE_BIG_ENDIAN,
1036     },
1037 };
1038
1039 SerialState *serial_mm_init(MemoryRegion *address_space,
1040                             hwaddr base, int it_shift,
1041                             qemu_irq irq, int baudbase,
1042                             Chardev *chr, enum device_endian end)
1043 {
1044     SerialState *s;
1045
1046     s = g_malloc0(sizeof(SerialState));
1047
1048     s->base = base;
1049     s->it_shift = it_shift;
1050     s->irq = irq;
1051     s->baudbase = baudbase;
1052     qemu_chr_fe_init(&s->chr, chr, &error_abort);
1053
1054     serial_realize_core(s, &error_fatal);
1055     vmstate_register(NULL, base, &vmstate_serial, s);
1056
1057     memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
1058                           "serial", 8 << it_shift);
1059     memory_region_add_subregion(address_space, base, &s->io);
1060     return s;
1061 }