hw/arm/s3c24xx_clkcon.c

   1 /* hw/s3c24xx_clkcon.c
   2  *
   3  * Samsung S3C24XX Clock control emulation
   4  *
   5  * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
   6  *
   7  * Copyright 2010, 2013 Stefan Weil
   8  *
   9  * This file is under the terms of the GNU General Public License Version 2.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "cpu.h"
  14 #include "hw/hw.h"
  15 #include "exec/address-spaces.h" /* get_system_memory */
  16 #include "migration/register.h"  /* register_savevm_live */
  17
  18 #include "s3c24xx.h"
  19
  20 /* Lock time RW */
  21 #define S3C_REG_LOCKTIME 0
  22
  23 /* MPLL Control RW */
  24 #define S3C_REG_MPLLCON 1
  25
  26 /* UPLL Control RW */
  27 #define S3C_REG_UPLLCON 2
  28
  29 /* Clock Generator Control RW */
  30 #define S3C_REG_CLKCON 3
  31
  32 /* CLKCON IDLE */
  33 #define S3C_REG_CLKCON_IDLE (1<<2)
  34
  35 /* Slow Clock Control RW */
  36 #define S3C_REG_CLKSLOW 4
  37
  38 /* Clock divider control RW */
  39 #define S3C_REG_CLKDIVN 5
  40
  41 /* Clock controller state */
  42 struct s3c24xx_clkcon_state_s {
  43     MemoryRegion mmio;
  44     CPUARMState *cpu_env;
  45     uint32_t ref_freq; /* frequency of reference xtal or extclock */
  46     uint32_t clkcon_reg[7];
  47 };
  48
  49 static void s3c24xx_clkcon_write(void *opaque, hwaddr addr_,
  50                                  uint64_t value, unsigned size)
  51 {
  52     struct s3c24xx_clkcon_state_s *s = opaque;
  53     unsigned addr = (addr_ & 0x1F) >> 2;
  54     int idle_rising_edge = 0;
  55
  56     assert(addr < ARRAY_SIZE(s->clkcon_reg));
  57
  58     if (addr == S3C_REG_CLKCON) {
  59         if (!(s->clkcon_reg[addr] & S3C_REG_CLKCON_IDLE) &&
  60             (value & S3C_REG_CLKCON_IDLE))
  61             idle_rising_edge = 1;
  62     }
  63
  64     s->clkcon_reg[addr] = value;
  65
  66     if (idle_rising_edge) {
  67         cpu_interrupt(CPU(s), CPU_INTERRUPT_HALT);
  68     }
  69 }
  70
  71 static uint64_t s3c24xx_clkcon_read(void *opaque, hwaddr addr_,
  72                                     unsigned size)
  73 {
  74     struct s3c24xx_clkcon_state_s *s = opaque;
  75     unsigned addr = (addr_ & 0x1F) >> 2;
  76
  77     assert(addr < ARRAY_SIZE(s->clkcon_reg));
  78
  79     return s->clkcon_reg[addr];
  80 }
  81
  82 static const MemoryRegionOps s3c24xx_clkcon_ops = {
  83     .read = s3c24xx_clkcon_read,
  84     .write = s3c24xx_clkcon_write,
  85     .endianness = DEVICE_NATIVE_ENDIAN,
  86     .valid = {
  87         .min_access_size = 1,
  88         .max_access_size = 4
  89     }
  90 };
  91
  92 static void s3c24xx_clkcon_save(QEMUFile *f, void *opaque)
  93 {
  94     struct s3c24xx_clkcon_state_s *s = (struct s3c24xx_clkcon_state_s *)opaque;
  95     int i;
  96
  97     for (i = 0; i < ARRAY_SIZE(s->clkcon_reg); i ++) {
  98         qemu_put_be32s(f, &s->clkcon_reg[i]);
  99     }
 100 }
 101
 102 static int s3c24xx_clkcon_load(QEMUFile *f, void *opaque, int version_id)
 103 {
 104     struct s3c24xx_clkcon_state_s *s = opaque;
 105     int i;
 106
 107     for (i = 0; i < ARRAY_SIZE(s->clkcon_reg); i ++) {
 108         qemu_get_be32s(f, &s->clkcon_reg[i]);
 109     }
 110
 111     return 0;
 112 }
 113
 114 static SaveVMHandlers savevm_s3c24xx_clkcon = {
 115     .save_state = s3c24xx_clkcon_save,
 116     .load_state = s3c24xx_clkcon_load
 117 };
 118
 119 struct s3c24xx_clkcon_state_s *
 120 s3c24xx_clkcon_init(S3CState *soc, hwaddr base_addr, uint32_t ref_freq)
 121 {
 122     struct s3c24xx_clkcon_state_s *s = g_new0(struct s3c24xx_clkcon_state_s, 1);
 123
 124     memory_region_init_io(&s->mmio, OBJECT(s), &s3c24xx_clkcon_ops, s,
 125                           "s3c24xx.clkcon", ARRAY_SIZE(s->clkcon_reg) * 4);
 126     memory_region_add_subregion(get_system_memory(), base_addr, &s->mmio);
 127     register_savevm_live(NULL, "s3c24xx_clkcon", 0, 0, &savevm_s3c24xx_clkcon, s);
 128
 129     s->cpu_env = &soc->cpu->env;
 130     s->ref_freq = ref_freq;
 131
 132     /* initialise register values to power on defaults */
 133     s->clkcon_reg[S3C_REG_LOCKTIME] = 0x00FFFFFF;
 134     s->clkcon_reg[S3C_REG_MPLLCON] = 0x0005C080;
 135     s->clkcon_reg[S3C_REG_UPLLCON] = 0x00028080;
 136     s->clkcon_reg[S3C_REG_CLKCON] = 0x0007FFF0;
 137     s->clkcon_reg[S3C_REG_CLKSLOW] = 0x00000004;
 138     s->clkcon_reg[S3C_REG_CLKDIVN] = 0x00000000;
 139
 140     return s;
 141 }