target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #ifndef CONFIG_USER_ONLY
  26 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  27 #endif
  28
  29 /*****************************************************************************/
  30 /* Exceptions processing helpers */
  31
  32 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  33                                                         uint32_t exception,
  34                                                         int error_code,
  35                                                         uintptr_t pc)
  36 {
  37     CPUState *cs = CPU(mips_env_get_cpu(env));
  38
  39     if (exception < EXCP_SC) {
  40         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  41     }
  42     cs->exception_index = exception;
  43     env->error_code = error_code;
  44
  45     if (pc) {
  46         /* now we have a real cpu fault */
  47         cpu_restore_state(cs, pc);
  48     }
  49
  50     cpu_loop_exit(cs);
  51 }
  52
  53 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  54                                                     uint32_t exception,
  55                                                     uintptr_t pc)
  56 {
  57     do_raise_exception_err(env, exception, 0, pc);
  58 }
  59
  60 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  61                                 int error_code)
  62 {
  63     do_raise_exception_err(env, exception, error_code, 0);
  64 }
  65
  66 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  67 {
  68     do_raise_exception(env, exception, 0);
  69 }
  70
  71 #if defined(CONFIG_USER_ONLY)
  72 #define HELPER_LD(name, insn, type)                                     \
  73 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  74                              int mem_idx)                               \
  75 {                                                                       \
  76     return (type) insn##_raw(addr);                                     \
  77 }
  78 #else
  79 #define HELPER_LD(name, insn, type)                                     \
  80 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  81                              int mem_idx)                               \
  82 {                                                                       \
  83     switch (mem_idx)                                                    \
  84     {                                                                   \
  85     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  86     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  87     default:                                                            \
  88     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  89     }                                                                   \
  90 }
  91 #endif
  92 HELPER_LD(lbu, ldub, uint8_t)
  93 HELPER_LD(lw, ldl, int32_t)
  94 #ifdef TARGET_MIPS64
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     insn##_raw(addr, val);                                              \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #ifdef TARGET_MIPS64
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 #ifndef CONFIG_USER_ONLY
 269
 270 static inline hwaddr do_translate_address(CPUMIPSState *env,
 271                                                       target_ulong address,
 272                                                       int rw)
 273 {
 274     hwaddr lladdr;
 275
 276     lladdr = cpu_mips_translate_address(env, address, rw);
 277
 278     if (lladdr == -1LL) {
 279         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 280     } else {
 281         return lladdr;
 282     }
 283 }
 284
 285 #define HELPER_LD_ATOMIC(name, insn)                                          \
 286 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 287 {                                                                             \
 288     env->lladdr = do_translate_address(env, arg, 0);                          \
 289     env->llval = do_##insn(env, arg, mem_idx);                                \
 290     return env->llval;                                                        \
 291 }
 292 HELPER_LD_ATOMIC(ll, lw)
 293 #ifdef TARGET_MIPS64
 294 HELPER_LD_ATOMIC(lld, ld)
 295 #endif
 296 #undef HELPER_LD_ATOMIC
 297
 298 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 299 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 300                            target_ulong arg2, int mem_idx)                    \
 301 {                                                                             \
 302     target_long tmp;                                                          \
 303                                                                               \
 304     if (arg2 & almask) {                                                      \
 305         env->CP0_BadVAddr = arg2;                                             \
 306         helper_raise_exception(env, EXCP_AdES);                               \
 307     }                                                                         \
 308     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 309         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 310         if (tmp == env->llval) {                                              \
 311             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 312             return 1;                                                         \
 313         }                                                                     \
 314     }                                                                         \
 315     return 0;                                                                 \
 316 }
 317 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 318 #ifdef TARGET_MIPS64
 319 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 320 #endif
 321 #undef HELPER_ST_ATOMIC
 322 #endif
 323
 324 #ifdef TARGET_WORDS_BIGENDIAN
 325 #define GET_LMASK(v) ((v) & 3)
 326 #define GET_OFFSET(addr, offset) (addr + (offset))
 327 #else
 328 #define GET_LMASK(v) (((v) & 3) ^ 3)
 329 #define GET_OFFSET(addr, offset) (addr - (offset))
 330 #endif
 331
 332 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 333                 int mem_idx)
 334 {
 335     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 336
 337     if (GET_LMASK(arg2) <= 2)
 338         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 339
 340     if (GET_LMASK(arg2) <= 1)
 341         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 342
 343     if (GET_LMASK(arg2) == 0)
 344         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 345 }
 346
 347 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 348                 int mem_idx)
 349 {
 350     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 351
 352     if (GET_LMASK(arg2) >= 1)
 353         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 354
 355     if (GET_LMASK(arg2) >= 2)
 356         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 357
 358     if (GET_LMASK(arg2) == 3)
 359         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 360 }
 361
 362 #if defined(TARGET_MIPS64)
 363 /* "half" load and stores.  We must do the memory access inline,
 364    or fault handling won't work.  */
 365
 366 #ifdef TARGET_WORDS_BIGENDIAN
 367 #define GET_LMASK64(v) ((v) & 7)
 368 #else
 369 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 370 #endif
 371
 372 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 373                 int mem_idx)
 374 {
 375     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 376
 377     if (GET_LMASK64(arg2) <= 6)
 378         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 379
 380     if (GET_LMASK64(arg2) <= 5)
 381         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 382
 383     if (GET_LMASK64(arg2) <= 4)
 384         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 385
 386     if (GET_LMASK64(arg2) <= 3)
 387         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 388
 389     if (GET_LMASK64(arg2) <= 2)
 390         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 391
 392     if (GET_LMASK64(arg2) <= 1)
 393         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 394
 395     if (GET_LMASK64(arg2) <= 0)
 396         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 397 }
 398
 399 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 400                 int mem_idx)
 401 {
 402     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 403
 404     if (GET_LMASK64(arg2) >= 1)
 405         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 406
 407     if (GET_LMASK64(arg2) >= 2)
 408         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 409
 410     if (GET_LMASK64(arg2) >= 3)
 411         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 412
 413     if (GET_LMASK64(arg2) >= 4)
 414         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 415
 416     if (GET_LMASK64(arg2) >= 5)
 417         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 418
 419     if (GET_LMASK64(arg2) >= 6)
 420         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 421
 422     if (GET_LMASK64(arg2) == 7)
 423         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 424 }
 425 #endif /* TARGET_MIPS64 */
 426
 427 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 428
 429 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 430                 uint32_t mem_idx)
 431 {
 432     target_ulong base_reglist = reglist & 0xf;
 433     target_ulong do_r31 = reglist & 0x10;
 434
 435     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 436         target_ulong i;
 437
 438         for (i = 0; i < base_reglist; i++) {
 439             env->active_tc.gpr[multiple_regs[i]] =
 440                 (target_long)do_lw(env, addr, mem_idx);
 441             addr += 4;
 442         }
 443     }
 444
 445     if (do_r31) {
 446         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 447     }
 448 }
 449
 450 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 451                 uint32_t mem_idx)
 452 {
 453     target_ulong base_reglist = reglist & 0xf;
 454     target_ulong do_r31 = reglist & 0x10;
 455
 456     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 457         target_ulong i;
 458
 459         for (i = 0; i < base_reglist; i++) {
 460             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 461             addr += 4;
 462         }
 463     }
 464
 465     if (do_r31) {
 466         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 467     }
 468 }
 469
 470 #if defined(TARGET_MIPS64)
 471 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 472                 uint32_t mem_idx)
 473 {
 474     target_ulong base_reglist = reglist & 0xf;
 475     target_ulong do_r31 = reglist & 0x10;
 476
 477     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 478         target_ulong i;
 479
 480         for (i = 0; i < base_reglist; i++) {
 481             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 482             addr += 8;
 483         }
 484     }
 485
 486     if (do_r31) {
 487         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 488     }
 489 }
 490
 491 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 492                 uint32_t mem_idx)
 493 {
 494     target_ulong base_reglist = reglist & 0xf;
 495     target_ulong do_r31 = reglist & 0x10;
 496
 497     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 498         target_ulong i;
 499
 500         for (i = 0; i < base_reglist; i++) {
 501             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 502             addr += 8;
 503         }
 504     }
 505
 506     if (do_r31) {
 507         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 508     }
 509 }
 510 #endif
 511
 512 #ifndef CONFIG_USER_ONLY
 513 /* SMP helpers.  */
 514 static bool mips_vpe_is_wfi(MIPSCPU *c)
 515 {
 516     CPUState *cpu = CPU(c);
 517     CPUMIPSState *env = &c->env;
 518
 519     /* If the VPE is halted but otherwise active, it means it's waiting for
 520        an interrupt.  */
 521     return cpu->halted && mips_vpe_active(env);
 522 }
 523
 524 static inline void mips_vpe_wake(MIPSCPU *c)
 525 {
 526     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 527        because there might be other conditions that state that c should
 528        be sleeping.  */
 529     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 530 }
 531
 532 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 533 {
 534     CPUState *cs = CPU(cpu);
 535
 536     /* The VPE was shut off, really go to bed.
 537        Reset any old _WAKE requests.  */
 538     cs->halted = 1;
 539     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 540 }
 541
 542 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 543 {
 544     CPUMIPSState *c = &cpu->env;
 545
 546     /* FIXME: TC reschedule.  */
 547     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 548         mips_vpe_wake(cpu);
 549     }
 550 }
 551
 552 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 553 {
 554     CPUMIPSState *c = &cpu->env;
 555
 556     /* FIXME: TC reschedule.  */
 557     if (!mips_vpe_active(c)) {
 558         mips_vpe_sleep(cpu);
 559     }
 560 }
 561
 562 /**
 563  * mips_cpu_map_tc:
 564  * @env: CPU from which mapping is performed.
 565  * @tc: Should point to an int with the value of the global TC index.
 566  *
 567  * This function will transform @tc into a local index within the
 568  * returned #CPUMIPSState.
 569  */
 570 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 571           which depends on runtime setup. Can probably be fixed by
 572           walking the list of CPUMIPSStates.  */
 573 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 574 {
 575     MIPSCPU *cpu;
 576     CPUState *cs;
 577     CPUState *other_cs;
 578     int vpe_idx;
 579     int tc_idx = *tc;
 580
 581     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 582         /* Not allowed to address other CPUs.  */
 583         *tc = env->current_tc;
 584         return env;
 585     }
 586
 587     cs = CPU(mips_env_get_cpu(env));
 588     vpe_idx = tc_idx / cs->nr_threads;
 589     *tc = tc_idx % cs->nr_threads;
 590     other_cs = qemu_get_cpu(vpe_idx);
 591     if (other_cs == NULL) {
 592         return env;
 593     }
 594     cpu = MIPS_CPU(other_cs);
 595     return &cpu->env;
 596 }
 597
 598 /* The per VPE CP0_Status register shares some fields with the per TC
 599    CP0_TCStatus registers. These fields are wired to the same registers,
 600    so changes to either of them should be reflected on both registers.
 601
 602    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 603
 604    These helper call synchronizes the regs for a given cpu.  */
 605
 606 /* Called for updates to CP0_Status.  */
 607 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 608 {
 609     int32_t tcstatus, *tcst;
 610     uint32_t v = cpu->CP0_Status;
 611     uint32_t cu, mx, asid, ksu;
 612     uint32_t mask = ((1 << CP0TCSt_TCU3)
 613                        | (1 << CP0TCSt_TCU2)
 614                        | (1 << CP0TCSt_TCU1)
 615                        | (1 << CP0TCSt_TCU0)
 616                        | (1 << CP0TCSt_TMX)
 617                        | (3 << CP0TCSt_TKSU)
 618                        | (0xff << CP0TCSt_TASID));
 619
 620     cu = (v >> CP0St_CU0) & 0xf;
 621     mx = (v >> CP0St_MX) & 0x1;
 622     ksu = (v >> CP0St_KSU) & 0x3;
 623     asid = env->CP0_EntryHi & 0xff;
 624
 625     tcstatus = cu << CP0TCSt_TCU0;
 626     tcstatus |= mx << CP0TCSt_TMX;
 627     tcstatus |= ksu << CP0TCSt_TKSU;
 628     tcstatus |= asid;
 629
 630     if (tc == cpu->current_tc) {
 631         tcst = &cpu->active_tc.CP0_TCStatus;
 632     } else {
 633         tcst = &cpu->tcs[tc].CP0_TCStatus;
 634     }
 635
 636     *tcst &= ~mask;
 637     *tcst |= tcstatus;
 638     compute_hflags(cpu);
 639 }
 640
 641 /* Called for updates to CP0_TCStatus.  */
 642 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 643                              target_ulong v)
 644 {
 645     uint32_t status;
 646     uint32_t tcu, tmx, tasid, tksu;
 647     uint32_t mask = ((1U << CP0St_CU3)
 648                        | (1 << CP0St_CU2)
 649                        | (1 << CP0St_CU1)
 650                        | (1 << CP0St_CU0)
 651                        | (1 << CP0St_MX)
 652                        | (3 << CP0St_KSU));
 653
 654     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 655     tmx = (v >> CP0TCSt_TMX) & 0x1;
 656     tasid = v & 0xff;
 657     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 658
 659     status = tcu << CP0St_CU0;
 660     status |= tmx << CP0St_MX;
 661     status |= tksu << CP0St_KSU;
 662
 663     cpu->CP0_Status &= ~mask;
 664     cpu->CP0_Status |= status;
 665
 666     /* Sync the TASID with EntryHi.  */
 667     cpu->CP0_EntryHi &= ~0xff;
 668     cpu->CP0_EntryHi = tasid;
 669
 670     compute_hflags(cpu);
 671 }
 672
 673 /* Called for updates to CP0_EntryHi.  */
 674 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 675 {
 676     int32_t *tcst;
 677     uint32_t asid, v = cpu->CP0_EntryHi;
 678
 679     asid = v & 0xff;
 680
 681     if (tc == cpu->current_tc) {
 682         tcst = &cpu->active_tc.CP0_TCStatus;
 683     } else {
 684         tcst = &cpu->tcs[tc].CP0_TCStatus;
 685     }
 686
 687     *tcst &= ~0xff;
 688     *tcst |= asid;
 689 }
 690
 691 /* CP0 helpers */
 692 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 693 {
 694     return env->mvp->CP0_MVPControl;
 695 }
 696
 697 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 698 {
 699     return env->mvp->CP0_MVPConf0;
 700 }
 701
 702 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 703 {
 704     return env->mvp->CP0_MVPConf1;
 705 }
 706
 707 target_ulong helper_mfc0_random(CPUMIPSState *env)
 708 {
 709     return (int32_t)cpu_mips_get_random(env);
 710 }
 711
 712 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 713 {
 714     return env->active_tc.CP0_TCStatus;
 715 }
 716
 717 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 718 {
 719     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 720     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 721
 722     if (other_tc == other->current_tc)
 723         return other->active_tc.CP0_TCStatus;
 724     else
 725         return other->tcs[other_tc].CP0_TCStatus;
 726 }
 727
 728 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 729 {
 730     return env->active_tc.CP0_TCBind;
 731 }
 732
 733 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 734 {
 735     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 736     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 737
 738     if (other_tc == other->current_tc)
 739         return other->active_tc.CP0_TCBind;
 740     else
 741         return other->tcs[other_tc].CP0_TCBind;
 742 }
 743
 744 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 745 {
 746     return env->active_tc.PC;
 747 }
 748
 749 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 750 {
 751     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 752     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 753
 754     if (other_tc == other->current_tc)
 755         return other->active_tc.PC;
 756     else
 757         return other->tcs[other_tc].PC;
 758 }
 759
 760 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 761 {
 762     return env->active_tc.CP0_TCHalt;
 763 }
 764
 765 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 766 {
 767     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 768     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 769
 770     if (other_tc == other->current_tc)
 771         return other->active_tc.CP0_TCHalt;
 772     else
 773         return other->tcs[other_tc].CP0_TCHalt;
 774 }
 775
 776 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 777 {
 778     return env->active_tc.CP0_TCContext;
 779 }
 780
 781 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 782 {
 783     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 784     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 785
 786     if (other_tc == other->current_tc)
 787         return other->active_tc.CP0_TCContext;
 788     else
 789         return other->tcs[other_tc].CP0_TCContext;
 790 }
 791
 792 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 793 {
 794     return env->active_tc.CP0_TCSchedule;
 795 }
 796
 797 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 798 {
 799     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 800     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 801
 802     if (other_tc == other->current_tc)
 803         return other->active_tc.CP0_TCSchedule;
 804     else
 805         return other->tcs[other_tc].CP0_TCSchedule;
 806 }
 807
 808 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 809 {
 810     return env->active_tc.CP0_TCScheFBack;
 811 }
 812
 813 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 814 {
 815     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 816     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 817
 818     if (other_tc == other->current_tc)
 819         return other->active_tc.CP0_TCScheFBack;
 820     else
 821         return other->tcs[other_tc].CP0_TCScheFBack;
 822 }
 823
 824 target_ulong helper_mfc0_count(CPUMIPSState *env)
 825 {
 826     return (int32_t)cpu_mips_get_count(env);
 827 }
 828
 829 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 830 {
 831     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 832     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 833
 834     return other->CP0_EntryHi;
 835 }
 836
 837 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 838 {
 839     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 840     int32_t tccause;
 841     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 842
 843     if (other_tc == other->current_tc) {
 844         tccause = other->CP0_Cause;
 845     } else {
 846         tccause = other->CP0_Cause;
 847     }
 848
 849     return tccause;
 850 }
 851
 852 target_ulong helper_mftc0_status(CPUMIPSState *env)
 853 {
 854     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 855     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 856
 857     return other->CP0_Status;
 858 }
 859
 860 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 861 {
 862     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 863 }
 864
 865 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 866 {
 867     return (int32_t)env->CP0_WatchLo[sel];
 868 }
 869
 870 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 871 {
 872     return env->CP0_WatchHi[sel];
 873 }
 874
 875 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 876 {
 877     target_ulong t0 = env->CP0_Debug;
 878     if (env->hflags & MIPS_HFLAG_DM)
 879         t0 |= 1 << CP0DB_DM;
 880
 881     return t0;
 882 }
 883
 884 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 885 {
 886     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 887     int32_t tcstatus;
 888     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 889
 890     if (other_tc == other->current_tc)
 891         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 892     else
 893         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 894
 895     /* XXX: Might be wrong, check with EJTAG spec. */
 896     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 897             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 898 }
 899
 900 #if defined(TARGET_MIPS64)
 901 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 902 {
 903     return env->active_tc.PC;
 904 }
 905
 906 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 907 {
 908     return env->active_tc.CP0_TCHalt;
 909 }
 910
 911 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 912 {
 913     return env->active_tc.CP0_TCContext;
 914 }
 915
 916 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 917 {
 918     return env->active_tc.CP0_TCSchedule;
 919 }
 920
 921 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 922 {
 923     return env->active_tc.CP0_TCScheFBack;
 924 }
 925
 926 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 927 {
 928     return env->lladdr >> env->CP0_LLAddr_shift;
 929 }
 930
 931 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 932 {
 933     return env->CP0_WatchLo[sel];
 934 }
 935 #endif /* TARGET_MIPS64 */
 936
 937 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 938 {
 939     int num = 1;
 940     unsigned int tmp = env->tlb->nb_tlb;
 941
 942     do {
 943         tmp >>= 1;
 944         num <<= 1;
 945     } while (tmp);
 946     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 947 }
 948
 949 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 950 {
 951     uint32_t mask = 0;
 952     uint32_t newval;
 953
 954     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 955         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 956                 (1 << CP0MVPCo_EVP);
 957     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 958         mask |= (1 << CP0MVPCo_STLB);
 959     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 960
 961     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 962
 963     env->mvp->CP0_MVPControl = newval;
 964 }
 965
 966 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 967 {
 968     uint32_t mask;
 969     uint32_t newval;
 970
 971     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 972            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 973     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 974
 975     /* Yield scheduler intercept not implemented. */
 976     /* Gating storage scheduler intercept not implemented. */
 977
 978     // TODO: Enable/disable TCs.
 979
 980     env->CP0_VPEControl = newval;
 981 }
 982
 983 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 984 {
 985     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 986     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 987     uint32_t mask;
 988     uint32_t newval;
 989
 990     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 991            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 992     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 993
 994     /* TODO: Enable/disable TCs.  */
 995
 996     other->CP0_VPEControl = newval;
 997 }
 998
 999 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1000 {
1001     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1002     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1003     /* FIXME: Mask away return zero on read bits.  */
1004     return other->CP0_VPEControl;
1005 }
1006
1007 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1008 {
1009     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1010     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011
1012     return other->CP0_VPEConf0;
1013 }
1014
1015 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1016 {
1017     uint32_t mask = 0;
1018     uint32_t newval;
1019
1020     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1021         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1022             mask |= (0xff << CP0VPEC0_XTC);
1023         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1024     }
1025     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1026
1027     // TODO: TC exclusive handling due to ERL/EXL.
1028
1029     env->CP0_VPEConf0 = newval;
1030 }
1031
1032 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1033 {
1034     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1035     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1036     uint32_t mask = 0;
1037     uint32_t newval;
1038
1039     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1040     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1041
1042     /* TODO: TC exclusive handling due to ERL/EXL.  */
1043     other->CP0_VPEConf0 = newval;
1044 }
1045
1046 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1047 {
1048     uint32_t mask = 0;
1049     uint32_t newval;
1050
1051     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1052         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1053                 (0xff << CP0VPEC1_NCP1);
1054     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1055
1056     /* UDI not implemented. */
1057     /* CP2 not implemented. */
1058
1059     // TODO: Handle FPU (CP1) binding.
1060
1061     env->CP0_VPEConf1 = newval;
1062 }
1063
1064 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1065 {
1066     /* Yield qualifier inputs not implemented. */
1067     env->CP0_YQMask = 0x00000000;
1068 }
1069
1070 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1071 {
1072     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1073 }
1074
1075 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1076 {
1077     /* Large physaddr (PABITS) not implemented */
1078     /* 1k pages not implemented */
1079     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1080 }
1081
1082 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1083 {
1084     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1085     uint32_t newval;
1086
1087     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1088
1089     env->active_tc.CP0_TCStatus = newval;
1090     sync_c0_tcstatus(env, env->current_tc, newval);
1091 }
1092
1093 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1094 {
1095     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1096     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1097
1098     if (other_tc == other->current_tc)
1099         other->active_tc.CP0_TCStatus = arg1;
1100     else
1101         other->tcs[other_tc].CP0_TCStatus = arg1;
1102     sync_c0_tcstatus(other, other_tc, arg1);
1103 }
1104
1105 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1106 {
1107     uint32_t mask = (1 << CP0TCBd_TBE);
1108     uint32_t newval;
1109
1110     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1111         mask |= (1 << CP0TCBd_CurVPE);
1112     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1113     env->active_tc.CP0_TCBind = newval;
1114 }
1115
1116 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1117 {
1118     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1119     uint32_t mask = (1 << CP0TCBd_TBE);
1120     uint32_t newval;
1121     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1122
1123     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1124         mask |= (1 << CP0TCBd_CurVPE);
1125     if (other_tc == other->current_tc) {
1126         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1127         other->active_tc.CP0_TCBind = newval;
1128     } else {
1129         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1130         other->tcs[other_tc].CP0_TCBind = newval;
1131     }
1132 }
1133
1134 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1135 {
1136     env->active_tc.PC = arg1;
1137     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1138     env->lladdr = 0ULL;
1139     /* MIPS16 not implemented. */
1140 }
1141
1142 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1143 {
1144     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1145     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1146
1147     if (other_tc == other->current_tc) {
1148         other->active_tc.PC = arg1;
1149         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1150         other->lladdr = 0ULL;
1151         /* MIPS16 not implemented. */
1152     } else {
1153         other->tcs[other_tc].PC = arg1;
1154         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1155         other->lladdr = 0ULL;
1156         /* MIPS16 not implemented. */
1157     }
1158 }
1159
1160 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1161 {
1162     MIPSCPU *cpu = mips_env_get_cpu(env);
1163
1164     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1165
1166     // TODO: Halt TC / Restart (if allocated+active) TC.
1167     if (env->active_tc.CP0_TCHalt & 1) {
1168         mips_tc_sleep(cpu, env->current_tc);
1169     } else {
1170         mips_tc_wake(cpu, env->current_tc);
1171     }
1172 }
1173
1174 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1175 {
1176     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1177     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1178     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1179
1180     // TODO: Halt TC / Restart (if allocated+active) TC.
1181
1182     if (other_tc == other->current_tc)
1183         other->active_tc.CP0_TCHalt = arg1;
1184     else
1185         other->tcs[other_tc].CP0_TCHalt = arg1;
1186
1187     if (arg1 & 1) {
1188         mips_tc_sleep(other_cpu, other_tc);
1189     } else {
1190         mips_tc_wake(other_cpu, other_tc);
1191     }
1192 }
1193
1194 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1195 {
1196     env->active_tc.CP0_TCContext = arg1;
1197 }
1198
1199 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1200 {
1201     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1202     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1203
1204     if (other_tc == other->current_tc)
1205         other->active_tc.CP0_TCContext = arg1;
1206     else
1207         other->tcs[other_tc].CP0_TCContext = arg1;
1208 }
1209
1210 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1211 {
1212     env->active_tc.CP0_TCSchedule = arg1;
1213 }
1214
1215 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1216 {
1217     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1218     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1219
1220     if (other_tc == other->current_tc)
1221         other->active_tc.CP0_TCSchedule = arg1;
1222     else
1223         other->tcs[other_tc].CP0_TCSchedule = arg1;
1224 }
1225
1226 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1227 {
1228     env->active_tc.CP0_TCScheFBack = arg1;
1229 }
1230
1231 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1232 {
1233     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235
1236     if (other_tc == other->current_tc)
1237         other->active_tc.CP0_TCScheFBack = arg1;
1238     else
1239         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1240 }
1241
1242 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1243 {
1244     /* Large physaddr (PABITS) not implemented */
1245     /* 1k pages not implemented */
1246     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1247 }
1248
1249 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1250 {
1251     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1252 }
1253
1254 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1255 {
1256     /* 1k pages not implemented */
1257     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1258 }
1259
1260 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1261 {
1262     /* SmartMIPS not implemented */
1263     /* Large physaddr (PABITS) not implemented */
1264     /* 1k pages not implemented */
1265     env->CP0_PageGrain = 0;
1266 }
1267
1268 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1269 {
1270     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1271 }
1272
1273 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1274 {
1275     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1276 }
1277
1278 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1279 {
1280     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1281 }
1282
1283 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1284 {
1285     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1286 }
1287
1288 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1289 {
1290     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1291 }
1292
1293 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1294 {
1295     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1296 }
1297
1298 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1299 {
1300     env->CP0_HWREna = arg1 & 0x0000000F;
1301 }
1302
1303 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1304 {
1305     cpu_mips_store_count(env, arg1);
1306 }
1307
1308 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1309 {
1310     target_ulong old, val;
1311
1312     /* 1k pages not implemented */
1313     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1314 #if defined(TARGET_MIPS64)
1315     val &= env->SEGMask;
1316 #endif
1317     old = env->CP0_EntryHi;
1318     env->CP0_EntryHi = val;
1319     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1320         sync_c0_entryhi(env, env->current_tc);
1321     }
1322     /* If the ASID changes, flush qemu's TLB.  */
1323     if ((old & 0xFF) != (val & 0xFF))
1324         cpu_mips_tlb_flush(env, 1);
1325 }
1326
1327 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1328 {
1329     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1330     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1331
1332     other->CP0_EntryHi = arg1;
1333     sync_c0_entryhi(other, other_tc);
1334 }
1335
1336 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1337 {
1338     cpu_mips_store_compare(env, arg1);
1339 }
1340
1341 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1342 {
1343     MIPSCPU *cpu = mips_env_get_cpu(env);
1344     uint32_t val, old;
1345     uint32_t mask = env->CP0_Status_rw_bitmask;
1346
1347     val = arg1 & mask;
1348     old = env->CP0_Status;
1349     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1350     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1351         sync_c0_status(env, env, env->current_tc);
1352     } else {
1353         compute_hflags(env);
1354     }
1355
1356     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1357         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1358                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1359                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1360                 env->CP0_Cause);
1361         switch (env->hflags & MIPS_HFLAG_KSU) {
1362         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1363         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1364         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1365         default:
1366             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1367             break;
1368         }
1369     }
1370 }
1371
1372 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1373 {
1374     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1375     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1376
1377     other->CP0_Status = arg1 & ~0xf1000018;
1378     sync_c0_status(env, other, other_tc);
1379 }
1380
1381 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1382 {
1383     /* vectored interrupts not implemented, no performance counters. */
1384     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1385 }
1386
1387 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1388 {
1389     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1390     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1391 }
1392
1393 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1394 {
1395     uint32_t mask = 0x00C00300;
1396     uint32_t old = cpu->CP0_Cause;
1397     int i;
1398
1399     if (cpu->insn_flags & ISA_MIPS32R2) {
1400         mask |= 1 << CP0Ca_DC;
1401     }
1402
1403     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1404
1405     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1406         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1407             cpu_mips_stop_count(cpu);
1408         } else {
1409             cpu_mips_start_count(cpu);
1410         }
1411     }
1412
1413     /* Set/reset software interrupts */
1414     for (i = 0 ; i < 2 ; i++) {
1415         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1416             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1417         }
1418     }
1419 }
1420
1421 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1422 {
1423     mtc0_cause(env, arg1);
1424 }
1425
1426 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1427 {
1428     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1429     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1430
1431     mtc0_cause(other, arg1);
1432 }
1433
1434 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1435 {
1436     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1437     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1438
1439     return other->CP0_EPC;
1440 }
1441
1442 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1443 {
1444     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1445     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1446
1447     return other->CP0_EBase;
1448 }
1449
1450 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1451 {
1452     /* vectored interrupts not implemented */
1453     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1454 }
1455
1456 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1457 {
1458     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1459     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1460     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1461 }
1462
1463 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1464 {
1465     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1466     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1467
1468     switch (idx) {
1469     case 0: return other->CP0_Config0;
1470     case 1: return other->CP0_Config1;
1471     case 2: return other->CP0_Config2;
1472     case 3: return other->CP0_Config3;
1473     /* 4 and 5 are reserved.  */
1474     case 6: return other->CP0_Config6;
1475     case 7: return other->CP0_Config7;
1476     default:
1477         break;
1478     }
1479     return 0;
1480 }
1481
1482 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1483 {
1484     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1485 }
1486
1487 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1488 {
1489     /* tertiary/secondary caches not implemented */
1490     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1491 }
1492
1493 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1494 {
1495     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1496                        (arg1 & env->CP0_Config4_rw_bitmask);
1497 }
1498
1499 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1500 {
1501     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1502                        (arg1 & env->CP0_Config5_rw_bitmask);
1503 }
1504
1505 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1506 {
1507     target_long mask = env->CP0_LLAddr_rw_bitmask;
1508     arg1 = arg1 << env->CP0_LLAddr_shift;
1509     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1510 }
1511
1512 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1513 {
1514     /* Watch exceptions for instructions, data loads, data stores
1515        not implemented. */
1516     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1517 }
1518
1519 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1520 {
1521     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1522     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1523 }
1524
1525 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1526 {
1527     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1528     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1529 }
1530
1531 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1532 {
1533     env->CP0_Framemask = arg1; /* XXX */
1534 }
1535
1536 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1537 {
1538     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1539     if (arg1 & (1 << CP0DB_DM))
1540         env->hflags |= MIPS_HFLAG_DM;
1541     else
1542         env->hflags &= ~MIPS_HFLAG_DM;
1543 }
1544
1545 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1546 {
1547     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1548     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1549     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1550
1551     /* XXX: Might be wrong, check with EJTAG spec. */
1552     if (other_tc == other->current_tc)
1553         other->active_tc.CP0_Debug_tcstatus = val;
1554     else
1555         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1556     other->CP0_Debug = (other->CP0_Debug &
1557                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1558                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1559 }
1560
1561 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1562 {
1563     env->CP0_Performance0 = arg1 & 0x000007ff;
1564 }
1565
1566 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1567 {
1568     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1569 }
1570
1571 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1572 {
1573     env->CP0_DataLo = arg1; /* XXX */
1574 }
1575
1576 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1577 {
1578     env->CP0_TagHi = arg1; /* XXX */
1579 }
1580
1581 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1582 {
1583     env->CP0_DataHi = arg1; /* XXX */
1584 }
1585
1586 /* MIPS MT functions */
1587 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1588 {
1589     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1590     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1591
1592     if (other_tc == other->current_tc)
1593         return other->active_tc.gpr[sel];
1594     else
1595         return other->tcs[other_tc].gpr[sel];
1596 }
1597
1598 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1599 {
1600     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1601     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1602
1603     if (other_tc == other->current_tc)
1604         return other->active_tc.LO[sel];
1605     else
1606         return other->tcs[other_tc].LO[sel];
1607 }
1608
1609 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1610 {
1611     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1612     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1613
1614     if (other_tc == other->current_tc)
1615         return other->active_tc.HI[sel];
1616     else
1617         return other->tcs[other_tc].HI[sel];
1618 }
1619
1620 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1621 {
1622     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1623     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1624
1625     if (other_tc == other->current_tc)
1626         return other->active_tc.ACX[sel];
1627     else
1628         return other->tcs[other_tc].ACX[sel];
1629 }
1630
1631 target_ulong helper_mftdsp(CPUMIPSState *env)
1632 {
1633     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1634     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1635
1636     if (other_tc == other->current_tc)
1637         return other->active_tc.DSPControl;
1638     else
1639         return other->tcs[other_tc].DSPControl;
1640 }
1641
1642 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1643 {
1644     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1645     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1646
1647     if (other_tc == other->current_tc)
1648         other->active_tc.gpr[sel] = arg1;
1649     else
1650         other->tcs[other_tc].gpr[sel] = arg1;
1651 }
1652
1653 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1654 {
1655     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1656     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1657
1658     if (other_tc == other->current_tc)
1659         other->active_tc.LO[sel] = arg1;
1660     else
1661         other->tcs[other_tc].LO[sel] = arg1;
1662 }
1663
1664 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1665 {
1666     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1667     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1668
1669     if (other_tc == other->current_tc)
1670         other->active_tc.HI[sel] = arg1;
1671     else
1672         other->tcs[other_tc].HI[sel] = arg1;
1673 }
1674
1675 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1676 {
1677     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1678     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1679
1680     if (other_tc == other->current_tc)
1681         other->active_tc.ACX[sel] = arg1;
1682     else
1683         other->tcs[other_tc].ACX[sel] = arg1;
1684 }
1685
1686 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1687 {
1688     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1689     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1690
1691     if (other_tc == other->current_tc)
1692         other->active_tc.DSPControl = arg1;
1693     else
1694         other->tcs[other_tc].DSPControl = arg1;
1695 }
1696
1697 /* MIPS MT functions */
1698 target_ulong helper_dmt(void)
1699 {
1700     // TODO
1701      return 0;
1702 }
1703
1704 target_ulong helper_emt(void)
1705 {
1706     // TODO
1707     return 0;
1708 }
1709
1710 target_ulong helper_dvpe(CPUMIPSState *env)
1711 {
1712     CPUState *other_cs = first_cpu;
1713     target_ulong prev = env->mvp->CP0_MVPControl;
1714
1715     CPU_FOREACH(other_cs) {
1716         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1717         /* Turn off all VPEs except the one executing the dvpe.  */
1718         if (&other_cpu->env != env) {
1719             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1720             mips_vpe_sleep(other_cpu);
1721         }
1722     }
1723     return prev;
1724 }
1725
1726 target_ulong helper_evpe(CPUMIPSState *env)
1727 {
1728     CPUState *other_cs = first_cpu;
1729     target_ulong prev = env->mvp->CP0_MVPControl;
1730
1731     CPU_FOREACH(other_cs) {
1732         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1733
1734         if (&other_cpu->env != env
1735             /* If the VPE is WFI, don't disturb its sleep.  */
1736             && !mips_vpe_is_wfi(other_cpu)) {
1737             /* Enable the VPE.  */
1738             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1739             mips_vpe_wake(other_cpu); /* And wake it up.  */
1740         }
1741     }
1742     return prev;
1743 }
1744 #endif /* !CONFIG_USER_ONLY */
1745
1746 void helper_fork(target_ulong arg1, target_ulong arg2)
1747 {
1748     // arg1 = rt, arg2 = rs
1749     // TODO: store to TC register
1750 }
1751
1752 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1753 {
1754     target_long arg1 = arg;
1755
1756     if (arg1 < 0) {
1757         /* No scheduling policy implemented. */
1758         if (arg1 != -2) {
1759             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1760                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1761                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1762                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1763                 helper_raise_exception(env, EXCP_THREAD);
1764             }
1765         }
1766     } else if (arg1 == 0) {
1767         if (0 /* TODO: TC underflow */) {
1768             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1769             helper_raise_exception(env, EXCP_THREAD);
1770         } else {
1771             // TODO: Deallocate TC
1772         }
1773     } else if (arg1 > 0) {
1774         /* Yield qualifier inputs not implemented. */
1775         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1776         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1777         helper_raise_exception(env, EXCP_THREAD);
1778     }
1779     return env->CP0_YQMask;
1780 }
1781
1782 #ifndef CONFIG_USER_ONLY
1783 /* TLB management */
1784 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1785 {
1786     MIPSCPU *cpu = mips_env_get_cpu(env);
1787
1788     /* Flush qemu's TLB and discard all shadowed entries.  */
1789     tlb_flush(CPU(cpu), flush_global);
1790     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1791 }
1792
1793 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1794 {
1795     /* Discard entries from env->tlb[first] onwards.  */
1796     while (env->tlb->tlb_in_use > first) {
1797         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1798     }
1799 }
1800
1801 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1802 {
1803     r4k_tlb_t *tlb;
1804
1805     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1806     tlb = &env->tlb->mmu.r4k.tlb[idx];
1807     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1808 #if defined(TARGET_MIPS64)
1809     tlb->VPN &= env->SEGMask;
1810 #endif
1811     tlb->ASID = env->CP0_EntryHi & 0xFF;
1812     tlb->PageMask = env->CP0_PageMask;
1813     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1814     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1815     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1816     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1817     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1818     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1819     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1820     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1821     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1822 }
1823
1824 void r4k_helper_tlbwi(CPUMIPSState *env)
1825 {
1826     r4k_tlb_t *tlb;
1827     int idx;
1828     target_ulong VPN;
1829     uint8_t ASID;
1830     bool G, V0, D0, V1, D1;
1831
1832     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1833     tlb = &env->tlb->mmu.r4k.tlb[idx];
1834     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1835 #if defined(TARGET_MIPS64)
1836     VPN &= env->SEGMask;
1837 #endif
1838     ASID = env->CP0_EntryHi & 0xff;
1839     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1840     V0 = (env->CP0_EntryLo0 & 2) != 0;
1841     D0 = (env->CP0_EntryLo0 & 4) != 0;
1842     V1 = (env->CP0_EntryLo1 & 2) != 0;
1843     D1 = (env->CP0_EntryLo1 & 4) != 0;
1844
1845     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1846        permissions on the current entry. */
1847     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1848         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1849         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1850         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1851     }
1852
1853     r4k_invalidate_tlb(env, idx, 0);
1854     r4k_fill_tlb(env, idx);
1855 }
1856
1857 void r4k_helper_tlbwr(CPUMIPSState *env)
1858 {
1859     int r = cpu_mips_get_random(env);
1860
1861     r4k_invalidate_tlb(env, r, 1);
1862     r4k_fill_tlb(env, r);
1863 }
1864
1865 void r4k_helper_tlbp(CPUMIPSState *env)
1866 {
1867     r4k_tlb_t *tlb;
1868     target_ulong mask;
1869     target_ulong tag;
1870     target_ulong VPN;
1871     uint8_t ASID;
1872     int i;
1873
1874     ASID = env->CP0_EntryHi & 0xFF;
1875     for (i = 0; i < env->tlb->nb_tlb; i++) {
1876         tlb = &env->tlb->mmu.r4k.tlb[i];
1877         /* 1k pages are not supported. */
1878         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1879         tag = env->CP0_EntryHi & ~mask;
1880         VPN = tlb->VPN & ~mask;
1881 #if defined(TARGET_MIPS64)
1882         tag &= env->SEGMask;
1883 #endif
1884         /* Check ASID, virtual page number & size */
1885         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1886             /* TLB match */
1887             env->CP0_Index = i;
1888             break;
1889         }
1890     }
1891     if (i == env->tlb->nb_tlb) {
1892         /* No match.  Discard any shadow entries, if any of them match.  */
1893         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1894             tlb = &env->tlb->mmu.r4k.tlb[i];
1895             /* 1k pages are not supported. */
1896             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1897             tag = env->CP0_EntryHi & ~mask;
1898             VPN = tlb->VPN & ~mask;
1899 #if defined(TARGET_MIPS64)
1900             tag &= env->SEGMask;
1901 #endif
1902             /* Check ASID, virtual page number & size */
1903             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1904                 r4k_mips_tlb_flush_extra (env, i);
1905                 break;
1906             }
1907         }
1908
1909         env->CP0_Index |= 0x80000000;
1910     }
1911 }
1912
1913 void r4k_helper_tlbr(CPUMIPSState *env)
1914 {
1915     r4k_tlb_t *tlb;
1916     uint8_t ASID;
1917     int idx;
1918
1919     ASID = env->CP0_EntryHi & 0xFF;
1920     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1921     tlb = &env->tlb->mmu.r4k.tlb[idx];
1922
1923     /* If this will change the current ASID, flush qemu's TLB.  */
1924     if (ASID != tlb->ASID)
1925         cpu_mips_tlb_flush (env, 1);
1926
1927     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1928
1929     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1930     env->CP0_PageMask = tlb->PageMask;
1931     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1932                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1933     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1934                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1935 }
1936
1937 void helper_tlbwi(CPUMIPSState *env)
1938 {
1939     env->tlb->helper_tlbwi(env);
1940 }
1941
1942 void helper_tlbwr(CPUMIPSState *env)
1943 {
1944     env->tlb->helper_tlbwr(env);
1945 }
1946
1947 void helper_tlbp(CPUMIPSState *env)
1948 {
1949     env->tlb->helper_tlbp(env);
1950 }
1951
1952 void helper_tlbr(CPUMIPSState *env)
1953 {
1954     env->tlb->helper_tlbr(env);
1955 }
1956
1957 /* Specials */
1958 target_ulong helper_di(CPUMIPSState *env)
1959 {
1960     target_ulong t0 = env->CP0_Status;
1961
1962     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1963     return t0;
1964 }
1965
1966 target_ulong helper_ei(CPUMIPSState *env)
1967 {
1968     target_ulong t0 = env->CP0_Status;
1969
1970     env->CP0_Status = t0 | (1 << CP0St_IE);
1971     return t0;
1972 }
1973
1974 static void debug_pre_eret(CPUMIPSState *env)
1975 {
1976     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1977         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1978                 env->active_tc.PC, env->CP0_EPC);
1979         if (env->CP0_Status & (1 << CP0St_ERL))
1980             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1981         if (env->hflags & MIPS_HFLAG_DM)
1982             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1983         qemu_log("\n");
1984     }
1985 }
1986
1987 static void debug_post_eret(CPUMIPSState *env)
1988 {
1989     MIPSCPU *cpu = mips_env_get_cpu(env);
1990
1991     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1992         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1993                 env->active_tc.PC, env->CP0_EPC);
1994         if (env->CP0_Status & (1 << CP0St_ERL))
1995             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1996         if (env->hflags & MIPS_HFLAG_DM)
1997             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1998         switch (env->hflags & MIPS_HFLAG_KSU) {
1999         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2000         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2001         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2002         default:
2003             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2004             break;
2005         }
2006     }
2007 }
2008
2009 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2010 {
2011     env->active_tc.PC = error_pc & ~(target_ulong)1;
2012     if (error_pc & 1) {
2013         env->hflags |= MIPS_HFLAG_M16;
2014     } else {
2015         env->hflags &= ~(MIPS_HFLAG_M16);
2016     }
2017 }
2018
2019 void helper_eret(CPUMIPSState *env)
2020 {
2021     debug_pre_eret(env);
2022     if (env->CP0_Status & (1 << CP0St_ERL)) {
2023         set_pc(env, env->CP0_ErrorEPC);
2024         env->CP0_Status &= ~(1 << CP0St_ERL);
2025     } else {
2026         set_pc(env, env->CP0_EPC);
2027         env->CP0_Status &= ~(1 << CP0St_EXL);
2028     }
2029     compute_hflags(env);
2030     debug_post_eret(env);
2031     env->lladdr = 1;
2032 }
2033
2034 void helper_deret(CPUMIPSState *env)
2035 {
2036     debug_pre_eret(env);
2037     set_pc(env, env->CP0_DEPC);
2038
2039     env->hflags &= MIPS_HFLAG_DM;
2040     compute_hflags(env);
2041     debug_post_eret(env);
2042     env->lladdr = 1;
2043 }
2044 #endif /* !CONFIG_USER_ONLY */
2045
2046 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2047 {
2048     if ((env->hflags & MIPS_HFLAG_CP0) ||
2049         (env->CP0_HWREna & (1 << 0)))
2050         return env->CP0_EBase & 0x3ff;
2051     else
2052         helper_raise_exception(env, EXCP_RI);
2053
2054     return 0;
2055 }
2056
2057 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2058 {
2059     if ((env->hflags & MIPS_HFLAG_CP0) ||
2060         (env->CP0_HWREna & (1 << 1)))
2061         return env->SYNCI_Step;
2062     else
2063         helper_raise_exception(env, EXCP_RI);
2064
2065     return 0;
2066 }
2067
2068 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2069 {
2070     if ((env->hflags & MIPS_HFLAG_CP0) ||
2071         (env->CP0_HWREna & (1 << 2)))
2072         return env->CP0_Count;
2073     else
2074         helper_raise_exception(env, EXCP_RI);
2075
2076     return 0;
2077 }
2078
2079 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2080 {
2081     if ((env->hflags & MIPS_HFLAG_CP0) ||
2082         (env->CP0_HWREna & (1 << 3)))
2083         return env->CCRes;
2084     else
2085         helper_raise_exception(env, EXCP_RI);
2086
2087     return 0;
2088 }
2089
2090 void helper_pmon(CPUMIPSState *env, int function)
2091 {
2092     function /= 2;
2093     switch (function) {
2094     case 2: /* TODO: char inbyte(int waitflag); */
2095         if (env->active_tc.gpr[4] == 0)
2096             env->active_tc.gpr[2] = -1;
2097         /* Fall through */
2098     case 11: /* TODO: char inbyte (void); */
2099         env->active_tc.gpr[2] = -1;
2100         break;
2101     case 3:
2102     case 12:
2103         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2104         break;
2105     case 17:
2106         break;
2107     case 158:
2108         {
2109             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2110             printf("%s", fmt);
2111         }
2112         break;
2113     }
2114 }
2115
2116 void helper_wait(CPUMIPSState *env)
2117 {
2118     CPUState *cs = CPU(mips_env_get_cpu(env));
2119
2120     cs->halted = 1;
2121     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2122     helper_raise_exception(env, EXCP_HLT);
2123 }
2124
2125 #if !defined(CONFIG_USER_ONLY)
2126
2127 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2128                                   int is_write, int is_user, uintptr_t retaddr)
2129 {
2130     MIPSCPU *cpu = MIPS_CPU(cs);
2131     CPUMIPSState *env = &cpu->env;
2132
2133     env->CP0_BadVAddr = addr;
2134     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2135 }
2136
2137 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2138               uintptr_t retaddr)
2139 {
2140     int ret;
2141
2142     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2143     if (ret) {
2144         MIPSCPU *cpu = MIPS_CPU(cs);
2145         CPUMIPSState *env = &cpu->env;
2146
2147         do_raise_exception_err(env, cs->exception_index,
2148                                env->error_code, retaddr);
2149     }
2150 }
2151
2152 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2153                                 bool is_write, bool is_exec, int unused,
2154                                 unsigned size)
2155 {
2156     MIPSCPU *cpu = MIPS_CPU(cs);
2157     CPUMIPSState *env = &cpu->env;
2158
2159     if (is_exec) {
2160         helper_raise_exception(env, EXCP_IBE);
2161     } else {
2162         helper_raise_exception(env, EXCP_DBE);
2163     }
2164 }
2165 #endif /* !CONFIG_USER_ONLY */
2166
2167 /* Complex FPU operations which may need stack space. */
2168
2169 #define FLOAT_TWO32 make_float32(1 << 30)
2170 #define FLOAT_TWO64 make_float64(1ULL << 62)
2171 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2172 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2173
2174 /* convert MIPS rounding mode in FCR31 to IEEE library */
2175 static unsigned int ieee_rm[] = {
2176     float_round_nearest_even,
2177     float_round_to_zero,
2178     float_round_up,
2179     float_round_down
2180 };
2181
2182 static inline void restore_rounding_mode(CPUMIPSState *env)
2183 {
2184     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2185                             &env->active_fpu.fp_status);
2186 }
2187
2188 static inline void restore_flush_mode(CPUMIPSState *env)
2189 {
2190     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2191                       &env->active_fpu.fp_status);
2192 }
2193
2194 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2195 {
2196     target_ulong arg1 = 0;
2197
2198     switch (reg) {
2199     case 0:
2200         arg1 = (int32_t)env->active_fpu.fcr0;
2201         break;
2202     case 1:
2203         /* UFR Support - Read Status FR */
2204         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2205             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2206                 arg1 = (int32_t)
2207                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2208             } else {
2209                 helper_raise_exception(env, EXCP_RI);
2210             }
2211         }
2212         break;
2213     case 25:
2214         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2215         break;
2216     case 26:
2217         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2218         break;
2219     case 28:
2220         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2221         break;
2222     default:
2223         arg1 = (int32_t)env->active_fpu.fcr31;
2224         break;
2225     }
2226
2227     return arg1;
2228 }
2229
2230 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2231 {
2232     switch (fs) {
2233     case 1:
2234         /* UFR Alias - Reset Status FR */
2235         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2236             return;
2237         }
2238         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2239             env->CP0_Status &= ~(1 << CP0St_FR);
2240             compute_hflags(env);
2241         } else {
2242             helper_raise_exception(env, EXCP_RI);
2243         }
2244         break;
2245     case 4:
2246         /* UNFR Alias - Set Status FR */
2247         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2248             return;
2249         }
2250         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2251             env->CP0_Status |= (1 << CP0St_FR);
2252             compute_hflags(env);
2253         } else {
2254             helper_raise_exception(env, EXCP_RI);
2255         }
2256         break;
2257     case 25:
2258         if (arg1 & 0xffffff00)
2259             return;
2260         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2261                      ((arg1 & 0x1) << 23);
2262         break;
2263     case 26:
2264         if (arg1 & 0x007c0000)
2265             return;
2266         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2267         break;
2268     case 28:
2269         if (arg1 & 0x007c0000)
2270             return;
2271         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2272                      ((arg1 & 0x4) << 22);
2273         break;
2274     case 31:
2275         if (arg1 & 0x007c0000)
2276             return;
2277         env->active_fpu.fcr31 = arg1;
2278         break;
2279     default:
2280         return;
2281     }
2282     /* set rounding mode */
2283     restore_rounding_mode(env);
2284     /* set flush-to-zero mode */
2285     restore_flush_mode(env);
2286     set_float_exception_flags(0, &env->active_fpu.fp_status);
2287     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2288         do_raise_exception(env, EXCP_FPE, GETPC());
2289 }
2290
2291 static inline int ieee_ex_to_mips(int xcpt)
2292 {
2293     int ret = 0;
2294     if (xcpt) {
2295         if (xcpt & float_flag_invalid) {
2296             ret |= FP_INVALID;
2297         }
2298         if (xcpt & float_flag_overflow) {
2299             ret |= FP_OVERFLOW;
2300         }
2301         if (xcpt & float_flag_underflow) {
2302             ret |= FP_UNDERFLOW;
2303         }
2304         if (xcpt & float_flag_divbyzero) {
2305             ret |= FP_DIV0;
2306         }
2307         if (xcpt & float_flag_inexact) {
2308             ret |= FP_INEXACT;
2309         }
2310     }
2311     return ret;
2312 }
2313
2314 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2315 {
2316     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2317
2318     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2319
2320     if (tmp) {
2321         set_float_exception_flags(0, &env->active_fpu.fp_status);
2322
2323         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2324             do_raise_exception(env, EXCP_FPE, pc);
2325         } else {
2326             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2327         }
2328     }
2329 }
2330
2331 /* Float support.
2332    Single precition routines have a "s" suffix, double precision a
2333    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2334    paired single lower "pl", paired single upper "pu".  */
2335
2336 /* unary operations, modifying fp status  */
2337 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2338 {
2339     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2340     update_fcr31(env, GETPC());
2341     return fdt0;
2342 }
2343
2344 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2345 {
2346     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2347     update_fcr31(env, GETPC());
2348     return fst0;
2349 }
2350
2351 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2352 {
2353     uint64_t fdt2;
2354
2355     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2356     update_fcr31(env, GETPC());
2357     return fdt2;
2358 }
2359
2360 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2361 {
2362     uint64_t fdt2;
2363
2364     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2365     update_fcr31(env, GETPC());
2366     return fdt2;
2367 }
2368
2369 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2370 {
2371     uint64_t fdt2;
2372
2373     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2374     update_fcr31(env, GETPC());
2375     return fdt2;
2376 }
2377
2378 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2379 {
2380     uint64_t dt2;
2381
2382     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2383     if (get_float_exception_flags(&env->active_fpu.fp_status)
2384         & (float_flag_invalid | float_flag_overflow)) {
2385         dt2 = FP_TO_INT64_OVERFLOW;
2386     }
2387     update_fcr31(env, GETPC());
2388     return dt2;
2389 }
2390
2391 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2392 {
2393     uint64_t dt2;
2394
2395     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2396     if (get_float_exception_flags(&env->active_fpu.fp_status)
2397         & (float_flag_invalid | float_flag_overflow)) {
2398         dt2 = FP_TO_INT64_OVERFLOW;
2399     }
2400     update_fcr31(env, GETPC());
2401     return dt2;
2402 }
2403
2404 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2405 {
2406     uint32_t fst2;
2407     uint32_t fsth2;
2408
2409     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2410     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2411     update_fcr31(env, GETPC());
2412     return ((uint64_t)fsth2 << 32) | fst2;
2413 }
2414
2415 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2416 {
2417     uint32_t wt2;
2418     uint32_t wth2;
2419     int excp, excph;
2420
2421     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2422     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2423     if (excp & (float_flag_overflow | float_flag_invalid)) {
2424         wt2 = FP_TO_INT32_OVERFLOW;
2425     }
2426
2427     set_float_exception_flags(0, &env->active_fpu.fp_status);
2428     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2429     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2430     if (excph & (float_flag_overflow | float_flag_invalid)) {
2431         wth2 = FP_TO_INT32_OVERFLOW;
2432     }
2433
2434     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2435     update_fcr31(env, GETPC());
2436
2437     return ((uint64_t)wth2 << 32) | wt2;
2438 }
2439
2440 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2441 {
2442     uint32_t fst2;
2443
2444     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2445     update_fcr31(env, GETPC());
2446     return fst2;
2447 }
2448
2449 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2450 {
2451     uint32_t fst2;
2452
2453     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2454     update_fcr31(env, GETPC());
2455     return fst2;
2456 }
2457
2458 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2459 {
2460     uint32_t fst2;
2461
2462     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2463     update_fcr31(env, GETPC());
2464     return fst2;
2465 }
2466
2467 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2468 {
2469     uint32_t wt2;
2470
2471     wt2 = wt0;
2472     update_fcr31(env, GETPC());
2473     return wt2;
2474 }
2475
2476 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2477 {
2478     uint32_t wt2;
2479
2480     wt2 = wth0;
2481     update_fcr31(env, GETPC());
2482     return wt2;
2483 }
2484
2485 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2486 {
2487     uint32_t wt2;
2488
2489     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2490     update_fcr31(env, GETPC());
2491     if (get_float_exception_flags(&env->active_fpu.fp_status)
2492         & (float_flag_invalid | float_flag_overflow)) {
2493         wt2 = FP_TO_INT32_OVERFLOW;
2494     }
2495     return wt2;
2496 }
2497
2498 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2499 {
2500     uint32_t wt2;
2501
2502     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2503     if (get_float_exception_flags(&env->active_fpu.fp_status)
2504         & (float_flag_invalid | float_flag_overflow)) {
2505         wt2 = FP_TO_INT32_OVERFLOW;
2506     }
2507     update_fcr31(env, GETPC());
2508     return wt2;
2509 }
2510
2511 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2512 {
2513     uint64_t dt2;
2514
2515     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2516     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2517     restore_rounding_mode(env);
2518     if (get_float_exception_flags(&env->active_fpu.fp_status)
2519         & (float_flag_invalid | float_flag_overflow)) {
2520         dt2 = FP_TO_INT64_OVERFLOW;
2521     }
2522     update_fcr31(env, GETPC());
2523     return dt2;
2524 }
2525
2526 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2527 {
2528     uint64_t dt2;
2529
2530     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2531     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2532     restore_rounding_mode(env);
2533     if (get_float_exception_flags(&env->active_fpu.fp_status)
2534         & (float_flag_invalid | float_flag_overflow)) {
2535         dt2 = FP_TO_INT64_OVERFLOW;
2536     }
2537     update_fcr31(env, GETPC());
2538     return dt2;
2539 }
2540
2541 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2542 {
2543     uint32_t wt2;
2544
2545     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2546     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2547     restore_rounding_mode(env);
2548     if (get_float_exception_flags(&env->active_fpu.fp_status)
2549         & (float_flag_invalid | float_flag_overflow)) {
2550         wt2 = FP_TO_INT32_OVERFLOW;
2551     }
2552     update_fcr31(env, GETPC());
2553     return wt2;
2554 }
2555
2556 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2557 {
2558     uint32_t wt2;
2559
2560     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2561     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2562     restore_rounding_mode(env);
2563     if (get_float_exception_flags(&env->active_fpu.fp_status)
2564         & (float_flag_invalid | float_flag_overflow)) {
2565         wt2 = FP_TO_INT32_OVERFLOW;
2566     }
2567     update_fcr31(env, GETPC());
2568     return wt2;
2569 }
2570
2571 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2572 {
2573     uint64_t dt2;
2574
2575     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2576     if (get_float_exception_flags(&env->active_fpu.fp_status)
2577         & (float_flag_invalid | float_flag_overflow)) {
2578         dt2 = FP_TO_INT64_OVERFLOW;
2579     }
2580     update_fcr31(env, GETPC());
2581     return dt2;
2582 }
2583
2584 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2585 {
2586     uint64_t dt2;
2587
2588     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2589     if (get_float_exception_flags(&env->active_fpu.fp_status)
2590         & (float_flag_invalid | float_flag_overflow)) {
2591         dt2 = FP_TO_INT64_OVERFLOW;
2592     }
2593     update_fcr31(env, GETPC());
2594     return dt2;
2595 }
2596
2597 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2598 {
2599     uint32_t wt2;
2600
2601     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2602     if (get_float_exception_flags(&env->active_fpu.fp_status)
2603         & (float_flag_invalid | float_flag_overflow)) {
2604         wt2 = FP_TO_INT32_OVERFLOW;
2605     }
2606     update_fcr31(env, GETPC());
2607     return wt2;
2608 }
2609
2610 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2611 {
2612     uint32_t wt2;
2613
2614     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2615     if (get_float_exception_flags(&env->active_fpu.fp_status)
2616         & (float_flag_invalid | float_flag_overflow)) {
2617         wt2 = FP_TO_INT32_OVERFLOW;
2618     }
2619     update_fcr31(env, GETPC());
2620     return wt2;
2621 }
2622
2623 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2624 {
2625     uint64_t dt2;
2626
2627     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2628     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2629     restore_rounding_mode(env);
2630     if (get_float_exception_flags(&env->active_fpu.fp_status)
2631         & (float_flag_invalid | float_flag_overflow)) {
2632         dt2 = FP_TO_INT64_OVERFLOW;
2633     }
2634     update_fcr31(env, GETPC());
2635     return dt2;
2636 }
2637
2638 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2639 {
2640     uint64_t dt2;
2641
2642     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2643     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2644     restore_rounding_mode(env);
2645     if (get_float_exception_flags(&env->active_fpu.fp_status)
2646         & (float_flag_invalid | float_flag_overflow)) {
2647         dt2 = FP_TO_INT64_OVERFLOW;
2648     }
2649     update_fcr31(env, GETPC());
2650     return dt2;
2651 }
2652
2653 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2654 {
2655     uint32_t wt2;
2656
2657     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2658     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2659     restore_rounding_mode(env);
2660     if (get_float_exception_flags(&env->active_fpu.fp_status)
2661         & (float_flag_invalid | float_flag_overflow)) {
2662         wt2 = FP_TO_INT32_OVERFLOW;
2663     }
2664     update_fcr31(env, GETPC());
2665     return wt2;
2666 }
2667
2668 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2669 {
2670     uint32_t wt2;
2671
2672     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2673     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2674     restore_rounding_mode(env);
2675     if (get_float_exception_flags(&env->active_fpu.fp_status)
2676         & (float_flag_invalid | float_flag_overflow)) {
2677         wt2 = FP_TO_INT32_OVERFLOW;
2678     }
2679     update_fcr31(env, GETPC());
2680     return wt2;
2681 }
2682
2683 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2684 {
2685     uint64_t dt2;
2686
2687     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2688     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2689     restore_rounding_mode(env);
2690     if (get_float_exception_flags(&env->active_fpu.fp_status)
2691         & (float_flag_invalid | float_flag_overflow)) {
2692         dt2 = FP_TO_INT64_OVERFLOW;
2693     }
2694     update_fcr31(env, GETPC());
2695     return dt2;
2696 }
2697
2698 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2699 {
2700     uint64_t dt2;
2701
2702     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2703     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2704     restore_rounding_mode(env);
2705     if (get_float_exception_flags(&env->active_fpu.fp_status)
2706         & (float_flag_invalid | float_flag_overflow)) {
2707         dt2 = FP_TO_INT64_OVERFLOW;
2708     }
2709     update_fcr31(env, GETPC());
2710     return dt2;
2711 }
2712
2713 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2714 {
2715     uint32_t wt2;
2716
2717     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2718     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2719     restore_rounding_mode(env);
2720     if (get_float_exception_flags(&env->active_fpu.fp_status)
2721         & (float_flag_invalid | float_flag_overflow)) {
2722         wt2 = FP_TO_INT32_OVERFLOW;
2723     }
2724     update_fcr31(env, GETPC());
2725     return wt2;
2726 }
2727
2728 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2729 {
2730     uint32_t wt2;
2731
2732     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2733     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2734     restore_rounding_mode(env);
2735     if (get_float_exception_flags(&env->active_fpu.fp_status)
2736         & (float_flag_invalid | float_flag_overflow)) {
2737         wt2 = FP_TO_INT32_OVERFLOW;
2738     }
2739     update_fcr31(env, GETPC());
2740     return wt2;
2741 }
2742
2743 /* unary operations, not modifying fp status  */
2744 #define FLOAT_UNOP(name)                                       \
2745 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2746 {                                                              \
2747     return float64_ ## name(fdt0);                             \
2748 }                                                              \
2749 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2750 {                                                              \
2751     return float32_ ## name(fst0);                             \
2752 }                                                              \
2753 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2754 {                                                              \
2755     uint32_t wt0;                                              \
2756     uint32_t wth0;                                             \
2757                                                                \
2758     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2759     wth0 = float32_ ## name(fdt0 >> 32);                       \
2760     return ((uint64_t)wth0 << 32) | wt0;                       \
2761 }
2762 FLOAT_UNOP(abs)
2763 FLOAT_UNOP(chs)
2764 #undef FLOAT_UNOP
2765
2766 /* MIPS specific unary operations */
2767 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2768 {
2769     uint64_t fdt2;
2770
2771     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2772     update_fcr31(env, GETPC());
2773     return fdt2;
2774 }
2775
2776 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2777 {
2778     uint32_t fst2;
2779
2780     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2781     update_fcr31(env, GETPC());
2782     return fst2;
2783 }
2784
2785 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2786 {
2787     uint64_t fdt2;
2788
2789     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2790     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2791     update_fcr31(env, GETPC());
2792     return fdt2;
2793 }
2794
2795 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2796 {
2797     uint32_t fst2;
2798
2799     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2800     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2801     update_fcr31(env, GETPC());
2802     return fst2;
2803 }
2804
2805 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2806 {
2807     uint64_t fdt2;
2808
2809     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2810     update_fcr31(env, GETPC());
2811     return fdt2;
2812 }
2813
2814 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2815 {
2816     uint32_t fst2;
2817
2818     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2819     update_fcr31(env, GETPC());
2820     return fst2;
2821 }
2822
2823 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2824 {
2825     uint32_t fst2;
2826     uint32_t fsth2;
2827
2828     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2829     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2830     update_fcr31(env, GETPC());
2831     return ((uint64_t)fsth2 << 32) | fst2;
2832 }
2833
2834 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2835 {
2836     uint64_t fdt2;
2837
2838     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2839     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2840     update_fcr31(env, GETPC());
2841     return fdt2;
2842 }
2843
2844 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2845 {
2846     uint32_t fst2;
2847
2848     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2849     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2850     update_fcr31(env, GETPC());
2851     return fst2;
2852 }
2853
2854 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2855 {
2856     uint32_t fst2;
2857     uint32_t fsth2;
2858
2859     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2860     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2861     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2862     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2863     update_fcr31(env, GETPC());
2864     return ((uint64_t)fsth2 << 32) | fst2;
2865 }
2866
2867 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2868
2869 /* binary operations */
2870 #define FLOAT_BINOP(name)                                          \
2871 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2872                                      uint64_t fdt0, uint64_t fdt1) \
2873 {                                                                  \
2874     uint64_t dt2;                                                  \
2875                                                                    \
2876     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2877     update_fcr31(env, GETPC());                                    \
2878     return dt2;                                                    \
2879 }                                                                  \
2880                                                                    \
2881 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2882                                      uint32_t fst0, uint32_t fst1) \
2883 {                                                                  \
2884     uint32_t wt2;                                                  \
2885                                                                    \
2886     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2887     update_fcr31(env, GETPC());                                    \
2888     return wt2;                                                    \
2889 }                                                                  \
2890                                                                    \
2891 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2892                                       uint64_t fdt0,               \
2893                                       uint64_t fdt1)               \
2894 {                                                                  \
2895     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2896     uint32_t fsth0 = fdt0 >> 32;                                   \
2897     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2898     uint32_t fsth1 = fdt1 >> 32;                                   \
2899     uint32_t wt2;                                                  \
2900     uint32_t wth2;                                                 \
2901                                                                    \
2902     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2903     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2904     update_fcr31(env, GETPC());                                    \
2905     return ((uint64_t)wth2 << 32) | wt2;                           \
2906 }
2907
2908 FLOAT_BINOP(add)
2909 FLOAT_BINOP(sub)
2910 FLOAT_BINOP(mul)
2911 FLOAT_BINOP(div)
2912 #undef FLOAT_BINOP
2913
2914 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
2915 {                                                                    \
2916     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
2917     if ((flags) & float_muladd_negate_c) {                           \
2918         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
2919     } else {                                                         \
2920         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
2921     }                                                                \
2922     if ((flags) & float_muladd_negate_result) {                      \
2923         a = prefix##_chs(a);                                         \
2924     }                                                                \
2925 }
2926
2927 /* FMA based operations */
2928 #define FLOAT_FMA(name, type)                                        \
2929 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2930                                      uint64_t fdt0, uint64_t fdt1,   \
2931                                      uint64_t fdt2)                  \
2932 {                                                                    \
2933     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
2934     update_fcr31(env, GETPC());                                      \
2935     return fdt0;                                                     \
2936 }                                                                    \
2937                                                                      \
2938 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2939                                      uint32_t fst0, uint32_t fst1,   \
2940                                      uint32_t fst2)                  \
2941 {                                                                    \
2942     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2943     update_fcr31(env, GETPC());                                      \
2944     return fst0;                                                     \
2945 }                                                                    \
2946                                                                      \
2947 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2948                                       uint64_t fdt0, uint64_t fdt1,  \
2949                                       uint64_t fdt2)                 \
2950 {                                                                    \
2951     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2952     uint32_t fsth0 = fdt0 >> 32;                                     \
2953     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2954     uint32_t fsth1 = fdt1 >> 32;                                     \
2955     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2956     uint32_t fsth2 = fdt2 >> 32;                                     \
2957                                                                      \
2958     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
2959     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
2960     update_fcr31(env, GETPC());                                      \
2961     return ((uint64_t)fsth0 << 32) | fst0;                           \
2962 }
2963 FLOAT_FMA(madd, 0)
2964 FLOAT_FMA(msub, float_muladd_negate_c)
2965 FLOAT_FMA(nmadd, float_muladd_negate_result)
2966 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2967 #undef FLOAT_FMA
2968
2969 /* MIPS specific binary operations */
2970 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2971 {
2972     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2973     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2974     update_fcr31(env, GETPC());
2975     return fdt2;
2976 }
2977
2978 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2979 {
2980     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2981     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2982     update_fcr31(env, GETPC());
2983     return fst2;
2984 }
2985
2986 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2987 {
2988     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2989     uint32_t fsth0 = fdt0 >> 32;
2990     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2991     uint32_t fsth2 = fdt2 >> 32;
2992
2993     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2994     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2995     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2996     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2997     update_fcr31(env, GETPC());
2998     return ((uint64_t)fsth2 << 32) | fst2;
2999 }
3000
3001 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3002 {
3003     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3004     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3005     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3006     update_fcr31(env, GETPC());
3007     return fdt2;
3008 }
3009
3010 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3011 {
3012     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3013     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3014     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3015     update_fcr31(env, GETPC());
3016     return fst2;
3017 }
3018
3019 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3020 {
3021     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3022     uint32_t fsth0 = fdt0 >> 32;
3023     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3024     uint32_t fsth2 = fdt2 >> 32;
3025
3026     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3027     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3028     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3029     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3030     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3031     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3032     update_fcr31(env, GETPC());
3033     return ((uint64_t)fsth2 << 32) | fst2;
3034 }
3035
3036 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3037 {
3038     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3039     uint32_t fsth0 = fdt0 >> 32;
3040     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3041     uint32_t fsth1 = fdt1 >> 32;
3042     uint32_t fst2;
3043     uint32_t fsth2;
3044
3045     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3046     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3047     update_fcr31(env, GETPC());
3048     return ((uint64_t)fsth2 << 32) | fst2;
3049 }
3050
3051 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3052 {
3053     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3054     uint32_t fsth0 = fdt0 >> 32;
3055     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3056     uint32_t fsth1 = fdt1 >> 32;
3057     uint32_t fst2;
3058     uint32_t fsth2;
3059
3060     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3061     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3062     update_fcr31(env, GETPC());
3063     return ((uint64_t)fsth2 << 32) | fst2;
3064 }
3065
3066 /* compare operations */
3067 #define FOP_COND_D(op, cond)                                   \
3068 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3069                          uint64_t fdt1, int cc)                \
3070 {                                                              \
3071     int c;                                                     \
3072     c = cond;                                                  \
3073     update_fcr31(env, GETPC());                                \
3074     if (c)                                                     \
3075         SET_FP_COND(cc, env->active_fpu);                      \
3076     else                                                       \
3077         CLEAR_FP_COND(cc, env->active_fpu);                    \
3078 }                                                              \
3079 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3080                             uint64_t fdt1, int cc)             \
3081 {                                                              \
3082     int c;                                                     \
3083     fdt0 = float64_abs(fdt0);                                  \
3084     fdt1 = float64_abs(fdt1);                                  \
3085     c = cond;                                                  \
3086     update_fcr31(env, GETPC());                                \
3087     if (c)                                                     \
3088         SET_FP_COND(cc, env->active_fpu);                      \
3089     else                                                       \
3090         CLEAR_FP_COND(cc, env->active_fpu);                    \
3091 }
3092
3093 /* NOTE: the comma operator will make "cond" to eval to false,
3094  * but float64_unordered_quiet() is still called. */
3095 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3096 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3097 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3098 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3099 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3100 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3101 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3102 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3103 /* NOTE: the comma operator will make "cond" to eval to false,
3104  * but float64_unordered() is still called. */
3105 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3106 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3107 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3108 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3109 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3110 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3111 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3112 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3113
3114 #define FOP_COND_S(op, cond)                                   \
3115 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3116                          uint32_t fst1, int cc)                \
3117 {                                                              \
3118     int c;                                                     \
3119     c = cond;                                                  \
3120     update_fcr31(env, GETPC());                                \
3121     if (c)                                                     \
3122         SET_FP_COND(cc, env->active_fpu);                      \
3123     else                                                       \
3124         CLEAR_FP_COND(cc, env->active_fpu);                    \
3125 }                                                              \
3126 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3127                             uint32_t fst1, int cc)             \
3128 {                                                              \
3129     int c;                                                     \
3130     fst0 = float32_abs(fst0);                                  \
3131     fst1 = float32_abs(fst1);                                  \
3132     c = cond;                                                  \
3133     update_fcr31(env, GETPC());                                \
3134     if (c)                                                     \
3135         SET_FP_COND(cc, env->active_fpu);                      \
3136     else                                                       \
3137         CLEAR_FP_COND(cc, env->active_fpu);                    \
3138 }
3139
3140 /* NOTE: the comma operator will make "cond" to eval to false,
3141  * but float32_unordered_quiet() is still called. */
3142 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3143 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3144 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3145 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3146 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3147 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3148 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3149 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3150 /* NOTE: the comma operator will make "cond" to eval to false,
3151  * but float32_unordered() is still called. */
3152 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3153 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3154 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3155 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3156 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3157 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3158 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3159 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3160
3161 #define FOP_COND_PS(op, condl, condh)                           \
3162 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3163                           uint64_t fdt1, int cc)                \
3164 {                                                               \
3165     uint32_t fst0, fsth0, fst1, fsth1;                          \
3166     int ch, cl;                                                 \
3167     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3168     fsth0 = fdt0 >> 32;                                         \
3169     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3170     fsth1 = fdt1 >> 32;                                         \
3171     cl = condl;                                                 \
3172     ch = condh;                                                 \
3173     update_fcr31(env, GETPC());                                 \
3174     if (cl)                                                     \
3175         SET_FP_COND(cc, env->active_fpu);                       \
3176     else                                                        \
3177         CLEAR_FP_COND(cc, env->active_fpu);                     \
3178     if (ch)                                                     \
3179         SET_FP_COND(cc + 1, env->active_fpu);                   \
3180     else                                                        \
3181         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3182 }                                                               \
3183 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3184                              uint64_t fdt1, int cc)             \
3185 {                                                               \
3186     uint32_t fst0, fsth0, fst1, fsth1;                          \
3187     int ch, cl;                                                 \
3188     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3189     fsth0 = float32_abs(fdt0 >> 32);                            \
3190     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3191     fsth1 = float32_abs(fdt1 >> 32);                            \
3192     cl = condl;                                                 \
3193     ch = condh;                                                 \
3194     update_fcr31(env, GETPC());                                 \
3195     if (cl)                                                     \
3196         SET_FP_COND(cc, env->active_fpu);                       \
3197     else                                                        \
3198         CLEAR_FP_COND(cc, env->active_fpu);                     \
3199     if (ch)                                                     \
3200         SET_FP_COND(cc + 1, env->active_fpu);                   \
3201     else                                                        \
3202         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3203 }
3204
3205 /* NOTE: the comma operator will make "cond" to eval to false,
3206  * but float32_unordered_quiet() is still called. */
3207 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3208                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3209 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3210                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3211 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3212                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3213 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3214                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3215 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3216                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3217 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3218                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3219 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3220                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3221 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3222                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3223 /* NOTE: the comma operator will make "cond" to eval to false,
3224  * but float32_unordered() is still called. */
3225 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3226                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3227 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3228                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3229 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3230                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3231 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3232                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3233 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3234                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3235 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3236                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3237 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3238                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3239 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3240                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))