target-mips/kvm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10 */
  11
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "cpu.h"
  24 #include "sysemu/cpus.h"
  25 #include "kvm_mips.h"
  26
  27 #define DEBUG_KVM 0
  28
  29 #define DPRINTF(fmt, ...) \
  30     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
  31
  32 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  33     KVM_CAP_LAST_INFO
  34 };
  35
  36 static void kvm_mips_update_state(void *opaque, int running, RunState state);
  37
  38 unsigned long kvm_arch_vcpu_id(CPUState *cs)
  39 {
  40     return cs->cpu_index;
  41 }
  42
  43 int kvm_arch_init(KVMState *s)
  44 {
  45     /* MIPS has 128 signals */
  46     kvm_set_sigmask_len(s, 16);
  47
  48     DPRINTF("%s\n", __func__);
  49     return 0;
  50 }
  51
  52 int kvm_arch_init_vcpu(CPUState *cs)
  53 {
  54     int ret = 0;
  55
  56     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
  57
  58     DPRINTF("%s\n", __func__);
  59     return ret;
  60 }
  61
  62 void kvm_mips_reset_vcpu(MIPSCPU *cpu)
  63 {
  64     DPRINTF("%s\n", __func__);
  65 }
  66
  67 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  68 {
  69     DPRINTF("%s\n", __func__);
  70     return 0;
  71 }
  72
  73 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  74 {
  75     DPRINTF("%s\n", __func__);
  76     return 0;
  77 }
  78
  79 static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
  80 {
  81     CPUMIPSState *env = &cpu->env;
  82
  83     DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
  84     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
  85 }
  86
  87
  88 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  89 {
  90     MIPSCPU *cpu = MIPS_CPU(cs);
  91     int r;
  92     struct kvm_mips_interrupt intr;
  93
  94     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  95             cpu_mips_io_interrupts_pending(cpu)) {
  96         intr.cpu = -1;
  97         intr.irq = 2;
  98         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
  99         if (r < 0) {
 100             error_report("%s: cpu %d: failed to inject IRQ %x",
 101                          __func__, cs->cpu_index, intr.irq);
 102         }
 103     }
 104 }
 105
 106 void kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 107 {
 108     DPRINTF("%s\n", __func__);
 109 }
 110
 111 int kvm_arch_process_async_events(CPUState *cs)
 112 {
 113     return cs->halted;
 114 }
 115
 116 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 117 {
 118     int ret;
 119
 120     DPRINTF("%s\n", __func__);
 121     switch (run->exit_reason) {
 122     default:
 123         error_report("%s: unknown exit reason %d",
 124                      __func__, run->exit_reason);
 125         ret = -1;
 126         break;
 127     }
 128
 129     return ret;
 130 }
 131
 132 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 133 {
 134     DPRINTF("%s\n", __func__);
 135     return true;
 136 }
 137
 138 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 139 {
 140     DPRINTF("%s\n", __func__);
 141     return 1;
 142 }
 143
 144 int kvm_arch_on_sigbus(int code, void *addr)
 145 {
 146     DPRINTF("%s\n", __func__);
 147     return 1;
 148 }
 149
 150 void kvm_arch_init_irq_routing(KVMState *s)
 151 {
 152 }
 153
 154 int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
 155 {
 156     CPUState *cs = CPU(cpu);
 157     struct kvm_mips_interrupt intr;
 158
 159     if (!kvm_enabled()) {
 160         return 0;
 161     }
 162
 163     intr.cpu = -1;
 164
 165     if (level) {
 166         intr.irq = irq;
 167     } else {
 168         intr.irq = -irq;
 169     }
 170
 171     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 172
 173     return 0;
 174 }
 175
 176 int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 177 {
 178     CPUState *cs = current_cpu;
 179     CPUState *dest_cs = CPU(cpu);
 180     struct kvm_mips_interrupt intr;
 181
 182     if (!kvm_enabled()) {
 183         return 0;
 184     }
 185
 186     intr.cpu = dest_cs->cpu_index;
 187
 188     if (level) {
 189         intr.irq = irq;
 190     } else {
 191         intr.irq = -irq;
 192     }
 193
 194     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
 195
 196     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 197
 198     return 0;
 199 }
 200
 201 #define MIPS_CP0_32(_R, _S)                                     \
 202     (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
 203
 204 #define MIPS_CP0_64(_R, _S)                                     \
 205     (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
 206
 207 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
 208 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
 209 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
 210 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
 211 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
 212 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
 213 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
 214 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
 215 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
 216 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
 217 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 218 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 219 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
 220 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 221
 222 /* CP0_Count control */
 223 #define KVM_REG_MIPS_COUNT_CTL          (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 224                                          0x20000 | 0)
 225 #define KVM_REG_MIPS_COUNT_CTL_DC       0x00000001      /* master disable */
 226 /* CP0_Count resume monotonic nanoseconds */
 227 #define KVM_REG_MIPS_COUNT_RESUME       (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 228                                          0x20000 | 1)
 229 /* CP0_Count rate in Hz */
 230 #define KVM_REG_MIPS_COUNT_HZ           (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 231                                          0x20000 | 2)
 232
 233 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
 234                                        int32_t *addr)
 235 {
 236     uint64_t val64 = *addr;
 237     struct kvm_one_reg cp0reg = {
 238         .id = reg_id,
 239         .addr = (uintptr_t)&val64
 240     };
 241
 242     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 243 }
 244
 245 static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
 246                                          target_ulong *addr)
 247 {
 248     uint64_t val64 = *addr;
 249     struct kvm_one_reg cp0reg = {
 250         .id = reg_id,
 251         .addr = (uintptr_t)&val64
 252     };
 253
 254     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 255 }
 256
 257 static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
 258                                          uint64_t *addr)
 259 {
 260     struct kvm_one_reg cp0reg = {
 261         .id = reg_id,
 262         .addr = (uintptr_t)addr
 263     };
 264
 265     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 266 }
 267
 268 static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
 269                                        int32_t *addr)
 270 {
 271     int ret;
 272     uint64_t val64 = 0;
 273     struct kvm_one_reg cp0reg = {
 274         .id = reg_id,
 275         .addr = (uintptr_t)&val64
 276     };
 277
 278     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 279     if (ret >= 0) {
 280         *addr = val64;
 281     }
 282     return ret;
 283 }
 284
 285 static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id,
 286                                          target_ulong *addr)
 287 {
 288     int ret;
 289     uint64_t val64 = 0;
 290     struct kvm_one_reg cp0reg = {
 291         .id = reg_id,
 292         .addr = (uintptr_t)&val64
 293     };
 294
 295     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 296     if (ret >= 0) {
 297         *addr = val64;
 298     }
 299     return ret;
 300 }
 301
 302 static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64 reg_id,
 303                                          uint64_t *addr)
 304 {
 305     struct kvm_one_reg cp0reg = {
 306         .id = reg_id,
 307         .addr = (uintptr_t)addr
 308     };
 309
 310     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 311 }
 312
 313 /*
 314  * We freeze the KVM timer when either the VM clock is stopped or the state is
 315  * saved (the state is dirty).
 316  */
 317
 318 /*
 319  * Save the state of the KVM timer when VM clock is stopped or state is synced
 320  * to QEMU.
 321  */
 322 static int kvm_mips_save_count(CPUState *cs)
 323 {
 324     MIPSCPU *cpu = MIPS_CPU(cs);
 325     CPUMIPSState *env = &cpu->env;
 326     uint64_t count_ctl;
 327     int err, ret = 0;
 328
 329     /* freeze KVM timer */
 330     err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 331     if (err < 0) {
 332         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
 333         ret = err;
 334     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 335         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 336         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 337         if (err < 0) {
 338             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 339             ret = err;
 340         }
 341     }
 342
 343     /* read CP0_Cause */
 344     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 345     if (err < 0) {
 346         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
 347         ret = err;
 348     }
 349
 350     /* read CP0_Count */
 351     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 352     if (err < 0) {
 353         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
 354         ret = err;
 355     }
 356
 357     return ret;
 358 }
 359
 360 /*
 361  * Restore the state of the KVM timer when VM clock is restarted or state is
 362  * synced to KVM.
 363  */
 364 static int kvm_mips_restore_count(CPUState *cs)
 365 {
 366     MIPSCPU *cpu = MIPS_CPU(cs);
 367     CPUMIPSState *env = &cpu->env;
 368     uint64_t count_ctl;
 369     int err_dc, err, ret = 0;
 370
 371     /* check the timer is frozen */
 372     err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 373     if (err_dc < 0) {
 374         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
 375         ret = err_dc;
 376     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 377         /* freeze timer (sets COUNT_RESUME for us) */
 378         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 379         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 380         if (err < 0) {
 381             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 382             ret = err;
 383         }
 384     }
 385
 386     /* load CP0_Cause */
 387     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 388     if (err < 0) {
 389         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
 390         ret = err;
 391     }
 392
 393     /* load CP0_Count */
 394     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 395     if (err < 0) {
 396         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
 397         ret = err;
 398     }
 399
 400     /* resume KVM timer */
 401     if (err_dc >= 0) {
 402         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
 403         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 404         if (err < 0) {
 405             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
 406             ret = err;
 407         }
 408     }
 409
 410     return ret;
 411 }
 412
 413 /*
 414  * Handle the VM clock being started or stopped
 415  */
 416 static void kvm_mips_update_state(void *opaque, int running, RunState state)
 417 {
 418     CPUState *cs = opaque;
 419     int ret;
 420     uint64_t count_resume;
 421
 422     /*
 423      * If state is already dirty (synced to QEMU) then the KVM timer state is
 424      * already saved and can be restored when it is synced back to KVM.
 425      */
 426     if (!running) {
 427         if (!cs->kvm_vcpu_dirty) {
 428             ret = kvm_mips_save_count(cs);
 429             if (ret < 0) {
 430                 fprintf(stderr, "Failed saving count\n");
 431             }
 432         }
 433     } else {
 434         /* Set clock restore time to now */
 435         count_resume = get_clock();
 436         ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
 437                                      &count_resume);
 438         if (ret < 0) {
 439             fprintf(stderr, "Failed setting COUNT_RESUME\n");
 440             return;
 441         }
 442
 443         if (!cs->kvm_vcpu_dirty) {
 444             ret = kvm_mips_restore_count(cs);
 445             if (ret < 0) {
 446                 fprintf(stderr, "Failed restoring count\n");
 447             }
 448         }
 449     }
 450 }
 451
 452 static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
 453 {
 454     MIPSCPU *cpu = MIPS_CPU(cs);
 455     CPUMIPSState *env = &cpu->env;
 456     int err, ret = 0;
 457
 458     (void)level;
 459
 460     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 461     if (err < 0) {
 462         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 463         ret = err;
 464     }
 465     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 466                                  &env->CP0_Context);
 467     if (err < 0) {
 468         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
 469         ret = err;
 470     }
 471     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 472                                  &env->active_tc.CP0_UserLocal);
 473     if (err < 0) {
 474         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
 475         ret = err;
 476     }
 477     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 478                                &env->CP0_PageMask);
 479     if (err < 0) {
 480         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
 481         ret = err;
 482     }
 483     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 484     if (err < 0) {
 485         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
 486         ret = err;
 487     }
 488     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 489     if (err < 0) {
 490         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
 491         ret = err;
 492     }
 493     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 494                                  &env->CP0_BadVAddr);
 495     if (err < 0) {
 496         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
 497         ret = err;
 498     }
 499
 500     /* If VM clock stopped then state will be restored when it is restarted */
 501     if (runstate_is_running()) {
 502         err = kvm_mips_restore_count(cs);
 503         if (err < 0) {
 504             ret = err;
 505         }
 506     }
 507
 508     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 509                                  &env->CP0_EntryHi);
 510     if (err < 0) {
 511         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
 512         ret = err;
 513     }
 514     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 515                                &env->CP0_Compare);
 516     if (err < 0) {
 517         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
 518         ret = err;
 519     }
 520     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 521     if (err < 0) {
 522         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
 523         ret = err;
 524     }
 525     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 526     if (err < 0) {
 527         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
 528         ret = err;
 529     }
 530     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 531                                  &env->CP0_ErrorEPC);
 532     if (err < 0) {
 533         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
 534         ret = err;
 535     }
 536
 537     return ret;
 538 }
 539
 540 static int kvm_mips_get_cp0_registers(CPUState *cs)
 541 {
 542     MIPSCPU *cpu = MIPS_CPU(cs);
 543     CPUMIPSState *env = &cpu->env;
 544     int err, ret = 0;
 545
 546     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 547     if (err < 0) {
 548         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
 549         ret = err;
 550     }
 551     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 552                                  &env->CP0_Context);
 553     if (err < 0) {
 554         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
 555         ret = err;
 556     }
 557     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 558                                  &env->active_tc.CP0_UserLocal);
 559     if (err < 0) {
 560         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
 561         ret = err;
 562     }
 563     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 564                                &env->CP0_PageMask);
 565     if (err < 0) {
 566         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
 567         ret = err;
 568     }
 569     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 570     if (err < 0) {
 571         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
 572         ret = err;
 573     }
 574     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 575     if (err < 0) {
 576         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
 577         ret = err;
 578     }
 579     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 580                                  &env->CP0_BadVAddr);
 581     if (err < 0) {
 582         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
 583         ret = err;
 584     }
 585     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 586                                  &env->CP0_EntryHi);
 587     if (err < 0) {
 588         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
 589         ret = err;
 590     }
 591     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 592                                &env->CP0_Compare);
 593     if (err < 0) {
 594         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
 595         ret = err;
 596     }
 597     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 598     if (err < 0) {
 599         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
 600         ret = err;
 601     }
 602
 603     /* If VM clock stopped then state was already saved when it was stopped */
 604     if (runstate_is_running()) {
 605         err = kvm_mips_save_count(cs);
 606         if (err < 0) {
 607             ret = err;
 608         }
 609     }
 610
 611     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 612     if (err < 0) {
 613         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
 614         ret = err;
 615     }
 616     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 617                                  &env->CP0_ErrorEPC);
 618     if (err < 0) {
 619         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
 620         ret = err;
 621     }
 622
 623     return ret;
 624 }
 625
 626 int kvm_arch_put_registers(CPUState *cs, int level)
 627 {
 628     MIPSCPU *cpu = MIPS_CPU(cs);
 629     CPUMIPSState *env = &cpu->env;
 630     struct kvm_regs regs;
 631     int ret;
 632     int i;
 633
 634     /* Set the registers based on QEMU's view of things */
 635     for (i = 0; i < 32; i++) {
 636         regs.gpr[i] = env->active_tc.gpr[i];
 637     }
 638
 639     regs.hi = env->active_tc.HI[0];
 640     regs.lo = env->active_tc.LO[0];
 641     regs.pc = env->active_tc.PC;
 642
 643     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
 644
 645     if (ret < 0) {
 646         return ret;
 647     }
 648
 649     ret = kvm_mips_put_cp0_registers(cs, level);
 650     if (ret < 0) {
 651         return ret;
 652     }
 653
 654     return ret;
 655 }
 656
 657 int kvm_arch_get_registers(CPUState *cs)
 658 {
 659     MIPSCPU *cpu = MIPS_CPU(cs);
 660     CPUMIPSState *env = &cpu->env;
 661     int ret = 0;
 662     struct kvm_regs regs;
 663     int i;
 664
 665     /* Get the current register set as KVM seems it */
 666     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
 667
 668     if (ret < 0) {
 669         return ret;
 670     }
 671
 672     for (i = 0; i < 32; i++) {
 673         env->active_tc.gpr[i] = regs.gpr[i];
 674     }
 675
 676     env->active_tc.HI[0] = regs.hi;
 677     env->active_tc.LO[0] = regs.lo;
 678     env->active_tc.PC = regs.pc;
 679
 680     kvm_mips_get_cp0_registers(cs);
 681
 682     return ret;
 683 }