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target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate
[qemu/ar7.git] / target-ppc / translate.c
blobb392ecc9447c5b2969713b1e226bb7a0d39e707d
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUPPCState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
106 offsetof(CPUPPCState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv;
196 int mem_idx;
197 int access_type;
198 /* Translation flags */
199 int le_mode;
200 TCGMemOp default_tcg_memop_mask;
201 #if defined(TARGET_PPC64)
202 int sf_mode;
203 int has_cfar;
204 #endif
205 int fpu_enabled;
206 int altivec_enabled;
207 int vsx_enabled;
208 int spe_enabled;
209 int tm_enabled;
210 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
211 int singlestep_enabled;
212 uint64_t insns_flags;
213 uint64_t insns_flags2;
214 };
215
216 /* Return true iff byteswap is needed in a scalar memop */
217 static inline bool need_byteswap(const DisasContext *ctx)
218 {
219 #if defined(TARGET_WORDS_BIGENDIAN)
220 return ctx->le_mode;
221 #else
222 return !ctx->le_mode;
223 #endif
224 }
225
226 /* True when active word size < size of target_long. */
227 #ifdef TARGET_PPC64
228 # define NARROW_MODE(C) (!(C)->sf_mode)
229 #else
230 # define NARROW_MODE(C) 0
231 #endif
232
233 struct opc_handler_t {
234 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
235 uint32_t inval1;
236 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
237 uint32_t inval2;
238 /* instruction type */
239 uint64_t type;
240 /* extended instruction type */
241 uint64_t type2;
242 /* handler */
243 void (*handler)(DisasContext *ctx);
244 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
245 const char *oname;
246 #endif
247 #if defined(DO_PPC_STATISTICS)
248 uint64_t count;
249 #endif
250 };
251
252 static inline void gen_reset_fpstatus(void)
253 {
254 gen_helper_reset_fpstatus(cpu_env);
255 }
256
257 static inline void gen_compute_fprf(TCGv_i64 arg)
258 {
259 gen_helper_compute_fprf(cpu_env, arg);
260 gen_helper_float_check_status(cpu_env);
261 }
262
263 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
264 {
265 if (ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
269 }
270
271 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
272 {
273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
277 }
278
279 void gen_update_current_nip(void *opaque)
280 {
281 DisasContext *ctx = opaque;
282
283 tcg_gen_movi_tl(cpu_nip, ctx->nip);
284 }
285
286 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
287 {
288 TCGv_i32 t0, t1;
289 if (ctx->exception == POWERPC_EXCP_NONE) {
290 gen_update_nip(ctx, ctx->nip);
291 }
292 t0 = tcg_const_i32(excp);
293 t1 = tcg_const_i32(error);
294 gen_helper_raise_exception_err(cpu_env, t0, t1);
295 tcg_temp_free_i32(t0);
296 tcg_temp_free_i32(t1);
297 ctx->exception = (excp);
298 }
299
300 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
301 {
302 TCGv_i32 t0;
303 if (ctx->exception == POWERPC_EXCP_NONE) {
304 gen_update_nip(ctx, ctx->nip);
305 }
306 t0 = tcg_const_i32(excp);
307 gen_helper_raise_exception(cpu_env, t0);
308 tcg_temp_free_i32(t0);
309 ctx->exception = (excp);
310 }
311
312 static inline void gen_debug_exception(DisasContext *ctx)
313 {
314 TCGv_i32 t0;
315
316 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
317 (ctx->exception != POWERPC_EXCP_SYNC)) {
318 gen_update_nip(ctx, ctx->nip);
319 }
320 t0 = tcg_const_i32(EXCP_DEBUG);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 }
324
325 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
326 {
327 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
328 }
329
330 /* Stop translation */
331 static inline void gen_stop_exception(DisasContext *ctx)
332 {
333 gen_update_nip(ctx, ctx->nip);
334 ctx->exception = POWERPC_EXCP_STOP;
335 }
336
337 #ifndef CONFIG_USER_ONLY
338 /* No need to update nip here, as execution flow will change */
339 static inline void gen_sync_exception(DisasContext *ctx)
340 {
341 ctx->exception = POWERPC_EXCP_SYNC;
342 }
343 #endif
344
345 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
350
351 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
352 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
355 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
356
357 typedef struct opcode_t {
358 unsigned char opc1, opc2, opc3;
359 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
360 unsigned char pad[5];
361 #else
362 unsigned char pad[1];
363 #endif
364 opc_handler_t handler;
365 const char *oname;
366 } opcode_t;
367
368 /*****************************************************************************/
369 /*** Instruction decoding ***/
370 #define EXTRACT_HELPER(name, shift, nb) \
371 static inline uint32_t name(uint32_t opcode) \
372 { \
373 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374 }
375
376 #define EXTRACT_SHELPER(name, shift, nb) \
377 static inline int32_t name(uint32_t opcode) \
378 { \
379 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
380 }
381
382 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
383 static inline uint32_t name(uint32_t opcode) \
384 { \
385 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
386 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387 }
388 /* Opcode part 1 */
389 EXTRACT_HELPER(opc1, 26, 6);
390 /* Opcode part 2 */
391 EXTRACT_HELPER(opc2, 1, 5);
392 /* Opcode part 3 */
393 EXTRACT_HELPER(opc3, 6, 5);
394 /* Update Cr0 flags */
395 EXTRACT_HELPER(Rc, 0, 1);
396 /* Update Cr6 flags (Altivec) */
397 EXTRACT_HELPER(Rc21, 10, 1);
398 /* Destination */
399 EXTRACT_HELPER(rD, 21, 5);
400 /* Source */
401 EXTRACT_HELPER(rS, 21, 5);
402 /* First operand */
403 EXTRACT_HELPER(rA, 16, 5);
404 /* Second operand */
405 EXTRACT_HELPER(rB, 11, 5);
406 /* Third operand */
407 EXTRACT_HELPER(rC, 6, 5);
408 /*** Get CRn ***/
409 EXTRACT_HELPER(crfD, 23, 3);
410 EXTRACT_HELPER(crfS, 18, 3);
411 EXTRACT_HELPER(crbD, 21, 5);
412 EXTRACT_HELPER(crbA, 16, 5);
413 EXTRACT_HELPER(crbB, 11, 5);
414 /* SPR / TBL */
415 EXTRACT_HELPER(_SPR, 11, 10);
416 static inline uint32_t SPR(uint32_t opcode)
417 {
418 uint32_t sprn = _SPR(opcode);
419
420 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
421 }
422 /*** Get constants ***/
423 /* 16 bits signed immediate value */
424 EXTRACT_SHELPER(SIMM, 0, 16);
425 /* 16 bits unsigned immediate value */
426 EXTRACT_HELPER(UIMM, 0, 16);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(SIMM5, 16, 5);
429 /* 5 bits signed immediate value */
430 EXTRACT_HELPER(UIMM5, 16, 5);
431 /* Bit count */
432 EXTRACT_HELPER(NB, 11, 5);
433 /* Shift count */
434 EXTRACT_HELPER(SH, 11, 5);
435 /* Vector shift count */
436 EXTRACT_HELPER(VSH, 6, 4);
437 /* Mask start */
438 EXTRACT_HELPER(MB, 6, 5);
439 /* Mask end */
440 EXTRACT_HELPER(ME, 1, 5);
441 /* Trap operand */
442 EXTRACT_HELPER(TO, 21, 5);
443
444 EXTRACT_HELPER(CRM, 12, 8);
445
446 #ifndef CONFIG_USER_ONLY
447 EXTRACT_HELPER(SR, 16, 4);
448 #endif
449
450 /* mtfsf/mtfsfi */
451 EXTRACT_HELPER(FPBF, 23, 3);
452 EXTRACT_HELPER(FPIMM, 12, 4);
453 EXTRACT_HELPER(FPL, 25, 1);
454 EXTRACT_HELPER(FPFLM, 17, 8);
455 EXTRACT_HELPER(FPW, 16, 1);
456
457 /*** Jump target decoding ***/
458 /* Immediate address */
459 static inline target_ulong LI(uint32_t opcode)
460 {
461 return (opcode >> 0) & 0x03FFFFFC;
462 }
463
464 static inline uint32_t BD(uint32_t opcode)
465 {
466 return (opcode >> 0) & 0xFFFC;
467 }
468
469 EXTRACT_HELPER(BO, 21, 5);
470 EXTRACT_HELPER(BI, 16, 5);
471 /* Absolute/relative address */
472 EXTRACT_HELPER(AA, 1, 1);
473 /* Link */
474 EXTRACT_HELPER(LK, 0, 1);
475
476 /* DFP Z22-form */
477 EXTRACT_HELPER(DCM, 10, 6)
478
479 /* DFP Z23-form */
480 EXTRACT_HELPER(RMC, 9, 2)
481
482 /* Create a mask between <start> and <end> bits */
483 static inline target_ulong MASK(uint32_t start, uint32_t end)
484 {
485 target_ulong ret;
486
487 #if defined(TARGET_PPC64)
488 if (likely(start == 0)) {
489 ret = UINT64_MAX << (63 - end);
490 } else if (likely(end == 63)) {
491 ret = UINT64_MAX >> start;
492 }
493 #else
494 if (likely(start == 0)) {
495 ret = UINT32_MAX << (31 - end);
496 } else if (likely(end == 31)) {
497 ret = UINT32_MAX >> start;
498 }
499 #endif
500 else {
501 ret = (((target_ulong)(-1ULL)) >> (start)) ^
502 (((target_ulong)(-1ULL) >> (end)) >> 1);
503 if (unlikely(start > end))
504 return ~ret;
505 }
506
507 return ret;
508 }
509
510 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
511 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
513 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
514 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
515 EXTRACT_HELPER(DM, 8, 2);
516 EXTRACT_HELPER(UIM, 16, 2);
517 EXTRACT_HELPER(SHW, 8, 2);
518 EXTRACT_HELPER(SP, 19, 2);
519 /*****************************************************************************/
520 /* PowerPC instructions table */
521
522 #if defined(DO_PPC_STATISTICS)
523 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl, \
531 .type = _typ, \
532 .type2 = _typ2, \
533 .handler = &gen_##name, \
534 .oname = stringify(name), \
535 }, \
536 .oname = stringify(name), \
537 }
538 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
539 { \
540 .opc1 = op1, \
541 .opc2 = op2, \
542 .opc3 = op3, \
543 .pad = { 0, }, \
544 .handler = { \
545 .inval1 = invl1, \
546 .inval2 = invl2, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = stringify(name), \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 .oname = onam, \
566 }, \
567 .oname = onam, \
568 }
569 #else
570 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl1, \
592 .inval2 = invl2, \
593 .type = _typ, \
594 .type2 = _typ2, \
595 .handler = &gen_##name, \
596 }, \
597 .oname = stringify(name), \
598 }
599 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
600 { \
601 .opc1 = op1, \
602 .opc2 = op2, \
603 .opc3 = op3, \
604 .pad = { 0, }, \
605 .handler = { \
606 .inval1 = invl, \
607 .type = _typ, \
608 .type2 = _typ2, \
609 .handler = &gen_##name, \
610 }, \
611 .oname = onam, \
612 }
613 #endif
614
615 /* SPR load/store helpers */
616 static inline void gen_load_spr(TCGv t, int reg)
617 {
618 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
619 }
620
621 static inline void gen_store_spr(int reg, TCGv t)
622 {
623 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
624 }
625
626 /* Invalid instruction */
627 static void gen_invalid(DisasContext *ctx)
628 {
629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
630 }
631
632 static opc_handler_t invalid_handler = {
633 .inval1 = 0xFFFFFFFF,
634 .inval2 = 0xFFFFFFFF,
635 .type = PPC_NONE,
636 .type2 = PPC_NONE,
637 .handler = gen_invalid,
638 };
639
640 /*** Integer comparison ***/
641
642 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
643 {
644 TCGv t0 = tcg_temp_new();
645 TCGv_i32 t1 = tcg_temp_new_i32();
646
647 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
648
649 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
650 tcg_gen_trunc_tl_i32(t1, t0);
651 tcg_gen_shli_i32(t1, t1, CRF_LT);
652 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
653
654 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
655 tcg_gen_trunc_tl_i32(t1, t0);
656 tcg_gen_shli_i32(t1, t1, CRF_GT);
657 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
658
659 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
660 tcg_gen_trunc_tl_i32(t1, t0);
661 tcg_gen_shli_i32(t1, t1, CRF_EQ);
662 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
663
664 tcg_temp_free(t0);
665 tcg_temp_free_i32(t1);
666 }
667
668 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
669 {
670 TCGv t0 = tcg_const_tl(arg1);
671 gen_op_cmp(arg0, t0, s, crf);
672 tcg_temp_free(t0);
673 }
674
675 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
676 {
677 TCGv t0, t1;
678 t0 = tcg_temp_new();
679 t1 = tcg_temp_new();
680 if (s) {
681 tcg_gen_ext32s_tl(t0, arg0);
682 tcg_gen_ext32s_tl(t1, arg1);
683 } else {
684 tcg_gen_ext32u_tl(t0, arg0);
685 tcg_gen_ext32u_tl(t1, arg1);
686 }
687 gen_op_cmp(t0, t1, s, crf);
688 tcg_temp_free(t1);
689 tcg_temp_free(t0);
690 }
691
692 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
693 {
694 TCGv t0 = tcg_const_tl(arg1);
695 gen_op_cmp32(arg0, t0, s, crf);
696 tcg_temp_free(t0);
697 }
698
699 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
700 {
701 if (NARROW_MODE(ctx)) {
702 gen_op_cmpi32(reg, 0, 1, 0);
703 } else {
704 gen_op_cmpi(reg, 0, 1, 0);
705 }
706 }
707
708 /* cmp */
709 static void gen_cmp(DisasContext *ctx)
710 {
711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
712 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
714 } else {
715 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
716 1, crfD(ctx->opcode));
717 }
718 }
719
720 /* cmpi */
721 static void gen_cmpi(DisasContext *ctx)
722 {
723 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
724 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
726 } else {
727 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
728 1, crfD(ctx->opcode));
729 }
730 }
731
732 /* cmpl */
733 static void gen_cmpl(DisasContext *ctx)
734 {
735 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
736 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
738 } else {
739 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
740 0, crfD(ctx->opcode));
741 }
742 }
743
744 /* cmpli */
745 static void gen_cmpli(DisasContext *ctx)
746 {
747 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
748 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
750 } else {
751 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
752 0, crfD(ctx->opcode));
753 }
754 }
755
756 /* isel (PowerPC 2.03 specification) */
757 static void gen_isel(DisasContext *ctx)
758 {
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask = 0x08 >> (bi & 0x03);
761 TCGv t0 = tcg_temp_new();
762 TCGv zr;
763
764 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
765 tcg_gen_andi_tl(t0, t0, mask);
766
767 zr = tcg_const_tl(0);
768 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
769 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
770 cpu_gpr[rB(ctx->opcode)]);
771 tcg_temp_free(zr);
772 tcg_temp_free(t0);
773 }
774
775 /* cmpb: PowerPC 2.05 specification */
776 static void gen_cmpb(DisasContext *ctx)
777 {
778 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
779 cpu_gpr[rB(ctx->opcode)]);
780 }
781
782 /*** Integer arithmetic ***/
783
784 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
785 TCGv arg1, TCGv arg2, int sub)
786 {
787 TCGv t0 = tcg_temp_new();
788
789 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
790 tcg_gen_xor_tl(t0, arg1, arg2);
791 if (sub) {
792 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
793 } else {
794 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
795 }
796 tcg_temp_free(t0);
797 if (NARROW_MODE(ctx)) {
798 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
799 }
800 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
801 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
802 }
803
804 /* Common add function */
805 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
806 TCGv arg2, bool add_ca, bool compute_ca,
807 bool compute_ov, bool compute_rc0)
808 {
809 TCGv t0 = ret;
810
811 if (compute_ca || compute_ov) {
812 t0 = tcg_temp_new();
813 }
814
815 if (compute_ca) {
816 if (NARROW_MODE(ctx)) {
817 /* Caution: a non-obvious corner case of the spec is that we
818 must produce the *entire* 64-bit addition, but produce the
819 carry into bit 32. */
820 TCGv t1 = tcg_temp_new();
821 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
822 tcg_gen_add_tl(t0, arg1, arg2);
823 if (add_ca) {
824 tcg_gen_add_tl(t0, t0, cpu_ca);
825 }
826 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
827 tcg_temp_free(t1);
828 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
829 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
830 } else {
831 TCGv zero = tcg_const_tl(0);
832 if (add_ca) {
833 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
834 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
835 } else {
836 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
837 }
838 tcg_temp_free(zero);
839 }
840 } else {
841 tcg_gen_add_tl(t0, arg1, arg2);
842 if (add_ca) {
843 tcg_gen_add_tl(t0, t0, cpu_ca);
844 }
845 }
846
847 if (compute_ov) {
848 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
849 }
850 if (unlikely(compute_rc0)) {
851 gen_set_Rc0(ctx, t0);
852 }
853
854 if (!TCGV_EQUAL(t0, ret)) {
855 tcg_gen_mov_tl(ret, t0);
856 tcg_temp_free(t0);
857 }
858 }
859 /* Add functions with two operands */
860 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
861 static void glue(gen_, name)(DisasContext *ctx) \
862 { \
863 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
864 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
865 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
866 }
867 /* Add functions with one operand and one immediate */
868 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
869 add_ca, compute_ca, compute_ov) \
870 static void glue(gen_, name)(DisasContext *ctx) \
871 { \
872 TCGv t0 = tcg_const_tl(const_val); \
873 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
874 cpu_gpr[rA(ctx->opcode)], t0, \
875 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
876 tcg_temp_free(t0); \
877 }
878
879 /* add add. addo addo. */
880 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
881 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
882 /* addc addc. addco addco. */
883 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
884 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
885 /* adde adde. addeo addeo. */
886 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
887 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
888 /* addme addme. addmeo addmeo. */
889 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
890 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
891 /* addze addze. addzeo addzeo.*/
892 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
893 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
894 /* addi */
895 static void gen_addi(DisasContext *ctx)
896 {
897 target_long simm = SIMM(ctx->opcode);
898
899 if (rA(ctx->opcode) == 0) {
900 /* li case */
901 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
902 } else {
903 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
904 cpu_gpr[rA(ctx->opcode)], simm);
905 }
906 }
907 /* addic addic.*/
908 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
909 {
910 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
911 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
912 c, 0, 1, 0, compute_rc0);
913 tcg_temp_free(c);
914 }
915
916 static void gen_addic(DisasContext *ctx)
917 {
918 gen_op_addic(ctx, 0);
919 }
920
921 static void gen_addic_(DisasContext *ctx)
922 {
923 gen_op_addic(ctx, 1);
924 }
925
926 /* addis */
927 static void gen_addis(DisasContext *ctx)
928 {
929 target_long simm = SIMM(ctx->opcode);
930
931 if (rA(ctx->opcode) == 0) {
932 /* lis case */
933 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
934 } else {
935 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
936 cpu_gpr[rA(ctx->opcode)], simm << 16);
937 }
938 }
939
940 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
941 TCGv arg2, int sign, int compute_ov)
942 {
943 TCGLabel *l1 = gen_new_label();
944 TCGLabel *l2 = gen_new_label();
945 TCGv_i32 t0 = tcg_temp_local_new_i32();
946 TCGv_i32 t1 = tcg_temp_local_new_i32();
947
948 tcg_gen_trunc_tl_i32(t0, arg1);
949 tcg_gen_trunc_tl_i32(t1, arg2);
950 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
951 if (sign) {
952 TCGLabel *l3 = gen_new_label();
953 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
954 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
955 gen_set_label(l3);
956 tcg_gen_div_i32(t0, t0, t1);
957 } else {
958 tcg_gen_divu_i32(t0, t0, t1);
959 }
960 if (compute_ov) {
961 tcg_gen_movi_tl(cpu_ov, 0);
962 }
963 tcg_gen_br(l2);
964 gen_set_label(l1);
965 if (sign) {
966 tcg_gen_sari_i32(t0, t0, 31);
967 } else {
968 tcg_gen_movi_i32(t0, 0);
969 }
970 if (compute_ov) {
971 tcg_gen_movi_tl(cpu_ov, 1);
972 tcg_gen_movi_tl(cpu_so, 1);
973 }
974 gen_set_label(l2);
975 tcg_gen_extu_i32_tl(ret, t0);
976 tcg_temp_free_i32(t0);
977 tcg_temp_free_i32(t1);
978 if (unlikely(Rc(ctx->opcode) != 0))
979 gen_set_Rc0(ctx, ret);
980 }
981 /* Div functions */
982 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
983 static void glue(gen_, name)(DisasContext *ctx) \
984 { \
985 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
986 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
987 sign, compute_ov); \
988 }
989 /* divwu divwu. divwuo divwuo. */
990 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
991 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
992 /* divw divw. divwo divwo. */
993 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
994 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
995
996 /* div[wd]eu[o][.] */
997 #define GEN_DIVE(name, hlpr, compute_ov) \
998 static void gen_##name(DisasContext *ctx) \
999 { \
1000 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1001 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1002 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1003 tcg_temp_free_i32(t0); \
1004 if (unlikely(Rc(ctx->opcode) != 0)) { \
1005 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1006 } \
1007 }
1008
1009 GEN_DIVE(divweu, divweu, 0);
1010 GEN_DIVE(divweuo, divweu, 1);
1011 GEN_DIVE(divwe, divwe, 0);
1012 GEN_DIVE(divweo, divwe, 1);
1013
1014 #if defined(TARGET_PPC64)
1015 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1016 TCGv arg2, int sign, int compute_ov)
1017 {
1018 TCGLabel *l1 = gen_new_label();
1019 TCGLabel *l2 = gen_new_label();
1020
1021 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1022 if (sign) {
1023 TCGLabel *l3 = gen_new_label();
1024 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1026 gen_set_label(l3);
1027 tcg_gen_div_i64(ret, arg1, arg2);
1028 } else {
1029 tcg_gen_divu_i64(ret, arg1, arg2);
1030 }
1031 if (compute_ov) {
1032 tcg_gen_movi_tl(cpu_ov, 0);
1033 }
1034 tcg_gen_br(l2);
1035 gen_set_label(l1);
1036 if (sign) {
1037 tcg_gen_sari_i64(ret, arg1, 63);
1038 } else {
1039 tcg_gen_movi_i64(ret, 0);
1040 }
1041 if (compute_ov) {
1042 tcg_gen_movi_tl(cpu_ov, 1);
1043 tcg_gen_movi_tl(cpu_so, 1);
1044 }
1045 gen_set_label(l2);
1046 if (unlikely(Rc(ctx->opcode) != 0))
1047 gen_set_Rc0(ctx, ret);
1048 }
1049 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1050 static void glue(gen_, name)(DisasContext *ctx) \
1051 { \
1052 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1053 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1054 sign, compute_ov); \
1055 }
1056 /* divwu divwu. divwuo divwuo. */
1057 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1058 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1059 /* divw divw. divwo divwo. */
1060 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1061 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1062
1063 GEN_DIVE(divdeu, divdeu, 0);
1064 GEN_DIVE(divdeuo, divdeu, 1);
1065 GEN_DIVE(divde, divde, 0);
1066 GEN_DIVE(divdeo, divde, 1);
1067 #endif
1068
1069 /* mulhw mulhw. */
1070 static void gen_mulhw(DisasContext *ctx)
1071 {
1072 TCGv_i32 t0 = tcg_temp_new_i32();
1073 TCGv_i32 t1 = tcg_temp_new_i32();
1074
1075 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1076 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1077 tcg_gen_muls2_i32(t0, t1, t0, t1);
1078 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1079 tcg_temp_free_i32(t0);
1080 tcg_temp_free_i32(t1);
1081 if (unlikely(Rc(ctx->opcode) != 0))
1082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1083 }
1084
1085 /* mulhwu mulhwu. */
1086 static void gen_mulhwu(DisasContext *ctx)
1087 {
1088 TCGv_i32 t0 = tcg_temp_new_i32();
1089 TCGv_i32 t1 = tcg_temp_new_i32();
1090
1091 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1092 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1093 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1094 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1095 tcg_temp_free_i32(t0);
1096 tcg_temp_free_i32(t1);
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1099 }
1100
1101 /* mullw mullw. */
1102 static void gen_mullw(DisasContext *ctx)
1103 {
1104 #if defined(TARGET_PPC64)
1105 TCGv_i64 t0, t1;
1106 t0 = tcg_temp_new_i64();
1107 t1 = tcg_temp_new_i64();
1108 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1109 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1110 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1111 tcg_temp_free(t0);
1112 tcg_temp_free(t1);
1113 #else
1114 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 #endif
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119 }
1120
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext *ctx)
1123 {
1124 TCGv_i32 t0 = tcg_temp_new_i32();
1125 TCGv_i32 t1 = tcg_temp_new_i32();
1126
1127 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1128 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1129 tcg_gen_muls2_i32(t0, t1, t0, t1);
1130 #if defined(TARGET_PPC64)
1131 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1132 #else
1133 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1134 #endif
1135
1136 tcg_gen_sari_i32(t0, t0, 31);
1137 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1138 tcg_gen_extu_i32_tl(cpu_ov, t0);
1139 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1140
1141 tcg_temp_free_i32(t0);
1142 tcg_temp_free_i32(t1);
1143 if (unlikely(Rc(ctx->opcode) != 0))
1144 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1145 }
1146
1147 /* mulli */
1148 static void gen_mulli(DisasContext *ctx)
1149 {
1150 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1151 SIMM(ctx->opcode));
1152 }
1153
1154 #if defined(TARGET_PPC64)
1155 /* mulhd mulhd. */
1156 static void gen_mulhd(DisasContext *ctx)
1157 {
1158 TCGv lo = tcg_temp_new();
1159 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1161 tcg_temp_free(lo);
1162 if (unlikely(Rc(ctx->opcode) != 0)) {
1163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1164 }
1165 }
1166
1167 /* mulhdu mulhdu. */
1168 static void gen_mulhdu(DisasContext *ctx)
1169 {
1170 TCGv lo = tcg_temp_new();
1171 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1173 tcg_temp_free(lo);
1174 if (unlikely(Rc(ctx->opcode) != 0)) {
1175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1176 }
1177 }
1178
1179 /* mulld mulld. */
1180 static void gen_mulld(DisasContext *ctx)
1181 {
1182 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1183 cpu_gpr[rB(ctx->opcode)]);
1184 if (unlikely(Rc(ctx->opcode) != 0))
1185 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1186 }
1187
1188 /* mulldo mulldo. */
1189 static void gen_mulldo(DisasContext *ctx)
1190 {
1191 TCGv_i64 t0 = tcg_temp_new_i64();
1192 TCGv_i64 t1 = tcg_temp_new_i64();
1193
1194 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1195 cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1197
1198 tcg_gen_sari_i64(t0, t0, 63);
1199 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1200 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1201
1202 tcg_temp_free_i64(t0);
1203 tcg_temp_free_i64(t1);
1204
1205 if (unlikely(Rc(ctx->opcode) != 0)) {
1206 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1207 }
1208 }
1209 #endif
1210
1211 /* Common subf function */
1212 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1213 TCGv arg2, bool add_ca, bool compute_ca,
1214 bool compute_ov, bool compute_rc0)
1215 {
1216 TCGv t0 = ret;
1217
1218 if (compute_ca || compute_ov) {
1219 t0 = tcg_temp_new();
1220 }
1221
1222 if (compute_ca) {
1223 /* dest = ~arg1 + arg2 [+ ca]. */
1224 if (NARROW_MODE(ctx)) {
1225 /* Caution: a non-obvious corner case of the spec is that we
1226 must produce the *entire* 64-bit addition, but produce the
1227 carry into bit 32. */
1228 TCGv inv1 = tcg_temp_new();
1229 TCGv t1 = tcg_temp_new();
1230 tcg_gen_not_tl(inv1, arg1);
1231 if (add_ca) {
1232 tcg_gen_add_tl(t0, arg2, cpu_ca);
1233 } else {
1234 tcg_gen_addi_tl(t0, arg2, 1);
1235 }
1236 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1237 tcg_gen_add_tl(t0, t0, inv1);
1238 tcg_temp_free(inv1);
1239 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1240 tcg_temp_free(t1);
1241 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1242 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1243 } else if (add_ca) {
1244 TCGv zero, inv1 = tcg_temp_new();
1245 tcg_gen_not_tl(inv1, arg1);
1246 zero = tcg_const_tl(0);
1247 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1248 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1249 tcg_temp_free(zero);
1250 tcg_temp_free(inv1);
1251 } else {
1252 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1253 tcg_gen_sub_tl(t0, arg2, arg1);
1254 }
1255 } else if (add_ca) {
1256 /* Since we're ignoring carry-out, we can simplify the
1257 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1258 tcg_gen_sub_tl(t0, arg2, arg1);
1259 tcg_gen_add_tl(t0, t0, cpu_ca);
1260 tcg_gen_subi_tl(t0, t0, 1);
1261 } else {
1262 tcg_gen_sub_tl(t0, arg2, arg1);
1263 }
1264
1265 if (compute_ov) {
1266 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1267 }
1268 if (unlikely(compute_rc0)) {
1269 gen_set_Rc0(ctx, t0);
1270 }
1271
1272 if (!TCGV_EQUAL(t0, ret)) {
1273 tcg_gen_mov_tl(ret, t0);
1274 tcg_temp_free(t0);
1275 }
1276 }
1277 /* Sub functions with Two operands functions */
1278 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1279 static void glue(gen_, name)(DisasContext *ctx) \
1280 { \
1281 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1282 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1283 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1284 }
1285 /* Sub functions with one operand and one immediate */
1286 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1287 add_ca, compute_ca, compute_ov) \
1288 static void glue(gen_, name)(DisasContext *ctx) \
1289 { \
1290 TCGv t0 = tcg_const_tl(const_val); \
1291 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1292 cpu_gpr[rA(ctx->opcode)], t0, \
1293 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1294 tcg_temp_free(t0); \
1295 }
1296 /* subf subf. subfo subfo. */
1297 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1298 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1299 /* subfc subfc. subfco subfco. */
1300 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1301 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1302 /* subfe subfe. subfeo subfo. */
1303 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1304 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1305 /* subfme subfme. subfmeo subfmeo. */
1306 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1307 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1308 /* subfze subfze. subfzeo subfzeo.*/
1309 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1310 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1311
1312 /* subfic */
1313 static void gen_subfic(DisasContext *ctx)
1314 {
1315 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1316 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1317 c, 0, 1, 0, 0);
1318 tcg_temp_free(c);
1319 }
1320
1321 /* neg neg. nego nego. */
1322 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1323 {
1324 TCGv zero = tcg_const_tl(0);
1325 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1326 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1327 tcg_temp_free(zero);
1328 }
1329
1330 static void gen_neg(DisasContext *ctx)
1331 {
1332 gen_op_arith_neg(ctx, 0);
1333 }
1334
1335 static void gen_nego(DisasContext *ctx)
1336 {
1337 gen_op_arith_neg(ctx, 1);
1338 }
1339
1340 /*** Integer logical ***/
1341 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1342 static void glue(gen_, name)(DisasContext *ctx) \
1343 { \
1344 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1345 cpu_gpr[rB(ctx->opcode)]); \
1346 if (unlikely(Rc(ctx->opcode) != 0)) \
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1348 }
1349
1350 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1351 static void glue(gen_, name)(DisasContext *ctx) \
1352 { \
1353 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1354 if (unlikely(Rc(ctx->opcode) != 0)) \
1355 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1356 }
1357
1358 /* and & and. */
1359 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1360 /* andc & andc. */
1361 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1362
1363 /* andi. */
1364 static void gen_andi_(DisasContext *ctx)
1365 {
1366 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1367 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1368 }
1369
1370 /* andis. */
1371 static void gen_andis_(DisasContext *ctx)
1372 {
1373 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1375 }
1376
1377 /* cntlzw */
1378 static void gen_cntlzw(DisasContext *ctx)
1379 {
1380 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1381 if (unlikely(Rc(ctx->opcode) != 0))
1382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1383 }
1384 /* eqv & eqv. */
1385 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1386 /* extsb & extsb. */
1387 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1388 /* extsh & extsh. */
1389 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1390 /* nand & nand. */
1391 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1392 /* nor & nor. */
1393 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1394
1395 /* or & or. */
1396 static void gen_or(DisasContext *ctx)
1397 {
1398 int rs, ra, rb;
1399
1400 rs = rS(ctx->opcode);
1401 ra = rA(ctx->opcode);
1402 rb = rB(ctx->opcode);
1403 /* Optimisation for mr. ri case */
1404 if (rs != ra || rs != rb) {
1405 if (rs != rb)
1406 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1407 else
1408 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1409 if (unlikely(Rc(ctx->opcode) != 0))
1410 gen_set_Rc0(ctx, cpu_gpr[ra]);
1411 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1412 gen_set_Rc0(ctx, cpu_gpr[rs]);
1413 #if defined(TARGET_PPC64)
1414 } else {
1415 int prio = 0;
1416
1417 switch (rs) {
1418 case 1:
1419 /* Set process priority to low */
1420 prio = 2;
1421 break;
1422 case 6:
1423 /* Set process priority to medium-low */
1424 prio = 3;
1425 break;
1426 case 2:
1427 /* Set process priority to normal */
1428 prio = 4;
1429 break;
1430 #if !defined(CONFIG_USER_ONLY)
1431 case 31:
1432 if (!ctx->pr) {
1433 /* Set process priority to very low */
1434 prio = 1;
1435 }
1436 break;
1437 case 5:
1438 if (!ctx->pr) {
1439 /* Set process priority to medium-hight */
1440 prio = 5;
1441 }
1442 break;
1443 case 3:
1444 if (!ctx->pr) {
1445 /* Set process priority to high */
1446 prio = 6;
1447 }
1448 break;
1449 case 7:
1450 if (ctx->hv) {
1451 /* Set process priority to very high */
1452 prio = 7;
1453 }
1454 break;
1455 #endif
1456 default:
1457 /* nop */
1458 break;
1459 }
1460 if (prio) {
1461 TCGv t0 = tcg_temp_new();
1462 gen_load_spr(t0, SPR_PPR);
1463 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1464 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1465 gen_store_spr(SPR_PPR, t0);
1466 tcg_temp_free(t0);
1467 }
1468 #endif
1469 }
1470 }
1471 /* orc & orc. */
1472 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1473
1474 /* xor & xor. */
1475 static void gen_xor(DisasContext *ctx)
1476 {
1477 /* Optimisation for "set to zero" case */
1478 if (rS(ctx->opcode) != rB(ctx->opcode))
1479 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1480 else
1481 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1482 if (unlikely(Rc(ctx->opcode) != 0))
1483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1484 }
1485
1486 /* ori */
1487 static void gen_ori(DisasContext *ctx)
1488 {
1489 target_ulong uimm = UIMM(ctx->opcode);
1490
1491 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1492 /* NOP */
1493 /* XXX: should handle special NOPs for POWER series */
1494 return;
1495 }
1496 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1497 }
1498
1499 /* oris */
1500 static void gen_oris(DisasContext *ctx)
1501 {
1502 target_ulong uimm = UIMM(ctx->opcode);
1503
1504 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1505 /* NOP */
1506 return;
1507 }
1508 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1509 }
1510
1511 /* xori */
1512 static void gen_xori(DisasContext *ctx)
1513 {
1514 target_ulong uimm = UIMM(ctx->opcode);
1515
1516 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1517 /* NOP */
1518 return;
1519 }
1520 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1521 }
1522
1523 /* xoris */
1524 static void gen_xoris(DisasContext *ctx)
1525 {
1526 target_ulong uimm = UIMM(ctx->opcode);
1527
1528 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1529 /* NOP */
1530 return;
1531 }
1532 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1533 }
1534
1535 /* popcntb : PowerPC 2.03 specification */
1536 static void gen_popcntb(DisasContext *ctx)
1537 {
1538 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1539 }
1540
1541 static void gen_popcntw(DisasContext *ctx)
1542 {
1543 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1544 }
1545
1546 #if defined(TARGET_PPC64)
1547 /* popcntd: PowerPC 2.06 specification */
1548 static void gen_popcntd(DisasContext *ctx)
1549 {
1550 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1551 }
1552 #endif
1553
1554 /* prtyw: PowerPC 2.05 specification */
1555 static void gen_prtyw(DisasContext *ctx)
1556 {
1557 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1558 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1559 TCGv t0 = tcg_temp_new();
1560 tcg_gen_shri_tl(t0, rs, 16);
1561 tcg_gen_xor_tl(ra, rs, t0);
1562 tcg_gen_shri_tl(t0, ra, 8);
1563 tcg_gen_xor_tl(ra, ra, t0);
1564 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1565 tcg_temp_free(t0);
1566 }
1567
1568 #if defined(TARGET_PPC64)
1569 /* prtyd: PowerPC 2.05 specification */
1570 static void gen_prtyd(DisasContext *ctx)
1571 {
1572 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1573 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1574 TCGv t0 = tcg_temp_new();
1575 tcg_gen_shri_tl(t0, rs, 32);
1576 tcg_gen_xor_tl(ra, rs, t0);
1577 tcg_gen_shri_tl(t0, ra, 16);
1578 tcg_gen_xor_tl(ra, ra, t0);
1579 tcg_gen_shri_tl(t0, ra, 8);
1580 tcg_gen_xor_tl(ra, ra, t0);
1581 tcg_gen_andi_tl(ra, ra, 1);
1582 tcg_temp_free(t0);
1583 }
1584 #endif
1585
1586 #if defined(TARGET_PPC64)
1587 /* bpermd */
1588 static void gen_bpermd(DisasContext *ctx)
1589 {
1590 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1591 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1592 }
1593 #endif
1594
1595 #if defined(TARGET_PPC64)
1596 /* extsw & extsw. */
1597 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1598
1599 /* cntlzd */
1600 static void gen_cntlzd(DisasContext *ctx)
1601 {
1602 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1603 if (unlikely(Rc(ctx->opcode) != 0))
1604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1605 }
1606 #endif
1607
1608 /*** Integer rotate ***/
1609
1610 /* rlwimi & rlwimi. */
1611 static void gen_rlwimi(DisasContext *ctx)
1612 {
1613 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1614 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1615 uint32_t sh = SH(ctx->opcode);
1616 uint32_t mb = MB(ctx->opcode);
1617 uint32_t me = ME(ctx->opcode);
1618
1619 if (sh == (31-me) && mb <= me) {
1620 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1621 } else {
1622 target_ulong mask;
1623 TCGv_i32 t0;
1624 TCGv t1;
1625
1626 #if defined(TARGET_PPC64)
1627 mb += 32;
1628 me += 32;
1629 #endif
1630 mask = MASK(mb, me);
1631
1632 t0 = tcg_temp_new_i32();
1633 t1 = tcg_temp_new();
1634 tcg_gen_trunc_tl_i32(t0, t_rs);
1635 tcg_gen_rotli_i32(t0, t0, sh);
1636 tcg_gen_extu_i32_tl(t1, t0);
1637 tcg_temp_free_i32(t0);
1638
1639 tcg_gen_andi_tl(t1, t1, mask);
1640 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1641 tcg_gen_or_tl(t_ra, t_ra, t1);
1642 tcg_temp_free(t1);
1643 }
1644 if (unlikely(Rc(ctx->opcode) != 0)) {
1645 gen_set_Rc0(ctx, t_ra);
1646 }
1647 }
1648
1649 /* rlwinm & rlwinm. */
1650 static void gen_rlwinm(DisasContext *ctx)
1651 {
1652 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1653 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1654 uint32_t sh = SH(ctx->opcode);
1655 uint32_t mb = MB(ctx->opcode);
1656 uint32_t me = ME(ctx->opcode);
1657
1658 if (mb == 0 && me == (31 - sh)) {
1659 tcg_gen_shli_tl(t_ra, t_rs, sh);
1660 tcg_gen_ext32u_tl(t_ra, t_ra);
1661 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1662 tcg_gen_ext32u_tl(t_ra, t_rs);
1663 tcg_gen_shri_tl(t_ra, t_ra, mb);
1664 } else {
1665 #if defined(TARGET_PPC64)
1666 mb += 32;
1667 me += 32;
1668 #endif
1669 if (sh == 0) {
1670 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1671 } else {
1672 TCGv_i32 t0 = tcg_temp_new_i32();
1673
1674 tcg_gen_trunc_tl_i32(t0, t_rs);
1675 tcg_gen_rotli_i32(t0, t0, sh);
1676 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1677 tcg_gen_extu_i32_tl(t_ra, t0);
1678 tcg_temp_free_i32(t0);
1679 }
1680 }
1681 if (unlikely(Rc(ctx->opcode) != 0)) {
1682 gen_set_Rc0(ctx, t_ra);
1683 }
1684 }
1685
1686 /* rlwnm & rlwnm. */
1687 static void gen_rlwnm(DisasContext *ctx)
1688 {
1689 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1690 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1691 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1692 uint32_t mb = MB(ctx->opcode);
1693 uint32_t me = ME(ctx->opcode);
1694 TCGv_i32 t0, t1;
1695
1696 #if defined(TARGET_PPC64)
1697 mb += 32;
1698 me += 32;
1699 #endif
1700
1701 t0 = tcg_temp_new_i32();
1702 t1 = tcg_temp_new_i32();
1703 tcg_gen_trunc_tl_i32(t0, t_rb);
1704 tcg_gen_trunc_tl_i32(t1, t_rs);
1705 tcg_gen_andi_i32(t0, t0, 0x1f);
1706 tcg_gen_rotl_i32(t1, t1, t0);
1707 tcg_temp_free_i32(t0);
1708
1709 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1710 tcg_gen_extu_i32_tl(t_ra, t1);
1711 tcg_temp_free_i32(t1);
1712
1713 if (unlikely(Rc(ctx->opcode) != 0)) {
1714 gen_set_Rc0(ctx, t_ra);
1715 }
1716 }
1717
1718 #if defined(TARGET_PPC64)
1719 #define GEN_PPC64_R2(name, opc1, opc2) \
1720 static void glue(gen_, name##0)(DisasContext *ctx) \
1721 { \
1722 gen_##name(ctx, 0); \
1723 } \
1724 \
1725 static void glue(gen_, name##1)(DisasContext *ctx) \
1726 { \
1727 gen_##name(ctx, 1); \
1728 }
1729 #define GEN_PPC64_R4(name, opc1, opc2) \
1730 static void glue(gen_, name##0)(DisasContext *ctx) \
1731 { \
1732 gen_##name(ctx, 0, 0); \
1733 } \
1734 \
1735 static void glue(gen_, name##1)(DisasContext *ctx) \
1736 { \
1737 gen_##name(ctx, 0, 1); \
1738 } \
1739 \
1740 static void glue(gen_, name##2)(DisasContext *ctx) \
1741 { \
1742 gen_##name(ctx, 1, 0); \
1743 } \
1744 \
1745 static void glue(gen_, name##3)(DisasContext *ctx) \
1746 { \
1747 gen_##name(ctx, 1, 1); \
1748 }
1749
1750 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1751 uint32_t sh)
1752 {
1753 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1754 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1755 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1756 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1757 } else {
1758 TCGv t0 = tcg_temp_new();
1759 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1760 if (likely(mb == 0 && me == 63)) {
1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1762 } else {
1763 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1764 }
1765 tcg_temp_free(t0);
1766 }
1767 if (unlikely(Rc(ctx->opcode) != 0))
1768 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1769 }
1770 /* rldicl - rldicl. */
1771 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1772 {
1773 uint32_t sh, mb;
1774
1775 sh = SH(ctx->opcode) | (shn << 5);
1776 mb = MB(ctx->opcode) | (mbn << 5);
1777 gen_rldinm(ctx, mb, 63, sh);
1778 }
1779 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1780 /* rldicr - rldicr. */
1781 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1782 {
1783 uint32_t sh, me;
1784
1785 sh = SH(ctx->opcode) | (shn << 5);
1786 me = MB(ctx->opcode) | (men << 5);
1787 gen_rldinm(ctx, 0, me, sh);
1788 }
1789 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1790 /* rldic - rldic. */
1791 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1792 {
1793 uint32_t sh, mb;
1794
1795 sh = SH(ctx->opcode) | (shn << 5);
1796 mb = MB(ctx->opcode) | (mbn << 5);
1797 gen_rldinm(ctx, mb, 63 - sh, sh);
1798 }
1799 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1800
1801 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1802 {
1803 TCGv t0;
1804
1805 t0 = tcg_temp_new();
1806 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1807 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1808 if (unlikely(mb != 0 || me != 63)) {
1809 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1810 } else {
1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1812 }
1813 tcg_temp_free(t0);
1814 if (unlikely(Rc(ctx->opcode) != 0))
1815 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1816 }
1817
1818 /* rldcl - rldcl. */
1819 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1820 {
1821 uint32_t mb;
1822
1823 mb = MB(ctx->opcode) | (mbn << 5);
1824 gen_rldnm(ctx, mb, 63);
1825 }
1826 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1827 /* rldcr - rldcr. */
1828 static inline void gen_rldcr(DisasContext *ctx, int men)
1829 {
1830 uint32_t me;
1831
1832 me = MB(ctx->opcode) | (men << 5);
1833 gen_rldnm(ctx, 0, me);
1834 }
1835 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1836 /* rldimi - rldimi. */
1837 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1838 {
1839 uint32_t sh, mb, me;
1840
1841 sh = SH(ctx->opcode) | (shn << 5);
1842 mb = MB(ctx->opcode) | (mbn << 5);
1843 me = 63 - sh;
1844 if (unlikely(sh == 0 && mb == 0)) {
1845 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1846 } else {
1847 TCGv t0, t1;
1848 target_ulong mask;
1849
1850 t0 = tcg_temp_new();
1851 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1852 t1 = tcg_temp_new();
1853 mask = MASK(mb, me);
1854 tcg_gen_andi_tl(t0, t0, mask);
1855 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1856 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1857 tcg_temp_free(t0);
1858 tcg_temp_free(t1);
1859 }
1860 if (unlikely(Rc(ctx->opcode) != 0))
1861 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1862 }
1863 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1864 #endif
1865
1866 /*** Integer shift ***/
1867
1868 /* slw & slw. */
1869 static void gen_slw(DisasContext *ctx)
1870 {
1871 TCGv t0, t1;
1872
1873 t0 = tcg_temp_new();
1874 /* AND rS with a mask that is 0 when rB >= 0x20 */
1875 #if defined(TARGET_PPC64)
1876 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1877 tcg_gen_sari_tl(t0, t0, 0x3f);
1878 #else
1879 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1880 tcg_gen_sari_tl(t0, t0, 0x1f);
1881 #endif
1882 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1883 t1 = tcg_temp_new();
1884 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1885 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1886 tcg_temp_free(t1);
1887 tcg_temp_free(t0);
1888 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1889 if (unlikely(Rc(ctx->opcode) != 0))
1890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1891 }
1892
1893 /* sraw & sraw. */
1894 static void gen_sraw(DisasContext *ctx)
1895 {
1896 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1897 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1898 if (unlikely(Rc(ctx->opcode) != 0))
1899 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1900 }
1901
1902 /* srawi & srawi. */
1903 static void gen_srawi(DisasContext *ctx)
1904 {
1905 int sh = SH(ctx->opcode);
1906 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1907 TCGv src = cpu_gpr[rS(ctx->opcode)];
1908 if (sh == 0) {
1909 tcg_gen_ext32s_tl(dst, src);
1910 tcg_gen_movi_tl(cpu_ca, 0);
1911 } else {
1912 TCGv t0;
1913 tcg_gen_ext32s_tl(dst, src);
1914 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1915 t0 = tcg_temp_new();
1916 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1917 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1918 tcg_temp_free(t0);
1919 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1920 tcg_gen_sari_tl(dst, dst, sh);
1921 }
1922 if (unlikely(Rc(ctx->opcode) != 0)) {
1923 gen_set_Rc0(ctx, dst);
1924 }
1925 }
1926
1927 /* srw & srw. */
1928 static void gen_srw(DisasContext *ctx)
1929 {
1930 TCGv t0, t1;
1931
1932 t0 = tcg_temp_new();
1933 /* AND rS with a mask that is 0 when rB >= 0x20 */
1934 #if defined(TARGET_PPC64)
1935 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1936 tcg_gen_sari_tl(t0, t0, 0x3f);
1937 #else
1938 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1939 tcg_gen_sari_tl(t0, t0, 0x1f);
1940 #endif
1941 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1942 tcg_gen_ext32u_tl(t0, t0);
1943 t1 = tcg_temp_new();
1944 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1945 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1946 tcg_temp_free(t1);
1947 tcg_temp_free(t0);
1948 if (unlikely(Rc(ctx->opcode) != 0))
1949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1950 }
1951
1952 #if defined(TARGET_PPC64)
1953 /* sld & sld. */
1954 static void gen_sld(DisasContext *ctx)
1955 {
1956 TCGv t0, t1;
1957
1958 t0 = tcg_temp_new();
1959 /* AND rS with a mask that is 0 when rB >= 0x40 */
1960 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1961 tcg_gen_sari_tl(t0, t0, 0x3f);
1962 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1963 t1 = tcg_temp_new();
1964 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1965 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1966 tcg_temp_free(t1);
1967 tcg_temp_free(t0);
1968 if (unlikely(Rc(ctx->opcode) != 0))
1969 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1970 }
1971
1972 /* srad & srad. */
1973 static void gen_srad(DisasContext *ctx)
1974 {
1975 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1976 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1977 if (unlikely(Rc(ctx->opcode) != 0))
1978 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1979 }
1980 /* sradi & sradi. */
1981 static inline void gen_sradi(DisasContext *ctx, int n)
1982 {
1983 int sh = SH(ctx->opcode) + (n << 5);
1984 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1985 TCGv src = cpu_gpr[rS(ctx->opcode)];
1986 if (sh == 0) {
1987 tcg_gen_mov_tl(dst, src);
1988 tcg_gen_movi_tl(cpu_ca, 0);
1989 } else {
1990 TCGv t0;
1991 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1992 t0 = tcg_temp_new();
1993 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1994 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1995 tcg_temp_free(t0);
1996 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1997 tcg_gen_sari_tl(dst, src, sh);
1998 }
1999 if (unlikely(Rc(ctx->opcode) != 0)) {
2000 gen_set_Rc0(ctx, dst);
2001 }
2002 }
2003
2004 static void gen_sradi0(DisasContext *ctx)
2005 {
2006 gen_sradi(ctx, 0);
2007 }
2008
2009 static void gen_sradi1(DisasContext *ctx)
2010 {
2011 gen_sradi(ctx, 1);
2012 }
2013
2014 /* srd & srd. */
2015 static void gen_srd(DisasContext *ctx)
2016 {
2017 TCGv t0, t1;
2018
2019 t0 = tcg_temp_new();
2020 /* AND rS with a mask that is 0 when rB >= 0x40 */
2021 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2022 tcg_gen_sari_tl(t0, t0, 0x3f);
2023 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2024 t1 = tcg_temp_new();
2025 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2026 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2027 tcg_temp_free(t1);
2028 tcg_temp_free(t0);
2029 if (unlikely(Rc(ctx->opcode) != 0))
2030 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2031 }
2032 #endif
2033
2034 #if defined(TARGET_PPC64)
2035 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2036 {
2037 TCGv_i32 tmp = tcg_temp_new_i32();
2038 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2039 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2040 tcg_temp_free_i32(tmp);
2041 }
2042 #else
2043 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2044 {
2045 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2046 }
2047 #endif
2048
2049 /*** Floating-Point arithmetic ***/
2050 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2052 { \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2055 return; \
2056 } \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rA(ctx->opcode)], \
2062 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2063 if (isfloat) { \
2064 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2065 cpu_fpr[rD(ctx->opcode)]); \
2066 } \
2067 if (set_fprf) { \
2068 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2069 } \
2070 if (unlikely(Rc(ctx->opcode) != 0)) { \
2071 gen_set_cr1_from_fpscr(ctx); \
2072 } \
2073 }
2074
2075 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2076 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2077 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2078
2079 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2080 static void gen_f##name(DisasContext *ctx) \
2081 { \
2082 if (unlikely(!ctx->fpu_enabled)) { \
2083 gen_exception(ctx, POWERPC_EXCP_FPU); \
2084 return; \
2085 } \
2086 /* NIP cannot be restored if the memory exception comes from an helper */ \
2087 gen_update_nip(ctx, ctx->nip - 4); \
2088 gen_reset_fpstatus(); \
2089 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2090 cpu_fpr[rA(ctx->opcode)], \
2091 cpu_fpr[rB(ctx->opcode)]); \
2092 if (isfloat) { \
2093 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2094 cpu_fpr[rD(ctx->opcode)]); \
2095 } \
2096 if (set_fprf) { \
2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2098 } \
2099 if (unlikely(Rc(ctx->opcode) != 0)) { \
2100 gen_set_cr1_from_fpscr(ctx); \
2101 } \
2102 }
2103 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2104 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2105 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2106
2107 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2108 static void gen_f##name(DisasContext *ctx) \
2109 { \
2110 if (unlikely(!ctx->fpu_enabled)) { \
2111 gen_exception(ctx, POWERPC_EXCP_FPU); \
2112 return; \
2113 } \
2114 /* NIP cannot be restored if the memory exception comes from an helper */ \
2115 gen_update_nip(ctx, ctx->nip - 4); \
2116 gen_reset_fpstatus(); \
2117 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2118 cpu_fpr[rA(ctx->opcode)], \
2119 cpu_fpr[rC(ctx->opcode)]); \
2120 if (isfloat) { \
2121 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2122 cpu_fpr[rD(ctx->opcode)]); \
2123 } \
2124 if (set_fprf) { \
2125 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2126 } \
2127 if (unlikely(Rc(ctx->opcode) != 0)) { \
2128 gen_set_cr1_from_fpscr(ctx); \
2129 } \
2130 }
2131 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2132 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2133 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2134
2135 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2136 static void gen_f##name(DisasContext *ctx) \
2137 { \
2138 if (unlikely(!ctx->fpu_enabled)) { \
2139 gen_exception(ctx, POWERPC_EXCP_FPU); \
2140 return; \
2141 } \
2142 /* NIP cannot be restored if the memory exception comes from an helper */ \
2143 gen_update_nip(ctx, ctx->nip - 4); \
2144 gen_reset_fpstatus(); \
2145 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2146 cpu_fpr[rB(ctx->opcode)]); \
2147 if (set_fprf) { \
2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2149 } \
2150 if (unlikely(Rc(ctx->opcode) != 0)) { \
2151 gen_set_cr1_from_fpscr(ctx); \
2152 } \
2153 }
2154
2155 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2156 static void gen_f##name(DisasContext *ctx) \
2157 { \
2158 if (unlikely(!ctx->fpu_enabled)) { \
2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
2160 return; \
2161 } \
2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
2164 gen_reset_fpstatus(); \
2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2166 cpu_fpr[rB(ctx->opcode)]); \
2167 if (set_fprf) { \
2168 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2169 } \
2170 if (unlikely(Rc(ctx->opcode) != 0)) { \
2171 gen_set_cr1_from_fpscr(ctx); \
2172 } \
2173 }
2174
2175 /* fadd - fadds */
2176 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2177 /* fdiv - fdivs */
2178 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2179 /* fmul - fmuls */
2180 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2181
2182 /* fre */
2183 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2184
2185 /* fres */
2186 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2187
2188 /* frsqrte */
2189 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2190
2191 /* frsqrtes */
2192 static void gen_frsqrtes(DisasContext *ctx)
2193 {
2194 if (unlikely(!ctx->fpu_enabled)) {
2195 gen_exception(ctx, POWERPC_EXCP_FPU);
2196 return;
2197 }
2198 /* NIP cannot be restored if the memory exception comes from an helper */
2199 gen_update_nip(ctx, ctx->nip - 4);
2200 gen_reset_fpstatus();
2201 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2202 cpu_fpr[rB(ctx->opcode)]);
2203 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2204 cpu_fpr[rD(ctx->opcode)]);
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2206 if (unlikely(Rc(ctx->opcode) != 0)) {
2207 gen_set_cr1_from_fpscr(ctx);
2208 }
2209 }
2210
2211 /* fsel */
2212 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2213 /* fsub - fsubs */
2214 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2215 /* Optional: */
2216
2217 /* fsqrt */
2218 static void gen_fsqrt(DisasContext *ctx)
2219 {
2220 if (unlikely(!ctx->fpu_enabled)) {
2221 gen_exception(ctx, POWERPC_EXCP_FPU);
2222 return;
2223 }
2224 /* NIP cannot be restored if the memory exception comes from an helper */
2225 gen_update_nip(ctx, ctx->nip - 4);
2226 gen_reset_fpstatus();
2227 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2228 cpu_fpr[rB(ctx->opcode)]);
2229 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2230 if (unlikely(Rc(ctx->opcode) != 0)) {
2231 gen_set_cr1_from_fpscr(ctx);
2232 }
2233 }
2234
2235 static void gen_fsqrts(DisasContext *ctx)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
2243 gen_reset_fpstatus();
2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2245 cpu_fpr[rB(ctx->opcode)]);
2246 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2247 cpu_fpr[rD(ctx->opcode)]);
2248 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2249 if (unlikely(Rc(ctx->opcode) != 0)) {
2250 gen_set_cr1_from_fpscr(ctx);
2251 }
2252 }
2253
2254 /*** Floating-Point multiply-and-add ***/
2255 /* fmadd - fmadds */
2256 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2257 /* fmsub - fmsubs */
2258 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2259 /* fnmadd - fnmadds */
2260 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2261 /* fnmsub - fnmsubs */
2262 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2263
2264 /*** Floating-Point round & convert ***/
2265 /* fctiw */
2266 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2267 /* fctiwu */
2268 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2269 /* fctiwz */
2270 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2271 /* fctiwuz */
2272 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2273 /* frsp */
2274 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2275 /* fcfid */
2276 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2277 /* fcfids */
2278 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2279 /* fcfidu */
2280 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2281 /* fcfidus */
2282 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2283 /* fctid */
2284 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2285 /* fctidu */
2286 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2287 /* fctidz */
2288 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2289 /* fctidu */
2290 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2291
2292 /* frin */
2293 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2294 /* friz */
2295 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2296 /* frip */
2297 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2298 /* frim */
2299 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2300
2301 static void gen_ftdiv(DisasContext *ctx)
2302 {
2303 if (unlikely(!ctx->fpu_enabled)) {
2304 gen_exception(ctx, POWERPC_EXCP_FPU);
2305 return;
2306 }
2307 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2308 cpu_fpr[rB(ctx->opcode)]);
2309 }
2310
2311 static void gen_ftsqrt(DisasContext *ctx)
2312 {
2313 if (unlikely(!ctx->fpu_enabled)) {
2314 gen_exception(ctx, POWERPC_EXCP_FPU);
2315 return;
2316 }
2317 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2318 }
2319
2320
2321
2322 /*** Floating-Point compare ***/
2323
2324 /* fcmpo */
2325 static void gen_fcmpo(DisasContext *ctx)
2326 {
2327 TCGv_i32 crf;
2328 if (unlikely(!ctx->fpu_enabled)) {
2329 gen_exception(ctx, POWERPC_EXCP_FPU);
2330 return;
2331 }
2332 /* NIP cannot be restored if the memory exception comes from an helper */
2333 gen_update_nip(ctx, ctx->nip - 4);
2334 gen_reset_fpstatus();
2335 crf = tcg_const_i32(crfD(ctx->opcode));
2336 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2337 cpu_fpr[rB(ctx->opcode)], crf);
2338 tcg_temp_free_i32(crf);
2339 gen_helper_float_check_status(cpu_env);
2340 }
2341
2342 /* fcmpu */
2343 static void gen_fcmpu(DisasContext *ctx)
2344 {
2345 TCGv_i32 crf;
2346 if (unlikely(!ctx->fpu_enabled)) {
2347 gen_exception(ctx, POWERPC_EXCP_FPU);
2348 return;
2349 }
2350 /* NIP cannot be restored if the memory exception comes from an helper */
2351 gen_update_nip(ctx, ctx->nip - 4);
2352 gen_reset_fpstatus();
2353 crf = tcg_const_i32(crfD(ctx->opcode));
2354 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2355 cpu_fpr[rB(ctx->opcode)], crf);
2356 tcg_temp_free_i32(crf);
2357 gen_helper_float_check_status(cpu_env);
2358 }
2359
2360 /*** Floating-point move ***/
2361 /* fabs */
2362 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2363 static void gen_fabs(DisasContext *ctx)
2364 {
2365 if (unlikely(!ctx->fpu_enabled)) {
2366 gen_exception(ctx, POWERPC_EXCP_FPU);
2367 return;
2368 }
2369 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2370 ~(1ULL << 63));
2371 if (unlikely(Rc(ctx->opcode))) {
2372 gen_set_cr1_from_fpscr(ctx);
2373 }
2374 }
2375
2376 /* fmr - fmr. */
2377 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2378 static void gen_fmr(DisasContext *ctx)
2379 {
2380 if (unlikely(!ctx->fpu_enabled)) {
2381 gen_exception(ctx, POWERPC_EXCP_FPU);
2382 return;
2383 }
2384 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2385 if (unlikely(Rc(ctx->opcode))) {
2386 gen_set_cr1_from_fpscr(ctx);
2387 }
2388 }
2389
2390 /* fnabs */
2391 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2392 static void gen_fnabs(DisasContext *ctx)
2393 {
2394 if (unlikely(!ctx->fpu_enabled)) {
2395 gen_exception(ctx, POWERPC_EXCP_FPU);
2396 return;
2397 }
2398 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2399 1ULL << 63);
2400 if (unlikely(Rc(ctx->opcode))) {
2401 gen_set_cr1_from_fpscr(ctx);
2402 }
2403 }
2404
2405 /* fneg */
2406 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2407 static void gen_fneg(DisasContext *ctx)
2408 {
2409 if (unlikely(!ctx->fpu_enabled)) {
2410 gen_exception(ctx, POWERPC_EXCP_FPU);
2411 return;
2412 }
2413 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2414 1ULL << 63);
2415 if (unlikely(Rc(ctx->opcode))) {
2416 gen_set_cr1_from_fpscr(ctx);
2417 }
2418 }
2419
2420 /* fcpsgn: PowerPC 2.05 specification */
2421 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2422 static void gen_fcpsgn(DisasContext *ctx)
2423 {
2424 if (unlikely(!ctx->fpu_enabled)) {
2425 gen_exception(ctx, POWERPC_EXCP_FPU);
2426 return;
2427 }
2428 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2429 cpu_fpr[rB(ctx->opcode)], 0, 63);
2430 if (unlikely(Rc(ctx->opcode))) {
2431 gen_set_cr1_from_fpscr(ctx);
2432 }
2433 }
2434
2435 static void gen_fmrgew(DisasContext *ctx)
2436 {
2437 TCGv_i64 b0;
2438 if (unlikely(!ctx->fpu_enabled)) {
2439 gen_exception(ctx, POWERPC_EXCP_FPU);
2440 return;
2441 }
2442 b0 = tcg_temp_new_i64();
2443 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2444 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2445 b0, 0, 32);
2446 tcg_temp_free_i64(b0);
2447 }
2448
2449 static void gen_fmrgow(DisasContext *ctx)
2450 {
2451 if (unlikely(!ctx->fpu_enabled)) {
2452 gen_exception(ctx, POWERPC_EXCP_FPU);
2453 return;
2454 }
2455 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2456 cpu_fpr[rB(ctx->opcode)],
2457 cpu_fpr[rA(ctx->opcode)],
2458 32, 32);
2459 }
2460
2461 /*** Floating-Point status & ctrl register ***/
2462
2463 /* mcrfs */
2464 static void gen_mcrfs(DisasContext *ctx)
2465 {
2466 TCGv tmp = tcg_temp_new();
2467 TCGv_i32 tmask;
2468 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2469 int bfa;
2470 int nibble;
2471 int shift;
2472
2473 if (unlikely(!ctx->fpu_enabled)) {
2474 gen_exception(ctx, POWERPC_EXCP_FPU);
2475 return;
2476 }
2477 bfa = crfS(ctx->opcode);
2478 nibble = 7 - bfa;
2479 shift = 4 * nibble;
2480 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2481 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2482 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2483 tcg_temp_free(tmp);
2484 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2485 /* Only the exception bits (including FX) should be cleared if read */
2486 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2487 /* FEX and VX need to be updated, so don't set fpscr directly */
2488 tmask = tcg_const_i32(1 << nibble);
2489 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2490 tcg_temp_free_i32(tmask);
2491 tcg_temp_free_i64(tnew_fpscr);
2492 }
2493
2494 /* mffs */
2495 static void gen_mffs(DisasContext *ctx)
2496 {
2497 if (unlikely(!ctx->fpu_enabled)) {
2498 gen_exception(ctx, POWERPC_EXCP_FPU);
2499 return;
2500 }
2501 gen_reset_fpstatus();
2502 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2503 if (unlikely(Rc(ctx->opcode))) {
2504 gen_set_cr1_from_fpscr(ctx);
2505 }
2506 }
2507
2508 /* mtfsb0 */
2509 static void gen_mtfsb0(DisasContext *ctx)
2510 {
2511 uint8_t crb;
2512
2513 if (unlikely(!ctx->fpu_enabled)) {
2514 gen_exception(ctx, POWERPC_EXCP_FPU);
2515 return;
2516 }
2517 crb = 31 - crbD(ctx->opcode);
2518 gen_reset_fpstatus();
2519 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2520 TCGv_i32 t0;
2521 /* NIP cannot be restored if the memory exception comes from an helper */
2522 gen_update_nip(ctx, ctx->nip - 4);
2523 t0 = tcg_const_i32(crb);
2524 gen_helper_fpscr_clrbit(cpu_env, t0);
2525 tcg_temp_free_i32(t0);
2526 }
2527 if (unlikely(Rc(ctx->opcode) != 0)) {
2528 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2529 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2530 }
2531 }
2532
2533 /* mtfsb1 */
2534 static void gen_mtfsb1(DisasContext *ctx)
2535 {
2536 uint8_t crb;
2537
2538 if (unlikely(!ctx->fpu_enabled)) {
2539 gen_exception(ctx, POWERPC_EXCP_FPU);
2540 return;
2541 }
2542 crb = 31 - crbD(ctx->opcode);
2543 gen_reset_fpstatus();
2544 /* XXX: we pretend we can only do IEEE floating-point computations */
2545 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2546 TCGv_i32 t0;
2547 /* NIP cannot be restored if the memory exception comes from an helper */
2548 gen_update_nip(ctx, ctx->nip - 4);
2549 t0 = tcg_const_i32(crb);
2550 gen_helper_fpscr_setbit(cpu_env, t0);
2551 tcg_temp_free_i32(t0);
2552 }
2553 if (unlikely(Rc(ctx->opcode) != 0)) {
2554 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2555 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2556 }
2557 /* We can raise a differed exception */
2558 gen_helper_float_check_status(cpu_env);
2559 }
2560
2561 /* mtfsf */
2562 static void gen_mtfsf(DisasContext *ctx)
2563 {
2564 TCGv_i32 t0;
2565 int flm, l, w;
2566
2567 if (unlikely(!ctx->fpu_enabled)) {
2568 gen_exception(ctx, POWERPC_EXCP_FPU);
2569 return;
2570 }
2571 flm = FPFLM(ctx->opcode);
2572 l = FPL(ctx->opcode);
2573 w = FPW(ctx->opcode);
2574 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2575 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2576 return;
2577 }
2578 /* NIP cannot be restored if the memory exception comes from an helper */
2579 gen_update_nip(ctx, ctx->nip - 4);
2580 gen_reset_fpstatus();
2581 if (l) {
2582 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2583 } else {
2584 t0 = tcg_const_i32(flm << (w * 8));
2585 }
2586 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2587 tcg_temp_free_i32(t0);
2588 if (unlikely(Rc(ctx->opcode) != 0)) {
2589 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2590 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2591 }
2592 /* We can raise a differed exception */
2593 gen_helper_float_check_status(cpu_env);
2594 }
2595
2596 /* mtfsfi */
2597 static void gen_mtfsfi(DisasContext *ctx)
2598 {
2599 int bf, sh, w;
2600 TCGv_i64 t0;
2601 TCGv_i32 t1;
2602
2603 if (unlikely(!ctx->fpu_enabled)) {
2604 gen_exception(ctx, POWERPC_EXCP_FPU);
2605 return;
2606 }
2607 w = FPW(ctx->opcode);
2608 bf = FPBF(ctx->opcode);
2609 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2610 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2611 return;
2612 }
2613 sh = (8 * w) + 7 - bf;
2614 /* NIP cannot be restored if the memory exception comes from an helper */
2615 gen_update_nip(ctx, ctx->nip - 4);
2616 gen_reset_fpstatus();
2617 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2618 t1 = tcg_const_i32(1 << sh);
2619 gen_helper_store_fpscr(cpu_env, t0, t1);
2620 tcg_temp_free_i64(t0);
2621 tcg_temp_free_i32(t1);
2622 if (unlikely(Rc(ctx->opcode) != 0)) {
2623 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2624 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2625 }
2626 /* We can raise a differed exception */
2627 gen_helper_float_check_status(cpu_env);
2628 }
2629
2630 /*** Addressing modes ***/
2631 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2632 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2633 target_long maskl)
2634 {
2635 target_long simm = SIMM(ctx->opcode);
2636
2637 simm &= ~maskl;
2638 if (rA(ctx->opcode) == 0) {
2639 if (NARROW_MODE(ctx)) {
2640 simm = (uint32_t)simm;
2641 }
2642 tcg_gen_movi_tl(EA, simm);
2643 } else if (likely(simm != 0)) {
2644 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2645 if (NARROW_MODE(ctx)) {
2646 tcg_gen_ext32u_tl(EA, EA);
2647 }
2648 } else {
2649 if (NARROW_MODE(ctx)) {
2650 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2651 } else {
2652 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2653 }
2654 }
2655 }
2656
2657 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2658 {
2659 if (rA(ctx->opcode) == 0) {
2660 if (NARROW_MODE(ctx)) {
2661 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2662 } else {
2663 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2664 }
2665 } else {
2666 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2667 if (NARROW_MODE(ctx)) {
2668 tcg_gen_ext32u_tl(EA, EA);
2669 }
2670 }
2671 }
2672
2673 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2674 {
2675 if (rA(ctx->opcode) == 0) {
2676 tcg_gen_movi_tl(EA, 0);
2677 } else if (NARROW_MODE(ctx)) {
2678 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2679 } else {
2680 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2681 }
2682 }
2683
2684 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2685 target_long val)
2686 {
2687 tcg_gen_addi_tl(ret, arg1, val);
2688 if (NARROW_MODE(ctx)) {
2689 tcg_gen_ext32u_tl(ret, ret);
2690 }
2691 }
2692
2693 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2694 {
2695 TCGLabel *l1 = gen_new_label();
2696 TCGv t0 = tcg_temp_new();
2697 TCGv_i32 t1, t2;
2698 /* NIP cannot be restored if the memory exception comes from an helper */
2699 gen_update_nip(ctx, ctx->nip - 4);
2700 tcg_gen_andi_tl(t0, EA, mask);
2701 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2702 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2703 t2 = tcg_const_i32(0);
2704 gen_helper_raise_exception_err(cpu_env, t1, t2);
2705 tcg_temp_free_i32(t1);
2706 tcg_temp_free_i32(t2);
2707 gen_set_label(l1);
2708 tcg_temp_free(t0);
2709 }
2710
2711 /*** Integer load ***/
2712 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2713 {
2714 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2715 }
2716
2717 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2718 {
2719 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2720 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2721 }
2722
2723 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2724 {
2725 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2726 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2727 }
2728
2729 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2730 {
2731 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2732 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2733 }
2734
2735 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2736 {
2737 TCGv tmp = tcg_temp_new();
2738 gen_qemu_ld32u(ctx, tmp, addr);
2739 tcg_gen_extu_tl_i64(val, tmp);
2740 tcg_temp_free(tmp);
2741 }
2742
2743 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2744 {
2745 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2746 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2747 }
2748
2749 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2750 {
2751 TCGv tmp = tcg_temp_new();
2752 gen_qemu_ld32s(ctx, tmp, addr);
2753 tcg_gen_ext_tl_i64(val, tmp);
2754 tcg_temp_free(tmp);
2755 }
2756
2757 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2758 {
2759 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2760 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2761 }
2762
2763 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2764 {
2765 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2766 }
2767
2768 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2769 {
2770 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2771 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2772 }
2773
2774 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2775 {
2776 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2777 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2778 }
2779
2780 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2781 {
2782 TCGv tmp = tcg_temp_new();
2783 tcg_gen_trunc_i64_tl(tmp, val);
2784 gen_qemu_st32(ctx, tmp, addr);
2785 tcg_temp_free(tmp);
2786 }
2787
2788 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2789 {
2790 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2791 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2792 }
2793
2794 #define GEN_LD(name, ldop, opc, type) \
2795 static void glue(gen_, name)(DisasContext *ctx) \
2796 { \
2797 TCGv EA; \
2798 gen_set_access_type(ctx, ACCESS_INT); \
2799 EA = tcg_temp_new(); \
2800 gen_addr_imm_index(ctx, EA, 0); \
2801 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2802 tcg_temp_free(EA); \
2803 }
2804
2805 #define GEN_LDU(name, ldop, opc, type) \
2806 static void glue(gen_, name##u)(DisasContext *ctx) \
2807 { \
2808 TCGv EA; \
2809 if (unlikely(rA(ctx->opcode) == 0 || \
2810 rA(ctx->opcode) == rD(ctx->opcode))) { \
2811 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2812 return; \
2813 } \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 if (type == PPC_64B) \
2817 gen_addr_imm_index(ctx, EA, 0x03); \
2818 else \
2819 gen_addr_imm_index(ctx, EA, 0); \
2820 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2822 tcg_temp_free(EA); \
2823 }
2824
2825 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2826 static void glue(gen_, name##ux)(DisasContext *ctx) \
2827 { \
2828 TCGv EA; \
2829 if (unlikely(rA(ctx->opcode) == 0 || \
2830 rA(ctx->opcode) == rD(ctx->opcode))) { \
2831 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2832 return; \
2833 } \
2834 gen_set_access_type(ctx, ACCESS_INT); \
2835 EA = tcg_temp_new(); \
2836 gen_addr_reg_index(ctx, EA); \
2837 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2838 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2839 tcg_temp_free(EA); \
2840 }
2841
2842 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2843 static void glue(gen_, name##x)(DisasContext *ctx) \
2844 { \
2845 TCGv EA; \
2846 gen_set_access_type(ctx, ACCESS_INT); \
2847 EA = tcg_temp_new(); \
2848 gen_addr_reg_index(ctx, EA); \
2849 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2850 tcg_temp_free(EA); \
2851 }
2852 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2853 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2854
2855 #define GEN_LDS(name, ldop, op, type) \
2856 GEN_LD(name, ldop, op | 0x20, type); \
2857 GEN_LDU(name, ldop, op | 0x21, type); \
2858 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2859 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2860
2861 /* lbz lbzu lbzux lbzx */
2862 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2863 /* lha lhau lhaux lhax */
2864 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2865 /* lhz lhzu lhzux lhzx */
2866 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2867 /* lwz lwzu lwzux lwzx */
2868 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2869 #if defined(TARGET_PPC64)
2870 /* lwaux */
2871 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2872 /* lwax */
2873 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2874 /* ldux */
2875 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2876 /* ldx */
2877 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2878
2879 static void gen_ld(DisasContext *ctx)
2880 {
2881 TCGv EA;
2882 if (Rc(ctx->opcode)) {
2883 if (unlikely(rA(ctx->opcode) == 0 ||
2884 rA(ctx->opcode) == rD(ctx->opcode))) {
2885 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2886 return;
2887 }
2888 }
2889 gen_set_access_type(ctx, ACCESS_INT);
2890 EA = tcg_temp_new();
2891 gen_addr_imm_index(ctx, EA, 0x03);
2892 if (ctx->opcode & 0x02) {
2893 /* lwa (lwau is undefined) */
2894 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2895 } else {
2896 /* ld - ldu */
2897 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2898 }
2899 if (Rc(ctx->opcode))
2900 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2901 tcg_temp_free(EA);
2902 }
2903
2904 /* lq */
2905 static void gen_lq(DisasContext *ctx)
2906 {
2907 int ra, rd;
2908 TCGv EA;
2909
2910 /* lq is a legal user mode instruction starting in ISA 2.07 */
2911 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2912 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2913
2914 if (!legal_in_user_mode && ctx->pr) {
2915 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2916 return;
2917 }
2918
2919 if (!le_is_supported && ctx->le_mode) {
2920 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2921 return;
2922 }
2923
2924 ra = rA(ctx->opcode);
2925 rd = rD(ctx->opcode);
2926 if (unlikely((rd & 1) || rd == ra)) {
2927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2928 return;
2929 }
2930
2931 gen_set_access_type(ctx, ACCESS_INT);
2932 EA = tcg_temp_new();
2933 gen_addr_imm_index(ctx, EA, 0x0F);
2934
2935 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2936 64-bit byteswap already. */
2937 if (unlikely(ctx->le_mode)) {
2938 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2939 gen_addr_add(ctx, EA, EA, 8);
2940 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2941 } else {
2942 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2943 gen_addr_add(ctx, EA, EA, 8);
2944 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2945 }
2946 tcg_temp_free(EA);
2947 }
2948 #endif
2949
2950 /*** Integer store ***/
2951 #define GEN_ST(name, stop, opc, type) \
2952 static void glue(gen_, name)(DisasContext *ctx) \
2953 { \
2954 TCGv EA; \
2955 gen_set_access_type(ctx, ACCESS_INT); \
2956 EA = tcg_temp_new(); \
2957 gen_addr_imm_index(ctx, EA, 0); \
2958 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2959 tcg_temp_free(EA); \
2960 }
2961
2962 #define GEN_STU(name, stop, opc, type) \
2963 static void glue(gen_, stop##u)(DisasContext *ctx) \
2964 { \
2965 TCGv EA; \
2966 if (unlikely(rA(ctx->opcode) == 0)) { \
2967 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2968 return; \
2969 } \
2970 gen_set_access_type(ctx, ACCESS_INT); \
2971 EA = tcg_temp_new(); \
2972 if (type == PPC_64B) \
2973 gen_addr_imm_index(ctx, EA, 0x03); \
2974 else \
2975 gen_addr_imm_index(ctx, EA, 0); \
2976 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2977 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2978 tcg_temp_free(EA); \
2979 }
2980
2981 #define GEN_STUX(name, stop, opc2, opc3, type) \
2982 static void glue(gen_, name##ux)(DisasContext *ctx) \
2983 { \
2984 TCGv EA; \
2985 if (unlikely(rA(ctx->opcode) == 0)) { \
2986 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2987 return; \
2988 } \
2989 gen_set_access_type(ctx, ACCESS_INT); \
2990 EA = tcg_temp_new(); \
2991 gen_addr_reg_index(ctx, EA); \
2992 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2993 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2994 tcg_temp_free(EA); \
2995 }
2996
2997 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2998 static void glue(gen_, name##x)(DisasContext *ctx) \
2999 { \
3000 TCGv EA; \
3001 gen_set_access_type(ctx, ACCESS_INT); \
3002 EA = tcg_temp_new(); \
3003 gen_addr_reg_index(ctx, EA); \
3004 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3005 tcg_temp_free(EA); \
3006 }
3007 #define GEN_STX(name, stop, opc2, opc3, type) \
3008 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3009
3010 #define GEN_STS(name, stop, op, type) \
3011 GEN_ST(name, stop, op | 0x20, type); \
3012 GEN_STU(name, stop, op | 0x21, type); \
3013 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3014 GEN_STX(name, stop, 0x17, op | 0x00, type)
3015
3016 /* stb stbu stbux stbx */
3017 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3018 /* sth sthu sthux sthx */
3019 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3020 /* stw stwu stwux stwx */
3021 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3022 #if defined(TARGET_PPC64)
3023 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3024 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3025
3026 static void gen_std(DisasContext *ctx)
3027 {
3028 int rs;
3029 TCGv EA;
3030
3031 rs = rS(ctx->opcode);
3032 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3033
3034 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3035 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3036
3037 if (!legal_in_user_mode && ctx->pr) {
3038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3039 return;
3040 }
3041
3042 if (!le_is_supported && ctx->le_mode) {
3043 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3044 return;
3045 }
3046
3047 if (unlikely(rs & 1)) {
3048 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3049 return;
3050 }
3051 gen_set_access_type(ctx, ACCESS_INT);
3052 EA = tcg_temp_new();
3053 gen_addr_imm_index(ctx, EA, 0x03);
3054
3055 /* We only need to swap high and low halves. gen_qemu_st64 does
3056 necessary 64-bit byteswap already. */
3057 if (unlikely(ctx->le_mode)) {
3058 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3059 gen_addr_add(ctx, EA, EA, 8);
3060 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3061 } else {
3062 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3063 gen_addr_add(ctx, EA, EA, 8);
3064 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3065 }
3066 tcg_temp_free(EA);
3067 } else {
3068 /* std / stdu*/
3069 if (Rc(ctx->opcode)) {
3070 if (unlikely(rA(ctx->opcode) == 0)) {
3071 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3072 return;
3073 }
3074 }
3075 gen_set_access_type(ctx, ACCESS_INT);
3076 EA = tcg_temp_new();
3077 gen_addr_imm_index(ctx, EA, 0x03);
3078 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3079 if (Rc(ctx->opcode))
3080 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3081 tcg_temp_free(EA);
3082 }
3083 }
3084 #endif
3085 /*** Integer load and store with byte reverse ***/
3086
3087 /* lhbrx */
3088 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3089 {
3090 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3091 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3092 }
3093 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3094
3095 /* lwbrx */
3096 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3097 {
3098 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3099 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3100 }
3101 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3102
3103 #if defined(TARGET_PPC64)
3104 /* ldbrx */
3105 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3106 {
3107 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3108 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3109 }
3110 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3111 #endif /* TARGET_PPC64 */
3112
3113 /* sthbrx */
3114 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3115 {
3116 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3117 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3118 }
3119 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3120
3121 /* stwbrx */
3122 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3123 {
3124 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3125 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3126 }
3127 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3128
3129 #if defined(TARGET_PPC64)
3130 /* stdbrx */
3131 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3132 {
3133 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3134 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3135 }
3136 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3137 #endif /* TARGET_PPC64 */
3138
3139 /*** Integer load and store multiple ***/
3140
3141 /* lmw */
3142 static void gen_lmw(DisasContext *ctx)
3143 {
3144 TCGv t0;
3145 TCGv_i32 t1;
3146 gen_set_access_type(ctx, ACCESS_INT);
3147 /* NIP cannot be restored if the memory exception comes from an helper */
3148 gen_update_nip(ctx, ctx->nip - 4);
3149 t0 = tcg_temp_new();
3150 t1 = tcg_const_i32(rD(ctx->opcode));
3151 gen_addr_imm_index(ctx, t0, 0);
3152 gen_helper_lmw(cpu_env, t0, t1);
3153 tcg_temp_free(t0);
3154 tcg_temp_free_i32(t1);
3155 }
3156
3157 /* stmw */
3158 static void gen_stmw(DisasContext *ctx)
3159 {
3160 TCGv t0;
3161 TCGv_i32 t1;
3162 gen_set_access_type(ctx, ACCESS_INT);
3163 /* NIP cannot be restored if the memory exception comes from an helper */
3164 gen_update_nip(ctx, ctx->nip - 4);
3165 t0 = tcg_temp_new();
3166 t1 = tcg_const_i32(rS(ctx->opcode));
3167 gen_addr_imm_index(ctx, t0, 0);
3168 gen_helper_stmw(cpu_env, t0, t1);
3169 tcg_temp_free(t0);
3170 tcg_temp_free_i32(t1);
3171 }
3172
3173 /*** Integer load and store strings ***/
3174
3175 /* lswi */
3176 /* PowerPC32 specification says we must generate an exception if
3177 * rA is in the range of registers to be loaded.
3178 * In an other hand, IBM says this is valid, but rA won't be loaded.
3179 * For now, I'll follow the spec...
3180 */
3181 static void gen_lswi(DisasContext *ctx)
3182 {
3183 TCGv t0;
3184 TCGv_i32 t1, t2;
3185 int nb = NB(ctx->opcode);
3186 int start = rD(ctx->opcode);
3187 int ra = rA(ctx->opcode);
3188 int nr;
3189
3190 if (nb == 0)
3191 nb = 32;
3192 nr = (nb + 3) / 4;
3193 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3194 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3195 return;
3196 }
3197 gen_set_access_type(ctx, ACCESS_INT);
3198 /* NIP cannot be restored if the memory exception comes from an helper */
3199 gen_update_nip(ctx, ctx->nip - 4);
3200 t0 = tcg_temp_new();
3201 gen_addr_register(ctx, t0);
3202 t1 = tcg_const_i32(nb);
3203 t2 = tcg_const_i32(start);
3204 gen_helper_lsw(cpu_env, t0, t1, t2);
3205 tcg_temp_free(t0);
3206 tcg_temp_free_i32(t1);
3207 tcg_temp_free_i32(t2);
3208 }
3209
3210 /* lswx */
3211 static void gen_lswx(DisasContext *ctx)
3212 {
3213 TCGv t0;
3214 TCGv_i32 t1, t2, t3;
3215 gen_set_access_type(ctx, ACCESS_INT);
3216 /* NIP cannot be restored if the memory exception comes from an helper */
3217 gen_update_nip(ctx, ctx->nip - 4);
3218 t0 = tcg_temp_new();
3219 gen_addr_reg_index(ctx, t0);
3220 t1 = tcg_const_i32(rD(ctx->opcode));
3221 t2 = tcg_const_i32(rA(ctx->opcode));
3222 t3 = tcg_const_i32(rB(ctx->opcode));
3223 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3224 tcg_temp_free(t0);
3225 tcg_temp_free_i32(t1);
3226 tcg_temp_free_i32(t2);
3227 tcg_temp_free_i32(t3);
3228 }
3229
3230 /* stswi */
3231 static void gen_stswi(DisasContext *ctx)
3232 {
3233 TCGv t0;
3234 TCGv_i32 t1, t2;
3235 int nb = NB(ctx->opcode);
3236 gen_set_access_type(ctx, ACCESS_INT);
3237 /* NIP cannot be restored if the memory exception comes from an helper */
3238 gen_update_nip(ctx, ctx->nip - 4);
3239 t0 = tcg_temp_new();
3240 gen_addr_register(ctx, t0);
3241 if (nb == 0)
3242 nb = 32;
3243 t1 = tcg_const_i32(nb);
3244 t2 = tcg_const_i32(rS(ctx->opcode));
3245 gen_helper_stsw(cpu_env, t0, t1, t2);
3246 tcg_temp_free(t0);
3247 tcg_temp_free_i32(t1);
3248 tcg_temp_free_i32(t2);
3249 }
3250
3251 /* stswx */
3252 static void gen_stswx(DisasContext *ctx)
3253 {
3254 TCGv t0;
3255 TCGv_i32 t1, t2;
3256 gen_set_access_type(ctx, ACCESS_INT);
3257 /* NIP cannot be restored if the memory exception comes from an helper */
3258 gen_update_nip(ctx, ctx->nip - 4);
3259 t0 = tcg_temp_new();
3260 gen_addr_reg_index(ctx, t0);
3261 t1 = tcg_temp_new_i32();
3262 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3263 tcg_gen_andi_i32(t1, t1, 0x7F);
3264 t2 = tcg_const_i32(rS(ctx->opcode));
3265 gen_helper_stsw(cpu_env, t0, t1, t2);
3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
3269 }
3270
3271 /*** Memory synchronisation ***/
3272 /* eieio */
3273 static void gen_eieio(DisasContext *ctx)
3274 {
3275 }
3276
3277 /* isync */
3278 static void gen_isync(DisasContext *ctx)
3279 {
3280 gen_stop_exception(ctx);
3281 }
3282
3283 #define LARX(name, len, loadop) \
3284 static void gen_##name(DisasContext *ctx) \
3285 { \
3286 TCGv t0; \
3287 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3288 gen_set_access_type(ctx, ACCESS_RES); \
3289 t0 = tcg_temp_local_new(); \
3290 gen_addr_reg_index(ctx, t0); \
3291 if ((len) > 1) { \
3292 gen_check_align(ctx, t0, (len)-1); \
3293 } \
3294 gen_qemu_##loadop(ctx, gpr, t0); \
3295 tcg_gen_mov_tl(cpu_reserve, t0); \
3296 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3297 tcg_temp_free(t0); \
3298 }
3299
3300 /* lwarx */
3301 LARX(lbarx, 1, ld8u);
3302 LARX(lharx, 2, ld16u);
3303 LARX(lwarx, 4, ld32u);
3304
3305
3306 #if defined(CONFIG_USER_ONLY)
3307 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3308 int reg, int size)
3309 {
3310 TCGv t0 = tcg_temp_new();
3311 uint32_t save_exception = ctx->exception;
3312
3313 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3314 tcg_gen_movi_tl(t0, (size << 5) | reg);
3315 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3316 tcg_temp_free(t0);
3317 gen_update_nip(ctx, ctx->nip-4);
3318 ctx->exception = POWERPC_EXCP_BRANCH;
3319 gen_exception(ctx, POWERPC_EXCP_STCX);
3320 ctx->exception = save_exception;
3321 }
3322 #else
3323 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3324 int reg, int size)
3325 {
3326 TCGLabel *l1;
3327
3328 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3329 l1 = gen_new_label();
3330 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3331 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3332 #if defined(TARGET_PPC64)
3333 if (size == 8) {
3334 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3335 } else
3336 #endif
3337 if (size == 4) {
3338 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3339 } else if (size == 2) {
3340 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3341 #if defined(TARGET_PPC64)
3342 } else if (size == 16) {
3343 TCGv gpr1, gpr2 , EA8;
3344 if (unlikely(ctx->le_mode)) {
3345 gpr1 = cpu_gpr[reg+1];
3346 gpr2 = cpu_gpr[reg];
3347 } else {
3348 gpr1 = cpu_gpr[reg];
3349 gpr2 = cpu_gpr[reg+1];
3350 }
3351 gen_qemu_st64(ctx, gpr1, EA);
3352 EA8 = tcg_temp_local_new();
3353 gen_addr_add(ctx, EA8, EA, 8);
3354 gen_qemu_st64(ctx, gpr2, EA8);
3355 tcg_temp_free(EA8);
3356 #endif
3357 } else {
3358 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3359 }
3360 gen_set_label(l1);
3361 tcg_gen_movi_tl(cpu_reserve, -1);
3362 }
3363 #endif
3364
3365 #define STCX(name, len) \
3366 static void gen_##name(DisasContext *ctx) \
3367 { \
3368 TCGv t0; \
3369 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3370 gen_inval_exception(ctx, \
3371 POWERPC_EXCP_INVAL_INVAL); \
3372 return; \
3373 } \
3374 gen_set_access_type(ctx, ACCESS_RES); \
3375 t0 = tcg_temp_local_new(); \
3376 gen_addr_reg_index(ctx, t0); \
3377 if (len > 1) { \
3378 gen_check_align(ctx, t0, (len)-1); \
3379 } \
3380 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3381 tcg_temp_free(t0); \
3382 }
3383
3384 STCX(stbcx_, 1);
3385 STCX(sthcx_, 2);
3386 STCX(stwcx_, 4);
3387
3388 #if defined(TARGET_PPC64)
3389 /* ldarx */
3390 LARX(ldarx, 8, ld64);
3391
3392 /* lqarx */
3393 static void gen_lqarx(DisasContext *ctx)
3394 {
3395 TCGv EA;
3396 int rd = rD(ctx->opcode);
3397 TCGv gpr1, gpr2;
3398
3399 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3400 (rd == rB(ctx->opcode)))) {
3401 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3402 return;
3403 }
3404
3405 gen_set_access_type(ctx, ACCESS_RES);
3406 EA = tcg_temp_local_new();
3407 gen_addr_reg_index(ctx, EA);
3408 gen_check_align(ctx, EA, 15);
3409 if (unlikely(ctx->le_mode)) {
3410 gpr1 = cpu_gpr[rd+1];
3411 gpr2 = cpu_gpr[rd];
3412 } else {
3413 gpr1 = cpu_gpr[rd];
3414 gpr2 = cpu_gpr[rd+1];
3415 }
3416 gen_qemu_ld64(ctx, gpr1, EA);
3417 tcg_gen_mov_tl(cpu_reserve, EA);
3418
3419 gen_addr_add(ctx, EA, EA, 8);
3420 gen_qemu_ld64(ctx, gpr2, EA);
3421
3422 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3423 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3424
3425 tcg_temp_free(EA);
3426 }
3427
3428 /* stdcx. */
3429 STCX(stdcx_, 8);
3430 STCX(stqcx_, 16);
3431 #endif /* defined(TARGET_PPC64) */
3432
3433 /* sync */
3434 static void gen_sync(DisasContext *ctx)
3435 {
3436 }
3437
3438 /* wait */
3439 static void gen_wait(DisasContext *ctx)
3440 {
3441 TCGv_i32 t0 = tcg_temp_new_i32();
3442 tcg_gen_st_i32(t0, cpu_env,
3443 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3444 tcg_temp_free_i32(t0);
3445 /* Stop translation, as the CPU is supposed to sleep from now */
3446 gen_exception_err(ctx, EXCP_HLT, 1);
3447 }
3448
3449 /*** Floating-point load ***/
3450 #define GEN_LDF(name, ldop, opc, type) \
3451 static void glue(gen_, name)(DisasContext *ctx) \
3452 { \
3453 TCGv EA; \
3454 if (unlikely(!ctx->fpu_enabled)) { \
3455 gen_exception(ctx, POWERPC_EXCP_FPU); \
3456 return; \
3457 } \
3458 gen_set_access_type(ctx, ACCESS_FLOAT); \
3459 EA = tcg_temp_new(); \
3460 gen_addr_imm_index(ctx, EA, 0); \
3461 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3462 tcg_temp_free(EA); \
3463 }
3464
3465 #define GEN_LDUF(name, ldop, opc, type) \
3466 static void glue(gen_, name##u)(DisasContext *ctx) \
3467 { \
3468 TCGv EA; \
3469 if (unlikely(!ctx->fpu_enabled)) { \
3470 gen_exception(ctx, POWERPC_EXCP_FPU); \
3471 return; \
3472 } \
3473 if (unlikely(rA(ctx->opcode) == 0)) { \
3474 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3475 return; \
3476 } \
3477 gen_set_access_type(ctx, ACCESS_FLOAT); \
3478 EA = tcg_temp_new(); \
3479 gen_addr_imm_index(ctx, EA, 0); \
3480 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3481 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3482 tcg_temp_free(EA); \
3483 }
3484
3485 #define GEN_LDUXF(name, ldop, opc, type) \
3486 static void glue(gen_, name##ux)(DisasContext *ctx) \
3487 { \
3488 TCGv EA; \
3489 if (unlikely(!ctx->fpu_enabled)) { \
3490 gen_exception(ctx, POWERPC_EXCP_FPU); \
3491 return; \
3492 } \
3493 if (unlikely(rA(ctx->opcode) == 0)) { \
3494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3495 return; \
3496 } \
3497 gen_set_access_type(ctx, ACCESS_FLOAT); \
3498 EA = tcg_temp_new(); \
3499 gen_addr_reg_index(ctx, EA); \
3500 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3501 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3502 tcg_temp_free(EA); \
3503 }
3504
3505 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3506 static void glue(gen_, name##x)(DisasContext *ctx) \
3507 { \
3508 TCGv EA; \
3509 if (unlikely(!ctx->fpu_enabled)) { \
3510 gen_exception(ctx, POWERPC_EXCP_FPU); \
3511 return; \
3512 } \
3513 gen_set_access_type(ctx, ACCESS_FLOAT); \
3514 EA = tcg_temp_new(); \
3515 gen_addr_reg_index(ctx, EA); \
3516 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3517 tcg_temp_free(EA); \
3518 }
3519
3520 #define GEN_LDFS(name, ldop, op, type) \
3521 GEN_LDF(name, ldop, op | 0x20, type); \
3522 GEN_LDUF(name, ldop, op | 0x21, type); \
3523 GEN_LDUXF(name, ldop, op | 0x01, type); \
3524 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3525
3526 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3527 {
3528 TCGv t0 = tcg_temp_new();
3529 TCGv_i32 t1 = tcg_temp_new_i32();
3530 gen_qemu_ld32u(ctx, t0, arg2);
3531 tcg_gen_trunc_tl_i32(t1, t0);
3532 tcg_temp_free(t0);
3533 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3534 tcg_temp_free_i32(t1);
3535 }
3536
3537 /* lfd lfdu lfdux lfdx */
3538 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3539 /* lfs lfsu lfsux lfsx */
3540 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3541
3542 /* lfdp */
3543 static void gen_lfdp(DisasContext *ctx)
3544 {
3545 TCGv EA;
3546 if (unlikely(!ctx->fpu_enabled)) {
3547 gen_exception(ctx, POWERPC_EXCP_FPU);
3548 return;
3549 }
3550 gen_set_access_type(ctx, ACCESS_FLOAT);
3551 EA = tcg_temp_new();
3552 gen_addr_imm_index(ctx, EA, 0);
3553 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3554 64-bit byteswap already. */
3555 if (unlikely(ctx->le_mode)) {
3556 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3557 tcg_gen_addi_tl(EA, EA, 8);
3558 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3559 } else {
3560 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3561 tcg_gen_addi_tl(EA, EA, 8);
3562 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3563 }
3564 tcg_temp_free(EA);
3565 }
3566
3567 /* lfdpx */
3568 static void gen_lfdpx(DisasContext *ctx)
3569 {
3570 TCGv EA;
3571 if (unlikely(!ctx->fpu_enabled)) {
3572 gen_exception(ctx, POWERPC_EXCP_FPU);
3573 return;
3574 }
3575 gen_set_access_type(ctx, ACCESS_FLOAT);
3576 EA = tcg_temp_new();
3577 gen_addr_reg_index(ctx, EA);
3578 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3579 64-bit byteswap already. */
3580 if (unlikely(ctx->le_mode)) {
3581 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3582 tcg_gen_addi_tl(EA, EA, 8);
3583 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3584 } else {
3585 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3586 tcg_gen_addi_tl(EA, EA, 8);
3587 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3588 }
3589 tcg_temp_free(EA);
3590 }
3591
3592 /* lfiwax */
3593 static void gen_lfiwax(DisasContext *ctx)
3594 {
3595 TCGv EA;
3596 TCGv t0;
3597 if (unlikely(!ctx->fpu_enabled)) {
3598 gen_exception(ctx, POWERPC_EXCP_FPU);
3599 return;
3600 }
3601 gen_set_access_type(ctx, ACCESS_FLOAT);
3602 EA = tcg_temp_new();
3603 t0 = tcg_temp_new();
3604 gen_addr_reg_index(ctx, EA);
3605 gen_qemu_ld32s(ctx, t0, EA);
3606 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3607 tcg_temp_free(EA);
3608 tcg_temp_free(t0);
3609 }
3610
3611 /* lfiwzx */
3612 static void gen_lfiwzx(DisasContext *ctx)
3613 {
3614 TCGv EA;
3615 if (unlikely(!ctx->fpu_enabled)) {
3616 gen_exception(ctx, POWERPC_EXCP_FPU);
3617 return;
3618 }
3619 gen_set_access_type(ctx, ACCESS_FLOAT);
3620 EA = tcg_temp_new();
3621 gen_addr_reg_index(ctx, EA);
3622 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3623 tcg_temp_free(EA);
3624 }
3625 /*** Floating-point store ***/
3626 #define GEN_STF(name, stop, opc, type) \
3627 static void glue(gen_, name)(DisasContext *ctx) \
3628 { \
3629 TCGv EA; \
3630 if (unlikely(!ctx->fpu_enabled)) { \
3631 gen_exception(ctx, POWERPC_EXCP_FPU); \
3632 return; \
3633 } \
3634 gen_set_access_type(ctx, ACCESS_FLOAT); \
3635 EA = tcg_temp_new(); \
3636 gen_addr_imm_index(ctx, EA, 0); \
3637 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3638 tcg_temp_free(EA); \
3639 }
3640
3641 #define GEN_STUF(name, stop, opc, type) \
3642 static void glue(gen_, name##u)(DisasContext *ctx) \
3643 { \
3644 TCGv EA; \
3645 if (unlikely(!ctx->fpu_enabled)) { \
3646 gen_exception(ctx, POWERPC_EXCP_FPU); \
3647 return; \
3648 } \
3649 if (unlikely(rA(ctx->opcode) == 0)) { \
3650 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3651 return; \
3652 } \
3653 gen_set_access_type(ctx, ACCESS_FLOAT); \
3654 EA = tcg_temp_new(); \
3655 gen_addr_imm_index(ctx, EA, 0); \
3656 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3657 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3658 tcg_temp_free(EA); \
3659 }
3660
3661 #define GEN_STUXF(name, stop, opc, type) \
3662 static void glue(gen_, name##ux)(DisasContext *ctx) \
3663 { \
3664 TCGv EA; \
3665 if (unlikely(!ctx->fpu_enabled)) { \
3666 gen_exception(ctx, POWERPC_EXCP_FPU); \
3667 return; \
3668 } \
3669 if (unlikely(rA(ctx->opcode) == 0)) { \
3670 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3671 return; \
3672 } \
3673 gen_set_access_type(ctx, ACCESS_FLOAT); \
3674 EA = tcg_temp_new(); \
3675 gen_addr_reg_index(ctx, EA); \
3676 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3677 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3678 tcg_temp_free(EA); \
3679 }
3680
3681 #define GEN_STXF(name, stop, opc2, opc3, type) \
3682 static void glue(gen_, name##x)(DisasContext *ctx) \
3683 { \
3684 TCGv EA; \
3685 if (unlikely(!ctx->fpu_enabled)) { \
3686 gen_exception(ctx, POWERPC_EXCP_FPU); \
3687 return; \
3688 } \
3689 gen_set_access_type(ctx, ACCESS_FLOAT); \
3690 EA = tcg_temp_new(); \
3691 gen_addr_reg_index(ctx, EA); \
3692 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3693 tcg_temp_free(EA); \
3694 }
3695
3696 #define GEN_STFS(name, stop, op, type) \
3697 GEN_STF(name, stop, op | 0x20, type); \
3698 GEN_STUF(name, stop, op | 0x21, type); \
3699 GEN_STUXF(name, stop, op | 0x01, type); \
3700 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3701
3702 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3703 {
3704 TCGv_i32 t0 = tcg_temp_new_i32();
3705 TCGv t1 = tcg_temp_new();
3706 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3707 tcg_gen_extu_i32_tl(t1, t0);
3708 tcg_temp_free_i32(t0);
3709 gen_qemu_st32(ctx, t1, arg2);
3710 tcg_temp_free(t1);
3711 }
3712
3713 /* stfd stfdu stfdux stfdx */
3714 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3715 /* stfs stfsu stfsux stfsx */
3716 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3717
3718 /* stfdp */
3719 static void gen_stfdp(DisasContext *ctx)
3720 {
3721 TCGv EA;
3722 if (unlikely(!ctx->fpu_enabled)) {
3723 gen_exception(ctx, POWERPC_EXCP_FPU);
3724 return;
3725 }
3726 gen_set_access_type(ctx, ACCESS_FLOAT);
3727 EA = tcg_temp_new();
3728 gen_addr_imm_index(ctx, EA, 0);
3729 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3730 64-bit byteswap already. */
3731 if (unlikely(ctx->le_mode)) {
3732 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3733 tcg_gen_addi_tl(EA, EA, 8);
3734 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3735 } else {
3736 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3737 tcg_gen_addi_tl(EA, EA, 8);
3738 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3739 }
3740 tcg_temp_free(EA);
3741 }
3742
3743 /* stfdpx */
3744 static void gen_stfdpx(DisasContext *ctx)
3745 {
3746 TCGv EA;
3747 if (unlikely(!ctx->fpu_enabled)) {
3748 gen_exception(ctx, POWERPC_EXCP_FPU);
3749 return;
3750 }
3751 gen_set_access_type(ctx, ACCESS_FLOAT);
3752 EA = tcg_temp_new();
3753 gen_addr_reg_index(ctx, EA);
3754 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3755 64-bit byteswap already. */
3756 if (unlikely(ctx->le_mode)) {
3757 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3758 tcg_gen_addi_tl(EA, EA, 8);
3759 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3760 } else {
3761 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3762 tcg_gen_addi_tl(EA, EA, 8);
3763 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3764 }
3765 tcg_temp_free(EA);
3766 }
3767
3768 /* Optional: */
3769 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3770 {
3771 TCGv t0 = tcg_temp_new();
3772 tcg_gen_trunc_i64_tl(t0, arg1),
3773 gen_qemu_st32(ctx, t0, arg2);
3774 tcg_temp_free(t0);
3775 }
3776 /* stfiwx */
3777 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3778
3779 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3780 {
3781 #if defined(TARGET_PPC64)
3782 if (ctx->has_cfar)
3783 tcg_gen_movi_tl(cpu_cfar, nip);
3784 #endif
3785 }
3786
3787 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3788 {
3789 if (unlikely(ctx->singlestep_enabled)) {
3790 return false;
3791 }
3792
3793 #ifndef CONFIG_USER_ONLY
3794 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3795 #else
3796 return true;
3797 #endif
3798 }
3799
3800 /*** Branch ***/
3801 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3802 {
3803 if (NARROW_MODE(ctx)) {
3804 dest = (uint32_t) dest;
3805 }
3806 if (use_goto_tb(ctx, dest)) {
3807 tcg_gen_goto_tb(n);
3808 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3809 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3810 } else {
3811 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3812 if (unlikely(ctx->singlestep_enabled)) {
3813 if ((ctx->singlestep_enabled &
3814 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3815 (ctx->exception == POWERPC_EXCP_BRANCH ||
3816 ctx->exception == POWERPC_EXCP_TRACE)) {
3817 target_ulong tmp = ctx->nip;
3818 ctx->nip = dest;
3819 gen_exception(ctx, POWERPC_EXCP_TRACE);
3820 ctx->nip = tmp;
3821 }
3822 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3823 gen_debug_exception(ctx);
3824 }
3825 }
3826 tcg_gen_exit_tb(0);
3827 }
3828 }
3829
3830 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3831 {
3832 if (NARROW_MODE(ctx)) {
3833 nip = (uint32_t)nip;
3834 }
3835 tcg_gen_movi_tl(cpu_lr, nip);
3836 }
3837
3838 /* b ba bl bla */
3839 static void gen_b(DisasContext *ctx)
3840 {
3841 target_ulong li, target;
3842
3843 ctx->exception = POWERPC_EXCP_BRANCH;
3844 /* sign extend LI */
3845 li = LI(ctx->opcode);
3846 li = (li ^ 0x02000000) - 0x02000000;
3847 if (likely(AA(ctx->opcode) == 0)) {
3848 target = ctx->nip + li - 4;
3849 } else {
3850 target = li;
3851 }
3852 if (LK(ctx->opcode)) {
3853 gen_setlr(ctx, ctx->nip);
3854 }
3855 gen_update_cfar(ctx, ctx->nip);
3856 gen_goto_tb(ctx, 0, target);
3857 }
3858
3859 #define BCOND_IM 0
3860 #define BCOND_LR 1
3861 #define BCOND_CTR 2
3862 #define BCOND_TAR 3
3863
3864 static inline void gen_bcond(DisasContext *ctx, int type)
3865 {
3866 uint32_t bo = BO(ctx->opcode);
3867 TCGLabel *l1;
3868 TCGv target;
3869
3870 ctx->exception = POWERPC_EXCP_BRANCH;
3871 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3872 target = tcg_temp_local_new();
3873 if (type == BCOND_CTR)
3874 tcg_gen_mov_tl(target, cpu_ctr);
3875 else if (type == BCOND_TAR)
3876 gen_load_spr(target, SPR_TAR);
3877 else
3878 tcg_gen_mov_tl(target, cpu_lr);
3879 } else {
3880 TCGV_UNUSED(target);
3881 }
3882 if (LK(ctx->opcode))
3883 gen_setlr(ctx, ctx->nip);
3884 l1 = gen_new_label();
3885 if ((bo & 0x4) == 0) {
3886 /* Decrement and test CTR */
3887 TCGv temp = tcg_temp_new();
3888 if (unlikely(type == BCOND_CTR)) {
3889 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3890 return;
3891 }
3892 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3893 if (NARROW_MODE(ctx)) {
3894 tcg_gen_ext32u_tl(temp, cpu_ctr);
3895 } else {
3896 tcg_gen_mov_tl(temp, cpu_ctr);
3897 }
3898 if (bo & 0x2) {
3899 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3900 } else {
3901 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3902 }
3903 tcg_temp_free(temp);
3904 }
3905 if ((bo & 0x10) == 0) {
3906 /* Test CR */
3907 uint32_t bi = BI(ctx->opcode);
3908 uint32_t mask = 0x08 >> (bi & 0x03);
3909 TCGv_i32 temp = tcg_temp_new_i32();
3910
3911 if (bo & 0x8) {
3912 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3913 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3914 } else {
3915 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3916 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3917 }
3918 tcg_temp_free_i32(temp);
3919 }
3920 gen_update_cfar(ctx, ctx->nip);
3921 if (type == BCOND_IM) {
3922 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3923 if (likely(AA(ctx->opcode) == 0)) {
3924 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3925 } else {
3926 gen_goto_tb(ctx, 0, li);
3927 }
3928 gen_set_label(l1);
3929 gen_goto_tb(ctx, 1, ctx->nip);
3930 } else {
3931 if (NARROW_MODE(ctx)) {
3932 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3933 } else {
3934 tcg_gen_andi_tl(cpu_nip, target, ~3);
3935 }
3936 tcg_gen_exit_tb(0);
3937 gen_set_label(l1);
3938 gen_update_nip(ctx, ctx->nip);
3939 tcg_gen_exit_tb(0);
3940 }
3941 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3942 tcg_temp_free(target);
3943 }
3944 }
3945
3946 static void gen_bc(DisasContext *ctx)
3947 {
3948 gen_bcond(ctx, BCOND_IM);
3949 }
3950
3951 static void gen_bcctr(DisasContext *ctx)
3952 {
3953 gen_bcond(ctx, BCOND_CTR);
3954 }
3955
3956 static void gen_bclr(DisasContext *ctx)
3957 {
3958 gen_bcond(ctx, BCOND_LR);
3959 }
3960
3961 static void gen_bctar(DisasContext *ctx)
3962 {
3963 gen_bcond(ctx, BCOND_TAR);
3964 }
3965
3966 /*** Condition register logical ***/
3967 #define GEN_CRLOGIC(name, tcg_op, opc) \
3968 static void glue(gen_, name)(DisasContext *ctx) \
3969 { \
3970 uint8_t bitmask; \
3971 int sh; \
3972 TCGv_i32 t0, t1; \
3973 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3974 t0 = tcg_temp_new_i32(); \
3975 if (sh > 0) \
3976 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3977 else if (sh < 0) \
3978 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3979 else \
3980 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3981 t1 = tcg_temp_new_i32(); \
3982 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3983 if (sh > 0) \
3984 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3985 else if (sh < 0) \
3986 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3987 else \
3988 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3989 tcg_op(t0, t0, t1); \
3990 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3991 tcg_gen_andi_i32(t0, t0, bitmask); \
3992 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3993 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3994 tcg_temp_free_i32(t0); \
3995 tcg_temp_free_i32(t1); \
3996 }
3997
3998 /* crand */
3999 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4000 /* crandc */
4001 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4002 /* creqv */
4003 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4004 /* crnand */
4005 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4006 /* crnor */
4007 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4008 /* cror */
4009 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4010 /* crorc */
4011 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4012 /* crxor */
4013 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4014
4015 /* mcrf */
4016 static void gen_mcrf(DisasContext *ctx)
4017 {
4018 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4019 }
4020
4021 /*** System linkage ***/
4022
4023 /* rfi (supervisor only) */
4024 static void gen_rfi(DisasContext *ctx)
4025 {
4026 #if defined(CONFIG_USER_ONLY)
4027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4028 #else
4029 /* Restore CPU state */
4030 if (unlikely(ctx->pr)) {
4031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4032 return;
4033 }
4034 gen_update_cfar(ctx, ctx->nip);
4035 gen_helper_rfi(cpu_env);
4036 gen_sync_exception(ctx);
4037 #endif
4038 }
4039
4040 #if defined(TARGET_PPC64)
4041 static void gen_rfid(DisasContext *ctx)
4042 {
4043 #if defined(CONFIG_USER_ONLY)
4044 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4045 #else
4046 /* Restore CPU state */
4047 if (unlikely(ctx->pr)) {
4048 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4049 return;
4050 }
4051 gen_update_cfar(ctx, ctx->nip);
4052 gen_helper_rfid(cpu_env);
4053 gen_sync_exception(ctx);
4054 #endif
4055 }
4056
4057 static void gen_hrfid(DisasContext *ctx)
4058 {
4059 #if defined(CONFIG_USER_ONLY)
4060 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4061 #else
4062 /* Restore CPU state */
4063 if (unlikely(!ctx->hv)) {
4064 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4065 return;
4066 }
4067 gen_helper_hrfid(cpu_env);
4068 gen_sync_exception(ctx);
4069 #endif
4070 }
4071 #endif
4072
4073 /* sc */
4074 #if defined(CONFIG_USER_ONLY)
4075 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4076 #else
4077 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4078 #endif
4079 static void gen_sc(DisasContext *ctx)
4080 {
4081 uint32_t lev;
4082
4083 lev = (ctx->opcode >> 5) & 0x7F;
4084 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4085 }
4086
4087 /*** Trap ***/
4088
4089 /* tw */
4090 static void gen_tw(DisasContext *ctx)
4091 {
4092 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4093 /* Update the nip since this might generate a trap exception */
4094 gen_update_nip(ctx, ctx->nip);
4095 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4096 t0);
4097 tcg_temp_free_i32(t0);
4098 }
4099
4100 /* twi */
4101 static void gen_twi(DisasContext *ctx)
4102 {
4103 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4104 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4105 /* Update the nip since this might generate a trap exception */
4106 gen_update_nip(ctx, ctx->nip);
4107 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4108 tcg_temp_free(t0);
4109 tcg_temp_free_i32(t1);
4110 }
4111
4112 #if defined(TARGET_PPC64)
4113 /* td */
4114 static void gen_td(DisasContext *ctx)
4115 {
4116 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4117 /* Update the nip since this might generate a trap exception */
4118 gen_update_nip(ctx, ctx->nip);
4119 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4120 t0);
4121 tcg_temp_free_i32(t0);
4122 }
4123
4124 /* tdi */
4125 static void gen_tdi(DisasContext *ctx)
4126 {
4127 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4128 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4129 /* Update the nip since this might generate a trap exception */
4130 gen_update_nip(ctx, ctx->nip);
4131 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4132 tcg_temp_free(t0);
4133 tcg_temp_free_i32(t1);
4134 }
4135 #endif
4136
4137 /*** Processor control ***/
4138
4139 static void gen_read_xer(TCGv dst)
4140 {
4141 TCGv t0 = tcg_temp_new();
4142 TCGv t1 = tcg_temp_new();
4143 TCGv t2 = tcg_temp_new();
4144 tcg_gen_mov_tl(dst, cpu_xer);
4145 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4146 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4147 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4148 tcg_gen_or_tl(t0, t0, t1);
4149 tcg_gen_or_tl(dst, dst, t2);
4150 tcg_gen_or_tl(dst, dst, t0);
4151 tcg_temp_free(t0);
4152 tcg_temp_free(t1);
4153 tcg_temp_free(t2);
4154 }
4155
4156 static void gen_write_xer(TCGv src)
4157 {
4158 tcg_gen_andi_tl(cpu_xer, src,
4159 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4160 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4161 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4162 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4163 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4164 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4165 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4166 }
4167
4168 /* mcrxr */
4169 static void gen_mcrxr(DisasContext *ctx)
4170 {
4171 TCGv_i32 t0 = tcg_temp_new_i32();
4172 TCGv_i32 t1 = tcg_temp_new_i32();
4173 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4174
4175 tcg_gen_trunc_tl_i32(t0, cpu_so);
4176 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4177 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4178 tcg_gen_shli_i32(t0, t0, 3);
4179 tcg_gen_shli_i32(t1, t1, 2);
4180 tcg_gen_shli_i32(dst, dst, 1);
4181 tcg_gen_or_i32(dst, dst, t0);
4182 tcg_gen_or_i32(dst, dst, t1);
4183 tcg_temp_free_i32(t0);
4184 tcg_temp_free_i32(t1);
4185
4186 tcg_gen_movi_tl(cpu_so, 0);
4187 tcg_gen_movi_tl(cpu_ov, 0);
4188 tcg_gen_movi_tl(cpu_ca, 0);
4189 }
4190
4191 /* mfcr mfocrf */
4192 static void gen_mfcr(DisasContext *ctx)
4193 {
4194 uint32_t crm, crn;
4195
4196 if (likely(ctx->opcode & 0x00100000)) {
4197 crm = CRM(ctx->opcode);
4198 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4199 crn = ctz32 (crm);
4200 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4201 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4202 cpu_gpr[rD(ctx->opcode)], crn * 4);
4203 }
4204 } else {
4205 TCGv_i32 t0 = tcg_temp_new_i32();
4206 tcg_gen_mov_i32(t0, cpu_crf[0]);
4207 tcg_gen_shli_i32(t0, t0, 4);
4208 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4209 tcg_gen_shli_i32(t0, t0, 4);
4210 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4211 tcg_gen_shli_i32(t0, t0, 4);
4212 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4213 tcg_gen_shli_i32(t0, t0, 4);
4214 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4215 tcg_gen_shli_i32(t0, t0, 4);
4216 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4217 tcg_gen_shli_i32(t0, t0, 4);
4218 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4219 tcg_gen_shli_i32(t0, t0, 4);
4220 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4221 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4222 tcg_temp_free_i32(t0);
4223 }
4224 }
4225
4226 /* mfmsr */
4227 static void gen_mfmsr(DisasContext *ctx)
4228 {
4229 #if defined(CONFIG_USER_ONLY)
4230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4231 #else
4232 if (unlikely(ctx->pr)) {
4233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4234 return;
4235 }
4236 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4237 #endif
4238 }
4239
4240 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4241 {
4242 #if 0
4243 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4244 printf("ERROR: try to access SPR %d !\n", sprn);
4245 #endif
4246 }
4247 #define SPR_NOACCESS (&spr_noaccess)
4248
4249 /* mfspr */
4250 static inline void gen_op_mfspr(DisasContext *ctx)
4251 {
4252 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4253 uint32_t sprn = SPR(ctx->opcode);
4254
4255 #if defined(CONFIG_USER_ONLY)
4256 read_cb = ctx->spr_cb[sprn].uea_read;
4257 #else
4258 if (ctx->pr) {
4259 read_cb = ctx->spr_cb[sprn].uea_read;
4260 } else if (ctx->hv) {
4261 read_cb = ctx->spr_cb[sprn].hea_read;
4262 } else {
4263 read_cb = ctx->spr_cb[sprn].oea_read;
4264 }
4265 #endif
4266 if (likely(read_cb != NULL)) {
4267 if (likely(read_cb != SPR_NOACCESS)) {
4268 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4269 } else {
4270 /* Privilege exception */
4271 /* This is a hack to avoid warnings when running Linux:
4272 * this OS breaks the PowerPC virtualisation model,
4273 * allowing userland application to read the PVR
4274 */
4275 if (sprn != SPR_PVR) {
4276 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4277 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4278 if (qemu_log_separate()) {
4279 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4280 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4281 }
4282 }
4283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4284 }
4285 } else {
4286 /* Not defined */
4287 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4288 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4289 if (qemu_log_separate()) {
4290 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4291 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4292 }
4293 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4294 }
4295 }
4296
4297 static void gen_mfspr(DisasContext *ctx)
4298 {
4299 gen_op_mfspr(ctx);
4300 }
4301
4302 /* mftb */
4303 static void gen_mftb(DisasContext *ctx)
4304 {
4305 gen_op_mfspr(ctx);
4306 }
4307
4308 /* mtcrf mtocrf*/
4309 static void gen_mtcrf(DisasContext *ctx)
4310 {
4311 uint32_t crm, crn;
4312
4313 crm = CRM(ctx->opcode);
4314 if (likely((ctx->opcode & 0x00100000))) {
4315 if (crm && ((crm & (crm - 1)) == 0)) {
4316 TCGv_i32 temp = tcg_temp_new_i32();
4317 crn = ctz32 (crm);
4318 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4319 tcg_gen_shri_i32(temp, temp, crn * 4);
4320 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4321 tcg_temp_free_i32(temp);
4322 }
4323 } else {
4324 TCGv_i32 temp = tcg_temp_new_i32();
4325 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4326 for (crn = 0 ; crn < 8 ; crn++) {
4327 if (crm & (1 << crn)) {
4328 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4329 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4330 }
4331 }
4332 tcg_temp_free_i32(temp);
4333 }
4334 }
4335
4336 /* mtmsr */
4337 #if defined(TARGET_PPC64)
4338 static void gen_mtmsrd(DisasContext *ctx)
4339 {
4340 #if defined(CONFIG_USER_ONLY)
4341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4342 #else
4343 if (unlikely(ctx->pr)) {
4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4345 return;
4346 }
4347 if (ctx->opcode & 0x00010000) {
4348 /* Special form that does not need any synchronisation */
4349 TCGv t0 = tcg_temp_new();
4350 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4351 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4352 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4353 tcg_temp_free(t0);
4354 } else {
4355 /* XXX: we need to update nip before the store
4356 * if we enter power saving mode, we will exit the loop
4357 * directly from ppc_store_msr
4358 */
4359 gen_update_nip(ctx, ctx->nip);
4360 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4361 /* Must stop the translation as machine state (may have) changed */
4362 /* Note that mtmsr is not always defined as context-synchronizing */
4363 gen_stop_exception(ctx);
4364 }
4365 #endif
4366 }
4367 #endif
4368
4369 static void gen_mtmsr(DisasContext *ctx)
4370 {
4371 #if defined(CONFIG_USER_ONLY)
4372 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4373 #else
4374 if (unlikely(ctx->pr)) {
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4376 return;
4377 }
4378 if (ctx->opcode & 0x00010000) {
4379 /* Special form that does not need any synchronisation */
4380 TCGv t0 = tcg_temp_new();
4381 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4382 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4383 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4384 tcg_temp_free(t0);
4385 } else {
4386 TCGv msr = tcg_temp_new();
4387
4388 /* XXX: we need to update nip before the store
4389 * if we enter power saving mode, we will exit the loop
4390 * directly from ppc_store_msr
4391 */
4392 gen_update_nip(ctx, ctx->nip);
4393 #if defined(TARGET_PPC64)
4394 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4395 #else
4396 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4397 #endif
4398 gen_helper_store_msr(cpu_env, msr);
4399 tcg_temp_free(msr);
4400 /* Must stop the translation as machine state (may have) changed */
4401 /* Note that mtmsr is not always defined as context-synchronizing */
4402 gen_stop_exception(ctx);
4403 }
4404 #endif
4405 }
4406
4407 /* mtspr */
4408 static void gen_mtspr(DisasContext *ctx)
4409 {
4410 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4411 uint32_t sprn = SPR(ctx->opcode);
4412
4413 #if defined(CONFIG_USER_ONLY)
4414 write_cb = ctx->spr_cb[sprn].uea_write;
4415 #else
4416 if (ctx->pr) {
4417 write_cb = ctx->spr_cb[sprn].uea_write;
4418 } else if (ctx->hv) {
4419 write_cb = ctx->spr_cb[sprn].hea_write;
4420 } else {
4421 write_cb = ctx->spr_cb[sprn].oea_write;
4422 }
4423 #endif
4424 if (likely(write_cb != NULL)) {
4425 if (likely(write_cb != SPR_NOACCESS)) {
4426 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4427 } else {
4428 /* Privilege exception */
4429 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4430 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4431 if (qemu_log_separate()) {
4432 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4433 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4434 }
4435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4436 }
4437 } else {
4438 /* Not defined */
4439 if (qemu_log_separate()) {
4440 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4441 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4442 }
4443 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4444 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4445 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4446 }
4447 }
4448
4449 /*** Cache management ***/
4450
4451 /* dcbf */
4452 static void gen_dcbf(DisasContext *ctx)
4453 {
4454 /* XXX: specification says this is treated as a load by the MMU */
4455 TCGv t0;
4456 gen_set_access_type(ctx, ACCESS_CACHE);
4457 t0 = tcg_temp_new();
4458 gen_addr_reg_index(ctx, t0);
4459 gen_qemu_ld8u(ctx, t0, t0);
4460 tcg_temp_free(t0);
4461 }
4462
4463 /* dcbi (Supervisor only) */
4464 static void gen_dcbi(DisasContext *ctx)
4465 {
4466 #if defined(CONFIG_USER_ONLY)
4467 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4468 #else
4469 TCGv EA, val;
4470 if (unlikely(ctx->pr)) {
4471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4472 return;
4473 }
4474 EA = tcg_temp_new();
4475 gen_set_access_type(ctx, ACCESS_CACHE);
4476 gen_addr_reg_index(ctx, EA);
4477 val = tcg_temp_new();
4478 /* XXX: specification says this should be treated as a store by the MMU */
4479 gen_qemu_ld8u(ctx, val, EA);
4480 gen_qemu_st8(ctx, val, EA);
4481 tcg_temp_free(val);
4482 tcg_temp_free(EA);
4483 #endif
4484 }
4485
4486 /* dcdst */
4487 static void gen_dcbst(DisasContext *ctx)
4488 {
4489 /* XXX: specification say this is treated as a load by the MMU */
4490 TCGv t0;
4491 gen_set_access_type(ctx, ACCESS_CACHE);
4492 t0 = tcg_temp_new();
4493 gen_addr_reg_index(ctx, t0);
4494 gen_qemu_ld8u(ctx, t0, t0);
4495 tcg_temp_free(t0);
4496 }
4497
4498 /* dcbt */
4499 static void gen_dcbt(DisasContext *ctx)
4500 {
4501 /* interpreted as no-op */
4502 /* XXX: specification say this is treated as a load by the MMU
4503 * but does not generate any exception
4504 */
4505 }
4506
4507 /* dcbtst */
4508 static void gen_dcbtst(DisasContext *ctx)
4509 {
4510 /* interpreted as no-op */
4511 /* XXX: specification say this is treated as a load by the MMU
4512 * but does not generate any exception
4513 */
4514 }
4515
4516 /* dcbtls */
4517 static void gen_dcbtls(DisasContext *ctx)
4518 {
4519 /* Always fails locking the cache */
4520 TCGv t0 = tcg_temp_new();
4521 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4522 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4523 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4524 tcg_temp_free(t0);
4525 }
4526
4527 /* dcbz */
4528 static void gen_dcbz(DisasContext *ctx)
4529 {
4530 TCGv tcgv_addr;
4531 TCGv_i32 tcgv_is_dcbzl;
4532 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4533
4534 gen_set_access_type(ctx, ACCESS_CACHE);
4535 /* NIP cannot be restored if the memory exception comes from an helper */
4536 gen_update_nip(ctx, ctx->nip - 4);
4537 tcgv_addr = tcg_temp_new();
4538 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4539
4540 gen_addr_reg_index(ctx, tcgv_addr);
4541 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4542
4543 tcg_temp_free(tcgv_addr);
4544 tcg_temp_free_i32(tcgv_is_dcbzl);
4545 }
4546
4547 /* dst / dstt */
4548 static void gen_dst(DisasContext *ctx)
4549 {
4550 if (rA(ctx->opcode) == 0) {
4551 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4552 } else {
4553 /* interpreted as no-op */
4554 }
4555 }
4556
4557 /* dstst /dststt */
4558 static void gen_dstst(DisasContext *ctx)
4559 {
4560 if (rA(ctx->opcode) == 0) {
4561 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4562 } else {
4563 /* interpreted as no-op */
4564 }
4565
4566 }
4567
4568 /* dss / dssall */
4569 static void gen_dss(DisasContext *ctx)
4570 {
4571 /* interpreted as no-op */
4572 }
4573
4574 /* icbi */
4575 static void gen_icbi(DisasContext *ctx)
4576 {
4577 TCGv t0;
4578 gen_set_access_type(ctx, ACCESS_CACHE);
4579 /* NIP cannot be restored if the memory exception comes from an helper */
4580 gen_update_nip(ctx, ctx->nip - 4);
4581 t0 = tcg_temp_new();
4582 gen_addr_reg_index(ctx, t0);
4583 gen_helper_icbi(cpu_env, t0);
4584 tcg_temp_free(t0);
4585 }
4586
4587 /* Optional: */
4588 /* dcba */
4589 static void gen_dcba(DisasContext *ctx)
4590 {
4591 /* interpreted as no-op */
4592 /* XXX: specification say this is treated as a store by the MMU
4593 * but does not generate any exception
4594 */
4595 }
4596
4597 /*** Segment register manipulation ***/
4598 /* Supervisor only: */
4599
4600 /* mfsr */
4601 static void gen_mfsr(DisasContext *ctx)
4602 {
4603 #if defined(CONFIG_USER_ONLY)
4604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4605 #else
4606 TCGv t0;
4607 if (unlikely(ctx->pr)) {
4608 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4609 return;
4610 }
4611 t0 = tcg_const_tl(SR(ctx->opcode));
4612 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4613 tcg_temp_free(t0);
4614 #endif
4615 }
4616
4617 /* mfsrin */
4618 static void gen_mfsrin(DisasContext *ctx)
4619 {
4620 #if defined(CONFIG_USER_ONLY)
4621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4622 #else
4623 TCGv t0;
4624 if (unlikely(ctx->pr)) {
4625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4626 return;
4627 }
4628 t0 = tcg_temp_new();
4629 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4630 tcg_gen_andi_tl(t0, t0, 0xF);
4631 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4632 tcg_temp_free(t0);
4633 #endif
4634 }
4635
4636 /* mtsr */
4637 static void gen_mtsr(DisasContext *ctx)
4638 {
4639 #if defined(CONFIG_USER_ONLY)
4640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4641 #else
4642 TCGv t0;
4643 if (unlikely(ctx->pr)) {
4644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4645 return;
4646 }
4647 t0 = tcg_const_tl(SR(ctx->opcode));
4648 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4649 tcg_temp_free(t0);
4650 #endif
4651 }
4652
4653 /* mtsrin */
4654 static void gen_mtsrin(DisasContext *ctx)
4655 {
4656 #if defined(CONFIG_USER_ONLY)
4657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4658 #else
4659 TCGv t0;
4660 if (unlikely(ctx->pr)) {
4661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4662 return;
4663 }
4664 t0 = tcg_temp_new();
4665 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4666 tcg_gen_andi_tl(t0, t0, 0xF);
4667 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4668 tcg_temp_free(t0);
4669 #endif
4670 }
4671
4672 #if defined(TARGET_PPC64)
4673 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4674
4675 /* mfsr */
4676 static void gen_mfsr_64b(DisasContext *ctx)
4677 {
4678 #if defined(CONFIG_USER_ONLY)
4679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4680 #else
4681 TCGv t0;
4682 if (unlikely(ctx->pr)) {
4683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4684 return;
4685 }
4686 t0 = tcg_const_tl(SR(ctx->opcode));
4687 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4688 tcg_temp_free(t0);
4689 #endif
4690 }
4691
4692 /* mfsrin */
4693 static void gen_mfsrin_64b(DisasContext *ctx)
4694 {
4695 #if defined(CONFIG_USER_ONLY)
4696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4697 #else
4698 TCGv t0;
4699 if (unlikely(ctx->pr)) {
4700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4701 return;
4702 }
4703 t0 = tcg_temp_new();
4704 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4705 tcg_gen_andi_tl(t0, t0, 0xF);
4706 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4707 tcg_temp_free(t0);
4708 #endif
4709 }
4710
4711 /* mtsr */
4712 static void gen_mtsr_64b(DisasContext *ctx)
4713 {
4714 #if defined(CONFIG_USER_ONLY)
4715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4716 #else
4717 TCGv t0;
4718 if (unlikely(ctx->pr)) {
4719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4720 return;
4721 }
4722 t0 = tcg_const_tl(SR(ctx->opcode));
4723 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4724 tcg_temp_free(t0);
4725 #endif
4726 }
4727
4728 /* mtsrin */
4729 static void gen_mtsrin_64b(DisasContext *ctx)
4730 {
4731 #if defined(CONFIG_USER_ONLY)
4732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4733 #else
4734 TCGv t0;
4735 if (unlikely(ctx->pr)) {
4736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4737 return;
4738 }
4739 t0 = tcg_temp_new();
4740 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4741 tcg_gen_andi_tl(t0, t0, 0xF);
4742 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4743 tcg_temp_free(t0);
4744 #endif
4745 }
4746
4747 /* slbmte */
4748 static void gen_slbmte(DisasContext *ctx)
4749 {
4750 #if defined(CONFIG_USER_ONLY)
4751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4752 #else
4753 if (unlikely(ctx->pr)) {
4754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4755 return;
4756 }
4757 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4758 cpu_gpr[rS(ctx->opcode)]);
4759 #endif
4760 }
4761
4762 static void gen_slbmfee(DisasContext *ctx)
4763 {
4764 #if defined(CONFIG_USER_ONLY)
4765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4766 #else
4767 if (unlikely(ctx->pr)) {
4768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4769 return;
4770 }
4771 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4772 cpu_gpr[rB(ctx->opcode)]);
4773 #endif
4774 }
4775
4776 static void gen_slbmfev(DisasContext *ctx)
4777 {
4778 #if defined(CONFIG_USER_ONLY)
4779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4780 #else
4781 if (unlikely(ctx->pr)) {
4782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4783 return;
4784 }
4785 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4786 cpu_gpr[rB(ctx->opcode)]);
4787 #endif
4788 }
4789 #endif /* defined(TARGET_PPC64) */
4790
4791 /*** Lookaside buffer management ***/
4792 /* Optional & supervisor only: */
4793
4794 /* tlbia */
4795 static void gen_tlbia(DisasContext *ctx)
4796 {
4797 #if defined(CONFIG_USER_ONLY)
4798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4799 #else
4800 if (unlikely(ctx->pr)) {
4801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4802 return;
4803 }
4804 gen_helper_tlbia(cpu_env);
4805 #endif
4806 }
4807
4808 /* tlbiel */
4809 static void gen_tlbiel(DisasContext *ctx)
4810 {
4811 #if defined(CONFIG_USER_ONLY)
4812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4813 #else
4814 if (unlikely(ctx->pr)) {
4815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4816 return;
4817 }
4818 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4819 #endif
4820 }
4821
4822 /* tlbie */
4823 static void gen_tlbie(DisasContext *ctx)
4824 {
4825 #if defined(CONFIG_USER_ONLY)
4826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4827 #else
4828 if (unlikely(ctx->pr)) {
4829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4830 return;
4831 }
4832 if (NARROW_MODE(ctx)) {
4833 TCGv t0 = tcg_temp_new();
4834 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4835 gen_helper_tlbie(cpu_env, t0);
4836 tcg_temp_free(t0);
4837 } else {
4838 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4839 }
4840 #endif
4841 }
4842
4843 /* tlbsync */
4844 static void gen_tlbsync(DisasContext *ctx)
4845 {
4846 #if defined(CONFIG_USER_ONLY)
4847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4848 #else
4849 if (unlikely(ctx->pr)) {
4850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4851 return;
4852 }
4853 /* This has no effect: it should ensure that all previous
4854 * tlbie have completed
4855 */
4856 gen_stop_exception(ctx);
4857 #endif
4858 }
4859
4860 #if defined(TARGET_PPC64)
4861 /* slbia */
4862 static void gen_slbia(DisasContext *ctx)
4863 {
4864 #if defined(CONFIG_USER_ONLY)
4865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4866 #else
4867 if (unlikely(ctx->pr)) {
4868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4869 return;
4870 }
4871 gen_helper_slbia(cpu_env);
4872 #endif
4873 }
4874
4875 /* slbie */
4876 static void gen_slbie(DisasContext *ctx)
4877 {
4878 #if defined(CONFIG_USER_ONLY)
4879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4880 #else
4881 if (unlikely(ctx->pr)) {
4882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4883 return;
4884 }
4885 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4886 #endif
4887 }
4888 #endif
4889
4890 /*** External control ***/
4891 /* Optional: */
4892
4893 /* eciwx */
4894 static void gen_eciwx(DisasContext *ctx)
4895 {
4896 TCGv t0;
4897 /* Should check EAR[E] ! */
4898 gen_set_access_type(ctx, ACCESS_EXT);
4899 t0 = tcg_temp_new();
4900 gen_addr_reg_index(ctx, t0);
4901 gen_check_align(ctx, t0, 0x03);
4902 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4903 tcg_temp_free(t0);
4904 }
4905
4906 /* ecowx */
4907 static void gen_ecowx(DisasContext *ctx)
4908 {
4909 TCGv t0;
4910 /* Should check EAR[E] ! */
4911 gen_set_access_type(ctx, ACCESS_EXT);
4912 t0 = tcg_temp_new();
4913 gen_addr_reg_index(ctx, t0);
4914 gen_check_align(ctx, t0, 0x03);
4915 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4916 tcg_temp_free(t0);
4917 }
4918
4919 /* PowerPC 601 specific instructions */
4920
4921 /* abs - abs. */
4922 static void gen_abs(DisasContext *ctx)
4923 {
4924 TCGLabel *l1 = gen_new_label();
4925 TCGLabel *l2 = gen_new_label();
4926 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4927 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4928 tcg_gen_br(l2);
4929 gen_set_label(l1);
4930 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4931 gen_set_label(l2);
4932 if (unlikely(Rc(ctx->opcode) != 0))
4933 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4934 }
4935
4936 /* abso - abso. */
4937 static void gen_abso(DisasContext *ctx)
4938 {
4939 TCGLabel *l1 = gen_new_label();
4940 TCGLabel *l2 = gen_new_label();
4941 TCGLabel *l3 = gen_new_label();
4942 /* Start with XER OV disabled, the most likely case */
4943 tcg_gen_movi_tl(cpu_ov, 0);
4944 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4945 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4946 tcg_gen_movi_tl(cpu_ov, 1);
4947 tcg_gen_movi_tl(cpu_so, 1);
4948 tcg_gen_br(l2);
4949 gen_set_label(l1);
4950 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4951 tcg_gen_br(l3);
4952 gen_set_label(l2);
4953 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4954 gen_set_label(l3);
4955 if (unlikely(Rc(ctx->opcode) != 0))
4956 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4957 }
4958
4959 /* clcs */
4960 static void gen_clcs(DisasContext *ctx)
4961 {
4962 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4963 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4964 tcg_temp_free_i32(t0);
4965 /* Rc=1 sets CR0 to an undefined state */
4966 }
4967
4968 /* div - div. */
4969 static void gen_div(DisasContext *ctx)
4970 {
4971 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4972 cpu_gpr[rB(ctx->opcode)]);
4973 if (unlikely(Rc(ctx->opcode) != 0))
4974 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4975 }
4976
4977 /* divo - divo. */
4978 static void gen_divo(DisasContext *ctx)
4979 {
4980 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4981 cpu_gpr[rB(ctx->opcode)]);
4982 if (unlikely(Rc(ctx->opcode) != 0))
4983 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4984 }
4985
4986 /* divs - divs. */
4987 static void gen_divs(DisasContext *ctx)
4988 {
4989 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4990 cpu_gpr[rB(ctx->opcode)]);
4991 if (unlikely(Rc(ctx->opcode) != 0))
4992 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4993 }
4994
4995 /* divso - divso. */
4996 static void gen_divso(DisasContext *ctx)
4997 {
4998 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4999 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5002 }
5003
5004 /* doz - doz. */
5005 static void gen_doz(DisasContext *ctx)
5006 {
5007 TCGLabel *l1 = gen_new_label();
5008 TCGLabel *l2 = gen_new_label();
5009 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5010 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5011 tcg_gen_br(l2);
5012 gen_set_label(l1);
5013 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5014 gen_set_label(l2);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5017 }
5018
5019 /* dozo - dozo. */
5020 static void gen_dozo(DisasContext *ctx)
5021 {
5022 TCGLabel *l1 = gen_new_label();
5023 TCGLabel *l2 = gen_new_label();
5024 TCGv t0 = tcg_temp_new();
5025 TCGv t1 = tcg_temp_new();
5026 TCGv t2 = tcg_temp_new();
5027 /* Start with XER OV disabled, the most likely case */
5028 tcg_gen_movi_tl(cpu_ov, 0);
5029 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5030 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5031 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5032 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5033 tcg_gen_andc_tl(t1, t1, t2);
5034 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5035 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5036 tcg_gen_movi_tl(cpu_ov, 1);
5037 tcg_gen_movi_tl(cpu_so, 1);
5038 tcg_gen_br(l2);
5039 gen_set_label(l1);
5040 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5041 gen_set_label(l2);
5042 tcg_temp_free(t0);
5043 tcg_temp_free(t1);
5044 tcg_temp_free(t2);
5045 if (unlikely(Rc(ctx->opcode) != 0))
5046 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5047 }
5048
5049 /* dozi */
5050 static void gen_dozi(DisasContext *ctx)
5051 {
5052 target_long simm = SIMM(ctx->opcode);
5053 TCGLabel *l1 = gen_new_label();
5054 TCGLabel *l2 = gen_new_label();
5055 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5056 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5057 tcg_gen_br(l2);
5058 gen_set_label(l1);
5059 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5060 gen_set_label(l2);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5063 }
5064
5065 /* lscbx - lscbx. */
5066 static void gen_lscbx(DisasContext *ctx)
5067 {
5068 TCGv t0 = tcg_temp_new();
5069 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5070 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5071 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5072
5073 gen_addr_reg_index(ctx, t0);
5074 /* NIP cannot be restored if the memory exception comes from an helper */
5075 gen_update_nip(ctx, ctx->nip - 4);
5076 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5077 tcg_temp_free_i32(t1);
5078 tcg_temp_free_i32(t2);
5079 tcg_temp_free_i32(t3);
5080 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5081 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5082 if (unlikely(Rc(ctx->opcode) != 0))
5083 gen_set_Rc0(ctx, t0);
5084 tcg_temp_free(t0);
5085 }
5086
5087 /* maskg - maskg. */
5088 static void gen_maskg(DisasContext *ctx)
5089 {
5090 TCGLabel *l1 = gen_new_label();
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 TCGv t2 = tcg_temp_new();
5094 TCGv t3 = tcg_temp_new();
5095 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5096 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5097 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5098 tcg_gen_addi_tl(t2, t0, 1);
5099 tcg_gen_shr_tl(t2, t3, t2);
5100 tcg_gen_shr_tl(t3, t3, t1);
5101 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5102 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5103 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5104 gen_set_label(l1);
5105 tcg_temp_free(t0);
5106 tcg_temp_free(t1);
5107 tcg_temp_free(t2);
5108 tcg_temp_free(t3);
5109 if (unlikely(Rc(ctx->opcode) != 0))
5110 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5111 }
5112
5113 /* maskir - maskir. */
5114 static void gen_maskir(DisasContext *ctx)
5115 {
5116 TCGv t0 = tcg_temp_new();
5117 TCGv t1 = tcg_temp_new();
5118 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5119 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5120 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5121 tcg_temp_free(t0);
5122 tcg_temp_free(t1);
5123 if (unlikely(Rc(ctx->opcode) != 0))
5124 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5125 }
5126
5127 /* mul - mul. */
5128 static void gen_mul(DisasContext *ctx)
5129 {
5130 TCGv_i64 t0 = tcg_temp_new_i64();
5131 TCGv_i64 t1 = tcg_temp_new_i64();
5132 TCGv t2 = tcg_temp_new();
5133 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5134 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5135 tcg_gen_mul_i64(t0, t0, t1);
5136 tcg_gen_trunc_i64_tl(t2, t0);
5137 gen_store_spr(SPR_MQ, t2);
5138 tcg_gen_shri_i64(t1, t0, 32);
5139 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5140 tcg_temp_free_i64(t0);
5141 tcg_temp_free_i64(t1);
5142 tcg_temp_free(t2);
5143 if (unlikely(Rc(ctx->opcode) != 0))
5144 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5145 }
5146
5147 /* mulo - mulo. */
5148 static void gen_mulo(DisasContext *ctx)
5149 {
5150 TCGLabel *l1 = gen_new_label();
5151 TCGv_i64 t0 = tcg_temp_new_i64();
5152 TCGv_i64 t1 = tcg_temp_new_i64();
5153 TCGv t2 = tcg_temp_new();
5154 /* Start with XER OV disabled, the most likely case */
5155 tcg_gen_movi_tl(cpu_ov, 0);
5156 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5157 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5158 tcg_gen_mul_i64(t0, t0, t1);
5159 tcg_gen_trunc_i64_tl(t2, t0);
5160 gen_store_spr(SPR_MQ, t2);
5161 tcg_gen_shri_i64(t1, t0, 32);
5162 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5163 tcg_gen_ext32s_i64(t1, t0);
5164 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5165 tcg_gen_movi_tl(cpu_ov, 1);
5166 tcg_gen_movi_tl(cpu_so, 1);
5167 gen_set_label(l1);
5168 tcg_temp_free_i64(t0);
5169 tcg_temp_free_i64(t1);
5170 tcg_temp_free(t2);
5171 if (unlikely(Rc(ctx->opcode) != 0))
5172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5173 }
5174
5175 /* nabs - nabs. */
5176 static void gen_nabs(DisasContext *ctx)
5177 {
5178 TCGLabel *l1 = gen_new_label();
5179 TCGLabel *l2 = gen_new_label();
5180 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5181 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5182 tcg_gen_br(l2);
5183 gen_set_label(l1);
5184 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5185 gen_set_label(l2);
5186 if (unlikely(Rc(ctx->opcode) != 0))
5187 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5188 }
5189
5190 /* nabso - nabso. */
5191 static void gen_nabso(DisasContext *ctx)
5192 {
5193 TCGLabel *l1 = gen_new_label();
5194 TCGLabel *l2 = gen_new_label();
5195 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5196 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5197 tcg_gen_br(l2);
5198 gen_set_label(l1);
5199 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5200 gen_set_label(l2);
5201 /* nabs never overflows */
5202 tcg_gen_movi_tl(cpu_ov, 0);
5203 if (unlikely(Rc(ctx->opcode) != 0))
5204 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5205 }
5206
5207 /* rlmi - rlmi. */
5208 static void gen_rlmi(DisasContext *ctx)
5209 {
5210 uint32_t mb = MB(ctx->opcode);
5211 uint32_t me = ME(ctx->opcode);
5212 TCGv t0 = tcg_temp_new();
5213 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5214 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5215 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5216 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5217 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5218 tcg_temp_free(t0);
5219 if (unlikely(Rc(ctx->opcode) != 0))
5220 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5221 }
5222
5223 /* rrib - rrib. */
5224 static void gen_rrib(DisasContext *ctx)
5225 {
5226 TCGv t0 = tcg_temp_new();
5227 TCGv t1 = tcg_temp_new();
5228 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5229 tcg_gen_movi_tl(t1, 0x80000000);
5230 tcg_gen_shr_tl(t1, t1, t0);
5231 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5232 tcg_gen_and_tl(t0, t0, t1);
5233 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5234 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5235 tcg_temp_free(t0);
5236 tcg_temp_free(t1);
5237 if (unlikely(Rc(ctx->opcode) != 0))
5238 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5239 }
5240
5241 /* sle - sle. */
5242 static void gen_sle(DisasContext *ctx)
5243 {
5244 TCGv t0 = tcg_temp_new();
5245 TCGv t1 = tcg_temp_new();
5246 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5247 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5248 tcg_gen_subfi_tl(t1, 32, t1);
5249 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5250 tcg_gen_or_tl(t1, t0, t1);
5251 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5252 gen_store_spr(SPR_MQ, t1);
5253 tcg_temp_free(t0);
5254 tcg_temp_free(t1);
5255 if (unlikely(Rc(ctx->opcode) != 0))
5256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5257 }
5258
5259 /* sleq - sleq. */
5260 static void gen_sleq(DisasContext *ctx)
5261 {
5262 TCGv t0 = tcg_temp_new();
5263 TCGv t1 = tcg_temp_new();
5264 TCGv t2 = tcg_temp_new();
5265 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5266 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5267 tcg_gen_shl_tl(t2, t2, t0);
5268 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5269 gen_load_spr(t1, SPR_MQ);
5270 gen_store_spr(SPR_MQ, t0);
5271 tcg_gen_and_tl(t0, t0, t2);
5272 tcg_gen_andc_tl(t1, t1, t2);
5273 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5274 tcg_temp_free(t0);
5275 tcg_temp_free(t1);
5276 tcg_temp_free(t2);
5277 if (unlikely(Rc(ctx->opcode) != 0))
5278 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5279 }
5280
5281 /* sliq - sliq. */
5282 static void gen_sliq(DisasContext *ctx)
5283 {
5284 int sh = SH(ctx->opcode);
5285 TCGv t0 = tcg_temp_new();
5286 TCGv t1 = tcg_temp_new();
5287 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5288 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5289 tcg_gen_or_tl(t1, t0, t1);
5290 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5291 gen_store_spr(SPR_MQ, t1);
5292 tcg_temp_free(t0);
5293 tcg_temp_free(t1);
5294 if (unlikely(Rc(ctx->opcode) != 0))
5295 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5296 }
5297
5298 /* slliq - slliq. */
5299 static void gen_slliq(DisasContext *ctx)
5300 {
5301 int sh = SH(ctx->opcode);
5302 TCGv t0 = tcg_temp_new();
5303 TCGv t1 = tcg_temp_new();
5304 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5305 gen_load_spr(t1, SPR_MQ);
5306 gen_store_spr(SPR_MQ, t0);
5307 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5308 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5309 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5310 tcg_temp_free(t0);
5311 tcg_temp_free(t1);
5312 if (unlikely(Rc(ctx->opcode) != 0))
5313 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5314 }
5315
5316 /* sllq - sllq. */
5317 static void gen_sllq(DisasContext *ctx)
5318 {
5319 TCGLabel *l1 = gen_new_label();
5320 TCGLabel *l2 = gen_new_label();
5321 TCGv t0 = tcg_temp_local_new();
5322 TCGv t1 = tcg_temp_local_new();
5323 TCGv t2 = tcg_temp_local_new();
5324 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5325 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5326 tcg_gen_shl_tl(t1, t1, t2);
5327 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5328 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5329 gen_load_spr(t0, SPR_MQ);
5330 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5331 tcg_gen_br(l2);
5332 gen_set_label(l1);
5333 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5334 gen_load_spr(t2, SPR_MQ);
5335 tcg_gen_andc_tl(t1, t2, t1);
5336 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5337 gen_set_label(l2);
5338 tcg_temp_free(t0);
5339 tcg_temp_free(t1);
5340 tcg_temp_free(t2);
5341 if (unlikely(Rc(ctx->opcode) != 0))
5342 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5343 }
5344
5345 /* slq - slq. */
5346 static void gen_slq(DisasContext *ctx)
5347 {
5348 TCGLabel *l1 = gen_new_label();
5349 TCGv t0 = tcg_temp_new();
5350 TCGv t1 = tcg_temp_new();
5351 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5352 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5353 tcg_gen_subfi_tl(t1, 32, t1);
5354 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5355 tcg_gen_or_tl(t1, t0, t1);
5356 gen_store_spr(SPR_MQ, t1);
5357 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5358 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5359 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5360 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5361 gen_set_label(l1);
5362 tcg_temp_free(t0);
5363 tcg_temp_free(t1);
5364 if (unlikely(Rc(ctx->opcode) != 0))
5365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5366 }
5367
5368 /* sraiq - sraiq. */
5369 static void gen_sraiq(DisasContext *ctx)
5370 {
5371 int sh = SH(ctx->opcode);
5372 TCGLabel *l1 = gen_new_label();
5373 TCGv t0 = tcg_temp_new();
5374 TCGv t1 = tcg_temp_new();
5375 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5376 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5377 tcg_gen_or_tl(t0, t0, t1);
5378 gen_store_spr(SPR_MQ, t0);
5379 tcg_gen_movi_tl(cpu_ca, 0);
5380 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5381 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5382 tcg_gen_movi_tl(cpu_ca, 1);
5383 gen_set_label(l1);
5384 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5385 tcg_temp_free(t0);
5386 tcg_temp_free(t1);
5387 if (unlikely(Rc(ctx->opcode) != 0))
5388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5389 }
5390
5391 /* sraq - sraq. */
5392 static void gen_sraq(DisasContext *ctx)
5393 {
5394 TCGLabel *l1 = gen_new_label();
5395 TCGLabel *l2 = gen_new_label();
5396 TCGv t0 = tcg_temp_new();
5397 TCGv t1 = tcg_temp_local_new();
5398 TCGv t2 = tcg_temp_local_new();
5399 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5400 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5401 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5402 tcg_gen_subfi_tl(t2, 32, t2);
5403 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5404 tcg_gen_or_tl(t0, t0, t2);
5405 gen_store_spr(SPR_MQ, t0);
5406 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5407 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5408 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5409 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5410 gen_set_label(l1);
5411 tcg_temp_free(t0);
5412 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5413 tcg_gen_movi_tl(cpu_ca, 0);
5414 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5415 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5416 tcg_gen_movi_tl(cpu_ca, 1);
5417 gen_set_label(l2);
5418 tcg_temp_free(t1);
5419 tcg_temp_free(t2);
5420 if (unlikely(Rc(ctx->opcode) != 0))
5421 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5422 }
5423
5424 /* sre - sre. */
5425 static void gen_sre(DisasContext *ctx)
5426 {
5427 TCGv t0 = tcg_temp_new();
5428 TCGv t1 = tcg_temp_new();
5429 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5430 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5431 tcg_gen_subfi_tl(t1, 32, t1);
5432 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5433 tcg_gen_or_tl(t1, t0, t1);
5434 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5435 gen_store_spr(SPR_MQ, t1);
5436 tcg_temp_free(t0);
5437 tcg_temp_free(t1);
5438 if (unlikely(Rc(ctx->opcode) != 0))
5439 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5440 }
5441
5442 /* srea - srea. */
5443 static void gen_srea(DisasContext *ctx)
5444 {
5445 TCGv t0 = tcg_temp_new();
5446 TCGv t1 = tcg_temp_new();
5447 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5448 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5449 gen_store_spr(SPR_MQ, t0);
5450 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5451 tcg_temp_free(t0);
5452 tcg_temp_free(t1);
5453 if (unlikely(Rc(ctx->opcode) != 0))
5454 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5455 }
5456
5457 /* sreq */
5458 static void gen_sreq(DisasContext *ctx)
5459 {
5460 TCGv t0 = tcg_temp_new();
5461 TCGv t1 = tcg_temp_new();
5462 TCGv t2 = tcg_temp_new();
5463 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5464 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5465 tcg_gen_shr_tl(t1, t1, t0);
5466 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5467 gen_load_spr(t2, SPR_MQ);
5468 gen_store_spr(SPR_MQ, t0);
5469 tcg_gen_and_tl(t0, t0, t1);
5470 tcg_gen_andc_tl(t2, t2, t1);
5471 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5472 tcg_temp_free(t0);
5473 tcg_temp_free(t1);
5474 tcg_temp_free(t2);
5475 if (unlikely(Rc(ctx->opcode) != 0))
5476 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5477 }
5478
5479 /* sriq */
5480 static void gen_sriq(DisasContext *ctx)
5481 {
5482 int sh = SH(ctx->opcode);
5483 TCGv t0 = tcg_temp_new();
5484 TCGv t1 = tcg_temp_new();
5485 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5486 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5487 tcg_gen_or_tl(t1, t0, t1);
5488 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5489 gen_store_spr(SPR_MQ, t1);
5490 tcg_temp_free(t0);
5491 tcg_temp_free(t1);
5492 if (unlikely(Rc(ctx->opcode) != 0))
5493 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5494 }
5495
5496 /* srliq */
5497 static void gen_srliq(DisasContext *ctx)
5498 {
5499 int sh = SH(ctx->opcode);
5500 TCGv t0 = tcg_temp_new();
5501 TCGv t1 = tcg_temp_new();
5502 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5503 gen_load_spr(t1, SPR_MQ);
5504 gen_store_spr(SPR_MQ, t0);
5505 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5506 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5507 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5508 tcg_temp_free(t0);
5509 tcg_temp_free(t1);
5510 if (unlikely(Rc(ctx->opcode) != 0))
5511 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5512 }
5513
5514 /* srlq */
5515 static void gen_srlq(DisasContext *ctx)
5516 {
5517 TCGLabel *l1 = gen_new_label();
5518 TCGLabel *l2 = gen_new_label();
5519 TCGv t0 = tcg_temp_local_new();
5520 TCGv t1 = tcg_temp_local_new();
5521 TCGv t2 = tcg_temp_local_new();
5522 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5523 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5524 tcg_gen_shr_tl(t2, t1, t2);
5525 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5526 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5527 gen_load_spr(t0, SPR_MQ);
5528 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5529 tcg_gen_br(l2);
5530 gen_set_label(l1);
5531 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5532 tcg_gen_and_tl(t0, t0, t2);
5533 gen_load_spr(t1, SPR_MQ);
5534 tcg_gen_andc_tl(t1, t1, t2);
5535 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5536 gen_set_label(l2);
5537 tcg_temp_free(t0);
5538 tcg_temp_free(t1);
5539 tcg_temp_free(t2);
5540 if (unlikely(Rc(ctx->opcode) != 0))
5541 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5542 }
5543
5544 /* srq */
5545 static void gen_srq(DisasContext *ctx)
5546 {
5547 TCGLabel *l1 = gen_new_label();
5548 TCGv t0 = tcg_temp_new();
5549 TCGv t1 = tcg_temp_new();
5550 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5551 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5552 tcg_gen_subfi_tl(t1, 32, t1);
5553 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5554 tcg_gen_or_tl(t1, t0, t1);
5555 gen_store_spr(SPR_MQ, t1);
5556 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5557 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5558 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5559 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5560 gen_set_label(l1);
5561 tcg_temp_free(t0);
5562 tcg_temp_free(t1);
5563 if (unlikely(Rc(ctx->opcode) != 0))
5564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5565 }
5566
5567 /* PowerPC 602 specific instructions */
5568
5569 /* dsa */
5570 static void gen_dsa(DisasContext *ctx)
5571 {
5572 /* XXX: TODO */
5573 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5574 }
5575
5576 /* esa */
5577 static void gen_esa(DisasContext *ctx)
5578 {
5579 /* XXX: TODO */
5580 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5581 }
5582
5583 /* mfrom */
5584 static void gen_mfrom(DisasContext *ctx)
5585 {
5586 #if defined(CONFIG_USER_ONLY)
5587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5588 #else
5589 if (unlikely(ctx->pr)) {
5590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5591 return;
5592 }
5593 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5594 #endif
5595 }
5596
5597 /* 602 - 603 - G2 TLB management */
5598
5599 /* tlbld */
5600 static void gen_tlbld_6xx(DisasContext *ctx)
5601 {
5602 #if defined(CONFIG_USER_ONLY)
5603 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5604 #else
5605 if (unlikely(ctx->pr)) {
5606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5607 return;
5608 }
5609 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5610 #endif
5611 }
5612
5613 /* tlbli */
5614 static void gen_tlbli_6xx(DisasContext *ctx)
5615 {
5616 #if defined(CONFIG_USER_ONLY)
5617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5618 #else
5619 if (unlikely(ctx->pr)) {
5620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5621 return;
5622 }
5623 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5624 #endif
5625 }
5626
5627 /* 74xx TLB management */
5628
5629 /* tlbld */
5630 static void gen_tlbld_74xx(DisasContext *ctx)
5631 {
5632 #if defined(CONFIG_USER_ONLY)
5633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5634 #else
5635 if (unlikely(ctx->pr)) {
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5637 return;
5638 }
5639 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5640 #endif
5641 }
5642
5643 /* tlbli */
5644 static void gen_tlbli_74xx(DisasContext *ctx)
5645 {
5646 #if defined(CONFIG_USER_ONLY)
5647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5648 #else
5649 if (unlikely(ctx->pr)) {
5650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5651 return;
5652 }
5653 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5654 #endif
5655 }
5656
5657 /* POWER instructions not in PowerPC 601 */
5658
5659 /* clf */
5660 static void gen_clf(DisasContext *ctx)
5661 {
5662 /* Cache line flush: implemented as no-op */
5663 }
5664
5665 /* cli */
5666 static void gen_cli(DisasContext *ctx)
5667 {
5668 /* Cache line invalidate: privileged and treated as no-op */
5669 #if defined(CONFIG_USER_ONLY)
5670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5671 #else
5672 if (unlikely(ctx->pr)) {
5673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5674 return;
5675 }
5676 #endif
5677 }
5678
5679 /* dclst */
5680 static void gen_dclst(DisasContext *ctx)
5681 {
5682 /* Data cache line store: treated as no-op */
5683 }
5684
5685 static void gen_mfsri(DisasContext *ctx)
5686 {
5687 #if defined(CONFIG_USER_ONLY)
5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5689 #else
5690 int ra = rA(ctx->opcode);
5691 int rd = rD(ctx->opcode);
5692 TCGv t0;
5693 if (unlikely(ctx->pr)) {
5694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5695 return;
5696 }
5697 t0 = tcg_temp_new();
5698 gen_addr_reg_index(ctx, t0);
5699 tcg_gen_shri_tl(t0, t0, 28);
5700 tcg_gen_andi_tl(t0, t0, 0xF);
5701 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5702 tcg_temp_free(t0);
5703 if (ra != 0 && ra != rd)
5704 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5705 #endif
5706 }
5707
5708 static void gen_rac(DisasContext *ctx)
5709 {
5710 #if defined(CONFIG_USER_ONLY)
5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5712 #else
5713 TCGv t0;
5714 if (unlikely(ctx->pr)) {
5715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5716 return;
5717 }
5718 t0 = tcg_temp_new();
5719 gen_addr_reg_index(ctx, t0);
5720 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5721 tcg_temp_free(t0);
5722 #endif
5723 }
5724
5725 static void gen_rfsvc(DisasContext *ctx)
5726 {
5727 #if defined(CONFIG_USER_ONLY)
5728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5729 #else
5730 if (unlikely(ctx->pr)) {
5731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5732 return;
5733 }
5734 gen_helper_rfsvc(cpu_env);
5735 gen_sync_exception(ctx);
5736 #endif
5737 }
5738
5739 /* svc is not implemented for now */
5740
5741 /* POWER2 specific instructions */
5742 /* Quad manipulation (load/store two floats at a time) */
5743
5744 /* lfq */
5745 static void gen_lfq(DisasContext *ctx)
5746 {
5747 int rd = rD(ctx->opcode);
5748 TCGv t0;
5749 gen_set_access_type(ctx, ACCESS_FLOAT);
5750 t0 = tcg_temp_new();
5751 gen_addr_imm_index(ctx, t0, 0);
5752 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5753 gen_addr_add(ctx, t0, t0, 8);
5754 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5755 tcg_temp_free(t0);
5756 }
5757
5758 /* lfqu */
5759 static void gen_lfqu(DisasContext *ctx)
5760 {
5761 int ra = rA(ctx->opcode);
5762 int rd = rD(ctx->opcode);
5763 TCGv t0, t1;
5764 gen_set_access_type(ctx, ACCESS_FLOAT);
5765 t0 = tcg_temp_new();
5766 t1 = tcg_temp_new();
5767 gen_addr_imm_index(ctx, t0, 0);
5768 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5769 gen_addr_add(ctx, t1, t0, 8);
5770 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5771 if (ra != 0)
5772 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5773 tcg_temp_free(t0);
5774 tcg_temp_free(t1);
5775 }
5776
5777 /* lfqux */
5778 static void gen_lfqux(DisasContext *ctx)
5779 {
5780 int ra = rA(ctx->opcode);
5781 int rd = rD(ctx->opcode);
5782 gen_set_access_type(ctx, ACCESS_FLOAT);
5783 TCGv t0, t1;
5784 t0 = tcg_temp_new();
5785 gen_addr_reg_index(ctx, t0);
5786 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5787 t1 = tcg_temp_new();
5788 gen_addr_add(ctx, t1, t0, 8);
5789 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5790 tcg_temp_free(t1);
5791 if (ra != 0)
5792 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5793 tcg_temp_free(t0);
5794 }
5795
5796 /* lfqx */
5797 static void gen_lfqx(DisasContext *ctx)
5798 {
5799 int rd = rD(ctx->opcode);
5800 TCGv t0;
5801 gen_set_access_type(ctx, ACCESS_FLOAT);
5802 t0 = tcg_temp_new();
5803 gen_addr_reg_index(ctx, t0);
5804 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5805 gen_addr_add(ctx, t0, t0, 8);
5806 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5807 tcg_temp_free(t0);
5808 }
5809
5810 /* stfq */
5811 static void gen_stfq(DisasContext *ctx)
5812 {
5813 int rd = rD(ctx->opcode);
5814 TCGv t0;
5815 gen_set_access_type(ctx, ACCESS_FLOAT);
5816 t0 = tcg_temp_new();
5817 gen_addr_imm_index(ctx, t0, 0);
5818 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5819 gen_addr_add(ctx, t0, t0, 8);
5820 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5821 tcg_temp_free(t0);
5822 }
5823
5824 /* stfqu */
5825 static void gen_stfqu(DisasContext *ctx)
5826 {
5827 int ra = rA(ctx->opcode);
5828 int rd = rD(ctx->opcode);
5829 TCGv t0, t1;
5830 gen_set_access_type(ctx, ACCESS_FLOAT);
5831 t0 = tcg_temp_new();
5832 gen_addr_imm_index(ctx, t0, 0);
5833 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5834 t1 = tcg_temp_new();
5835 gen_addr_add(ctx, t1, t0, 8);
5836 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5837 tcg_temp_free(t1);
5838 if (ra != 0)
5839 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5840 tcg_temp_free(t0);
5841 }
5842
5843 /* stfqux */
5844 static void gen_stfqux(DisasContext *ctx)
5845 {
5846 int ra = rA(ctx->opcode);
5847 int rd = rD(ctx->opcode);
5848 TCGv t0, t1;
5849 gen_set_access_type(ctx, ACCESS_FLOAT);
5850 t0 = tcg_temp_new();
5851 gen_addr_reg_index(ctx, t0);
5852 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5853 t1 = tcg_temp_new();
5854 gen_addr_add(ctx, t1, t0, 8);
5855 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5856 tcg_temp_free(t1);
5857 if (ra != 0)
5858 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5859 tcg_temp_free(t0);
5860 }
5861
5862 /* stfqx */
5863 static void gen_stfqx(DisasContext *ctx)
5864 {
5865 int rd = rD(ctx->opcode);
5866 TCGv t0;
5867 gen_set_access_type(ctx, ACCESS_FLOAT);
5868 t0 = tcg_temp_new();
5869 gen_addr_reg_index(ctx, t0);
5870 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5871 gen_addr_add(ctx, t0, t0, 8);
5872 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5873 tcg_temp_free(t0);
5874 }
5875
5876 /* BookE specific instructions */
5877
5878 /* XXX: not implemented on 440 ? */
5879 static void gen_mfapidi(DisasContext *ctx)
5880 {
5881 /* XXX: TODO */
5882 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5883 }
5884
5885 /* XXX: not implemented on 440 ? */
5886 static void gen_tlbiva(DisasContext *ctx)
5887 {
5888 #if defined(CONFIG_USER_ONLY)
5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5890 #else
5891 TCGv t0;
5892 if (unlikely(ctx->pr)) {
5893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5894 return;
5895 }
5896 t0 = tcg_temp_new();
5897 gen_addr_reg_index(ctx, t0);
5898 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5899 tcg_temp_free(t0);
5900 #endif
5901 }
5902
5903 /* All 405 MAC instructions are translated here */
5904 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5905 int ra, int rb, int rt, int Rc)
5906 {
5907 TCGv t0, t1;
5908
5909 t0 = tcg_temp_local_new();
5910 t1 = tcg_temp_local_new();
5911
5912 switch (opc3 & 0x0D) {
5913 case 0x05:
5914 /* macchw - macchw. - macchwo - macchwo. */
5915 /* macchws - macchws. - macchwso - macchwso. */
5916 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5917 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5918 /* mulchw - mulchw. */
5919 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5920 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5921 tcg_gen_ext16s_tl(t1, t1);
5922 break;
5923 case 0x04:
5924 /* macchwu - macchwu. - macchwuo - macchwuo. */
5925 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5926 /* mulchwu - mulchwu. */
5927 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5928 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5929 tcg_gen_ext16u_tl(t1, t1);
5930 break;
5931 case 0x01:
5932 /* machhw - machhw. - machhwo - machhwo. */
5933 /* machhws - machhws. - machhwso - machhwso. */
5934 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5935 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5936 /* mulhhw - mulhhw. */
5937 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5938 tcg_gen_ext16s_tl(t0, t0);
5939 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5940 tcg_gen_ext16s_tl(t1, t1);
5941 break;
5942 case 0x00:
5943 /* machhwu - machhwu. - machhwuo - machhwuo. */
5944 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5945 /* mulhhwu - mulhhwu. */
5946 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5947 tcg_gen_ext16u_tl(t0, t0);
5948 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5949 tcg_gen_ext16u_tl(t1, t1);
5950 break;
5951 case 0x0D:
5952 /* maclhw - maclhw. - maclhwo - maclhwo. */
5953 /* maclhws - maclhws. - maclhwso - maclhwso. */
5954 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5955 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5956 /* mullhw - mullhw. */
5957 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5958 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5959 break;
5960 case 0x0C:
5961 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5962 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5963 /* mullhwu - mullhwu. */
5964 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5965 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5966 break;
5967 }
5968 if (opc2 & 0x04) {
5969 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5970 tcg_gen_mul_tl(t1, t0, t1);
5971 if (opc2 & 0x02) {
5972 /* nmultiply-and-accumulate (0x0E) */
5973 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5974 } else {
5975 /* multiply-and-accumulate (0x0C) */
5976 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5977 }
5978
5979 if (opc3 & 0x12) {
5980 /* Check overflow and/or saturate */
5981 TCGLabel *l1 = gen_new_label();
5982
5983 if (opc3 & 0x10) {
5984 /* Start with XER OV disabled, the most likely case */
5985 tcg_gen_movi_tl(cpu_ov, 0);
5986 }
5987 if (opc3 & 0x01) {
5988 /* Signed */
5989 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5990 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5991 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5992 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5993 if (opc3 & 0x02) {
5994 /* Saturate */
5995 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5996 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5997 }
5998 } else {
5999 /* Unsigned */
6000 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6001 if (opc3 & 0x02) {
6002 /* Saturate */
6003 tcg_gen_movi_tl(t0, UINT32_MAX);
6004 }
6005 }
6006 if (opc3 & 0x10) {
6007 /* Check overflow */
6008 tcg_gen_movi_tl(cpu_ov, 1);
6009 tcg_gen_movi_tl(cpu_so, 1);
6010 }
6011 gen_set_label(l1);
6012 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6013 }
6014 } else {
6015 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6016 }
6017 tcg_temp_free(t0);
6018 tcg_temp_free(t1);
6019 if (unlikely(Rc) != 0) {
6020 /* Update Rc0 */
6021 gen_set_Rc0(ctx, cpu_gpr[rt]);
6022 }
6023 }
6024
6025 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6026 static void glue(gen_, name)(DisasContext *ctx) \
6027 { \
6028 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6029 rD(ctx->opcode), Rc(ctx->opcode)); \
6030 }
6031
6032 /* macchw - macchw. */
6033 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6034 /* macchwo - macchwo. */
6035 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6036 /* macchws - macchws. */
6037 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6038 /* macchwso - macchwso. */
6039 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6040 /* macchwsu - macchwsu. */
6041 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6042 /* macchwsuo - macchwsuo. */
6043 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6044 /* macchwu - macchwu. */
6045 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6046 /* macchwuo - macchwuo. */
6047 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6048 /* machhw - machhw. */
6049 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6050 /* machhwo - machhwo. */
6051 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6052 /* machhws - machhws. */
6053 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6054 /* machhwso - machhwso. */
6055 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6056 /* machhwsu - machhwsu. */
6057 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6058 /* machhwsuo - machhwsuo. */
6059 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6060 /* machhwu - machhwu. */
6061 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6062 /* machhwuo - machhwuo. */
6063 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6064 /* maclhw - maclhw. */
6065 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6066 /* maclhwo - maclhwo. */
6067 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6068 /* maclhws - maclhws. */
6069 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6070 /* maclhwso - maclhwso. */
6071 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6072 /* maclhwu - maclhwu. */
6073 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6074 /* maclhwuo - maclhwuo. */
6075 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6076 /* maclhwsu - maclhwsu. */
6077 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6078 /* maclhwsuo - maclhwsuo. */
6079 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6080 /* nmacchw - nmacchw. */
6081 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6082 /* nmacchwo - nmacchwo. */
6083 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6084 /* nmacchws - nmacchws. */
6085 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6086 /* nmacchwso - nmacchwso. */
6087 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6088 /* nmachhw - nmachhw. */
6089 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6090 /* nmachhwo - nmachhwo. */
6091 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6092 /* nmachhws - nmachhws. */
6093 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6094 /* nmachhwso - nmachhwso. */
6095 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6096 /* nmaclhw - nmaclhw. */
6097 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6098 /* nmaclhwo - nmaclhwo. */
6099 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6100 /* nmaclhws - nmaclhws. */
6101 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6102 /* nmaclhwso - nmaclhwso. */
6103 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6104
6105 /* mulchw - mulchw. */
6106 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6107 /* mulchwu - mulchwu. */
6108 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6109 /* mulhhw - mulhhw. */
6110 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6111 /* mulhhwu - mulhhwu. */
6112 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6113 /* mullhw - mullhw. */
6114 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6115 /* mullhwu - mullhwu. */
6116 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6117
6118 /* mfdcr */
6119 static void gen_mfdcr(DisasContext *ctx)
6120 {
6121 #if defined(CONFIG_USER_ONLY)
6122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6123 #else
6124 TCGv dcrn;
6125 if (unlikely(ctx->pr)) {
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6127 return;
6128 }
6129 /* NIP cannot be restored if the memory exception comes from an helper */
6130 gen_update_nip(ctx, ctx->nip - 4);
6131 dcrn = tcg_const_tl(SPR(ctx->opcode));
6132 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6133 tcg_temp_free(dcrn);
6134 #endif
6135 }
6136
6137 /* mtdcr */
6138 static void gen_mtdcr(DisasContext *ctx)
6139 {
6140 #if defined(CONFIG_USER_ONLY)
6141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6142 #else
6143 TCGv dcrn;
6144 if (unlikely(ctx->pr)) {
6145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6146 return;
6147 }
6148 /* NIP cannot be restored if the memory exception comes from an helper */
6149 gen_update_nip(ctx, ctx->nip - 4);
6150 dcrn = tcg_const_tl(SPR(ctx->opcode));
6151 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6152 tcg_temp_free(dcrn);
6153 #endif
6154 }
6155
6156 /* mfdcrx */
6157 /* XXX: not implemented on 440 ? */
6158 static void gen_mfdcrx(DisasContext *ctx)
6159 {
6160 #if defined(CONFIG_USER_ONLY)
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6162 #else
6163 if (unlikely(ctx->pr)) {
6164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6165 return;
6166 }
6167 /* NIP cannot be restored if the memory exception comes from an helper */
6168 gen_update_nip(ctx, ctx->nip - 4);
6169 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6170 cpu_gpr[rA(ctx->opcode)]);
6171 /* Note: Rc update flag set leads to undefined state of Rc0 */
6172 #endif
6173 }
6174
6175 /* mtdcrx */
6176 /* XXX: not implemented on 440 ? */
6177 static void gen_mtdcrx(DisasContext *ctx)
6178 {
6179 #if defined(CONFIG_USER_ONLY)
6180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6181 #else
6182 if (unlikely(ctx->pr)) {
6183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6184 return;
6185 }
6186 /* NIP cannot be restored if the memory exception comes from an helper */
6187 gen_update_nip(ctx, ctx->nip - 4);
6188 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6189 cpu_gpr[rS(ctx->opcode)]);
6190 /* Note: Rc update flag set leads to undefined state of Rc0 */
6191 #endif
6192 }
6193
6194 /* mfdcrux (PPC 460) : user-mode access to DCR */
6195 static void gen_mfdcrux(DisasContext *ctx)
6196 {
6197 /* NIP cannot be restored if the memory exception comes from an helper */
6198 gen_update_nip(ctx, ctx->nip - 4);
6199 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6200 cpu_gpr[rA(ctx->opcode)]);
6201 /* Note: Rc update flag set leads to undefined state of Rc0 */
6202 }
6203
6204 /* mtdcrux (PPC 460) : user-mode access to DCR */
6205 static void gen_mtdcrux(DisasContext *ctx)
6206 {
6207 /* NIP cannot be restored if the memory exception comes from an helper */
6208 gen_update_nip(ctx, ctx->nip - 4);
6209 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6210 cpu_gpr[rS(ctx->opcode)]);
6211 /* Note: Rc update flag set leads to undefined state of Rc0 */
6212 }
6213
6214 /* dccci */
6215 static void gen_dccci(DisasContext *ctx)
6216 {
6217 #if defined(CONFIG_USER_ONLY)
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6219 #else
6220 if (unlikely(ctx->pr)) {
6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6222 return;
6223 }
6224 /* interpreted as no-op */
6225 #endif
6226 }
6227
6228 /* dcread */
6229 static void gen_dcread(DisasContext *ctx)
6230 {
6231 #if defined(CONFIG_USER_ONLY)
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 #else
6234 TCGv EA, val;
6235 if (unlikely(ctx->pr)) {
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 return;
6238 }
6239 gen_set_access_type(ctx, ACCESS_CACHE);
6240 EA = tcg_temp_new();
6241 gen_addr_reg_index(ctx, EA);
6242 val = tcg_temp_new();
6243 gen_qemu_ld32u(ctx, val, EA);
6244 tcg_temp_free(val);
6245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6246 tcg_temp_free(EA);
6247 #endif
6248 }
6249
6250 /* icbt */
6251 static void gen_icbt_40x(DisasContext *ctx)
6252 {
6253 /* interpreted as no-op */
6254 /* XXX: specification say this is treated as a load by the MMU
6255 * but does not generate any exception
6256 */
6257 }
6258
6259 /* iccci */
6260 static void gen_iccci(DisasContext *ctx)
6261 {
6262 #if defined(CONFIG_USER_ONLY)
6263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6264 #else
6265 if (unlikely(ctx->pr)) {
6266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6267 return;
6268 }
6269 /* interpreted as no-op */
6270 #endif
6271 }
6272
6273 /* icread */
6274 static void gen_icread(DisasContext *ctx)
6275 {
6276 #if defined(CONFIG_USER_ONLY)
6277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6278 #else
6279 if (unlikely(ctx->pr)) {
6280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6281 return;
6282 }
6283 /* interpreted as no-op */
6284 #endif
6285 }
6286
6287 /* rfci (supervisor only) */
6288 static void gen_rfci_40x(DisasContext *ctx)
6289 {
6290 #if defined(CONFIG_USER_ONLY)
6291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6292 #else
6293 if (unlikely(ctx->pr)) {
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 return;
6296 }
6297 /* Restore CPU state */
6298 gen_helper_40x_rfci(cpu_env);
6299 gen_sync_exception(ctx);
6300 #endif
6301 }
6302
6303 static void gen_rfci(DisasContext *ctx)
6304 {
6305 #if defined(CONFIG_USER_ONLY)
6306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6307 #else
6308 if (unlikely(ctx->pr)) {
6309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6310 return;
6311 }
6312 /* Restore CPU state */
6313 gen_helper_rfci(cpu_env);
6314 gen_sync_exception(ctx);
6315 #endif
6316 }
6317
6318 /* BookE specific */
6319
6320 /* XXX: not implemented on 440 ? */
6321 static void gen_rfdi(DisasContext *ctx)
6322 {
6323 #if defined(CONFIG_USER_ONLY)
6324 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6325 #else
6326 if (unlikely(ctx->pr)) {
6327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6328 return;
6329 }
6330 /* Restore CPU state */
6331 gen_helper_rfdi(cpu_env);
6332 gen_sync_exception(ctx);
6333 #endif
6334 }
6335
6336 /* XXX: not implemented on 440 ? */
6337 static void gen_rfmci(DisasContext *ctx)
6338 {
6339 #if defined(CONFIG_USER_ONLY)
6340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6341 #else
6342 if (unlikely(ctx->pr)) {
6343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6344 return;
6345 }
6346 /* Restore CPU state */
6347 gen_helper_rfmci(cpu_env);
6348 gen_sync_exception(ctx);
6349 #endif
6350 }
6351
6352 /* TLB management - PowerPC 405 implementation */
6353
6354 /* tlbre */
6355 static void gen_tlbre_40x(DisasContext *ctx)
6356 {
6357 #if defined(CONFIG_USER_ONLY)
6358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6359 #else
6360 if (unlikely(ctx->pr)) {
6361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6362 return;
6363 }
6364 switch (rB(ctx->opcode)) {
6365 case 0:
6366 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6367 cpu_gpr[rA(ctx->opcode)]);
6368 break;
6369 case 1:
6370 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6371 cpu_gpr[rA(ctx->opcode)]);
6372 break;
6373 default:
6374 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6375 break;
6376 }
6377 #endif
6378 }
6379
6380 /* tlbsx - tlbsx. */
6381 static void gen_tlbsx_40x(DisasContext *ctx)
6382 {
6383 #if defined(CONFIG_USER_ONLY)
6384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6385 #else
6386 TCGv t0;
6387 if (unlikely(ctx->pr)) {
6388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6389 return;
6390 }
6391 t0 = tcg_temp_new();
6392 gen_addr_reg_index(ctx, t0);
6393 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6394 tcg_temp_free(t0);
6395 if (Rc(ctx->opcode)) {
6396 TCGLabel *l1 = gen_new_label();
6397 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6398 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6399 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6400 gen_set_label(l1);
6401 }
6402 #endif
6403 }
6404
6405 /* tlbwe */
6406 static void gen_tlbwe_40x(DisasContext *ctx)
6407 {
6408 #if defined(CONFIG_USER_ONLY)
6409 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6410 #else
6411 if (unlikely(ctx->pr)) {
6412 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6413 return;
6414 }
6415 switch (rB(ctx->opcode)) {
6416 case 0:
6417 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6418 cpu_gpr[rS(ctx->opcode)]);
6419 break;
6420 case 1:
6421 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6422 cpu_gpr[rS(ctx->opcode)]);
6423 break;
6424 default:
6425 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6426 break;
6427 }
6428 #endif
6429 }
6430
6431 /* TLB management - PowerPC 440 implementation */
6432
6433 /* tlbre */
6434 static void gen_tlbre_440(DisasContext *ctx)
6435 {
6436 #if defined(CONFIG_USER_ONLY)
6437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6438 #else
6439 if (unlikely(ctx->pr)) {
6440 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6441 return;
6442 }
6443 switch (rB(ctx->opcode)) {
6444 case 0:
6445 case 1:
6446 case 2:
6447 {
6448 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6449 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6450 t0, cpu_gpr[rA(ctx->opcode)]);
6451 tcg_temp_free_i32(t0);
6452 }
6453 break;
6454 default:
6455 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6456 break;
6457 }
6458 #endif
6459 }
6460
6461 /* tlbsx - tlbsx. */
6462 static void gen_tlbsx_440(DisasContext *ctx)
6463 {
6464 #if defined(CONFIG_USER_ONLY)
6465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6466 #else
6467 TCGv t0;
6468 if (unlikely(ctx->pr)) {
6469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6470 return;
6471 }
6472 t0 = tcg_temp_new();
6473 gen_addr_reg_index(ctx, t0);
6474 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6475 tcg_temp_free(t0);
6476 if (Rc(ctx->opcode)) {
6477 TCGLabel *l1 = gen_new_label();
6478 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6479 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6480 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6481 gen_set_label(l1);
6482 }
6483 #endif
6484 }
6485
6486 /* tlbwe */
6487 static void gen_tlbwe_440(DisasContext *ctx)
6488 {
6489 #if defined(CONFIG_USER_ONLY)
6490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6491 #else
6492 if (unlikely(ctx->pr)) {
6493 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6494 return;
6495 }
6496 switch (rB(ctx->opcode)) {
6497 case 0:
6498 case 1:
6499 case 2:
6500 {
6501 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6502 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6503 cpu_gpr[rS(ctx->opcode)]);
6504 tcg_temp_free_i32(t0);
6505 }
6506 break;
6507 default:
6508 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6509 break;
6510 }
6511 #endif
6512 }
6513
6514 /* TLB management - PowerPC BookE 2.06 implementation */
6515
6516 /* tlbre */
6517 static void gen_tlbre_booke206(DisasContext *ctx)
6518 {
6519 #if defined(CONFIG_USER_ONLY)
6520 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6521 #else
6522 if (unlikely(ctx->pr)) {
6523 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6524 return;
6525 }
6526
6527 gen_helper_booke206_tlbre(cpu_env);
6528 #endif
6529 }
6530
6531 /* tlbsx - tlbsx. */
6532 static void gen_tlbsx_booke206(DisasContext *ctx)
6533 {
6534 #if defined(CONFIG_USER_ONLY)
6535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6536 #else
6537 TCGv t0;
6538 if (unlikely(ctx->pr)) {
6539 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6540 return;
6541 }
6542
6543 if (rA(ctx->opcode)) {
6544 t0 = tcg_temp_new();
6545 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6546 } else {
6547 t0 = tcg_const_tl(0);
6548 }
6549
6550 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6551 gen_helper_booke206_tlbsx(cpu_env, t0);
6552 tcg_temp_free(t0);
6553 #endif
6554 }
6555
6556 /* tlbwe */
6557 static void gen_tlbwe_booke206(DisasContext *ctx)
6558 {
6559 #if defined(CONFIG_USER_ONLY)
6560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6561 #else
6562 if (unlikely(ctx->pr)) {
6563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6564 return;
6565 }
6566 gen_update_nip(ctx, ctx->nip - 4);
6567 gen_helper_booke206_tlbwe(cpu_env);
6568 #endif
6569 }
6570
6571 static void gen_tlbivax_booke206(DisasContext *ctx)
6572 {
6573 #if defined(CONFIG_USER_ONLY)
6574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6575 #else
6576 TCGv t0;
6577 if (unlikely(ctx->pr)) {
6578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6579 return;
6580 }
6581
6582 t0 = tcg_temp_new();
6583 gen_addr_reg_index(ctx, t0);
6584
6585 gen_helper_booke206_tlbivax(cpu_env, t0);
6586 tcg_temp_free(t0);
6587 #endif
6588 }
6589
6590 static void gen_tlbilx_booke206(DisasContext *ctx)
6591 {
6592 #if defined(CONFIG_USER_ONLY)
6593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6594 #else
6595 TCGv t0;
6596 if (unlikely(ctx->pr)) {
6597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6598 return;
6599 }
6600
6601 t0 = tcg_temp_new();
6602 gen_addr_reg_index(ctx, t0);
6603
6604 switch((ctx->opcode >> 21) & 0x3) {
6605 case 0:
6606 gen_helper_booke206_tlbilx0(cpu_env, t0);
6607 break;
6608 case 1:
6609 gen_helper_booke206_tlbilx1(cpu_env, t0);
6610 break;
6611 case 3:
6612 gen_helper_booke206_tlbilx3(cpu_env, t0);
6613 break;
6614 default:
6615 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6616 break;
6617 }
6618
6619 tcg_temp_free(t0);
6620 #endif
6621 }
6622
6623
6624 /* wrtee */
6625 static void gen_wrtee(DisasContext *ctx)
6626 {
6627 #if defined(CONFIG_USER_ONLY)
6628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6629 #else
6630 TCGv t0;
6631 if (unlikely(ctx->pr)) {
6632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6633 return;
6634 }
6635 t0 = tcg_temp_new();
6636 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6637 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6638 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6639 tcg_temp_free(t0);
6640 /* Stop translation to have a chance to raise an exception
6641 * if we just set msr_ee to 1
6642 */
6643 gen_stop_exception(ctx);
6644 #endif
6645 }
6646
6647 /* wrteei */
6648 static void gen_wrteei(DisasContext *ctx)
6649 {
6650 #if defined(CONFIG_USER_ONLY)
6651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6652 #else
6653 if (unlikely(ctx->pr)) {
6654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6655 return;
6656 }
6657 if (ctx->opcode & 0x00008000) {
6658 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6659 /* Stop translation to have a chance to raise an exception */
6660 gen_stop_exception(ctx);
6661 } else {
6662 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6663 }
6664 #endif
6665 }
6666
6667 /* PowerPC 440 specific instructions */
6668
6669 /* dlmzb */
6670 static void gen_dlmzb(DisasContext *ctx)
6671 {
6672 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6673 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6674 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6675 tcg_temp_free_i32(t0);
6676 }
6677
6678 /* mbar replaces eieio on 440 */
6679 static void gen_mbar(DisasContext *ctx)
6680 {
6681 /* interpreted as no-op */
6682 }
6683
6684 /* msync replaces sync on 440 */
6685 static void gen_msync_4xx(DisasContext *ctx)
6686 {
6687 /* interpreted as no-op */
6688 }
6689
6690 /* icbt */
6691 static void gen_icbt_440(DisasContext *ctx)
6692 {
6693 /* interpreted as no-op */
6694 /* XXX: specification say this is treated as a load by the MMU
6695 * but does not generate any exception
6696 */
6697 }
6698
6699 /* Embedded.Processor Control */
6700
6701 static void gen_msgclr(DisasContext *ctx)
6702 {
6703 #if defined(CONFIG_USER_ONLY)
6704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6705 #else
6706 if (unlikely(ctx->pr)) {
6707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6708 return;
6709 }
6710
6711 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6712 #endif
6713 }
6714
6715 static void gen_msgsnd(DisasContext *ctx)
6716 {
6717 #if defined(CONFIG_USER_ONLY)
6718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6719 #else
6720 if (unlikely(ctx->pr)) {
6721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6722 return;
6723 }
6724
6725 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6726 #endif
6727 }
6728
6729 /*** Altivec vector extension ***/
6730 /* Altivec registers moves */
6731
6732 static inline TCGv_ptr gen_avr_ptr(int reg)
6733 {
6734 TCGv_ptr r = tcg_temp_new_ptr();
6735 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6736 return r;
6737 }
6738
6739 #define GEN_VR_LDX(name, opc2, opc3) \
6740 static void glue(gen_, name)(DisasContext *ctx) \
6741 { \
6742 TCGv EA; \
6743 if (unlikely(!ctx->altivec_enabled)) { \
6744 gen_exception(ctx, POWERPC_EXCP_VPU); \
6745 return; \
6746 } \
6747 gen_set_access_type(ctx, ACCESS_INT); \
6748 EA = tcg_temp_new(); \
6749 gen_addr_reg_index(ctx, EA); \
6750 tcg_gen_andi_tl(EA, EA, ~0xf); \
6751 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6752 64-bit byteswap already. */ \
6753 if (ctx->le_mode) { \
6754 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6755 tcg_gen_addi_tl(EA, EA, 8); \
6756 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6757 } else { \
6758 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6759 tcg_gen_addi_tl(EA, EA, 8); \
6760 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6761 } \
6762 tcg_temp_free(EA); \
6763 }
6764
6765 #define GEN_VR_STX(name, opc2, opc3) \
6766 static void gen_st##name(DisasContext *ctx) \
6767 { \
6768 TCGv EA; \
6769 if (unlikely(!ctx->altivec_enabled)) { \
6770 gen_exception(ctx, POWERPC_EXCP_VPU); \
6771 return; \
6772 } \
6773 gen_set_access_type(ctx, ACCESS_INT); \
6774 EA = tcg_temp_new(); \
6775 gen_addr_reg_index(ctx, EA); \
6776 tcg_gen_andi_tl(EA, EA, ~0xf); \
6777 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6778 64-bit byteswap already. */ \
6779 if (ctx->le_mode) { \
6780 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6781 tcg_gen_addi_tl(EA, EA, 8); \
6782 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6783 } else { \
6784 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6785 tcg_gen_addi_tl(EA, EA, 8); \
6786 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6787 } \
6788 tcg_temp_free(EA); \
6789 }
6790
6791 #define GEN_VR_LVE(name, opc2, opc3, size) \
6792 static void gen_lve##name(DisasContext *ctx) \
6793 { \
6794 TCGv EA; \
6795 TCGv_ptr rs; \
6796 if (unlikely(!ctx->altivec_enabled)) { \
6797 gen_exception(ctx, POWERPC_EXCP_VPU); \
6798 return; \
6799 } \
6800 gen_set_access_type(ctx, ACCESS_INT); \
6801 EA = tcg_temp_new(); \
6802 gen_addr_reg_index(ctx, EA); \
6803 if (size > 1) { \
6804 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6805 } \
6806 rs = gen_avr_ptr(rS(ctx->opcode)); \
6807 gen_helper_lve##name(cpu_env, rs, EA); \
6808 tcg_temp_free(EA); \
6809 tcg_temp_free_ptr(rs); \
6810 }
6811
6812 #define GEN_VR_STVE(name, opc2, opc3, size) \
6813 static void gen_stve##name(DisasContext *ctx) \
6814 { \
6815 TCGv EA; \
6816 TCGv_ptr rs; \
6817 if (unlikely(!ctx->altivec_enabled)) { \
6818 gen_exception(ctx, POWERPC_EXCP_VPU); \
6819 return; \
6820 } \
6821 gen_set_access_type(ctx, ACCESS_INT); \
6822 EA = tcg_temp_new(); \
6823 gen_addr_reg_index(ctx, EA); \
6824 if (size > 1) { \
6825 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6826 } \
6827 rs = gen_avr_ptr(rS(ctx->opcode)); \
6828 gen_helper_stve##name(cpu_env, rs, EA); \
6829 tcg_temp_free(EA); \
6830 tcg_temp_free_ptr(rs); \
6831 }
6832
6833 GEN_VR_LDX(lvx, 0x07, 0x03);
6834 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6835 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6836
6837 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6838 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6839 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6840
6841 GEN_VR_STX(svx, 0x07, 0x07);
6842 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6843 GEN_VR_STX(svxl, 0x07, 0x0F);
6844
6845 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6846 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6847 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6848
6849 static void gen_lvsl(DisasContext *ctx)
6850 {
6851 TCGv_ptr rd;
6852 TCGv EA;
6853 if (unlikely(!ctx->altivec_enabled)) {
6854 gen_exception(ctx, POWERPC_EXCP_VPU);
6855 return;
6856 }
6857 EA = tcg_temp_new();
6858 gen_addr_reg_index(ctx, EA);
6859 rd = gen_avr_ptr(rD(ctx->opcode));
6860 gen_helper_lvsl(rd, EA);
6861 tcg_temp_free(EA);
6862 tcg_temp_free_ptr(rd);
6863 }
6864
6865 static void gen_lvsr(DisasContext *ctx)
6866 {
6867 TCGv_ptr rd;
6868 TCGv EA;
6869 if (unlikely(!ctx->altivec_enabled)) {
6870 gen_exception(ctx, POWERPC_EXCP_VPU);
6871 return;
6872 }
6873 EA = tcg_temp_new();
6874 gen_addr_reg_index(ctx, EA);
6875 rd = gen_avr_ptr(rD(ctx->opcode));
6876 gen_helper_lvsr(rd, EA);
6877 tcg_temp_free(EA);
6878 tcg_temp_free_ptr(rd);
6879 }
6880
6881 static void gen_mfvscr(DisasContext *ctx)
6882 {
6883 TCGv_i32 t;
6884 if (unlikely(!ctx->altivec_enabled)) {
6885 gen_exception(ctx, POWERPC_EXCP_VPU);
6886 return;
6887 }
6888 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6889 t = tcg_temp_new_i32();
6890 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6891 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6892 tcg_temp_free_i32(t);
6893 }
6894
6895 static void gen_mtvscr(DisasContext *ctx)
6896 {
6897 TCGv_ptr p;
6898 if (unlikely(!ctx->altivec_enabled)) {
6899 gen_exception(ctx, POWERPC_EXCP_VPU);
6900 return;
6901 }
6902 p = gen_avr_ptr(rB(ctx->opcode));
6903 gen_helper_mtvscr(cpu_env, p);
6904 tcg_temp_free_ptr(p);
6905 }
6906
6907 /* Logical operations */
6908 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6909 static void glue(gen_, name)(DisasContext *ctx) \
6910 { \
6911 if (unlikely(!ctx->altivec_enabled)) { \
6912 gen_exception(ctx, POWERPC_EXCP_VPU); \
6913 return; \
6914 } \
6915 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6916 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6917 }
6918
6919 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6920 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6921 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6922 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6923 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6924 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6925 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6926 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6927
6928 #define GEN_VXFORM(name, opc2, opc3) \
6929 static void glue(gen_, name)(DisasContext *ctx) \
6930 { \
6931 TCGv_ptr ra, rb, rd; \
6932 if (unlikely(!ctx->altivec_enabled)) { \
6933 gen_exception(ctx, POWERPC_EXCP_VPU); \
6934 return; \
6935 } \
6936 ra = gen_avr_ptr(rA(ctx->opcode)); \
6937 rb = gen_avr_ptr(rB(ctx->opcode)); \
6938 rd = gen_avr_ptr(rD(ctx->opcode)); \
6939 gen_helper_##name (rd, ra, rb); \
6940 tcg_temp_free_ptr(ra); \
6941 tcg_temp_free_ptr(rb); \
6942 tcg_temp_free_ptr(rd); \
6943 }
6944
6945 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6946 static void glue(gen_, name)(DisasContext *ctx) \
6947 { \
6948 TCGv_ptr ra, rb, rd; \
6949 if (unlikely(!ctx->altivec_enabled)) { \
6950 gen_exception(ctx, POWERPC_EXCP_VPU); \
6951 return; \
6952 } \
6953 ra = gen_avr_ptr(rA(ctx->opcode)); \
6954 rb = gen_avr_ptr(rB(ctx->opcode)); \
6955 rd = gen_avr_ptr(rD(ctx->opcode)); \
6956 gen_helper_##name(cpu_env, rd, ra, rb); \
6957 tcg_temp_free_ptr(ra); \
6958 tcg_temp_free_ptr(rb); \
6959 tcg_temp_free_ptr(rd); \
6960 }
6961
6962 #define GEN_VXFORM3(name, opc2, opc3) \
6963 static void glue(gen_, name)(DisasContext *ctx) \
6964 { \
6965 TCGv_ptr ra, rb, rc, rd; \
6966 if (unlikely(!ctx->altivec_enabled)) { \
6967 gen_exception(ctx, POWERPC_EXCP_VPU); \
6968 return; \
6969 } \
6970 ra = gen_avr_ptr(rA(ctx->opcode)); \
6971 rb = gen_avr_ptr(rB(ctx->opcode)); \
6972 rc = gen_avr_ptr(rC(ctx->opcode)); \
6973 rd = gen_avr_ptr(rD(ctx->opcode)); \
6974 gen_helper_##name(rd, ra, rb, rc); \
6975 tcg_temp_free_ptr(ra); \
6976 tcg_temp_free_ptr(rb); \
6977 tcg_temp_free_ptr(rc); \
6978 tcg_temp_free_ptr(rd); \
6979 }
6980
6981 /*
6982 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6983 * an opcode bit. In general, these pairs come from different
6984 * versions of the ISA, so we must also support a pair of flags for
6985 * each instruction.
6986 */
6987 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6988 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6989 { \
6990 if ((Rc(ctx->opcode) == 0) && \
6991 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6992 gen_##name0(ctx); \
6993 } else if ((Rc(ctx->opcode) == 1) && \
6994 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6995 gen_##name1(ctx); \
6996 } else { \
6997 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6998 } \
6999 }
7000
7001 GEN_VXFORM(vaddubm, 0, 0);
7002 GEN_VXFORM(vadduhm, 0, 1);
7003 GEN_VXFORM(vadduwm, 0, 2);
7004 GEN_VXFORM(vaddudm, 0, 3);
7005 GEN_VXFORM(vsububm, 0, 16);
7006 GEN_VXFORM(vsubuhm, 0, 17);
7007 GEN_VXFORM(vsubuwm, 0, 18);
7008 GEN_VXFORM(vsubudm, 0, 19);
7009 GEN_VXFORM(vmaxub, 1, 0);
7010 GEN_VXFORM(vmaxuh, 1, 1);
7011 GEN_VXFORM(vmaxuw, 1, 2);
7012 GEN_VXFORM(vmaxud, 1, 3);
7013 GEN_VXFORM(vmaxsb, 1, 4);
7014 GEN_VXFORM(vmaxsh, 1, 5);
7015 GEN_VXFORM(vmaxsw, 1, 6);
7016 GEN_VXFORM(vmaxsd, 1, 7);
7017 GEN_VXFORM(vminub, 1, 8);
7018 GEN_VXFORM(vminuh, 1, 9);
7019 GEN_VXFORM(vminuw, 1, 10);
7020 GEN_VXFORM(vminud, 1, 11);
7021 GEN_VXFORM(vminsb, 1, 12);
7022 GEN_VXFORM(vminsh, 1, 13);
7023 GEN_VXFORM(vminsw, 1, 14);
7024 GEN_VXFORM(vminsd, 1, 15);
7025 GEN_VXFORM(vavgub, 1, 16);
7026 GEN_VXFORM(vavguh, 1, 17);
7027 GEN_VXFORM(vavguw, 1, 18);
7028 GEN_VXFORM(vavgsb, 1, 20);
7029 GEN_VXFORM(vavgsh, 1, 21);
7030 GEN_VXFORM(vavgsw, 1, 22);
7031 GEN_VXFORM(vmrghb, 6, 0);
7032 GEN_VXFORM(vmrghh, 6, 1);
7033 GEN_VXFORM(vmrghw, 6, 2);
7034 GEN_VXFORM(vmrglb, 6, 4);
7035 GEN_VXFORM(vmrglh, 6, 5);
7036 GEN_VXFORM(vmrglw, 6, 6);
7037
7038 static void gen_vmrgew(DisasContext *ctx)
7039 {
7040 TCGv_i64 tmp;
7041 int VT, VA, VB;
7042 if (unlikely(!ctx->altivec_enabled)) {
7043 gen_exception(ctx, POWERPC_EXCP_VPU);
7044 return;
7045 }
7046 VT = rD(ctx->opcode);
7047 VA = rA(ctx->opcode);
7048 VB = rB(ctx->opcode);
7049 tmp = tcg_temp_new_i64();
7050 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7051 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7052 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7053 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7054 tcg_temp_free_i64(tmp);
7055 }
7056
7057 static void gen_vmrgow(DisasContext *ctx)
7058 {
7059 int VT, VA, VB;
7060 if (unlikely(!ctx->altivec_enabled)) {
7061 gen_exception(ctx, POWERPC_EXCP_VPU);
7062 return;
7063 }
7064 VT = rD(ctx->opcode);
7065 VA = rA(ctx->opcode);
7066 VB = rB(ctx->opcode);
7067
7068 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7069 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7070 }
7071
7072 GEN_VXFORM(vmuloub, 4, 0);
7073 GEN_VXFORM(vmulouh, 4, 1);
7074 GEN_VXFORM(vmulouw, 4, 2);
7075 GEN_VXFORM(vmuluwm, 4, 2);
7076 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7077 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7078 GEN_VXFORM(vmulosb, 4, 4);
7079 GEN_VXFORM(vmulosh, 4, 5);
7080 GEN_VXFORM(vmulosw, 4, 6);
7081 GEN_VXFORM(vmuleub, 4, 8);
7082 GEN_VXFORM(vmuleuh, 4, 9);
7083 GEN_VXFORM(vmuleuw, 4, 10);
7084 GEN_VXFORM(vmulesb, 4, 12);
7085 GEN_VXFORM(vmulesh, 4, 13);
7086 GEN_VXFORM(vmulesw, 4, 14);
7087 GEN_VXFORM(vslb, 2, 4);
7088 GEN_VXFORM(vslh, 2, 5);
7089 GEN_VXFORM(vslw, 2, 6);
7090 GEN_VXFORM(vsld, 2, 23);
7091 GEN_VXFORM(vsrb, 2, 8);
7092 GEN_VXFORM(vsrh, 2, 9);
7093 GEN_VXFORM(vsrw, 2, 10);
7094 GEN_VXFORM(vsrd, 2, 27);
7095 GEN_VXFORM(vsrab, 2, 12);
7096 GEN_VXFORM(vsrah, 2, 13);
7097 GEN_VXFORM(vsraw, 2, 14);
7098 GEN_VXFORM(vsrad, 2, 15);
7099 GEN_VXFORM(vslo, 6, 16);
7100 GEN_VXFORM(vsro, 6, 17);
7101 GEN_VXFORM(vaddcuw, 0, 6);
7102 GEN_VXFORM(vsubcuw, 0, 22);
7103 GEN_VXFORM_ENV(vaddubs, 0, 8);
7104 GEN_VXFORM_ENV(vadduhs, 0, 9);
7105 GEN_VXFORM_ENV(vadduws, 0, 10);
7106 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7107 GEN_VXFORM_ENV(vaddshs, 0, 13);
7108 GEN_VXFORM_ENV(vaddsws, 0, 14);
7109 GEN_VXFORM_ENV(vsububs, 0, 24);
7110 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7111 GEN_VXFORM_ENV(vsubuws, 0, 26);
7112 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7113 GEN_VXFORM_ENV(vsubshs, 0, 29);
7114 GEN_VXFORM_ENV(vsubsws, 0, 30);
7115 GEN_VXFORM(vadduqm, 0, 4);
7116 GEN_VXFORM(vaddcuq, 0, 5);
7117 GEN_VXFORM3(vaddeuqm, 30, 0);
7118 GEN_VXFORM3(vaddecuq, 30, 0);
7119 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7120 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7121 GEN_VXFORM(vsubuqm, 0, 20);
7122 GEN_VXFORM(vsubcuq, 0, 21);
7123 GEN_VXFORM3(vsubeuqm, 31, 0);
7124 GEN_VXFORM3(vsubecuq, 31, 0);
7125 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7126 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7127 GEN_VXFORM(vrlb, 2, 0);
7128 GEN_VXFORM(vrlh, 2, 1);
7129 GEN_VXFORM(vrlw, 2, 2);
7130 GEN_VXFORM(vrld, 2, 3);
7131 GEN_VXFORM(vsl, 2, 7);
7132 GEN_VXFORM(vsr, 2, 11);
7133 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7134 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7135 GEN_VXFORM_ENV(vpkudum, 7, 17);
7136 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7137 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7138 GEN_VXFORM_ENV(vpkudus, 7, 19);
7139 GEN_VXFORM_ENV(vpkshus, 7, 4);
7140 GEN_VXFORM_ENV(vpkswus, 7, 5);
7141 GEN_VXFORM_ENV(vpksdus, 7, 21);
7142 GEN_VXFORM_ENV(vpkshss, 7, 6);
7143 GEN_VXFORM_ENV(vpkswss, 7, 7);
7144 GEN_VXFORM_ENV(vpksdss, 7, 23);
7145 GEN_VXFORM(vpkpx, 7, 12);
7146 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7147 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7148 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7149 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7150 GEN_VXFORM_ENV(vsumsws, 4, 30);
7151 GEN_VXFORM_ENV(vaddfp, 5, 0);
7152 GEN_VXFORM_ENV(vsubfp, 5, 1);
7153 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7154 GEN_VXFORM_ENV(vminfp, 5, 17);
7155
7156 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7157 static void glue(gen_, name)(DisasContext *ctx) \
7158 { \
7159 TCGv_ptr ra, rb, rd; \
7160 if (unlikely(!ctx->altivec_enabled)) { \
7161 gen_exception(ctx, POWERPC_EXCP_VPU); \
7162 return; \
7163 } \
7164 ra = gen_avr_ptr(rA(ctx->opcode)); \
7165 rb = gen_avr_ptr(rB(ctx->opcode)); \
7166 rd = gen_avr_ptr(rD(ctx->opcode)); \
7167 gen_helper_##opname(cpu_env, rd, ra, rb); \
7168 tcg_temp_free_ptr(ra); \
7169 tcg_temp_free_ptr(rb); \
7170 tcg_temp_free_ptr(rd); \
7171 }
7172
7173 #define GEN_VXRFORM(name, opc2, opc3) \
7174 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7175 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7176
7177 /*
7178 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7179 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7180 * come from different versions of the ISA, so we must also support a
7181 * pair of flags for each instruction.
7182 */
7183 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7184 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7185 { \
7186 if ((Rc(ctx->opcode) == 0) && \
7187 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7188 if (Rc21(ctx->opcode) == 0) { \
7189 gen_##name0(ctx); \
7190 } else { \
7191 gen_##name0##_(ctx); \
7192 } \
7193 } else if ((Rc(ctx->opcode) == 1) && \
7194 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7195 if (Rc21(ctx->opcode) == 0) { \
7196 gen_##name1(ctx); \
7197 } else { \
7198 gen_##name1##_(ctx); \
7199 } \
7200 } else { \
7201 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7202 } \
7203 }
7204
7205 GEN_VXRFORM(vcmpequb, 3, 0)
7206 GEN_VXRFORM(vcmpequh, 3, 1)
7207 GEN_VXRFORM(vcmpequw, 3, 2)
7208 GEN_VXRFORM(vcmpequd, 3, 3)
7209 GEN_VXRFORM(vcmpgtsb, 3, 12)
7210 GEN_VXRFORM(vcmpgtsh, 3, 13)
7211 GEN_VXRFORM(vcmpgtsw, 3, 14)
7212 GEN_VXRFORM(vcmpgtsd, 3, 15)
7213 GEN_VXRFORM(vcmpgtub, 3, 8)
7214 GEN_VXRFORM(vcmpgtuh, 3, 9)
7215 GEN_VXRFORM(vcmpgtuw, 3, 10)
7216 GEN_VXRFORM(vcmpgtud, 3, 11)
7217 GEN_VXRFORM(vcmpeqfp, 3, 3)
7218 GEN_VXRFORM(vcmpgefp, 3, 7)
7219 GEN_VXRFORM(vcmpgtfp, 3, 11)
7220 GEN_VXRFORM(vcmpbfp, 3, 15)
7221
7222 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7223 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7224 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7225 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7226 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7227 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7228
7229 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7230 static void glue(gen_, name)(DisasContext *ctx) \
7231 { \
7232 TCGv_ptr rd; \
7233 TCGv_i32 simm; \
7234 if (unlikely(!ctx->altivec_enabled)) { \
7235 gen_exception(ctx, POWERPC_EXCP_VPU); \
7236 return; \
7237 } \
7238 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7239 rd = gen_avr_ptr(rD(ctx->opcode)); \
7240 gen_helper_##name (rd, simm); \
7241 tcg_temp_free_i32(simm); \
7242 tcg_temp_free_ptr(rd); \
7243 }
7244
7245 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7246 GEN_VXFORM_SIMM(vspltish, 6, 13);
7247 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7248
7249 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7250 static void glue(gen_, name)(DisasContext *ctx) \
7251 { \
7252 TCGv_ptr rb, rd; \
7253 if (unlikely(!ctx->altivec_enabled)) { \
7254 gen_exception(ctx, POWERPC_EXCP_VPU); \
7255 return; \
7256 } \
7257 rb = gen_avr_ptr(rB(ctx->opcode)); \
7258 rd = gen_avr_ptr(rD(ctx->opcode)); \
7259 gen_helper_##name (rd, rb); \
7260 tcg_temp_free_ptr(rb); \
7261 tcg_temp_free_ptr(rd); \
7262 }
7263
7264 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7265 static void glue(gen_, name)(DisasContext *ctx) \
7266 { \
7267 TCGv_ptr rb, rd; \
7268 \
7269 if (unlikely(!ctx->altivec_enabled)) { \
7270 gen_exception(ctx, POWERPC_EXCP_VPU); \
7271 return; \
7272 } \
7273 rb = gen_avr_ptr(rB(ctx->opcode)); \
7274 rd = gen_avr_ptr(rD(ctx->opcode)); \
7275 gen_helper_##name(cpu_env, rd, rb); \
7276 tcg_temp_free_ptr(rb); \
7277 tcg_temp_free_ptr(rd); \
7278 }
7279
7280 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7281 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7282 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7283 GEN_VXFORM_NOA(vupklsb, 7, 10);
7284 GEN_VXFORM_NOA(vupklsh, 7, 11);
7285 GEN_VXFORM_NOA(vupklsw, 7, 27);
7286 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7287 GEN_VXFORM_NOA(vupklpx, 7, 15);
7288 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7289 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7290 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7291 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7292 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7293 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7294 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7295 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7296
7297 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7298 static void glue(gen_, name)(DisasContext *ctx) \
7299 { \
7300 TCGv_ptr rd; \
7301 TCGv_i32 simm; \
7302 if (unlikely(!ctx->altivec_enabled)) { \
7303 gen_exception(ctx, POWERPC_EXCP_VPU); \
7304 return; \
7305 } \
7306 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7307 rd = gen_avr_ptr(rD(ctx->opcode)); \
7308 gen_helper_##name (rd, simm); \
7309 tcg_temp_free_i32(simm); \
7310 tcg_temp_free_ptr(rd); \
7311 }
7312
7313 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7314 static void glue(gen_, name)(DisasContext *ctx) \
7315 { \
7316 TCGv_ptr rb, rd; \
7317 TCGv_i32 uimm; \
7318 if (unlikely(!ctx->altivec_enabled)) { \
7319 gen_exception(ctx, POWERPC_EXCP_VPU); \
7320 return; \
7321 } \
7322 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7323 rb = gen_avr_ptr(rB(ctx->opcode)); \
7324 rd = gen_avr_ptr(rD(ctx->opcode)); \
7325 gen_helper_##name (rd, rb, uimm); \
7326 tcg_temp_free_i32(uimm); \
7327 tcg_temp_free_ptr(rb); \
7328 tcg_temp_free_ptr(rd); \
7329 }
7330
7331 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7332 static void glue(gen_, name)(DisasContext *ctx) \
7333 { \
7334 TCGv_ptr rb, rd; \
7335 TCGv_i32 uimm; \
7336 \
7337 if (unlikely(!ctx->altivec_enabled)) { \
7338 gen_exception(ctx, POWERPC_EXCP_VPU); \
7339 return; \
7340 } \
7341 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7342 rb = gen_avr_ptr(rB(ctx->opcode)); \
7343 rd = gen_avr_ptr(rD(ctx->opcode)); \
7344 gen_helper_##name(cpu_env, rd, rb, uimm); \
7345 tcg_temp_free_i32(uimm); \
7346 tcg_temp_free_ptr(rb); \
7347 tcg_temp_free_ptr(rd); \
7348 }
7349
7350 GEN_VXFORM_UIMM(vspltb, 6, 8);
7351 GEN_VXFORM_UIMM(vsplth, 6, 9);
7352 GEN_VXFORM_UIMM(vspltw, 6, 10);
7353 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7354 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7355 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7356 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7357
7358 static void gen_vsldoi(DisasContext *ctx)
7359 {
7360 TCGv_ptr ra, rb, rd;
7361 TCGv_i32 sh;
7362 if (unlikely(!ctx->altivec_enabled)) {
7363 gen_exception(ctx, POWERPC_EXCP_VPU);
7364 return;
7365 }
7366 ra = gen_avr_ptr(rA(ctx->opcode));
7367 rb = gen_avr_ptr(rB(ctx->opcode));
7368 rd = gen_avr_ptr(rD(ctx->opcode));
7369 sh = tcg_const_i32(VSH(ctx->opcode));
7370 gen_helper_vsldoi (rd, ra, rb, sh);
7371 tcg_temp_free_ptr(ra);
7372 tcg_temp_free_ptr(rb);
7373 tcg_temp_free_ptr(rd);
7374 tcg_temp_free_i32(sh);
7375 }
7376
7377 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7378 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7379 { \
7380 TCGv_ptr ra, rb, rc, rd; \
7381 if (unlikely(!ctx->altivec_enabled)) { \
7382 gen_exception(ctx, POWERPC_EXCP_VPU); \
7383 return; \
7384 } \
7385 ra = gen_avr_ptr(rA(ctx->opcode)); \
7386 rb = gen_avr_ptr(rB(ctx->opcode)); \
7387 rc = gen_avr_ptr(rC(ctx->opcode)); \
7388 rd = gen_avr_ptr(rD(ctx->opcode)); \
7389 if (Rc(ctx->opcode)) { \
7390 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7391 } else { \
7392 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7393 } \
7394 tcg_temp_free_ptr(ra); \
7395 tcg_temp_free_ptr(rb); \
7396 tcg_temp_free_ptr(rc); \
7397 tcg_temp_free_ptr(rd); \
7398 }
7399
7400 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7401
7402 static void gen_vmladduhm(DisasContext *ctx)
7403 {
7404 TCGv_ptr ra, rb, rc, rd;
7405 if (unlikely(!ctx->altivec_enabled)) {
7406 gen_exception(ctx, POWERPC_EXCP_VPU);
7407 return;
7408 }
7409 ra = gen_avr_ptr(rA(ctx->opcode));
7410 rb = gen_avr_ptr(rB(ctx->opcode));
7411 rc = gen_avr_ptr(rC(ctx->opcode));
7412 rd = gen_avr_ptr(rD(ctx->opcode));
7413 gen_helper_vmladduhm(rd, ra, rb, rc);
7414 tcg_temp_free_ptr(ra);
7415 tcg_temp_free_ptr(rb);
7416 tcg_temp_free_ptr(rc);
7417 tcg_temp_free_ptr(rd);
7418 }
7419
7420 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7421 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7422 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7423 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7424 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7425
7426 GEN_VXFORM_NOA(vclzb, 1, 28)
7427 GEN_VXFORM_NOA(vclzh, 1, 29)
7428 GEN_VXFORM_NOA(vclzw, 1, 30)
7429 GEN_VXFORM_NOA(vclzd, 1, 31)
7430 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7431 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7432 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7433 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7434 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7435 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7436 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7437 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7438 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7439 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7440 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7441 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7442 GEN_VXFORM(vbpermq, 6, 21);
7443 GEN_VXFORM_NOA(vgbbd, 6, 20);
7444 GEN_VXFORM(vpmsumb, 4, 16)
7445 GEN_VXFORM(vpmsumh, 4, 17)
7446 GEN_VXFORM(vpmsumw, 4, 18)
7447 GEN_VXFORM(vpmsumd, 4, 19)
7448
7449 #define GEN_BCD(op) \
7450 static void gen_##op(DisasContext *ctx) \
7451 { \
7452 TCGv_ptr ra, rb, rd; \
7453 TCGv_i32 ps; \
7454 \
7455 if (unlikely(!ctx->altivec_enabled)) { \
7456 gen_exception(ctx, POWERPC_EXCP_VPU); \
7457 return; \
7458 } \
7459 \
7460 ra = gen_avr_ptr(rA(ctx->opcode)); \
7461 rb = gen_avr_ptr(rB(ctx->opcode)); \
7462 rd = gen_avr_ptr(rD(ctx->opcode)); \
7463 \
7464 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7465 \
7466 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7467 \
7468 tcg_temp_free_ptr(ra); \
7469 tcg_temp_free_ptr(rb); \
7470 tcg_temp_free_ptr(rd); \
7471 tcg_temp_free_i32(ps); \
7472 }
7473
7474 GEN_BCD(bcdadd)
7475 GEN_BCD(bcdsub)
7476
7477 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7478 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7479 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7480 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7481 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7482 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7483 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7484 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7485
7486 static void gen_vsbox(DisasContext *ctx)
7487 {
7488 TCGv_ptr ra, rd;
7489 if (unlikely(!ctx->altivec_enabled)) {
7490 gen_exception(ctx, POWERPC_EXCP_VPU);
7491 return;
7492 }
7493 ra = gen_avr_ptr(rA(ctx->opcode));
7494 rd = gen_avr_ptr(rD(ctx->opcode));
7495 gen_helper_vsbox(rd, ra);
7496 tcg_temp_free_ptr(ra);
7497 tcg_temp_free_ptr(rd);
7498 }
7499
7500 GEN_VXFORM(vcipher, 4, 20)
7501 GEN_VXFORM(vcipherlast, 4, 20)
7502 GEN_VXFORM(vncipher, 4, 21)
7503 GEN_VXFORM(vncipherlast, 4, 21)
7504
7505 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7506 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7507 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7508 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7509
7510 #define VSHASIGMA(op) \
7511 static void gen_##op(DisasContext *ctx) \
7512 { \
7513 TCGv_ptr ra, rd; \
7514 TCGv_i32 st_six; \
7515 if (unlikely(!ctx->altivec_enabled)) { \
7516 gen_exception(ctx, POWERPC_EXCP_VPU); \
7517 return; \
7518 } \
7519 ra = gen_avr_ptr(rA(ctx->opcode)); \
7520 rd = gen_avr_ptr(rD(ctx->opcode)); \
7521 st_six = tcg_const_i32(rB(ctx->opcode)); \
7522 gen_helper_##op(rd, ra, st_six); \
7523 tcg_temp_free_ptr(ra); \
7524 tcg_temp_free_ptr(rd); \
7525 tcg_temp_free_i32(st_six); \
7526 }
7527
7528 VSHASIGMA(vshasigmaw)
7529 VSHASIGMA(vshasigmad)
7530
7531 GEN_VXFORM3(vpermxor, 22, 0xFF)
7532 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7533 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7534
7535 /*** VSX extension ***/
7536
7537 static inline TCGv_i64 cpu_vsrh(int n)
7538 {
7539 if (n < 32) {
7540 return cpu_fpr[n];
7541 } else {
7542 return cpu_avrh[n-32];
7543 }
7544 }
7545
7546 static inline TCGv_i64 cpu_vsrl(int n)
7547 {
7548 if (n < 32) {
7549 return cpu_vsr[n];
7550 } else {
7551 return cpu_avrl[n-32];
7552 }
7553 }
7554
7555 #define VSX_LOAD_SCALAR(name, operation) \
7556 static void gen_##name(DisasContext *ctx) \
7557 { \
7558 TCGv EA; \
7559 if (unlikely(!ctx->vsx_enabled)) { \
7560 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7561 return; \
7562 } \
7563 gen_set_access_type(ctx, ACCESS_INT); \
7564 EA = tcg_temp_new(); \
7565 gen_addr_reg_index(ctx, EA); \
7566 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7567 /* NOTE: cpu_vsrl is undefined */ \
7568 tcg_temp_free(EA); \
7569 }
7570
7571 VSX_LOAD_SCALAR(lxsdx, ld64)
7572 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7573 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7574 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7575
7576 static void gen_lxvd2x(DisasContext *ctx)
7577 {
7578 TCGv EA;
7579 if (unlikely(!ctx->vsx_enabled)) {
7580 gen_exception(ctx, POWERPC_EXCP_VSXU);
7581 return;
7582 }
7583 gen_set_access_type(ctx, ACCESS_INT);
7584 EA = tcg_temp_new();
7585 gen_addr_reg_index(ctx, EA);
7586 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7587 tcg_gen_addi_tl(EA, EA, 8);
7588 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7589 tcg_temp_free(EA);
7590 }
7591
7592 static void gen_lxvdsx(DisasContext *ctx)
7593 {
7594 TCGv EA;
7595 if (unlikely(!ctx->vsx_enabled)) {
7596 gen_exception(ctx, POWERPC_EXCP_VSXU);
7597 return;
7598 }
7599 gen_set_access_type(ctx, ACCESS_INT);
7600 EA = tcg_temp_new();
7601 gen_addr_reg_index(ctx, EA);
7602 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7603 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7604 tcg_temp_free(EA);
7605 }
7606
7607 static void gen_lxvw4x(DisasContext *ctx)
7608 {
7609 TCGv EA;
7610 TCGv_i64 tmp;
7611 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7612 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7613 if (unlikely(!ctx->vsx_enabled)) {
7614 gen_exception(ctx, POWERPC_EXCP_VSXU);
7615 return;
7616 }
7617 gen_set_access_type(ctx, ACCESS_INT);
7618 EA = tcg_temp_new();
7619 tmp = tcg_temp_new_i64();
7620
7621 gen_addr_reg_index(ctx, EA);
7622 gen_qemu_ld32u_i64(ctx, tmp, EA);
7623 tcg_gen_addi_tl(EA, EA, 4);
7624 gen_qemu_ld32u_i64(ctx, xth, EA);
7625 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7626
7627 tcg_gen_addi_tl(EA, EA, 4);
7628 gen_qemu_ld32u_i64(ctx, tmp, EA);
7629 tcg_gen_addi_tl(EA, EA, 4);
7630 gen_qemu_ld32u_i64(ctx, xtl, EA);
7631 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7632
7633 tcg_temp_free(EA);
7634 tcg_temp_free_i64(tmp);
7635 }
7636
7637 #define VSX_STORE_SCALAR(name, operation) \
7638 static void gen_##name(DisasContext *ctx) \
7639 { \
7640 TCGv EA; \
7641 if (unlikely(!ctx->vsx_enabled)) { \
7642 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7643 return; \
7644 } \
7645 gen_set_access_type(ctx, ACCESS_INT); \
7646 EA = tcg_temp_new(); \
7647 gen_addr_reg_index(ctx, EA); \
7648 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7649 tcg_temp_free(EA); \
7650 }
7651
7652 VSX_STORE_SCALAR(stxsdx, st64)
7653 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7654 VSX_STORE_SCALAR(stxsspx, st32fs)
7655
7656 static void gen_stxvd2x(DisasContext *ctx)
7657 {
7658 TCGv EA;
7659 if (unlikely(!ctx->vsx_enabled)) {
7660 gen_exception(ctx, POWERPC_EXCP_VSXU);
7661 return;
7662 }
7663 gen_set_access_type(ctx, ACCESS_INT);
7664 EA = tcg_temp_new();
7665 gen_addr_reg_index(ctx, EA);
7666 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7667 tcg_gen_addi_tl(EA, EA, 8);
7668 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7669 tcg_temp_free(EA);
7670 }
7671
7672 static void gen_stxvw4x(DisasContext *ctx)
7673 {
7674 TCGv_i64 tmp;
7675 TCGv EA;
7676 if (unlikely(!ctx->vsx_enabled)) {
7677 gen_exception(ctx, POWERPC_EXCP_VSXU);
7678 return;
7679 }
7680 gen_set_access_type(ctx, ACCESS_INT);
7681 EA = tcg_temp_new();
7682 gen_addr_reg_index(ctx, EA);
7683 tmp = tcg_temp_new_i64();
7684
7685 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7686 gen_qemu_st32_i64(ctx, tmp, EA);
7687 tcg_gen_addi_tl(EA, EA, 4);
7688 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7689
7690 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7691 tcg_gen_addi_tl(EA, EA, 4);
7692 gen_qemu_st32_i64(ctx, tmp, EA);
7693 tcg_gen_addi_tl(EA, EA, 4);
7694 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7695
7696 tcg_temp_free(EA);
7697 tcg_temp_free_i64(tmp);
7698 }
7699
7700 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7701 static void gen_##name(DisasContext *ctx) \
7702 { \
7703 if (xS(ctx->opcode) < 32) { \
7704 if (unlikely(!ctx->fpu_enabled)) { \
7705 gen_exception(ctx, POWERPC_EXCP_FPU); \
7706 return; \
7707 } \
7708 } else { \
7709 if (unlikely(!ctx->altivec_enabled)) { \
7710 gen_exception(ctx, POWERPC_EXCP_VPU); \
7711 return; \
7712 } \
7713 } \
7714 TCGv_i64 tmp = tcg_temp_new_i64(); \
7715 tcg_gen_##tcgop1(tmp, source); \
7716 tcg_gen_##tcgop2(target, tmp); \
7717 tcg_temp_free_i64(tmp); \
7718 }
7719
7720
7721 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7722 cpu_vsrh(xS(ctx->opcode)))
7723 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7724 cpu_gpr[rA(ctx->opcode)])
7725 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7726 cpu_gpr[rA(ctx->opcode)])
7727
7728 #if defined(TARGET_PPC64)
7729 #define MV_VSRD(name, target, source) \
7730 static void gen_##name(DisasContext *ctx) \
7731 { \
7732 if (xS(ctx->opcode) < 32) { \
7733 if (unlikely(!ctx->fpu_enabled)) { \
7734 gen_exception(ctx, POWERPC_EXCP_FPU); \
7735 return; \
7736 } \
7737 } else { \
7738 if (unlikely(!ctx->altivec_enabled)) { \
7739 gen_exception(ctx, POWERPC_EXCP_VPU); \
7740 return; \
7741 } \
7742 } \
7743 tcg_gen_mov_i64(target, source); \
7744 }
7745
7746 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7747 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7748
7749 #endif
7750
7751 static void gen_xxpermdi(DisasContext *ctx)
7752 {
7753 if (unlikely(!ctx->vsx_enabled)) {
7754 gen_exception(ctx, POWERPC_EXCP_VSXU);
7755 return;
7756 }
7757
7758 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7759 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7760 TCGv_i64 xh, xl;
7761
7762 xh = tcg_temp_new_i64();
7763 xl = tcg_temp_new_i64();
7764
7765 if ((DM(ctx->opcode) & 2) == 0) {
7766 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7767 } else {
7768 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7769 }
7770 if ((DM(ctx->opcode) & 1) == 0) {
7771 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7772 } else {
7773 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7774 }
7775
7776 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7777 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7778
7779 tcg_temp_free_i64(xh);
7780 tcg_temp_free_i64(xl);
7781 } else {
7782 if ((DM(ctx->opcode) & 2) == 0) {
7783 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7784 } else {
7785 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7786 }
7787 if ((DM(ctx->opcode) & 1) == 0) {
7788 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7789 } else {
7790 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7791 }
7792 }
7793 }
7794
7795 #define OP_ABS 1
7796 #define OP_NABS 2
7797 #define OP_NEG 3
7798 #define OP_CPSGN 4
7799 #define SGN_MASK_DP 0x8000000000000000ull
7800 #define SGN_MASK_SP 0x8000000080000000ull
7801
7802 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7803 static void glue(gen_, name)(DisasContext * ctx) \
7804 { \
7805 TCGv_i64 xb, sgm; \
7806 if (unlikely(!ctx->vsx_enabled)) { \
7807 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7808 return; \
7809 } \
7810 xb = tcg_temp_new_i64(); \
7811 sgm = tcg_temp_new_i64(); \
7812 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7813 tcg_gen_movi_i64(sgm, sgn_mask); \
7814 switch (op) { \
7815 case OP_ABS: { \
7816 tcg_gen_andc_i64(xb, xb, sgm); \
7817 break; \
7818 } \
7819 case OP_NABS: { \
7820 tcg_gen_or_i64(xb, xb, sgm); \
7821 break; \
7822 } \
7823 case OP_NEG: { \
7824 tcg_gen_xor_i64(xb, xb, sgm); \
7825 break; \
7826 } \
7827 case OP_CPSGN: { \
7828 TCGv_i64 xa = tcg_temp_new_i64(); \
7829 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7830 tcg_gen_and_i64(xa, xa, sgm); \
7831 tcg_gen_andc_i64(xb, xb, sgm); \
7832 tcg_gen_or_i64(xb, xb, xa); \
7833 tcg_temp_free_i64(xa); \
7834 break; \
7835 } \
7836 } \
7837 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7838 tcg_temp_free_i64(xb); \
7839 tcg_temp_free_i64(sgm); \
7840 }
7841
7842 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7843 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7844 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7845 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7846
7847 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7848 static void glue(gen_, name)(DisasContext * ctx) \
7849 { \
7850 TCGv_i64 xbh, xbl, sgm; \
7851 if (unlikely(!ctx->vsx_enabled)) { \
7852 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7853 return; \
7854 } \
7855 xbh = tcg_temp_new_i64(); \
7856 xbl = tcg_temp_new_i64(); \
7857 sgm = tcg_temp_new_i64(); \
7858 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7859 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7860 tcg_gen_movi_i64(sgm, sgn_mask); \
7861 switch (op) { \
7862 case OP_ABS: { \
7863 tcg_gen_andc_i64(xbh, xbh, sgm); \
7864 tcg_gen_andc_i64(xbl, xbl, sgm); \
7865 break; \
7866 } \
7867 case OP_NABS: { \
7868 tcg_gen_or_i64(xbh, xbh, sgm); \
7869 tcg_gen_or_i64(xbl, xbl, sgm); \
7870 break; \
7871 } \
7872 case OP_NEG: { \
7873 tcg_gen_xor_i64(xbh, xbh, sgm); \
7874 tcg_gen_xor_i64(xbl, xbl, sgm); \
7875 break; \
7876 } \
7877 case OP_CPSGN: { \
7878 TCGv_i64 xah = tcg_temp_new_i64(); \
7879 TCGv_i64 xal = tcg_temp_new_i64(); \
7880 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7881 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7882 tcg_gen_and_i64(xah, xah, sgm); \
7883 tcg_gen_and_i64(xal, xal, sgm); \
7884 tcg_gen_andc_i64(xbh, xbh, sgm); \
7885 tcg_gen_andc_i64(xbl, xbl, sgm); \
7886 tcg_gen_or_i64(xbh, xbh, xah); \
7887 tcg_gen_or_i64(xbl, xbl, xal); \
7888 tcg_temp_free_i64(xah); \
7889 tcg_temp_free_i64(xal); \
7890 break; \
7891 } \
7892 } \
7893 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7894 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7895 tcg_temp_free_i64(xbh); \
7896 tcg_temp_free_i64(xbl); \
7897 tcg_temp_free_i64(sgm); \
7898 }
7899
7900 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7901 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7902 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7903 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7904 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7905 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7906 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7907 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7908
7909 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7910 static void gen_##name(DisasContext * ctx) \
7911 { \
7912 TCGv_i32 opc; \
7913 if (unlikely(!ctx->vsx_enabled)) { \
7914 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7915 return; \
7916 } \
7917 /* NIP cannot be restored if the memory exception comes from an helper */ \
7918 gen_update_nip(ctx, ctx->nip - 4); \
7919 opc = tcg_const_i32(ctx->opcode); \
7920 gen_helper_##name(cpu_env, opc); \
7921 tcg_temp_free_i32(opc); \
7922 }
7923
7924 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7925 static void gen_##name(DisasContext * ctx) \
7926 { \
7927 if (unlikely(!ctx->vsx_enabled)) { \
7928 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7929 return; \
7930 } \
7931 /* NIP cannot be restored if the exception comes */ \
7932 /* from a helper. */ \
7933 gen_update_nip(ctx, ctx->nip - 4); \
7934 \
7935 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7936 cpu_vsrh(xB(ctx->opcode))); \
7937 }
7938
7939 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7962 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7964 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7976
7977 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7978 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7979 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7980 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7981 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7982 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7983 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7984 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7985 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7986 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7987 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7988 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7989 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7990 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7991 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7992 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7993 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7994
7995 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8031
8032 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8033 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8068
8069 #define VSX_LOGICAL(name, tcg_op) \
8070 static void glue(gen_, name)(DisasContext * ctx) \
8071 { \
8072 if (unlikely(!ctx->vsx_enabled)) { \
8073 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8074 return; \
8075 } \
8076 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8077 cpu_vsrh(xB(ctx->opcode))); \
8078 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8079 cpu_vsrl(xB(ctx->opcode))); \
8080 }
8081
8082 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8083 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8084 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8085 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8086 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8087 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8088 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8089 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8090
8091 #define VSX_XXMRG(name, high) \
8092 static void glue(gen_, name)(DisasContext * ctx) \
8093 { \
8094 TCGv_i64 a0, a1, b0, b1; \
8095 if (unlikely(!ctx->vsx_enabled)) { \
8096 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8097 return; \
8098 } \
8099 a0 = tcg_temp_new_i64(); \
8100 a1 = tcg_temp_new_i64(); \
8101 b0 = tcg_temp_new_i64(); \
8102 b1 = tcg_temp_new_i64(); \
8103 if (high) { \
8104 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8105 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8106 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8107 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8108 } else { \
8109 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8110 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8111 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8112 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8113 } \
8114 tcg_gen_shri_i64(a0, a0, 32); \
8115 tcg_gen_shri_i64(b0, b0, 32); \
8116 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8117 b0, a0, 32, 32); \
8118 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8119 b1, a1, 32, 32); \
8120 tcg_temp_free_i64(a0); \
8121 tcg_temp_free_i64(a1); \
8122 tcg_temp_free_i64(b0); \
8123 tcg_temp_free_i64(b1); \
8124 }
8125
8126 VSX_XXMRG(xxmrghw, 1)
8127 VSX_XXMRG(xxmrglw, 0)
8128
8129 static void gen_xxsel(DisasContext * ctx)
8130 {
8131 TCGv_i64 a, b, c;
8132 if (unlikely(!ctx->vsx_enabled)) {
8133 gen_exception(ctx, POWERPC_EXCP_VSXU);
8134 return;
8135 }
8136 a = tcg_temp_new_i64();
8137 b = tcg_temp_new_i64();
8138 c = tcg_temp_new_i64();
8139
8140 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8141 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8142 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8143
8144 tcg_gen_and_i64(b, b, c);
8145 tcg_gen_andc_i64(a, a, c);
8146 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8147
8148 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8149 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8150 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8151
8152 tcg_gen_and_i64(b, b, c);
8153 tcg_gen_andc_i64(a, a, c);
8154 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8155
8156 tcg_temp_free_i64(a);
8157 tcg_temp_free_i64(b);
8158 tcg_temp_free_i64(c);
8159 }
8160
8161 static void gen_xxspltw(DisasContext *ctx)
8162 {
8163 TCGv_i64 b, b2;
8164 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8165 cpu_vsrl(xB(ctx->opcode)) :
8166 cpu_vsrh(xB(ctx->opcode));
8167
8168 if (unlikely(!ctx->vsx_enabled)) {
8169 gen_exception(ctx, POWERPC_EXCP_VSXU);
8170 return;
8171 }
8172
8173 b = tcg_temp_new_i64();
8174 b2 = tcg_temp_new_i64();
8175
8176 if (UIM(ctx->opcode) & 1) {
8177 tcg_gen_ext32u_i64(b, vsr);
8178 } else {
8179 tcg_gen_shri_i64(b, vsr, 32);
8180 }
8181
8182 tcg_gen_shli_i64(b2, b, 32);
8183 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8184 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8185
8186 tcg_temp_free_i64(b);
8187 tcg_temp_free_i64(b2);
8188 }
8189
8190 static void gen_xxsldwi(DisasContext *ctx)
8191 {
8192 TCGv_i64 xth, xtl;
8193 if (unlikely(!ctx->vsx_enabled)) {
8194 gen_exception(ctx, POWERPC_EXCP_VSXU);
8195 return;
8196 }
8197 xth = tcg_temp_new_i64();
8198 xtl = tcg_temp_new_i64();
8199
8200 switch (SHW(ctx->opcode)) {
8201 case 0: {
8202 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8203 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8204 break;
8205 }
8206 case 1: {
8207 TCGv_i64 t0 = tcg_temp_new_i64();
8208 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8209 tcg_gen_shli_i64(xth, xth, 32);
8210 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8211 tcg_gen_shri_i64(t0, t0, 32);
8212 tcg_gen_or_i64(xth, xth, t0);
8213 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8214 tcg_gen_shli_i64(xtl, xtl, 32);
8215 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8216 tcg_gen_shri_i64(t0, t0, 32);
8217 tcg_gen_or_i64(xtl, xtl, t0);
8218 tcg_temp_free_i64(t0);
8219 break;
8220 }
8221 case 2: {
8222 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8223 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8224 break;
8225 }
8226 case 3: {
8227 TCGv_i64 t0 = tcg_temp_new_i64();
8228 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8229 tcg_gen_shli_i64(xth, xth, 32);
8230 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8231 tcg_gen_shri_i64(t0, t0, 32);
8232 tcg_gen_or_i64(xth, xth, t0);
8233 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8234 tcg_gen_shli_i64(xtl, xtl, 32);
8235 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8236 tcg_gen_shri_i64(t0, t0, 32);
8237 tcg_gen_or_i64(xtl, xtl, t0);
8238 tcg_temp_free_i64(t0);
8239 break;
8240 }
8241 }
8242
8243 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8244 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8245
8246 tcg_temp_free_i64(xth);
8247 tcg_temp_free_i64(xtl);
8248 }
8249
8250 /*** Decimal Floating Point ***/
8251
8252 static inline TCGv_ptr gen_fprp_ptr(int reg)
8253 {
8254 TCGv_ptr r = tcg_temp_new_ptr();
8255 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8256 return r;
8257 }
8258
8259 #define GEN_DFP_T_A_B_Rc(name) \
8260 static void gen_##name(DisasContext *ctx) \
8261 { \
8262 TCGv_ptr rd, ra, rb; \
8263 if (unlikely(!ctx->fpu_enabled)) { \
8264 gen_exception(ctx, POWERPC_EXCP_FPU); \
8265 return; \
8266 } \
8267 gen_update_nip(ctx, ctx->nip - 4); \
8268 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8269 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8270 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8271 gen_helper_##name(cpu_env, rd, ra, rb); \
8272 if (unlikely(Rc(ctx->opcode) != 0)) { \
8273 gen_set_cr1_from_fpscr(ctx); \
8274 } \
8275 tcg_temp_free_ptr(rd); \
8276 tcg_temp_free_ptr(ra); \
8277 tcg_temp_free_ptr(rb); \
8278 }
8279
8280 #define GEN_DFP_BF_A_B(name) \
8281 static void gen_##name(DisasContext *ctx) \
8282 { \
8283 TCGv_ptr ra, rb; \
8284 if (unlikely(!ctx->fpu_enabled)) { \
8285 gen_exception(ctx, POWERPC_EXCP_FPU); \
8286 return; \
8287 } \
8288 gen_update_nip(ctx, ctx->nip - 4); \
8289 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8290 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8291 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8292 cpu_env, ra, rb); \
8293 tcg_temp_free_ptr(ra); \
8294 tcg_temp_free_ptr(rb); \
8295 }
8296
8297 #define GEN_DFP_BF_A_DCM(name) \
8298 static void gen_##name(DisasContext *ctx) \
8299 { \
8300 TCGv_ptr ra; \
8301 TCGv_i32 dcm; \
8302 if (unlikely(!ctx->fpu_enabled)) { \
8303 gen_exception(ctx, POWERPC_EXCP_FPU); \
8304 return; \
8305 } \
8306 gen_update_nip(ctx, ctx->nip - 4); \
8307 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8308 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8309 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8310 cpu_env, ra, dcm); \
8311 tcg_temp_free_ptr(ra); \
8312 tcg_temp_free_i32(dcm); \
8313 }
8314
8315 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8316 static void gen_##name(DisasContext *ctx) \
8317 { \
8318 TCGv_ptr rt, rb; \
8319 TCGv_i32 u32_1, u32_2; \
8320 if (unlikely(!ctx->fpu_enabled)) { \
8321 gen_exception(ctx, POWERPC_EXCP_FPU); \
8322 return; \
8323 } \
8324 gen_update_nip(ctx, ctx->nip - 4); \
8325 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8326 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8327 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8328 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8329 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8330 if (unlikely(Rc(ctx->opcode) != 0)) { \
8331 gen_set_cr1_from_fpscr(ctx); \
8332 } \
8333 tcg_temp_free_ptr(rt); \
8334 tcg_temp_free_ptr(rb); \
8335 tcg_temp_free_i32(u32_1); \
8336 tcg_temp_free_i32(u32_2); \
8337 }
8338
8339 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8340 static void gen_##name(DisasContext *ctx) \
8341 { \
8342 TCGv_ptr rt, ra, rb; \
8343 TCGv_i32 i32; \
8344 if (unlikely(!ctx->fpu_enabled)) { \
8345 gen_exception(ctx, POWERPC_EXCP_FPU); \
8346 return; \
8347 } \
8348 gen_update_nip(ctx, ctx->nip - 4); \
8349 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8350 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8351 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8352 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8353 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8354 if (unlikely(Rc(ctx->opcode) != 0)) { \
8355 gen_set_cr1_from_fpscr(ctx); \
8356 } \
8357 tcg_temp_free_ptr(rt); \
8358 tcg_temp_free_ptr(rb); \
8359 tcg_temp_free_ptr(ra); \
8360 tcg_temp_free_i32(i32); \
8361 }
8362
8363 #define GEN_DFP_T_B_Rc(name) \
8364 static void gen_##name(DisasContext *ctx) \
8365 { \
8366 TCGv_ptr rt, rb; \
8367 if (unlikely(!ctx->fpu_enabled)) { \
8368 gen_exception(ctx, POWERPC_EXCP_FPU); \
8369 return; \
8370 } \
8371 gen_update_nip(ctx, ctx->nip - 4); \
8372 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8373 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8374 gen_helper_##name(cpu_env, rt, rb); \
8375 if (unlikely(Rc(ctx->opcode) != 0)) { \
8376 gen_set_cr1_from_fpscr(ctx); \
8377 } \
8378 tcg_temp_free_ptr(rt); \
8379 tcg_temp_free_ptr(rb); \
8380 }
8381
8382 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8383 static void gen_##name(DisasContext *ctx) \
8384 { \
8385 TCGv_ptr rt, rs; \
8386 TCGv_i32 i32; \
8387 if (unlikely(!ctx->fpu_enabled)) { \
8388 gen_exception(ctx, POWERPC_EXCP_FPU); \
8389 return; \
8390 } \
8391 gen_update_nip(ctx, ctx->nip - 4); \
8392 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8393 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8394 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8395 gen_helper_##name(cpu_env, rt, rs, i32); \
8396 if (unlikely(Rc(ctx->opcode) != 0)) { \
8397 gen_set_cr1_from_fpscr(ctx); \
8398 } \
8399 tcg_temp_free_ptr(rt); \
8400 tcg_temp_free_ptr(rs); \
8401 tcg_temp_free_i32(i32); \
8402 }
8403
8404 GEN_DFP_T_A_B_Rc(dadd)
8405 GEN_DFP_T_A_B_Rc(daddq)
8406 GEN_DFP_T_A_B_Rc(dsub)
8407 GEN_DFP_T_A_B_Rc(dsubq)
8408 GEN_DFP_T_A_B_Rc(dmul)
8409 GEN_DFP_T_A_B_Rc(dmulq)
8410 GEN_DFP_T_A_B_Rc(ddiv)
8411 GEN_DFP_T_A_B_Rc(ddivq)
8412 GEN_DFP_BF_A_B(dcmpu)
8413 GEN_DFP_BF_A_B(dcmpuq)
8414 GEN_DFP_BF_A_B(dcmpo)
8415 GEN_DFP_BF_A_B(dcmpoq)
8416 GEN_DFP_BF_A_DCM(dtstdc)
8417 GEN_DFP_BF_A_DCM(dtstdcq)
8418 GEN_DFP_BF_A_DCM(dtstdg)
8419 GEN_DFP_BF_A_DCM(dtstdgq)
8420 GEN_DFP_BF_A_B(dtstex)
8421 GEN_DFP_BF_A_B(dtstexq)
8422 GEN_DFP_BF_A_B(dtstsf)
8423 GEN_DFP_BF_A_B(dtstsfq)
8424 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8425 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8426 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8427 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8428 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8429 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8430 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8431 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8432 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8433 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8434 GEN_DFP_T_B_Rc(dctdp)
8435 GEN_DFP_T_B_Rc(dctqpq)
8436 GEN_DFP_T_B_Rc(drsp)
8437 GEN_DFP_T_B_Rc(drdpq)
8438 GEN_DFP_T_B_Rc(dcffix)
8439 GEN_DFP_T_B_Rc(dcffixq)
8440 GEN_DFP_T_B_Rc(dctfix)
8441 GEN_DFP_T_B_Rc(dctfixq)
8442 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8443 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8444 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8445 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8446 GEN_DFP_T_B_Rc(dxex)
8447 GEN_DFP_T_B_Rc(dxexq)
8448 GEN_DFP_T_A_B_Rc(diex)
8449 GEN_DFP_T_A_B_Rc(diexq)
8450 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8451 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8452 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8453 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8454
8455 /*** SPE extension ***/
8456 /* Register moves */
8457
8458 static inline void gen_evmra(DisasContext *ctx)
8459 {
8460
8461 if (unlikely(!ctx->spe_enabled)) {
8462 gen_exception(ctx, POWERPC_EXCP_SPEU);
8463 return;
8464 }
8465
8466 TCGv_i64 tmp = tcg_temp_new_i64();
8467
8468 /* tmp := rA_lo + rA_hi << 32 */
8469 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8470
8471 /* spe_acc := tmp */
8472 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8473 tcg_temp_free_i64(tmp);
8474
8475 /* rD := rA */
8476 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8477 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8478 }
8479
8480 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8481 {
8482 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8483 }
8484
8485 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8486 {
8487 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8488 }
8489
8490 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8491 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8492 { \
8493 if (Rc(ctx->opcode)) \
8494 gen_##name1(ctx); \
8495 else \
8496 gen_##name0(ctx); \
8497 }
8498
8499 /* Handler for undefined SPE opcodes */
8500 static inline void gen_speundef(DisasContext *ctx)
8501 {
8502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8503 }
8504
8505 /* SPE logic */
8506 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8507 static inline void gen_##name(DisasContext *ctx) \
8508 { \
8509 if (unlikely(!ctx->spe_enabled)) { \
8510 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8511 return; \
8512 } \
8513 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8514 cpu_gpr[rB(ctx->opcode)]); \
8515 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8516 cpu_gprh[rB(ctx->opcode)]); \
8517 }
8518
8519 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8520 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8521 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8522 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8523 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8524 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8525 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8526 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8527
8528 /* SPE logic immediate */
8529 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8530 static inline void gen_##name(DisasContext *ctx) \
8531 { \
8532 TCGv_i32 t0; \
8533 if (unlikely(!ctx->spe_enabled)) { \
8534 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8535 return; \
8536 } \
8537 t0 = tcg_temp_new_i32(); \
8538 \
8539 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8540 tcg_opi(t0, t0, rB(ctx->opcode)); \
8541 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8542 \
8543 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8544 tcg_opi(t0, t0, rB(ctx->opcode)); \
8545 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8546 \
8547 tcg_temp_free_i32(t0); \
8548 }
8549 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8550 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8551 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8552 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8553
8554 /* SPE arithmetic */
8555 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8556 static inline void gen_##name(DisasContext *ctx) \
8557 { \
8558 TCGv_i32 t0; \
8559 if (unlikely(!ctx->spe_enabled)) { \
8560 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8561 return; \
8562 } \
8563 t0 = tcg_temp_new_i32(); \
8564 \
8565 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8566 tcg_op(t0, t0); \
8567 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8568 \
8569 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8570 tcg_op(t0, t0); \
8571 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8572 \
8573 tcg_temp_free_i32(t0); \
8574 }
8575
8576 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8577 {
8578 TCGLabel *l1 = gen_new_label();
8579 TCGLabel *l2 = gen_new_label();
8580
8581 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8582 tcg_gen_neg_i32(ret, arg1);
8583 tcg_gen_br(l2);
8584 gen_set_label(l1);
8585 tcg_gen_mov_i32(ret, arg1);
8586 gen_set_label(l2);
8587 }
8588 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8589 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8590 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8591 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8592 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8593 {
8594 tcg_gen_addi_i32(ret, arg1, 0x8000);
8595 tcg_gen_ext16u_i32(ret, ret);
8596 }
8597 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8598 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8599 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8600
8601 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8602 static inline void gen_##name(DisasContext *ctx) \
8603 { \
8604 TCGv_i32 t0, t1; \
8605 if (unlikely(!ctx->spe_enabled)) { \
8606 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8607 return; \
8608 } \
8609 t0 = tcg_temp_new_i32(); \
8610 t1 = tcg_temp_new_i32(); \
8611 \
8612 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8613 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8614 tcg_op(t0, t0, t1); \
8615 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8616 \
8617 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8618 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8619 tcg_op(t0, t0, t1); \
8620 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8621 \
8622 tcg_temp_free_i32(t0); \
8623 tcg_temp_free_i32(t1); \
8624 }
8625
8626 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8627 {
8628 TCGLabel *l1 = gen_new_label();
8629 TCGLabel *l2 = gen_new_label();
8630 TCGv_i32 t0 = tcg_temp_local_new_i32();
8631
8632 /* No error here: 6 bits are used */
8633 tcg_gen_andi_i32(t0, arg2, 0x3F);
8634 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8635 tcg_gen_shr_i32(ret, arg1, t0);
8636 tcg_gen_br(l2);
8637 gen_set_label(l1);
8638 tcg_gen_movi_i32(ret, 0);
8639 gen_set_label(l2);
8640 tcg_temp_free_i32(t0);
8641 }
8642 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8643 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8644 {
8645 TCGLabel *l1 = gen_new_label();
8646 TCGLabel *l2 = gen_new_label();
8647 TCGv_i32 t0 = tcg_temp_local_new_i32();
8648
8649 /* No error here: 6 bits are used */
8650 tcg_gen_andi_i32(t0, arg2, 0x3F);
8651 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8652 tcg_gen_sar_i32(ret, arg1, t0);
8653 tcg_gen_br(l2);
8654 gen_set_label(l1);
8655 tcg_gen_movi_i32(ret, 0);
8656 gen_set_label(l2);
8657 tcg_temp_free_i32(t0);
8658 }
8659 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8660 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8661 {
8662 TCGLabel *l1 = gen_new_label();
8663 TCGLabel *l2 = gen_new_label();
8664 TCGv_i32 t0 = tcg_temp_local_new_i32();
8665
8666 /* No error here: 6 bits are used */
8667 tcg_gen_andi_i32(t0, arg2, 0x3F);
8668 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8669 tcg_gen_shl_i32(ret, arg1, t0);
8670 tcg_gen_br(l2);
8671 gen_set_label(l1);
8672 tcg_gen_movi_i32(ret, 0);
8673 gen_set_label(l2);
8674 tcg_temp_free_i32(t0);
8675 }
8676 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8677 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8678 {
8679 TCGv_i32 t0 = tcg_temp_new_i32();
8680 tcg_gen_andi_i32(t0, arg2, 0x1F);
8681 tcg_gen_rotl_i32(ret, arg1, t0);
8682 tcg_temp_free_i32(t0);
8683 }
8684 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8685 static inline void gen_evmergehi(DisasContext *ctx)
8686 {
8687 if (unlikely(!ctx->spe_enabled)) {
8688 gen_exception(ctx, POWERPC_EXCP_SPEU);
8689 return;
8690 }
8691 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8692 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8693 }
8694 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8695 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8696 {
8697 tcg_gen_sub_i32(ret, arg2, arg1);
8698 }
8699 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8700
8701 /* SPE arithmetic immediate */
8702 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8703 static inline void gen_##name(DisasContext *ctx) \
8704 { \
8705 TCGv_i32 t0; \
8706 if (unlikely(!ctx->spe_enabled)) { \
8707 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8708 return; \
8709 } \
8710 t0 = tcg_temp_new_i32(); \
8711 \
8712 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8713 tcg_op(t0, t0, rA(ctx->opcode)); \
8714 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8715 \
8716 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8717 tcg_op(t0, t0, rA(ctx->opcode)); \
8718 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8719 \
8720 tcg_temp_free_i32(t0); \
8721 }
8722 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8723 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8724
8725 /* SPE comparison */
8726 #define GEN_SPEOP_COMP(name, tcg_cond) \
8727 static inline void gen_##name(DisasContext *ctx) \
8728 { \
8729 if (unlikely(!ctx->spe_enabled)) { \
8730 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8731 return; \
8732 } \
8733 TCGLabel *l1 = gen_new_label(); \
8734 TCGLabel *l2 = gen_new_label(); \
8735 TCGLabel *l3 = gen_new_label(); \
8736 TCGLabel *l4 = gen_new_label(); \
8737 \
8738 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8739 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8740 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8741 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8742 \
8743 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8744 cpu_gpr[rB(ctx->opcode)], l1); \
8745 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8746 tcg_gen_br(l2); \
8747 gen_set_label(l1); \
8748 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8749 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8750 gen_set_label(l2); \
8751 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8752 cpu_gprh[rB(ctx->opcode)], l3); \
8753 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8754 ~(CRF_CH | CRF_CH_AND_CL)); \
8755 tcg_gen_br(l4); \
8756 gen_set_label(l3); \
8757 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8758 CRF_CH | CRF_CH_OR_CL); \
8759 gen_set_label(l4); \
8760 }
8761 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8762 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8763 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8764 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8765 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8766
8767 /* SPE misc */
8768 static inline void gen_brinc(DisasContext *ctx)
8769 {
8770 /* Note: brinc is usable even if SPE is disabled */
8771 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8772 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8773 }
8774 static inline void gen_evmergelo(DisasContext *ctx)
8775 {
8776 if (unlikely(!ctx->spe_enabled)) {
8777 gen_exception(ctx, POWERPC_EXCP_SPEU);
8778 return;
8779 }
8780 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8781 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8782 }
8783 static inline void gen_evmergehilo(DisasContext *ctx)
8784 {
8785 if (unlikely(!ctx->spe_enabled)) {
8786 gen_exception(ctx, POWERPC_EXCP_SPEU);
8787 return;
8788 }
8789 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8790 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8791 }
8792 static inline void gen_evmergelohi(DisasContext *ctx)
8793 {
8794 if (unlikely(!ctx->spe_enabled)) {
8795 gen_exception(ctx, POWERPC_EXCP_SPEU);
8796 return;
8797 }
8798 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8799 TCGv tmp = tcg_temp_new();
8800 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8801 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8802 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8803 tcg_temp_free(tmp);
8804 } else {
8805 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8806 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8807 }
8808 }
8809 static inline void gen_evsplati(DisasContext *ctx)
8810 {
8811 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8812
8813 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8814 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8815 }
8816 static inline void gen_evsplatfi(DisasContext *ctx)
8817 {
8818 uint64_t imm = rA(ctx->opcode) << 27;
8819
8820 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8821 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8822 }
8823
8824 static inline void gen_evsel(DisasContext *ctx)
8825 {
8826 TCGLabel *l1 = gen_new_label();
8827 TCGLabel *l2 = gen_new_label();
8828 TCGLabel *l3 = gen_new_label();
8829 TCGLabel *l4 = gen_new_label();
8830 TCGv_i32 t0 = tcg_temp_local_new_i32();
8831
8832 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8833 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8834 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8835 tcg_gen_br(l2);
8836 gen_set_label(l1);
8837 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8838 gen_set_label(l2);
8839 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8840 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8841 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8842 tcg_gen_br(l4);
8843 gen_set_label(l3);
8844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8845 gen_set_label(l4);
8846 tcg_temp_free_i32(t0);
8847 }
8848
8849 static void gen_evsel0(DisasContext *ctx)
8850 {
8851 gen_evsel(ctx);
8852 }
8853
8854 static void gen_evsel1(DisasContext *ctx)
8855 {
8856 gen_evsel(ctx);
8857 }
8858
8859 static void gen_evsel2(DisasContext *ctx)
8860 {
8861 gen_evsel(ctx);
8862 }
8863
8864 static void gen_evsel3(DisasContext *ctx)
8865 {
8866 gen_evsel(ctx);
8867 }
8868
8869 /* Multiply */
8870
8871 static inline void gen_evmwumi(DisasContext *ctx)
8872 {
8873 TCGv_i64 t0, t1;
8874
8875 if (unlikely(!ctx->spe_enabled)) {
8876 gen_exception(ctx, POWERPC_EXCP_SPEU);
8877 return;
8878 }
8879
8880 t0 = tcg_temp_new_i64();
8881 t1 = tcg_temp_new_i64();
8882
8883 /* t0 := rA; t1 := rB */
8884 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8885 tcg_gen_ext32u_i64(t0, t0);
8886 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8887 tcg_gen_ext32u_i64(t1, t1);
8888
8889 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8890
8891 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8892
8893 tcg_temp_free_i64(t0);
8894 tcg_temp_free_i64(t1);
8895 }
8896
8897 static inline void gen_evmwumia(DisasContext *ctx)
8898 {
8899 TCGv_i64 tmp;
8900
8901 if (unlikely(!ctx->spe_enabled)) {
8902 gen_exception(ctx, POWERPC_EXCP_SPEU);
8903 return;
8904 }
8905
8906 gen_evmwumi(ctx); /* rD := rA * rB */
8907
8908 tmp = tcg_temp_new_i64();
8909
8910 /* acc := rD */
8911 gen_load_gpr64(tmp, rD(ctx->opcode));
8912 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8913 tcg_temp_free_i64(tmp);
8914 }
8915
8916 static inline void gen_evmwumiaa(DisasContext *ctx)
8917 {
8918 TCGv_i64 acc;
8919 TCGv_i64 tmp;
8920
8921 if (unlikely(!ctx->spe_enabled)) {
8922 gen_exception(ctx, POWERPC_EXCP_SPEU);
8923 return;
8924 }
8925
8926 gen_evmwumi(ctx); /* rD := rA * rB */
8927
8928 acc = tcg_temp_new_i64();
8929 tmp = tcg_temp_new_i64();
8930
8931 /* tmp := rD */
8932 gen_load_gpr64(tmp, rD(ctx->opcode));
8933
8934 /* Load acc */
8935 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8936
8937 /* acc := tmp + acc */
8938 tcg_gen_add_i64(acc, acc, tmp);
8939
8940 /* Store acc */
8941 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8942
8943 /* rD := acc */
8944 gen_store_gpr64(rD(ctx->opcode), acc);
8945
8946 tcg_temp_free_i64(acc);
8947 tcg_temp_free_i64(tmp);
8948 }
8949
8950 static inline void gen_evmwsmi(DisasContext *ctx)
8951 {
8952 TCGv_i64 t0, t1;
8953
8954 if (unlikely(!ctx->spe_enabled)) {
8955 gen_exception(ctx, POWERPC_EXCP_SPEU);
8956 return;
8957 }
8958
8959 t0 = tcg_temp_new_i64();
8960 t1 = tcg_temp_new_i64();
8961
8962 /* t0 := rA; t1 := rB */
8963 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8964 tcg_gen_ext32s_i64(t0, t0);
8965 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8966 tcg_gen_ext32s_i64(t1, t1);
8967
8968 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8969
8970 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8971
8972 tcg_temp_free_i64(t0);
8973 tcg_temp_free_i64(t1);
8974 }
8975
8976 static inline void gen_evmwsmia(DisasContext *ctx)
8977 {
8978 TCGv_i64 tmp;
8979
8980 gen_evmwsmi(ctx); /* rD := rA * rB */
8981
8982 tmp = tcg_temp_new_i64();
8983
8984 /* acc := rD */
8985 gen_load_gpr64(tmp, rD(ctx->opcode));
8986 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8987
8988 tcg_temp_free_i64(tmp);
8989 }
8990
8991 static inline void gen_evmwsmiaa(DisasContext *ctx)
8992 {
8993 TCGv_i64 acc = tcg_temp_new_i64();
8994 TCGv_i64 tmp = tcg_temp_new_i64();
8995
8996 gen_evmwsmi(ctx); /* rD := rA * rB */
8997
8998 acc = tcg_temp_new_i64();
8999 tmp = tcg_temp_new_i64();
9000
9001 /* tmp := rD */
9002 gen_load_gpr64(tmp, rD(ctx->opcode));
9003
9004 /* Load acc */
9005 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9006
9007 /* acc := tmp + acc */
9008 tcg_gen_add_i64(acc, acc, tmp);
9009
9010 /* Store acc */
9011 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9012
9013 /* rD := acc */
9014 gen_store_gpr64(rD(ctx->opcode), acc);
9015
9016 tcg_temp_free_i64(acc);
9017 tcg_temp_free_i64(tmp);
9018 }
9019
9020 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9021 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9022 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9023 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9024 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9025 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9026 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9027 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9028 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9029 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9030 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9031 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9032 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9033 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9034 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9035 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9036 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9037 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9038 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9039 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9040 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9041 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9042 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9043 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9044 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9045 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9046 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9047 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9048 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9049
9050 /* SPE load and stores */
9051 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9052 {
9053 target_ulong uimm = rB(ctx->opcode);
9054
9055 if (rA(ctx->opcode) == 0) {
9056 tcg_gen_movi_tl(EA, uimm << sh);
9057 } else {
9058 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9059 if (NARROW_MODE(ctx)) {
9060 tcg_gen_ext32u_tl(EA, EA);
9061 }
9062 }
9063 }
9064
9065 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9066 {
9067 TCGv_i64 t0 = tcg_temp_new_i64();
9068 gen_qemu_ld64(ctx, t0, addr);
9069 gen_store_gpr64(rD(ctx->opcode), t0);
9070 tcg_temp_free_i64(t0);
9071 }
9072
9073 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9074 {
9075 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9076 gen_addr_add(ctx, addr, addr, 4);
9077 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9078 }
9079
9080 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9081 {
9082 TCGv t0 = tcg_temp_new();
9083 gen_qemu_ld16u(ctx, t0, addr);
9084 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9085 gen_addr_add(ctx, addr, addr, 2);
9086 gen_qemu_ld16u(ctx, t0, addr);
9087 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9088 gen_addr_add(ctx, addr, addr, 2);
9089 gen_qemu_ld16u(ctx, t0, addr);
9090 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9091 gen_addr_add(ctx, addr, addr, 2);
9092 gen_qemu_ld16u(ctx, t0, addr);
9093 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9094 tcg_temp_free(t0);
9095 }
9096
9097 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9098 {
9099 TCGv t0 = tcg_temp_new();
9100 gen_qemu_ld16u(ctx, t0, addr);
9101 tcg_gen_shli_tl(t0, t0, 16);
9102 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9103 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9104 tcg_temp_free(t0);
9105 }
9106
9107 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9108 {
9109 TCGv t0 = tcg_temp_new();
9110 gen_qemu_ld16u(ctx, t0, addr);
9111 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9112 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9113 tcg_temp_free(t0);
9114 }
9115
9116 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9117 {
9118 TCGv t0 = tcg_temp_new();
9119 gen_qemu_ld16s(ctx, t0, addr);
9120 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9121 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9122 tcg_temp_free(t0);
9123 }
9124
9125 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9126 {
9127 TCGv t0 = tcg_temp_new();
9128 gen_qemu_ld16u(ctx, t0, addr);
9129 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9130 gen_addr_add(ctx, addr, addr, 2);
9131 gen_qemu_ld16u(ctx, t0, addr);
9132 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9133 tcg_temp_free(t0);
9134 }
9135
9136 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9137 {
9138 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9139 gen_addr_add(ctx, addr, addr, 2);
9140 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9141 }
9142
9143 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9144 {
9145 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9146 gen_addr_add(ctx, addr, addr, 2);
9147 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9148 }
9149
9150 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9151 {
9152 TCGv t0 = tcg_temp_new();
9153 gen_qemu_ld32u(ctx, t0, addr);
9154 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9155 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9156 tcg_temp_free(t0);
9157 }
9158
9159 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9160 {
9161 TCGv t0 = tcg_temp_new();
9162 gen_qemu_ld16u(ctx, t0, addr);
9163 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9164 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9165 gen_addr_add(ctx, addr, addr, 2);
9166 gen_qemu_ld16u(ctx, t0, addr);
9167 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9168 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9169 tcg_temp_free(t0);
9170 }
9171
9172 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9173 {
9174 TCGv_i64 t0 = tcg_temp_new_i64();
9175 gen_load_gpr64(t0, rS(ctx->opcode));
9176 gen_qemu_st64(ctx, t0, addr);
9177 tcg_temp_free_i64(t0);
9178 }
9179
9180 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9181 {
9182 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9183 gen_addr_add(ctx, addr, addr, 4);
9184 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9185 }
9186
9187 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9188 {
9189 TCGv t0 = tcg_temp_new();
9190 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9191 gen_qemu_st16(ctx, t0, addr);
9192 gen_addr_add(ctx, addr, addr, 2);
9193 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9194 gen_addr_add(ctx, addr, addr, 2);
9195 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9196 gen_qemu_st16(ctx, t0, addr);
9197 tcg_temp_free(t0);
9198 gen_addr_add(ctx, addr, addr, 2);
9199 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9200 }
9201
9202 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9203 {
9204 TCGv t0 = tcg_temp_new();
9205 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9206 gen_qemu_st16(ctx, t0, addr);
9207 gen_addr_add(ctx, addr, addr, 2);
9208 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9209 gen_qemu_st16(ctx, t0, addr);
9210 tcg_temp_free(t0);
9211 }
9212
9213 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9214 {
9215 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9216 gen_addr_add(ctx, addr, addr, 2);
9217 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9218 }
9219
9220 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9221 {
9222 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9223 }
9224
9225 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9226 {
9227 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9228 }
9229
9230 #define GEN_SPEOP_LDST(name, opc2, sh) \
9231 static void glue(gen_, name)(DisasContext *ctx) \
9232 { \
9233 TCGv t0; \
9234 if (unlikely(!ctx->spe_enabled)) { \
9235 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9236 return; \
9237 } \
9238 gen_set_access_type(ctx, ACCESS_INT); \
9239 t0 = tcg_temp_new(); \
9240 if (Rc(ctx->opcode)) { \
9241 gen_addr_spe_imm_index(ctx, t0, sh); \
9242 } else { \
9243 gen_addr_reg_index(ctx, t0); \
9244 } \
9245 gen_op_##name(ctx, t0); \
9246 tcg_temp_free(t0); \
9247 }
9248
9249 GEN_SPEOP_LDST(evldd, 0x00, 3);
9250 GEN_SPEOP_LDST(evldw, 0x01, 3);
9251 GEN_SPEOP_LDST(evldh, 0x02, 3);
9252 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9253 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9254 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9255 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9256 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9257 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9258 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9259 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9260
9261 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9262 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9263 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9264 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9265 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9266 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9267 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9268
9269 /* Multiply and add - TODO */
9270 #if 0
9271 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9272 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9273 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9274 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9275 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9276 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9280 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9281 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9282 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9283
9284 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9285 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9286 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9287 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9290 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9292 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9293 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9294 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296
9297 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9298 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9299 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9300 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9301 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9302
9303 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9304 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9305 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9306 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9307 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9308 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9309 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9310 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9312 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9314 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315
9316 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9317 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9318 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9319 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320
9321 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9322 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9323 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9324 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9325 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9326 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9328 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9330 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9331 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9332 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333
9334 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9335 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9337 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339 #endif
9340
9341 /*** SPE floating-point extension ***/
9342 #define GEN_SPEFPUOP_CONV_32_32(name) \
9343 static inline void gen_##name(DisasContext *ctx) \
9344 { \
9345 TCGv_i32 t0 = tcg_temp_new_i32(); \
9346 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9347 gen_helper_##name(t0, cpu_env, t0); \
9348 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9349 tcg_temp_free_i32(t0); \
9350 }
9351 #define GEN_SPEFPUOP_CONV_32_64(name) \
9352 static inline void gen_##name(DisasContext *ctx) \
9353 { \
9354 TCGv_i64 t0 = tcg_temp_new_i64(); \
9355 TCGv_i32 t1 = tcg_temp_new_i32(); \
9356 gen_load_gpr64(t0, rB(ctx->opcode)); \
9357 gen_helper_##name(t1, cpu_env, t0); \
9358 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9359 tcg_temp_free_i64(t0); \
9360 tcg_temp_free_i32(t1); \
9361 }
9362 #define GEN_SPEFPUOP_CONV_64_32(name) \
9363 static inline void gen_##name(DisasContext *ctx) \
9364 { \
9365 TCGv_i64 t0 = tcg_temp_new_i64(); \
9366 TCGv_i32 t1 = tcg_temp_new_i32(); \
9367 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9368 gen_helper_##name(t0, cpu_env, t1); \
9369 gen_store_gpr64(rD(ctx->opcode), t0); \
9370 tcg_temp_free_i64(t0); \
9371 tcg_temp_free_i32(t1); \
9372 }
9373 #define GEN_SPEFPUOP_CONV_64_64(name) \
9374 static inline void gen_##name(DisasContext *ctx) \
9375 { \
9376 TCGv_i64 t0 = tcg_temp_new_i64(); \
9377 gen_load_gpr64(t0, rB(ctx->opcode)); \
9378 gen_helper_##name(t0, cpu_env, t0); \
9379 gen_store_gpr64(rD(ctx->opcode), t0); \
9380 tcg_temp_free_i64(t0); \
9381 }
9382 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9383 static inline void gen_##name(DisasContext *ctx) \
9384 { \
9385 TCGv_i32 t0, t1; \
9386 if (unlikely(!ctx->spe_enabled)) { \
9387 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9388 return; \
9389 } \
9390 t0 = tcg_temp_new_i32(); \
9391 t1 = tcg_temp_new_i32(); \
9392 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9393 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9394 gen_helper_##name(t0, cpu_env, t0, t1); \
9395 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9396 \
9397 tcg_temp_free_i32(t0); \
9398 tcg_temp_free_i32(t1); \
9399 }
9400 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9401 static inline void gen_##name(DisasContext *ctx) \
9402 { \
9403 TCGv_i64 t0, t1; \
9404 if (unlikely(!ctx->spe_enabled)) { \
9405 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9406 return; \
9407 } \
9408 t0 = tcg_temp_new_i64(); \
9409 t1 = tcg_temp_new_i64(); \
9410 gen_load_gpr64(t0, rA(ctx->opcode)); \
9411 gen_load_gpr64(t1, rB(ctx->opcode)); \
9412 gen_helper_##name(t0, cpu_env, t0, t1); \
9413 gen_store_gpr64(rD(ctx->opcode), t0); \
9414 tcg_temp_free_i64(t0); \
9415 tcg_temp_free_i64(t1); \
9416 }
9417 #define GEN_SPEFPUOP_COMP_32(name) \
9418 static inline void gen_##name(DisasContext *ctx) \
9419 { \
9420 TCGv_i32 t0, t1; \
9421 if (unlikely(!ctx->spe_enabled)) { \
9422 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9423 return; \
9424 } \
9425 t0 = tcg_temp_new_i32(); \
9426 t1 = tcg_temp_new_i32(); \
9427 \
9428 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9429 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9430 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9431 \
9432 tcg_temp_free_i32(t0); \
9433 tcg_temp_free_i32(t1); \
9434 }
9435 #define GEN_SPEFPUOP_COMP_64(name) \
9436 static inline void gen_##name(DisasContext *ctx) \
9437 { \
9438 TCGv_i64 t0, t1; \
9439 if (unlikely(!ctx->spe_enabled)) { \
9440 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9441 return; \
9442 } \
9443 t0 = tcg_temp_new_i64(); \
9444 t1 = tcg_temp_new_i64(); \
9445 gen_load_gpr64(t0, rA(ctx->opcode)); \
9446 gen_load_gpr64(t1, rB(ctx->opcode)); \
9447 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9448 tcg_temp_free_i64(t0); \
9449 tcg_temp_free_i64(t1); \
9450 }
9451
9452 /* Single precision floating-point vectors operations */
9453 /* Arithmetic */
9454 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9455 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9456 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9457 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9458 static inline void gen_evfsabs(DisasContext *ctx)
9459 {
9460 if (unlikely(!ctx->spe_enabled)) {
9461 gen_exception(ctx, POWERPC_EXCP_SPEU);
9462 return;
9463 }
9464 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9465 ~0x80000000);
9466 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9467 ~0x80000000);
9468 }
9469 static inline void gen_evfsnabs(DisasContext *ctx)
9470 {
9471 if (unlikely(!ctx->spe_enabled)) {
9472 gen_exception(ctx, POWERPC_EXCP_SPEU);
9473 return;
9474 }
9475 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9476 0x80000000);
9477 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9478 0x80000000);
9479 }
9480 static inline void gen_evfsneg(DisasContext *ctx)
9481 {
9482 if (unlikely(!ctx->spe_enabled)) {
9483 gen_exception(ctx, POWERPC_EXCP_SPEU);
9484 return;
9485 }
9486 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9487 0x80000000);
9488 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9489 0x80000000);
9490 }
9491
9492 /* Conversion */
9493 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9494 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9495 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9496 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9497 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9498 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9499 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9500 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9501 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9502 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9503
9504 /* Comparison */
9505 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9506 GEN_SPEFPUOP_COMP_64(evfscmplt);
9507 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9508 GEN_SPEFPUOP_COMP_64(evfststgt);
9509 GEN_SPEFPUOP_COMP_64(evfststlt);
9510 GEN_SPEFPUOP_COMP_64(evfststeq);
9511
9512 /* Opcodes definitions */
9513 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9514 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9515 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9516 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9517 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9518 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9519 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9520 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9521 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9522 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9523 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9524 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9526 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9527
9528 /* Single precision floating-point operations */
9529 /* Arithmetic */
9530 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9531 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9532 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9533 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9534 static inline void gen_efsabs(DisasContext *ctx)
9535 {
9536 if (unlikely(!ctx->spe_enabled)) {
9537 gen_exception(ctx, POWERPC_EXCP_SPEU);
9538 return;
9539 }
9540 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9541 }
9542 static inline void gen_efsnabs(DisasContext *ctx)
9543 {
9544 if (unlikely(!ctx->spe_enabled)) {
9545 gen_exception(ctx, POWERPC_EXCP_SPEU);
9546 return;
9547 }
9548 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9549 }
9550 static inline void gen_efsneg(DisasContext *ctx)
9551 {
9552 if (unlikely(!ctx->spe_enabled)) {
9553 gen_exception(ctx, POWERPC_EXCP_SPEU);
9554 return;
9555 }
9556 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9557 }
9558
9559 /* Conversion */
9560 GEN_SPEFPUOP_CONV_32_32(efscfui);
9561 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9562 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9563 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9564 GEN_SPEFPUOP_CONV_32_32(efsctui);
9565 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9566 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9567 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9568 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9569 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9570 GEN_SPEFPUOP_CONV_32_64(efscfd);
9571
9572 /* Comparison */
9573 GEN_SPEFPUOP_COMP_32(efscmpgt);
9574 GEN_SPEFPUOP_COMP_32(efscmplt);
9575 GEN_SPEFPUOP_COMP_32(efscmpeq);
9576 GEN_SPEFPUOP_COMP_32(efststgt);
9577 GEN_SPEFPUOP_COMP_32(efststlt);
9578 GEN_SPEFPUOP_COMP_32(efststeq);
9579
9580 /* Opcodes definitions */
9581 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9582 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9583 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9584 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9585 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9586 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9587 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9588 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9589 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9590 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9591 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9592 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9593 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9594 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9595
9596 /* Double precision floating-point operations */
9597 /* Arithmetic */
9598 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9599 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9600 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9601 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9602 static inline void gen_efdabs(DisasContext *ctx)
9603 {
9604 if (unlikely(!ctx->spe_enabled)) {
9605 gen_exception(ctx, POWERPC_EXCP_SPEU);
9606 return;
9607 }
9608 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9609 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9610 ~0x80000000);
9611 }
9612 static inline void gen_efdnabs(DisasContext *ctx)
9613 {
9614 if (unlikely(!ctx->spe_enabled)) {
9615 gen_exception(ctx, POWERPC_EXCP_SPEU);
9616 return;
9617 }
9618 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9619 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9620 0x80000000);
9621 }
9622 static inline void gen_efdneg(DisasContext *ctx)
9623 {
9624 if (unlikely(!ctx->spe_enabled)) {
9625 gen_exception(ctx, POWERPC_EXCP_SPEU);
9626 return;
9627 }
9628 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9629 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9630 0x80000000);
9631 }
9632
9633 /* Conversion */
9634 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9635 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9636 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9637 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9638 GEN_SPEFPUOP_CONV_32_64(efdctui);
9639 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9640 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9641 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9642 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9643 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9644 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9645 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9646 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9647 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9648 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9649
9650 /* Comparison */
9651 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9652 GEN_SPEFPUOP_COMP_64(efdcmplt);
9653 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9654 GEN_SPEFPUOP_COMP_64(efdtstgt);
9655 GEN_SPEFPUOP_COMP_64(efdtstlt);
9656 GEN_SPEFPUOP_COMP_64(efdtsteq);
9657
9658 /* Opcodes definitions */
9659 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9660 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9661 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9662 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9663 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9664 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9665 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9666 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9667 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9668 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9669 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9670 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9672 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9673 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9674 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9675
9676 static void gen_tbegin(DisasContext *ctx)
9677 {
9678 if (unlikely(!ctx->tm_enabled)) {
9679 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9680 return;
9681 }
9682 gen_helper_tbegin(cpu_env);
9683 }
9684
9685 #define GEN_TM_NOOP(name) \
9686 static inline void gen_##name(DisasContext *ctx) \
9687 { \
9688 if (unlikely(!ctx->tm_enabled)) { \
9689 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9690 return; \
9691 } \
9692 /* Because tbegin always fails in QEMU, these user \
9693 * space instructions all have a simple implementation: \
9694 * \
9695 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9696 * = 0b0 || 0b00 || 0b0 \
9697 */ \
9698 tcg_gen_movi_i32(cpu_crf[0], 0); \
9699 }
9700
9701 GEN_TM_NOOP(tend);
9702 GEN_TM_NOOP(tabort);
9703 GEN_TM_NOOP(tabortwc);
9704 GEN_TM_NOOP(tabortwci);
9705 GEN_TM_NOOP(tabortdc);
9706 GEN_TM_NOOP(tabortdci);
9707 GEN_TM_NOOP(tsr);
9708
9709 static void gen_tcheck(DisasContext *ctx)
9710 {
9711 if (unlikely(!ctx->tm_enabled)) {
9712 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9713 return;
9714 }
9715 /* Because tbegin always fails, the tcheck implementation
9716 * is simple:
9717 *
9718 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9719 * = 0b1 || 0b00 || 0b0
9720 */
9721 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9722 }
9723
9724 #if defined(CONFIG_USER_ONLY)
9725 #define GEN_TM_PRIV_NOOP(name) \
9726 static inline void gen_##name(DisasContext *ctx) \
9727 { \
9728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9729 }
9730
9731 #else
9732
9733 #define GEN_TM_PRIV_NOOP(name) \
9734 static inline void gen_##name(DisasContext *ctx) \
9735 { \
9736 if (unlikely(ctx->pr)) { \
9737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9738 return; \
9739 } \
9740 if (unlikely(!ctx->tm_enabled)) { \
9741 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9742 return; \
9743 } \
9744 /* Because tbegin always fails, the implementation is \
9745 * simple: \
9746 * \
9747 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9748 * = 0b0 || 0b00 | 0b0 \
9749 */ \
9750 tcg_gen_movi_i32(cpu_crf[0], 0); \
9751 }
9752
9753 #endif
9754
9755 GEN_TM_PRIV_NOOP(treclaim);
9756 GEN_TM_PRIV_NOOP(trechkpt);
9757
9758 static opcode_t opcodes[] = {
9759 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9760 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9761 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9762 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9763 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9764 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9765 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9766 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9767 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9768 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9769 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9770 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9771 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9772 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9773 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9774 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9775 #if defined(TARGET_PPC64)
9776 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9777 #endif
9778 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9779 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9780 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9781 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9782 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9783 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9784 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9785 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9786 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9787 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9788 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9789 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9790 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9791 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9792 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9793 #if defined(TARGET_PPC64)
9794 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9795 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9796 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9797 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9798 #endif
9799 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9800 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9801 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9802 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9803 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9804 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9805 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9806 #if defined(TARGET_PPC64)
9807 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9808 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9809 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9810 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9811 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9812 #endif
9813 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9814 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9815 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9816 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9817 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9818 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9819 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9820 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9821 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9822 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9823 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9824 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9825 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9826 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9827 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9828 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9829 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9830 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9831 #if defined(TARGET_PPC64)
9832 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9833 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9834 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9835 #endif
9836 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9837 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9838 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9839 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9840 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9841 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9842 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9843 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9844 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9845 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9846 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9847 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9848 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9849 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9850 #if defined(TARGET_PPC64)
9851 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9852 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9853 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9854 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9855 #endif
9856 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9857 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9858 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9859 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9860 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9861 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9862 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9863 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9864 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9865 #if defined(TARGET_PPC64)
9866 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9867 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9868 #endif
9869 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9870 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9871 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9872 #if defined(TARGET_PPC64)
9873 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9874 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9875 #endif
9876 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9877 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9878 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9879 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9880 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9881 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9882 #if defined(TARGET_PPC64)
9883 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9884 #endif
9885 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9886 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9887 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9888 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9889 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9890 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9891 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9892 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9893 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9894 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9895 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9896 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9897 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9898 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9899 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9900 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9901 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9902 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9903 #if defined(TARGET_PPC64)
9904 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9905 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9906 PPC_SEGMENT_64B),
9907 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9908 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9909 PPC_SEGMENT_64B),
9910 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9911 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9912 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9913 #endif
9914 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9915 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9916 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9917 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9918 #if defined(TARGET_PPC64)
9919 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9920 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9921 #endif
9922 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9923 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9924 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9925 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9926 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9927 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9928 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9929 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9930 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9931 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9932 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9933 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9934 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9935 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9936 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9937 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9938 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9939 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9940 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9941 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9942 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9943 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9944 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9945 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9946 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9947 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9948 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9949 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9950 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9951 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9952 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9953 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9954 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9955 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9956 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9957 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9958 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9959 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9960 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9961 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9962 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9963 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9964 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9965 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9966 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9967 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9968 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9969 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9970 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9971 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9972 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9973 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9974 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9975 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9976 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9977 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9978 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9979 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9980 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9981 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9982 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9983 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9984 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9985 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9986 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9987 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9988 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9989 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9990 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9991 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9992 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9993 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9994 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9995 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9996 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9997 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9998 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9999 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10000 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10001 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10002 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10003 PPC_NONE, PPC2_BOOKE206),
10004 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10005 PPC_NONE, PPC2_BOOKE206),
10006 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10007 PPC_NONE, PPC2_BOOKE206),
10008 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10009 PPC_NONE, PPC2_BOOKE206),
10010 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10011 PPC_NONE, PPC2_BOOKE206),
10012 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10013 PPC_NONE, PPC2_PRCNTL),
10014 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10015 PPC_NONE, PPC2_PRCNTL),
10016 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10017 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10018 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10019 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10020 PPC_BOOKE, PPC2_BOOKE206),
10021 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10022 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10023 PPC_BOOKE, PPC2_BOOKE206),
10024 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10025 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10026 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10027 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10028 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10029 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10030 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10031 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10032 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10033
10034 #undef GEN_INT_ARITH_ADD
10035 #undef GEN_INT_ARITH_ADD_CONST
10036 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10037 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10038 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10039 add_ca, compute_ca, compute_ov) \
10040 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10041 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10042 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10043 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10044 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10045 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10046 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10047 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10048 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10049 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10050 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10051
10052 #undef GEN_INT_ARITH_DIVW
10053 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10054 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10055 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10056 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10057 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10058 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10059 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10060 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10061 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10062 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10063
10064 #if defined(TARGET_PPC64)
10065 #undef GEN_INT_ARITH_DIVD
10066 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10067 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10068 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10069 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10070 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10071 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10072
10073 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10074 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10075 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10076 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10077
10078 #undef GEN_INT_ARITH_MUL_HELPER
10079 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10080 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10081 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10082 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10083 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10084 #endif
10085
10086 #undef GEN_INT_ARITH_SUBF
10087 #undef GEN_INT_ARITH_SUBF_CONST
10088 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10089 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10090 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10091 add_ca, compute_ca, compute_ov) \
10092 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10093 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10094 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10095 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10096 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10097 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10098 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10099 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10100 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10101 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10102 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10103
10104 #undef GEN_LOGICAL1
10105 #undef GEN_LOGICAL2
10106 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10107 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10108 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10109 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10110 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10111 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10112 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10113 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10114 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10115 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10116 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10117 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10118 #if defined(TARGET_PPC64)
10119 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10120 #endif
10121
10122 #if defined(TARGET_PPC64)
10123 #undef GEN_PPC64_R2
10124 #undef GEN_PPC64_R4
10125 #define GEN_PPC64_R2(name, opc1, opc2) \
10126 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10127 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10128 PPC_64B)
10129 #define GEN_PPC64_R4(name, opc1, opc2) \
10130 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10131 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10132 PPC_64B), \
10133 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10134 PPC_64B), \
10135 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10136 PPC_64B)
10137 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10138 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10139 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10140 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10141 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10142 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10143 #endif
10144
10145 #undef _GEN_FLOAT_ACB
10146 #undef GEN_FLOAT_ACB
10147 #undef _GEN_FLOAT_AB
10148 #undef GEN_FLOAT_AB
10149 #undef _GEN_FLOAT_AC
10150 #undef GEN_FLOAT_AC
10151 #undef GEN_FLOAT_B
10152 #undef GEN_FLOAT_BS
10153 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10154 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10155 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10156 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10157 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10158 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10159 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10160 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10161 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10162 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10163 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10164 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10165 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10166 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10167 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10168 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10169 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10170 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10171 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10172
10173 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10174 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10175 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10176 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10177 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10178 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10179 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10180 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10181 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10182 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10183 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10184 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10185 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10186 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10187 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10188 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10189 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10190 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10191 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10192 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10193 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10194 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10195 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10196 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10197 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10198 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10199 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10200 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10201 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10202 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10203 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10204
10205 #undef GEN_LD
10206 #undef GEN_LDU
10207 #undef GEN_LDUX
10208 #undef GEN_LDX_E
10209 #undef GEN_LDS
10210 #define GEN_LD(name, ldop, opc, type) \
10211 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10212 #define GEN_LDU(name, ldop, opc, type) \
10213 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10214 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10215 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10216 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10217 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10218 #define GEN_LDS(name, ldop, op, type) \
10219 GEN_LD(name, ldop, op | 0x20, type) \
10220 GEN_LDU(name, ldop, op | 0x21, type) \
10221 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10222 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10223
10224 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10225 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10226 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10227 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10228 #if defined(TARGET_PPC64)
10229 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10230 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10231 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10232 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10233 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10234 #endif
10235 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10236 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10237
10238 #undef GEN_ST
10239 #undef GEN_STU
10240 #undef GEN_STUX
10241 #undef GEN_STX_E
10242 #undef GEN_STS
10243 #define GEN_ST(name, stop, opc, type) \
10244 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10245 #define GEN_STU(name, stop, opc, type) \
10246 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10247 #define GEN_STUX(name, stop, opc2, opc3, type) \
10248 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10249 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10250 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10251 #define GEN_STS(name, stop, op, type) \
10252 GEN_ST(name, stop, op | 0x20, type) \
10253 GEN_STU(name, stop, op | 0x21, type) \
10254 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10255 GEN_STX(name, stop, 0x17, op | 0x00, type)
10256
10257 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10258 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10259 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10260 #if defined(TARGET_PPC64)
10261 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10262 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10263 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10264 #endif
10265 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10266 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10267
10268 #undef GEN_LDF
10269 #undef GEN_LDUF
10270 #undef GEN_LDUXF
10271 #undef GEN_LDXF
10272 #undef GEN_LDFS
10273 #define GEN_LDF(name, ldop, opc, type) \
10274 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10275 #define GEN_LDUF(name, ldop, opc, type) \
10276 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10277 #define GEN_LDUXF(name, ldop, opc, type) \
10278 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10279 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10280 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10281 #define GEN_LDFS(name, ldop, op, type) \
10282 GEN_LDF(name, ldop, op | 0x20, type) \
10283 GEN_LDUF(name, ldop, op | 0x21, type) \
10284 GEN_LDUXF(name, ldop, op | 0x01, type) \
10285 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10286
10287 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10288 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10289 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10290 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10291 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10292 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10293
10294 #undef GEN_STF
10295 #undef GEN_STUF
10296 #undef GEN_STUXF
10297 #undef GEN_STXF
10298 #undef GEN_STFS
10299 #define GEN_STF(name, stop, opc, type) \
10300 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10301 #define GEN_STUF(name, stop, opc, type) \
10302 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10303 #define GEN_STUXF(name, stop, opc, type) \
10304 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10305 #define GEN_STXF(name, stop, opc2, opc3, type) \
10306 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10307 #define GEN_STFS(name, stop, op, type) \
10308 GEN_STF(name, stop, op | 0x20, type) \
10309 GEN_STUF(name, stop, op | 0x21, type) \
10310 GEN_STUXF(name, stop, op | 0x01, type) \
10311 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10312
10313 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10314 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10315 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10316 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10317 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10318
10319 #undef GEN_CRLOGIC
10320 #define GEN_CRLOGIC(name, tcg_op, opc) \
10321 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10322 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10323 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10324 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10325 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10326 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10327 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10328 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10329 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10330
10331 #undef GEN_MAC_HANDLER
10332 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10333 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10334 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10335 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10336 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10337 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10338 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10339 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10340 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10341 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10342 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10343 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10344 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10345 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10346 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10347 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10348 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10349 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10350 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10351 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10352 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10353 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10354 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10355 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10356 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10357 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10358 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10359 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10360 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10361 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10362 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10363 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10364 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10365 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10366 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10367 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10368 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10369 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10370 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10371 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10372 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10373 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10374 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10375 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10376
10377 #undef GEN_VR_LDX
10378 #undef GEN_VR_STX
10379 #undef GEN_VR_LVE
10380 #undef GEN_VR_STVE
10381 #define GEN_VR_LDX(name, opc2, opc3) \
10382 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10383 #define GEN_VR_STX(name, opc2, opc3) \
10384 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10385 #define GEN_VR_LVE(name, opc2, opc3) \
10386 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10387 #define GEN_VR_STVE(name, opc2, opc3) \
10388 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10389 GEN_VR_LDX(lvx, 0x07, 0x03),
10390 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10391 GEN_VR_LVE(bx, 0x07, 0x00),
10392 GEN_VR_LVE(hx, 0x07, 0x01),
10393 GEN_VR_LVE(wx, 0x07, 0x02),
10394 GEN_VR_STX(svx, 0x07, 0x07),
10395 GEN_VR_STX(svxl, 0x07, 0x0F),
10396 GEN_VR_STVE(bx, 0x07, 0x04),
10397 GEN_VR_STVE(hx, 0x07, 0x05),
10398 GEN_VR_STVE(wx, 0x07, 0x06),
10399
10400 #undef GEN_VX_LOGICAL
10401 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10402 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10403
10404 #undef GEN_VX_LOGICAL_207
10405 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10406 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10407
10408 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10409 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10410 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10411 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10412 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10413 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10414 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10415 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10416
10417 #undef GEN_VXFORM
10418 #define GEN_VXFORM(name, opc2, opc3) \
10419 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10420
10421 #undef GEN_VXFORM_207
10422 #define GEN_VXFORM_207(name, opc2, opc3) \
10423 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10424
10425 #undef GEN_VXFORM_DUAL
10426 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10427 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10428
10429 #undef GEN_VXRFORM_DUAL
10430 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10431 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10432 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10433
10434 GEN_VXFORM(vaddubm, 0, 0),
10435 GEN_VXFORM(vadduhm, 0, 1),
10436 GEN_VXFORM(vadduwm, 0, 2),
10437 GEN_VXFORM_207(vaddudm, 0, 3),
10438 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10439 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10440 GEN_VXFORM(vsubuwm, 0, 18),
10441 GEN_VXFORM_207(vsubudm, 0, 19),
10442 GEN_VXFORM(vmaxub, 1, 0),
10443 GEN_VXFORM(vmaxuh, 1, 1),
10444 GEN_VXFORM(vmaxuw, 1, 2),
10445 GEN_VXFORM_207(vmaxud, 1, 3),
10446 GEN_VXFORM(vmaxsb, 1, 4),
10447 GEN_VXFORM(vmaxsh, 1, 5),
10448 GEN_VXFORM(vmaxsw, 1, 6),
10449 GEN_VXFORM_207(vmaxsd, 1, 7),
10450 GEN_VXFORM(vminub, 1, 8),
10451 GEN_VXFORM(vminuh, 1, 9),
10452 GEN_VXFORM(vminuw, 1, 10),
10453 GEN_VXFORM_207(vminud, 1, 11),
10454 GEN_VXFORM(vminsb, 1, 12),
10455 GEN_VXFORM(vminsh, 1, 13),
10456 GEN_VXFORM(vminsw, 1, 14),
10457 GEN_VXFORM_207(vminsd, 1, 15),
10458 GEN_VXFORM(vavgub, 1, 16),
10459 GEN_VXFORM(vavguh, 1, 17),
10460 GEN_VXFORM(vavguw, 1, 18),
10461 GEN_VXFORM(vavgsb, 1, 20),
10462 GEN_VXFORM(vavgsh, 1, 21),
10463 GEN_VXFORM(vavgsw, 1, 22),
10464 GEN_VXFORM(vmrghb, 6, 0),
10465 GEN_VXFORM(vmrghh, 6, 1),
10466 GEN_VXFORM(vmrghw, 6, 2),
10467 GEN_VXFORM(vmrglb, 6, 4),
10468 GEN_VXFORM(vmrglh, 6, 5),
10469 GEN_VXFORM(vmrglw, 6, 6),
10470 GEN_VXFORM_207(vmrgew, 6, 30),
10471 GEN_VXFORM_207(vmrgow, 6, 26),
10472 GEN_VXFORM(vmuloub, 4, 0),
10473 GEN_VXFORM(vmulouh, 4, 1),
10474 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10475 GEN_VXFORM(vmulosb, 4, 4),
10476 GEN_VXFORM(vmulosh, 4, 5),
10477 GEN_VXFORM_207(vmulosw, 4, 6),
10478 GEN_VXFORM(vmuleub, 4, 8),
10479 GEN_VXFORM(vmuleuh, 4, 9),
10480 GEN_VXFORM_207(vmuleuw, 4, 10),
10481 GEN_VXFORM(vmulesb, 4, 12),
10482 GEN_VXFORM(vmulesh, 4, 13),
10483 GEN_VXFORM_207(vmulesw, 4, 14),
10484 GEN_VXFORM(vslb, 2, 4),
10485 GEN_VXFORM(vslh, 2, 5),
10486 GEN_VXFORM(vslw, 2, 6),
10487 GEN_VXFORM_207(vsld, 2, 23),
10488 GEN_VXFORM(vsrb, 2, 8),
10489 GEN_VXFORM(vsrh, 2, 9),
10490 GEN_VXFORM(vsrw, 2, 10),
10491 GEN_VXFORM_207(vsrd, 2, 27),
10492 GEN_VXFORM(vsrab, 2, 12),
10493 GEN_VXFORM(vsrah, 2, 13),
10494 GEN_VXFORM(vsraw, 2, 14),
10495 GEN_VXFORM_207(vsrad, 2, 15),
10496 GEN_VXFORM(vslo, 6, 16),
10497 GEN_VXFORM(vsro, 6, 17),
10498 GEN_VXFORM(vaddcuw, 0, 6),
10499 GEN_VXFORM(vsubcuw, 0, 22),
10500 GEN_VXFORM(vaddubs, 0, 8),
10501 GEN_VXFORM(vadduhs, 0, 9),
10502 GEN_VXFORM(vadduws, 0, 10),
10503 GEN_VXFORM(vaddsbs, 0, 12),
10504 GEN_VXFORM(vaddshs, 0, 13),
10505 GEN_VXFORM(vaddsws, 0, 14),
10506 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10507 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10508 GEN_VXFORM(vsubuws, 0, 26),
10509 GEN_VXFORM(vsubsbs, 0, 28),
10510 GEN_VXFORM(vsubshs, 0, 29),
10511 GEN_VXFORM(vsubsws, 0, 30),
10512 GEN_VXFORM_207(vadduqm, 0, 4),
10513 GEN_VXFORM_207(vaddcuq, 0, 5),
10514 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10515 GEN_VXFORM_207(vsubuqm, 0, 20),
10516 GEN_VXFORM_207(vsubcuq, 0, 21),
10517 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10518 GEN_VXFORM(vrlb, 2, 0),
10519 GEN_VXFORM(vrlh, 2, 1),
10520 GEN_VXFORM(vrlw, 2, 2),
10521 GEN_VXFORM_207(vrld, 2, 3),
10522 GEN_VXFORM(vsl, 2, 7),
10523 GEN_VXFORM(vsr, 2, 11),
10524 GEN_VXFORM(vpkuhum, 7, 0),
10525 GEN_VXFORM(vpkuwum, 7, 1),
10526 GEN_VXFORM_207(vpkudum, 7, 17),
10527 GEN_VXFORM(vpkuhus, 7, 2),
10528 GEN_VXFORM(vpkuwus, 7, 3),
10529 GEN_VXFORM_207(vpkudus, 7, 19),
10530 GEN_VXFORM(vpkshus, 7, 4),
10531 GEN_VXFORM(vpkswus, 7, 5),
10532 GEN_VXFORM_207(vpksdus, 7, 21),
10533 GEN_VXFORM(vpkshss, 7, 6),
10534 GEN_VXFORM(vpkswss, 7, 7),
10535 GEN_VXFORM_207(vpksdss, 7, 23),
10536 GEN_VXFORM(vpkpx, 7, 12),
10537 GEN_VXFORM(vsum4ubs, 4, 24),
10538 GEN_VXFORM(vsum4sbs, 4, 28),
10539 GEN_VXFORM(vsum4shs, 4, 25),
10540 GEN_VXFORM(vsum2sws, 4, 26),
10541 GEN_VXFORM(vsumsws, 4, 30),
10542 GEN_VXFORM(vaddfp, 5, 0),
10543 GEN_VXFORM(vsubfp, 5, 1),
10544 GEN_VXFORM(vmaxfp, 5, 16),
10545 GEN_VXFORM(vminfp, 5, 17),
10546
10547 #undef GEN_VXRFORM1
10548 #undef GEN_VXRFORM
10549 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10550 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10551 #define GEN_VXRFORM(name, opc2, opc3) \
10552 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10553 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10554 GEN_VXRFORM(vcmpequb, 3, 0)
10555 GEN_VXRFORM(vcmpequh, 3, 1)
10556 GEN_VXRFORM(vcmpequw, 3, 2)
10557 GEN_VXRFORM(vcmpgtsb, 3, 12)
10558 GEN_VXRFORM(vcmpgtsh, 3, 13)
10559 GEN_VXRFORM(vcmpgtsw, 3, 14)
10560 GEN_VXRFORM(vcmpgtub, 3, 8)
10561 GEN_VXRFORM(vcmpgtuh, 3, 9)
10562 GEN_VXRFORM(vcmpgtuw, 3, 10)
10563 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10564 GEN_VXRFORM(vcmpgefp, 3, 7)
10565 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10566 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10567
10568 #undef GEN_VXFORM_SIMM
10569 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10570 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10571 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10572 GEN_VXFORM_SIMM(vspltish, 6, 13),
10573 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10574
10575 #undef GEN_VXFORM_NOA
10576 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10577 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10578 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10579 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10580 GEN_VXFORM_207(vupkhsw, 7, 25),
10581 GEN_VXFORM_NOA(vupklsb, 7, 10),
10582 GEN_VXFORM_NOA(vupklsh, 7, 11),
10583 GEN_VXFORM_207(vupklsw, 7, 27),
10584 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10585 GEN_VXFORM_NOA(vupklpx, 7, 15),
10586 GEN_VXFORM_NOA(vrefp, 5, 4),
10587 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10588 GEN_VXFORM_NOA(vexptefp, 5, 6),
10589 GEN_VXFORM_NOA(vlogefp, 5, 7),
10590 GEN_VXFORM_NOA(vrfim, 5, 11),
10591 GEN_VXFORM_NOA(vrfin, 5, 8),
10592 GEN_VXFORM_NOA(vrfip, 5, 10),
10593 GEN_VXFORM_NOA(vrfiz, 5, 9),
10594
10595 #undef GEN_VXFORM_UIMM
10596 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10597 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10598 GEN_VXFORM_UIMM(vspltb, 6, 8),
10599 GEN_VXFORM_UIMM(vsplth, 6, 9),
10600 GEN_VXFORM_UIMM(vspltw, 6, 10),
10601 GEN_VXFORM_UIMM(vcfux, 5, 12),
10602 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10603 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10604 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10605
10606 #undef GEN_VAFORM_PAIRED
10607 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10608 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10609 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10610 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10611 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10612 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10613 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10614 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10615
10616 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10617 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10618 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10619 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10620
10621 GEN_VXFORM_207(vbpermq, 6, 21),
10622 GEN_VXFORM_207(vgbbd, 6, 20),
10623 GEN_VXFORM_207(vpmsumb, 4, 16),
10624 GEN_VXFORM_207(vpmsumh, 4, 17),
10625 GEN_VXFORM_207(vpmsumw, 4, 18),
10626 GEN_VXFORM_207(vpmsumd, 4, 19),
10627
10628 GEN_VXFORM_207(vsbox, 4, 23),
10629
10630 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10631 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10632
10633 GEN_VXFORM_207(vshasigmaw, 1, 26),
10634 GEN_VXFORM_207(vshasigmad, 1, 27),
10635
10636 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10637
10638 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10639 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10640 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10641 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10642 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10643 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10644 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10645
10646 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10647 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10648 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10649 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10650 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10651
10652 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10653 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10654 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10655 #if defined(TARGET_PPC64)
10656 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10657 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10658 #endif
10659
10660 #undef GEN_XX2FORM
10661 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10662 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10663 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10664
10665 #undef GEN_XX3FORM
10666 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10667 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10668 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10669 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10670 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10671
10672 #undef GEN_XX2IFORM
10673 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10674 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10675 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10676 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10677 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10678
10679 #undef GEN_XX3_RC_FORM
10680 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10681 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10682 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10683 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10684 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10685 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10686 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10687 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10688 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10689
10690 #undef GEN_XX3FORM_DM
10691 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10694 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10695 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10696 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10703 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10708
10709 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10710 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10711 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10712 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10713
10714 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10715 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10716 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10717 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10718 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10719 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10720 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10721 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10722
10723 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10724 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10725 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10726 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10727 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10728 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10729 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10730 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10731 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10732 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10733 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10734 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10735 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10736 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10737 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10738 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10739 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10740 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10741 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10742 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10743 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10744 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10745 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10746 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10747 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10748 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10749 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10750 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10751 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10752 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10753 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10754 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10755 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10756 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10757 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10758 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10759
10760 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10761 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10762 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10763 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10764 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10765 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10766 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10767 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10768 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10769 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10770 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10771 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10772 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10773 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10774 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10775 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10776 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10777 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10778
10779 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10780 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10781 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10782 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10783 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10784 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10785 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10786 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10787 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10788 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10789 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10790 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10791 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10792 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10793 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10794 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10795 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10796 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10797 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10798 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10799 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10800 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10801 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10802 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10803 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10804 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10805 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10806 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10807 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10808 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10809 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10810 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10811 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10812 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10813 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10814 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10815
10816 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10817 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10818 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10819 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10820 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10821 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10822 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10823 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10824 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10825 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10826 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10827 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10828 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10829 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10830 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10831 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10832 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10833 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10834 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10835 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10836 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10837 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10838 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10839 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10840 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10841 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10842 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10843 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10844 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10845 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10846 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10847 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10848 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10849 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10850 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10851 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10852
10853 #undef VSX_LOGICAL
10854 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10855 GEN_XX3FORM(name, opc2, opc3, fl2)
10856
10857 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10858 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10859 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10860 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10861 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10862 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10863 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10864 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10865 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10866 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10867 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10868 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10869
10870 #define GEN_XXSEL_ROW(opc3) \
10871 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10872 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10873 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10874 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10875 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10876 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10877 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10878 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10879
10880 GEN_XXSEL_ROW(0x00)
10881 GEN_XXSEL_ROW(0x01)
10882 GEN_XXSEL_ROW(0x02)
10883 GEN_XXSEL_ROW(0x03)
10884 GEN_XXSEL_ROW(0x04)
10885 GEN_XXSEL_ROW(0x05)
10886 GEN_XXSEL_ROW(0x06)
10887 GEN_XXSEL_ROW(0x07)
10888 GEN_XXSEL_ROW(0x08)
10889 GEN_XXSEL_ROW(0x09)
10890 GEN_XXSEL_ROW(0x0A)
10891 GEN_XXSEL_ROW(0x0B)
10892 GEN_XXSEL_ROW(0x0C)
10893 GEN_XXSEL_ROW(0x0D)
10894 GEN_XXSEL_ROW(0x0E)
10895 GEN_XXSEL_ROW(0x0F)
10896 GEN_XXSEL_ROW(0x10)
10897 GEN_XXSEL_ROW(0x11)
10898 GEN_XXSEL_ROW(0x12)
10899 GEN_XXSEL_ROW(0x13)
10900 GEN_XXSEL_ROW(0x14)
10901 GEN_XXSEL_ROW(0x15)
10902 GEN_XXSEL_ROW(0x16)
10903 GEN_XXSEL_ROW(0x17)
10904 GEN_XXSEL_ROW(0x18)
10905 GEN_XXSEL_ROW(0x19)
10906 GEN_XXSEL_ROW(0x1A)
10907 GEN_XXSEL_ROW(0x1B)
10908 GEN_XXSEL_ROW(0x1C)
10909 GEN_XXSEL_ROW(0x1D)
10910 GEN_XXSEL_ROW(0x1E)
10911 GEN_XXSEL_ROW(0x1F)
10912
10913 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10914
10915 #undef GEN_DFP_T_A_B_Rc
10916 #undef GEN_DFP_BF_A_B
10917 #undef GEN_DFP_BF_A_DCM
10918 #undef GEN_DFP_T_B_U32_U32_Rc
10919 #undef GEN_DFP_T_A_B_I32_Rc
10920 #undef GEN_DFP_T_B_Rc
10921 #undef GEN_DFP_T_FPR_I32_Rc
10922
10923 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10924 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10925
10926 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10927 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10928 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10929
10930 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10931 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10932 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10933 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10934 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10935
10936 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10937 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10938
10939 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10940 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10941 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10942
10943 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10944 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10945 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10946 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10947 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10948
10949 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10950 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10951
10952 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10953 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10954
10955 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10956 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10957
10958 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10959 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10960
10961 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10962 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10963
10964 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10965 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10966
10967 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10968 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10969
10970 #define GEN_DFP_BF_A_B(name, op1, op2) \
10971 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10972
10973 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10974 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10975
10976 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10977 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10978
10979 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10980 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10981
10982 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10983 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10984
10985 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10986 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10987
10988 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10989 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10990
10991 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10992 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10993
10994 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10995 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10996
10997 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10998 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10999
11000 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11001 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11002
11003 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11004 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11005
11006 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11007 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11008
11009 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11010 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11011
11012 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11013 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11014
11015 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11016 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11017
11018 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11019 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11020
11021 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11022 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11023
11024 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11025 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11026 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11027 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11028 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11029 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11030 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11031 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11032 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11033 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11034 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11035 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11036 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11037 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11038 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11039 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11040 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11041 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11042 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11043 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11044 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11045 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11046 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11047 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11048 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11049 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11050 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11051 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11052 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11053 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11054 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11055 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11056 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11057 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11058 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11059 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11060 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11061 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11062 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11063 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11064 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11065 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11066 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11067 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11068 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11069 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11070 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11071 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11072 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11073 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11074
11075 #undef GEN_SPE
11076 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11077 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11078 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11079 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11080 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11081 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11082 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11083 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11084 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11085 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11086 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11087 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11088 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11089 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11090 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11091 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11092 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11093 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11094 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11095 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11096 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11097 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11098 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11099 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11100 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11101 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11102 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11103 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11104 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11105 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11106 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11107
11108 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11109 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11110 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11111 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11112 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11113 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11114 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11115 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11116 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11117 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11118 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11119 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11120 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11121 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11122
11123 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11124 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11125 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11126 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11127 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11128 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11129 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11130 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11131 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11132 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11133 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11134 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11135 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11136 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11137
11138 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11139 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11140 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11141 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11142 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11143 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11144 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11145 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11146 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11147 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11148 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11149 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11150 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11151 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11152 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11153 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11154
11155 #undef GEN_SPEOP_LDST
11156 #define GEN_SPEOP_LDST(name, opc2, sh) \
11157 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11158 GEN_SPEOP_LDST(evldd, 0x00, 3),
11159 GEN_SPEOP_LDST(evldw, 0x01, 3),
11160 GEN_SPEOP_LDST(evldh, 0x02, 3),
11161 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11162 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11163 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11164 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11165 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11166 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11167 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11168 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11169
11170 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11171 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11172 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11173 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11174 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11175 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11176 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11177
11178 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11179 PPC_NONE, PPC2_TM),
11180 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11181 PPC_NONE, PPC2_TM),
11182 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11183 PPC_NONE, PPC2_TM),
11184 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11185 PPC_NONE, PPC2_TM),
11186 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11187 PPC_NONE, PPC2_TM),
11188 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11189 PPC_NONE, PPC2_TM),
11190 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11191 PPC_NONE, PPC2_TM),
11192 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11193 PPC_NONE, PPC2_TM),
11194 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11195 PPC_NONE, PPC2_TM),
11196 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11197 PPC_NONE, PPC2_TM),
11198 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11199 PPC_NONE, PPC2_TM),
11200 };
11201
11202 #include "helper_regs.h"
11203 #include "translate_init.c"
11204
11205 /*****************************************************************************/
11206 /* Misc PowerPC helpers */
11207 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11208 int flags)
11209 {
11210 #define RGPL 4
11211 #define RFPL 4
11212
11213 PowerPCCPU *cpu = POWERPC_CPU(cs);
11214 CPUPPCState *env = &cpu->env;
11215 int i;
11216
11217 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11218 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11219 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11220 cs->cpu_index);
11221 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11222 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11223 env->hflags, env->mmu_idx);
11224 #if !defined(NO_TIMER_DUMP)
11225 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11226 #if !defined(CONFIG_USER_ONLY)
11227 " DECR %08" PRIu32
11228 #endif
11229 "\n",
11230 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11231 #if !defined(CONFIG_USER_ONLY)
11232 , cpu_ppc_load_decr(env)
11233 #endif
11234 );
11235 #endif
11236 for (i = 0; i < 32; i++) {
11237 if ((i & (RGPL - 1)) == 0)
11238 cpu_fprintf(f, "GPR%02d", i);
11239 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11240 if ((i & (RGPL - 1)) == (RGPL - 1))
11241 cpu_fprintf(f, "\n");
11242 }
11243 cpu_fprintf(f, "CR ");
11244 for (i = 0; i < 8; i++)
11245 cpu_fprintf(f, "%01x", env->crf[i]);
11246 cpu_fprintf(f, " [");
11247 for (i = 0; i < 8; i++) {
11248 char a = '-';
11249 if (env->crf[i] & 0x08)
11250 a = 'L';
11251 else if (env->crf[i] & 0x04)
11252 a = 'G';
11253 else if (env->crf[i] & 0x02)
11254 a = 'E';
11255 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11256 }
11257 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11258 env->reserve_addr);
11259 for (i = 0; i < 32; i++) {
11260 if ((i & (RFPL - 1)) == 0)
11261 cpu_fprintf(f, "FPR%02d", i);
11262 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11263 if ((i & (RFPL - 1)) == (RFPL - 1))
11264 cpu_fprintf(f, "\n");
11265 }
11266 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11267 #if !defined(CONFIG_USER_ONLY)
11268 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11269 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11270 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11271 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11272
11273 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11274 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11275 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11276 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11277
11278 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11279 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11280 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11281 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11282
11283 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11284 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11285 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11286 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11287 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11288
11289 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11290 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11291 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11292 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11293
11294 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11295 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11296 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11297 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11298
11299 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11300 " EPR " TARGET_FMT_lx "\n",
11301 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11302 env->spr[SPR_BOOKE_EPR]);
11303
11304 /* FSL-specific */
11305 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11306 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11307 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11308 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11309
11310 /*
11311 * IVORs are left out as they are large and do not change often --
11312 * they can be read with "p $ivor0", "p $ivor1", etc.
11313 */
11314 }
11315
11316 #if defined(TARGET_PPC64)
11317 if (env->flags & POWERPC_FLAG_CFAR) {
11318 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11319 }
11320 #endif
11321
11322 switch (env->mmu_model) {
11323 case POWERPC_MMU_32B:
11324 case POWERPC_MMU_601:
11325 case POWERPC_MMU_SOFT_6xx:
11326 case POWERPC_MMU_SOFT_74xx:
11327 #if defined(TARGET_PPC64)
11328 case POWERPC_MMU_64B:
11329 case POWERPC_MMU_2_03:
11330 case POWERPC_MMU_2_06:
11331 case POWERPC_MMU_2_06a:
11332 case POWERPC_MMU_2_07:
11333 case POWERPC_MMU_2_07a:
11334 #endif
11335 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11336 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11337 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11338 break;
11339 case POWERPC_MMU_BOOKE206:
11340 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11341 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11342 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11343 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11344
11345 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11346 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11347 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11348 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11349
11350 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11351 " TLB1CFG " TARGET_FMT_lx "\n",
11352 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11353 env->spr[SPR_BOOKE_TLB1CFG]);
11354 break;
11355 default:
11356 break;
11357 }
11358 #endif
11359
11360 #undef RGPL
11361 #undef RFPL
11362 }
11363
11364 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11365 fprintf_function cpu_fprintf, int flags)
11366 {
11367 #if defined(DO_PPC_STATISTICS)
11368 PowerPCCPU *cpu = POWERPC_CPU(cs);
11369 opc_handler_t **t1, **t2, **t3, *handler;
11370 int op1, op2, op3;
11371
11372 t1 = cpu->env.opcodes;
11373 for (op1 = 0; op1 < 64; op1++) {
11374 handler = t1[op1];
11375 if (is_indirect_opcode(handler)) {
11376 t2 = ind_table(handler);
11377 for (op2 = 0; op2 < 32; op2++) {
11378 handler = t2[op2];
11379 if (is_indirect_opcode(handler)) {
11380 t3 = ind_table(handler);
11381 for (op3 = 0; op3 < 32; op3++) {
11382 handler = t3[op3];
11383 if (handler->count == 0)
11384 continue;
11385 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11386 "%016" PRIx64 " %" PRId64 "\n",
11387 op1, op2, op3, op1, (op3 << 5) | op2,
11388 handler->oname,
11389 handler->count, handler->count);
11390 }
11391 } else {
11392 if (handler->count == 0)
11393 continue;
11394 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11395 "%016" PRIx64 " %" PRId64 "\n",
11396 op1, op2, op1, op2, handler->oname,
11397 handler->count, handler->count);
11398 }
11399 }
11400 } else {
11401 if (handler->count == 0)
11402 continue;
11403 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11404 " %" PRId64 "\n",
11405 op1, op1, handler->oname,
11406 handler->count, handler->count);
11407 }
11408 }
11409 #endif
11410 }
11411
11412 /*****************************************************************************/
11413 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11414 {
11415 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11416 CPUState *cs = CPU(cpu);
11417 DisasContext ctx, *ctxp = &ctx;
11418 opc_handler_t **table, *handler;
11419 target_ulong pc_start;
11420 int num_insns;
11421 int max_insns;
11422
11423 pc_start = tb->pc;
11424 ctx.nip = pc_start;
11425 ctx.tb = tb;
11426 ctx.exception = POWERPC_EXCP_NONE;
11427 ctx.spr_cb = env->spr_cb;
11428 ctx.pr = msr_pr;
11429 ctx.hv = !msr_pr && msr_hv;
11430 ctx.mem_idx = env->mmu_idx;
11431 ctx.insns_flags = env->insns_flags;
11432 ctx.insns_flags2 = env->insns_flags2;
11433 ctx.access_type = -1;
11434 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11435 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11436 #if defined(TARGET_PPC64)
11437 ctx.sf_mode = msr_is_64bit(env, env->msr);
11438 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11439 #endif
11440 ctx.fpu_enabled = msr_fp;
11441 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11442 ctx.spe_enabled = msr_spe;
11443 else
11444 ctx.spe_enabled = 0;
11445 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11446 ctx.altivec_enabled = msr_vr;
11447 else
11448 ctx.altivec_enabled = 0;
11449 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11450 ctx.vsx_enabled = msr_vsx;
11451 } else {
11452 ctx.vsx_enabled = 0;
11453 }
11454 #if defined(TARGET_PPC64)
11455 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11456 ctx.tm_enabled = msr_tm;
11457 } else {
11458 ctx.tm_enabled = 0;
11459 }
11460 #endif
11461 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11462 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11463 else
11464 ctx.singlestep_enabled = 0;
11465 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11466 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11467 if (unlikely(cs->singlestep_enabled)) {
11468 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11469 }
11470 #if defined (DO_SINGLE_STEP) && 0
11471 /* Single step trace mode */
11472 msr_se = 1;
11473 #endif
11474 num_insns = 0;
11475 max_insns = tb->cflags & CF_COUNT_MASK;
11476 if (max_insns == 0) {
11477 max_insns = CF_COUNT_MASK;
11478 }
11479 if (max_insns > TCG_MAX_INSNS) {
11480 max_insns = TCG_MAX_INSNS;
11481 }
11482
11483 gen_tb_start(tb);
11484 tcg_clear_temp_count();
11485 /* Set env in case of segfault during code fetch */
11486 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11487 tcg_gen_insn_start(ctx.nip);
11488 num_insns++;
11489
11490 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11491 gen_debug_exception(ctxp);
11492 /* The address covered by the breakpoint must be included in
11493 [tb->pc, tb->pc + tb->size) in order to for it to be
11494 properly cleared -- thus we increment the PC here so that
11495 the logic setting tb->size below does the right thing. */
11496 ctx.nip += 4;
11497 break;
11498 }
11499
11500 LOG_DISAS("----------------\n");
11501 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11502 ctx.nip, ctx.mem_idx, (int)msr_ir);
11503 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11504 gen_io_start();
11505 if (unlikely(need_byteswap(&ctx))) {
11506 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11507 } else {
11508 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11509 }
11510 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11511 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11512 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11513 ctx.nip += 4;
11514 table = env->opcodes;
11515 handler = table[opc1(ctx.opcode)];
11516 if (is_indirect_opcode(handler)) {
11517 table = ind_table(handler);
11518 handler = table[opc2(ctx.opcode)];
11519 if (is_indirect_opcode(handler)) {
11520 table = ind_table(handler);
11521 handler = table[opc3(ctx.opcode)];
11522 }
11523 }
11524 /* Is opcode *REALLY* valid ? */
11525 if (unlikely(handler->handler == &gen_invalid)) {
11526 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11527 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11528 opc1(ctx.opcode), opc2(ctx.opcode),
11529 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11530 } else {
11531 uint32_t inval;
11532
11533 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11534 inval = handler->inval2;
11535 } else {
11536 inval = handler->inval1;
11537 }
11538
11539 if (unlikely((ctx.opcode & inval) != 0)) {
11540 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11541 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11542 ctx.opcode & inval, opc1(ctx.opcode),
11543 opc2(ctx.opcode), opc3(ctx.opcode),
11544 ctx.opcode, ctx.nip - 4);
11545 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11546 break;
11547 }
11548 }
11549 (*(handler->handler))(&ctx);
11550 #if defined(DO_PPC_STATISTICS)
11551 handler->count++;
11552 #endif
11553 /* Check trace mode exceptions */
11554 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11555 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11556 ctx.exception != POWERPC_SYSCALL &&
11557 ctx.exception != POWERPC_EXCP_TRAP &&
11558 ctx.exception != POWERPC_EXCP_BRANCH)) {
11559 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11560 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11561 (cs->singlestep_enabled) ||
11562 singlestep ||
11563 num_insns >= max_insns)) {
11564 /* if we reach a page boundary or are single stepping, stop
11565 * generation
11566 */
11567 break;
11568 }
11569 if (tcg_check_temp_count()) {
11570 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11571 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11572 ctx.opcode);
11573 exit(1);
11574 }
11575 }
11576 if (tb->cflags & CF_LAST_IO)
11577 gen_io_end();
11578 if (ctx.exception == POWERPC_EXCP_NONE) {
11579 gen_goto_tb(&ctx, 0, ctx.nip);
11580 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11581 if (unlikely(cs->singlestep_enabled)) {
11582 gen_debug_exception(ctxp);
11583 }
11584 /* Generate the return instruction */
11585 tcg_gen_exit_tb(0);
11586 }
11587 gen_tb_end(tb, num_insns);
11588
11589 tb->size = ctx.nip - pc_start;
11590 tb->icount = num_insns;
11591
11592 #if defined(DEBUG_DISAS)
11593 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11594 int flags;
11595 flags = env->bfd_mach;
11596 flags |= ctx.le_mode << 16;
11597 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11598 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11599 qemu_log("\n");
11600 }
11601 #endif
11602 }
11603
11604 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11605 target_ulong *data)
11606 {
11607 env->nip = data[0];
11608 }
AR7 emulation for QEMU