2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/ssi/ssi.h"
14 #include "hw/arm/boot.h"
15 #include "qemu/timer.h"
16 #include "hw/i2c/i2c.h"
18 #include "hw/boards.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/sysemu.h"
22 #include "hw/arm/armv7m.h"
23 #include "hw/char/pl011.h"
24 #include "hw/input/gamepad.h"
26 #include "hw/watchdog/cmsdk-apb-watchdog.h"
27 #include "migration/vmstate.h"
28 #include "hw/misc/unimp.h"
29 #include "hw/qdev-clock.h"
30 #include "qom/object.h"
40 #define BP_OLED_I2C 0x01
41 #define BP_OLED_SSI 0x02
42 #define BP_GAMEPAD 0x04
44 #define NUM_IRQ_LINES 64
46 typedef const struct {
56 } stellaris_board_info
;
58 /* General purpose timer module. */
60 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
61 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state
, STELLARIS_GPTM
)
64 SysBusDevice parent_obj
;
75 uint32_t match_prescale
[2];
78 struct gptm_state
*opaque
[2];
80 /* The timers have an alternate output used to trigger the ADC. */
85 static void gptm_update_irq(gptm_state
*s
)
88 level
= (s
->state
& s
->mask
) != 0;
89 qemu_set_irq(s
->irq
, level
);
92 static void gptm_stop(gptm_state
*s
, int n
)
94 timer_del(s
->timer
[n
]);
97 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
101 tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
105 if (s
->config
== 0) {
106 /* 32-bit CountDown. */
108 count
= s
->load
[0] | (s
->load
[1] << 16);
109 tick
+= (int64_t)count
* system_clock_scale
;
110 } else if (s
->config
== 1) {
111 /* 32-bit RTC. 1Hz tick. */
112 tick
+= NANOSECONDS_PER_SECOND
;
113 } else if (s
->mode
[n
] == 0xa) {
114 /* PWM mode. Not implemented. */
116 qemu_log_mask(LOG_UNIMP
,
117 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
122 timer_mod(s
->timer
[n
], tick
);
125 static void gptm_tick(void *opaque
)
127 gptm_state
**p
= (gptm_state
**)opaque
;
133 if (s
->config
== 0) {
135 if ((s
->control
& 0x20)) {
136 /* Output trigger. */
137 qemu_irq_pulse(s
->trigger
);
139 if (s
->mode
[0] & 1) {
144 gptm_reload(s
, 0, 0);
146 } else if (s
->config
== 1) {
150 match
= s
->match
[0] | (s
->match
[1] << 16);
156 gptm_reload(s
, 0, 0);
157 } else if (s
->mode
[n
] == 0xa) {
158 /* PWM mode. Not implemented. */
160 qemu_log_mask(LOG_UNIMP
,
161 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
167 static uint64_t gptm_read(void *opaque
, hwaddr offset
,
170 gptm_state
*s
= (gptm_state
*)opaque
;
175 case 0x04: /* TAMR */
177 case 0x08: /* TBMR */
186 return s
->state
& s
->mask
;
189 case 0x28: /* TAILR */
190 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
191 case 0x2c: /* TBILR */
193 case 0x30: /* TAMARCHR */
194 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
195 case 0x34: /* TBMATCHR */
197 case 0x38: /* TAPR */
198 return s
->prescale
[0];
199 case 0x3c: /* TBPR */
200 return s
->prescale
[1];
201 case 0x40: /* TAPMR */
202 return s
->match_prescale
[0];
203 case 0x44: /* TBPMR */
204 return s
->match_prescale
[1];
206 if (s
->config
== 1) {
209 qemu_log_mask(LOG_UNIMP
,
210 "GPTM: read of TAR but timer read not supported\n");
213 qemu_log_mask(LOG_UNIMP
,
214 "GPTM: read of TBR but timer read not supported\n");
217 qemu_log_mask(LOG_GUEST_ERROR
,
218 "GPTM: read at bad offset 0x02%" HWADDR_PRIx
"\n",
224 static void gptm_write(void *opaque
, hwaddr offset
,
225 uint64_t value
, unsigned size
)
227 gptm_state
*s
= (gptm_state
*)opaque
;
230 /* The timers should be disabled before changing the configuration.
231 We take advantage of this and defer everything until the timer
237 case 0x04: /* TAMR */
240 case 0x08: /* TBMR */
246 /* TODO: Implement pause. */
247 if ((oldval
^ value
) & 1) {
249 gptm_reload(s
, 0, 1);
254 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
256 gptm_reload(s
, 1, 1);
263 s
->mask
= value
& 0x77;
269 case 0x28: /* TAILR */
270 s
->load
[0] = value
& 0xffff;
272 s
->load
[1] = value
>> 16;
275 case 0x2c: /* TBILR */
276 s
->load
[1] = value
& 0xffff;
278 case 0x30: /* TAMARCHR */
279 s
->match
[0] = value
& 0xffff;
281 s
->match
[1] = value
>> 16;
284 case 0x34: /* TBMATCHR */
285 s
->match
[1] = value
>> 16;
287 case 0x38: /* TAPR */
288 s
->prescale
[0] = value
;
290 case 0x3c: /* TBPR */
291 s
->prescale
[1] = value
;
293 case 0x40: /* TAPMR */
294 s
->match_prescale
[0] = value
;
296 case 0x44: /* TBPMR */
297 s
->match_prescale
[0] = value
;
300 qemu_log_mask(LOG_GUEST_ERROR
,
301 "GPTM: write at bad offset 0x02%" HWADDR_PRIx
"\n",
307 static const MemoryRegionOps gptm_ops
= {
310 .endianness
= DEVICE_NATIVE_ENDIAN
,
313 static const VMStateDescription vmstate_stellaris_gptm
= {
314 .name
= "stellaris_gptm",
316 .minimum_version_id
= 1,
317 .fields
= (VMStateField
[]) {
318 VMSTATE_UINT32(config
, gptm_state
),
319 VMSTATE_UINT32_ARRAY(mode
, gptm_state
, 2),
320 VMSTATE_UINT32(control
, gptm_state
),
321 VMSTATE_UINT32(state
, gptm_state
),
322 VMSTATE_UINT32(mask
, gptm_state
),
324 VMSTATE_UINT32_ARRAY(load
, gptm_state
, 2),
325 VMSTATE_UINT32_ARRAY(match
, gptm_state
, 2),
326 VMSTATE_UINT32_ARRAY(prescale
, gptm_state
, 2),
327 VMSTATE_UINT32_ARRAY(match_prescale
, gptm_state
, 2),
328 VMSTATE_UINT32(rtc
, gptm_state
),
329 VMSTATE_INT64_ARRAY(tick
, gptm_state
, 2),
330 VMSTATE_TIMER_PTR_ARRAY(timer
, gptm_state
, 2),
331 VMSTATE_END_OF_LIST()
335 static void stellaris_gptm_init(Object
*obj
)
337 DeviceState
*dev
= DEVICE(obj
);
338 gptm_state
*s
= STELLARIS_GPTM(obj
);
339 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
341 sysbus_init_irq(sbd
, &s
->irq
);
342 qdev_init_gpio_out(dev
, &s
->trigger
, 1);
344 memory_region_init_io(&s
->iomem
, obj
, &gptm_ops
, s
,
346 sysbus_init_mmio(sbd
, &s
->iomem
);
348 s
->opaque
[0] = s
->opaque
[1] = s
;
351 static void stellaris_gptm_realize(DeviceState
*dev
, Error
**errp
)
353 gptm_state
*s
= STELLARIS_GPTM(dev
);
354 s
->timer
[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[0]);
355 s
->timer
[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[1]);
358 /* System controller. */
360 #define TYPE_STELLARIS_SYS "stellaris-sys"
361 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state
, STELLARIS_SYS
)
364 SysBusDevice parent_obj
;
381 /* Properties (all read-only registers) */
393 static void ssys_update(ssys_state
*s
)
395 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
398 static uint32_t pllcfg_sandstorm
[16] = {
400 0x1ae0, /* 1.8432 Mhz */
402 0xd573, /* 2.4576 Mhz */
403 0x37a6, /* 3.57954 Mhz */
404 0x1ae2, /* 3.6864 Mhz */
406 0x98bc, /* 4.906 Mhz */
407 0x935b, /* 4.9152 Mhz */
409 0x4dee, /* 5.12 Mhz */
411 0x75db, /* 6.144 Mhz */
412 0x1ae6, /* 7.3728 Mhz */
414 0x585b /* 8.192 Mhz */
417 static uint32_t pllcfg_fury
[16] = {
419 0x1b20, /* 1.8432 Mhz */
421 0xf42b, /* 2.4576 Mhz */
422 0x37e3, /* 3.57954 Mhz */
423 0x1b21, /* 3.6864 Mhz */
425 0x98ee, /* 4.906 Mhz */
426 0xd5b4, /* 4.9152 Mhz */
428 0x4e27, /* 5.12 Mhz */
430 0xec1c, /* 6.144 Mhz */
431 0x1b23, /* 7.3728 Mhz */
433 0xb11c /* 8.192 Mhz */
436 #define DID0_VER_MASK 0x70000000
437 #define DID0_VER_0 0x00000000
438 #define DID0_VER_1 0x10000000
440 #define DID0_CLASS_MASK 0x00FF0000
441 #define DID0_CLASS_SANDSTORM 0x00000000
442 #define DID0_CLASS_FURY 0x00010000
444 static int ssys_board_class(const ssys_state
*s
)
446 uint32_t did0
= s
->did0
;
447 switch (did0
& DID0_VER_MASK
) {
449 return DID0_CLASS_SANDSTORM
;
451 switch (did0
& DID0_CLASS_MASK
) {
452 case DID0_CLASS_SANDSTORM
:
453 case DID0_CLASS_FURY
:
454 return did0
& DID0_CLASS_MASK
;
456 /* for unknown classes, fall through */
458 /* This can only happen if the hardwired constant did0 value
459 * in this board's stellaris_board_info struct is wrong.
461 g_assert_not_reached();
465 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
468 ssys_state
*s
= (ssys_state
*)opaque
;
471 case 0x000: /* DID0 */
473 case 0x004: /* DID1 */
475 case 0x008: /* DC0 */
477 case 0x010: /* DC1 */
479 case 0x014: /* DC2 */
481 case 0x018: /* DC3 */
483 case 0x01c: /* DC4 */
485 case 0x030: /* PBORCTL */
487 case 0x034: /* LDOPCTL */
489 case 0x040: /* SRCR0 */
491 case 0x044: /* SRCR1 */
493 case 0x048: /* SRCR2 */
495 case 0x050: /* RIS */
496 return s
->int_status
;
497 case 0x054: /* IMC */
499 case 0x058: /* MISC */
500 return s
->int_status
& s
->int_mask
;
501 case 0x05c: /* RESC */
503 case 0x060: /* RCC */
505 case 0x064: /* PLLCFG */
508 xtal
= (s
->rcc
>> 6) & 0xf;
509 switch (ssys_board_class(s
)) {
510 case DID0_CLASS_FURY
:
511 return pllcfg_fury
[xtal
];
512 case DID0_CLASS_SANDSTORM
:
513 return pllcfg_sandstorm
[xtal
];
515 g_assert_not_reached();
518 case 0x070: /* RCC2 */
520 case 0x100: /* RCGC0 */
522 case 0x104: /* RCGC1 */
524 case 0x108: /* RCGC2 */
526 case 0x110: /* SCGC0 */
528 case 0x114: /* SCGC1 */
530 case 0x118: /* SCGC2 */
532 case 0x120: /* DCGC0 */
534 case 0x124: /* DCGC1 */
536 case 0x128: /* DCGC2 */
538 case 0x150: /* CLKVCLR */
540 case 0x160: /* LDOARST */
542 case 0x1e0: /* USER0 */
544 case 0x1e4: /* USER1 */
547 qemu_log_mask(LOG_GUEST_ERROR
,
548 "SSYS: read at bad offset 0x%x\n", (int)offset
);
553 static bool ssys_use_rcc2(ssys_state
*s
)
555 return (s
->rcc2
>> 31) & 0x1;
559 * Calculate the system clock period. We only want to propagate
560 * this change to the rest of the system if we're not being called
561 * from migration post-load.
563 static void ssys_calculate_system_clock(ssys_state
*s
, bool propagate_clock
)
566 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
567 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
568 * frequency by X is the same as multiplying the period by X.
570 if (ssys_use_rcc2(s
)) {
571 system_clock_scale
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
573 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
575 clock_set_ns(s
->sysclk
, system_clock_scale
);
576 if (propagate_clock
) {
577 clock_propagate(s
->sysclk
);
581 static void ssys_write(void *opaque
, hwaddr offset
,
582 uint64_t value
, unsigned size
)
584 ssys_state
*s
= (ssys_state
*)opaque
;
587 case 0x030: /* PBORCTL */
588 s
->pborctl
= value
& 0xffff;
590 case 0x034: /* LDOPCTL */
591 s
->ldopctl
= value
& 0x1f;
593 case 0x040: /* SRCR0 */
594 case 0x044: /* SRCR1 */
595 case 0x048: /* SRCR2 */
596 qemu_log_mask(LOG_UNIMP
, "Peripheral reset not implemented\n");
598 case 0x054: /* IMC */
599 s
->int_mask
= value
& 0x7f;
601 case 0x058: /* MISC */
602 s
->int_status
&= ~value
;
604 case 0x05c: /* RESC */
605 s
->resc
= value
& 0x3f;
607 case 0x060: /* RCC */
608 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
610 s
->int_status
|= (1 << 6);
613 ssys_calculate_system_clock(s
, true);
615 case 0x070: /* RCC2 */
616 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
620 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
622 s
->int_status
|= (1 << 6);
625 ssys_calculate_system_clock(s
, true);
627 case 0x100: /* RCGC0 */
630 case 0x104: /* RCGC1 */
633 case 0x108: /* RCGC2 */
636 case 0x110: /* SCGC0 */
639 case 0x114: /* SCGC1 */
642 case 0x118: /* SCGC2 */
645 case 0x120: /* DCGC0 */
648 case 0x124: /* DCGC1 */
651 case 0x128: /* DCGC2 */
654 case 0x150: /* CLKVCLR */
657 case 0x160: /* LDOARST */
661 qemu_log_mask(LOG_GUEST_ERROR
,
662 "SSYS: write at bad offset 0x%x\n", (int)offset
);
667 static const MemoryRegionOps ssys_ops
= {
670 .endianness
= DEVICE_NATIVE_ENDIAN
,
673 static void stellaris_sys_reset_enter(Object
*obj
, ResetType type
)
675 ssys_state
*s
= STELLARIS_SYS(obj
);
680 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
683 s
->rcc2
= 0x07802810;
690 static void stellaris_sys_reset_hold(Object
*obj
)
692 ssys_state
*s
= STELLARIS_SYS(obj
);
694 /* OK to propagate clocks from the hold phase */
695 ssys_calculate_system_clock(s
, true);
698 static void stellaris_sys_reset_exit(Object
*obj
)
702 static int stellaris_sys_post_load(void *opaque
, int version_id
)
704 ssys_state
*s
= opaque
;
706 ssys_calculate_system_clock(s
, false);
711 static const VMStateDescription vmstate_stellaris_sys
= {
712 .name
= "stellaris_sys",
714 .minimum_version_id
= 1,
715 .post_load
= stellaris_sys_post_load
,
716 .fields
= (VMStateField
[]) {
717 VMSTATE_UINT32(pborctl
, ssys_state
),
718 VMSTATE_UINT32(ldopctl
, ssys_state
),
719 VMSTATE_UINT32(int_mask
, ssys_state
),
720 VMSTATE_UINT32(int_status
, ssys_state
),
721 VMSTATE_UINT32(resc
, ssys_state
),
722 VMSTATE_UINT32(rcc
, ssys_state
),
723 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
724 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
725 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
726 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
727 VMSTATE_UINT32(clkvclr
, ssys_state
),
728 VMSTATE_UINT32(ldoarst
, ssys_state
),
729 /* No field for sysclk -- handled in post-load instead */
730 VMSTATE_END_OF_LIST()
734 static Property stellaris_sys_properties
[] = {
735 DEFINE_PROP_UINT32("user0", ssys_state
, user0
, 0),
736 DEFINE_PROP_UINT32("user1", ssys_state
, user1
, 0),
737 DEFINE_PROP_UINT32("did0", ssys_state
, did0
, 0),
738 DEFINE_PROP_UINT32("did1", ssys_state
, did1
, 0),
739 DEFINE_PROP_UINT32("dc0", ssys_state
, dc0
, 0),
740 DEFINE_PROP_UINT32("dc1", ssys_state
, dc1
, 0),
741 DEFINE_PROP_UINT32("dc2", ssys_state
, dc2
, 0),
742 DEFINE_PROP_UINT32("dc3", ssys_state
, dc3
, 0),
743 DEFINE_PROP_UINT32("dc4", ssys_state
, dc4
, 0),
744 DEFINE_PROP_END_OF_LIST()
747 static void stellaris_sys_instance_init(Object
*obj
)
749 ssys_state
*s
= STELLARIS_SYS(obj
);
750 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
752 memory_region_init_io(&s
->iomem
, obj
, &ssys_ops
, s
, "ssys", 0x00001000);
753 sysbus_init_mmio(sbd
, &s
->iomem
);
754 sysbus_init_irq(sbd
, &s
->irq
);
755 s
->sysclk
= qdev_init_clock_out(DEVICE(s
), "SYSCLK");
758 static DeviceState
*stellaris_sys_init(uint32_t base
, qemu_irq irq
,
759 stellaris_board_info
*board
,
762 DeviceState
*dev
= qdev_new(TYPE_STELLARIS_SYS
);
763 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
765 /* Most devices come preprogrammed with a MAC address in the user data. */
766 qdev_prop_set_uint32(dev
, "user0",
767 macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16));
768 qdev_prop_set_uint32(dev
, "user1",
769 macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16));
770 qdev_prop_set_uint32(dev
, "did0", board
->did0
);
771 qdev_prop_set_uint32(dev
, "did1", board
->did1
);
772 qdev_prop_set_uint32(dev
, "dc0", board
->dc0
);
773 qdev_prop_set_uint32(dev
, "dc1", board
->dc1
);
774 qdev_prop_set_uint32(dev
, "dc2", board
->dc2
);
775 qdev_prop_set_uint32(dev
, "dc3", board
->dc3
);
776 qdev_prop_set_uint32(dev
, "dc4", board
->dc4
);
778 sysbus_realize_and_unref(sbd
, &error_fatal
);
779 sysbus_mmio_map(sbd
, 0, base
);
780 sysbus_connect_irq(sbd
, 0, irq
);
785 /* I2C controller. */
787 #define TYPE_STELLARIS_I2C "stellaris-i2c"
788 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state
, STELLARIS_I2C
)
790 struct stellaris_i2c_state
{
791 SysBusDevice parent_obj
;
805 #define STELLARIS_I2C_MCS_BUSY 0x01
806 #define STELLARIS_I2C_MCS_ERROR 0x02
807 #define STELLARIS_I2C_MCS_ADRACK 0x04
808 #define STELLARIS_I2C_MCS_DATACK 0x08
809 #define STELLARIS_I2C_MCS_ARBLST 0x10
810 #define STELLARIS_I2C_MCS_IDLE 0x20
811 #define STELLARIS_I2C_MCS_BUSBSY 0x40
813 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
816 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
822 /* We don't emulate timing, so the controller is never busy. */
823 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
826 case 0x0c: /* MTPR */
828 case 0x10: /* MIMR */
830 case 0x14: /* MRIS */
832 case 0x18: /* MMIS */
833 return s
->mris
& s
->mimr
;
837 qemu_log_mask(LOG_GUEST_ERROR
,
838 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset
);
843 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
847 level
= (s
->mris
& s
->mimr
) != 0;
848 qemu_set_irq(s
->irq
, level
);
851 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
852 uint64_t value
, unsigned size
)
854 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
858 s
->msa
= value
& 0xff;
861 if ((s
->mcr
& 0x10) == 0) {
862 /* Disabled. Do nothing. */
865 /* Grab the bus if this is starting a transfer. */
866 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
867 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
868 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
870 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
871 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
874 /* If we don't have the bus then indicate an error. */
875 if (!i2c_bus_busy(s
->bus
)
876 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
877 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
880 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
882 /* Transfer a byte. */
883 /* TODO: Handle errors. */
886 s
->mdr
= i2c_recv(s
->bus
);
889 i2c_send(s
->bus
, s
->mdr
);
891 /* Raise an interrupt. */
895 /* Finish transfer. */
896 i2c_end_transfer(s
->bus
);
897 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
901 s
->mdr
= value
& 0xff;
903 case 0x0c: /* MTPR */
904 s
->mtpr
= value
& 0xff;
906 case 0x10: /* MIMR */
909 case 0x1c: /* MICR */
914 qemu_log_mask(LOG_UNIMP
,
915 "stellaris_i2c: Loopback not implemented\n");
918 qemu_log_mask(LOG_UNIMP
,
919 "stellaris_i2c: Slave mode not implemented\n");
921 s
->mcr
= value
& 0x31;
924 qemu_log_mask(LOG_GUEST_ERROR
,
925 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset
);
927 stellaris_i2c_update(s
);
930 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
932 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
933 i2c_end_transfer(s
->bus
);
942 stellaris_i2c_update(s
);
945 static const MemoryRegionOps stellaris_i2c_ops
= {
946 .read
= stellaris_i2c_read
,
947 .write
= stellaris_i2c_write
,
948 .endianness
= DEVICE_NATIVE_ENDIAN
,
951 static const VMStateDescription vmstate_stellaris_i2c
= {
952 .name
= "stellaris_i2c",
954 .minimum_version_id
= 1,
955 .fields
= (VMStateField
[]) {
956 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
957 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
958 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
959 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
960 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
961 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
962 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
963 VMSTATE_END_OF_LIST()
967 static void stellaris_i2c_init(Object
*obj
)
969 DeviceState
*dev
= DEVICE(obj
);
970 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
971 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
974 sysbus_init_irq(sbd
, &s
->irq
);
975 bus
= i2c_init_bus(dev
, "i2c");
978 memory_region_init_io(&s
->iomem
, obj
, &stellaris_i2c_ops
, s
,
980 sysbus_init_mmio(sbd
, &s
->iomem
);
981 /* ??? For now we only implement the master interface. */
982 stellaris_i2c_reset(s
);
985 /* Analogue to Digital Converter. This is only partially implemented,
986 enough for applications that use a combined ADC and timer tick. */
988 #define STELLARIS_ADC_EM_CONTROLLER 0
989 #define STELLARIS_ADC_EM_COMP 1
990 #define STELLARIS_ADC_EM_EXTERNAL 4
991 #define STELLARIS_ADC_EM_TIMER 5
992 #define STELLARIS_ADC_EM_PWM0 6
993 #define STELLARIS_ADC_EM_PWM1 7
994 #define STELLARIS_ADC_EM_PWM2 8
996 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
997 #define STELLARIS_ADC_FIFO_FULL 0x1000
999 #define TYPE_STELLARIS_ADC "stellaris-adc"
1000 typedef struct StellarisADCState stellaris_adc_state
;
1001 DECLARE_INSTANCE_CHECKER(stellaris_adc_state
, STELLARIS_ADC
,
1004 struct StellarisADCState
{
1005 SysBusDevice parent_obj
;
1026 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
1030 tail
= s
->fifo
[n
].state
& 0xf;
1031 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
1034 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
1035 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
1036 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
1037 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
1039 return s
->fifo
[n
].data
[tail
];
1042 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
1047 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
1048 FIFO fir each sequencer. */
1049 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
1050 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
1054 s
->fifo
[n
].data
[head
] = value
;
1055 head
= (head
+ 1) & 0xf;
1056 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
1057 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
1058 if ((s
->fifo
[n
].state
& 0xf) == head
)
1059 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
1062 static void stellaris_adc_update(stellaris_adc_state
*s
)
1067 for (n
= 0; n
< 4; n
++) {
1068 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
1069 qemu_set_irq(s
->irq
[n
], level
);
1073 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
1075 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1078 for (n
= 0; n
< 4; n
++) {
1079 if ((s
->actss
& (1 << n
)) == 0) {
1083 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
1087 /* Some applications use the ADC as a random number source, so introduce
1088 some variation into the signal. */
1089 s
->noise
= s
->noise
* 314159 + 1;
1090 /* ??? actual inputs not implemented. Return an arbitrary value. */
1091 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
1093 stellaris_adc_update(s
);
1097 static void stellaris_adc_reset(stellaris_adc_state
*s
)
1101 for (n
= 0; n
< 4; n
++) {
1104 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
1108 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
1111 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1113 /* TODO: Implement this. */
1114 if (offset
>= 0x40 && offset
< 0xc0) {
1116 n
= (offset
- 0x40) >> 5;
1117 switch (offset
& 0x1f) {
1118 case 0x00: /* SSMUX */
1120 case 0x04: /* SSCTL */
1122 case 0x08: /* SSFIFO */
1123 return stellaris_adc_fifo_read(s
, n
);
1124 case 0x0c: /* SSFSTAT */
1125 return s
->fifo
[n
].state
;
1131 case 0x00: /* ACTSS */
1133 case 0x04: /* RIS */
1137 case 0x0c: /* ISC */
1138 return s
->ris
& s
->im
;
1139 case 0x10: /* OSTAT */
1141 case 0x14: /* EMUX */
1143 case 0x18: /* USTAT */
1145 case 0x20: /* SSPRI */
1147 case 0x30: /* SAC */
1150 qemu_log_mask(LOG_GUEST_ERROR
,
1151 "stellaris_adc: read at bad offset 0x%x\n", (int)offset
);
1156 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
1157 uint64_t value
, unsigned size
)
1159 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1161 /* TODO: Implement this. */
1162 if (offset
>= 0x40 && offset
< 0xc0) {
1164 n
= (offset
- 0x40) >> 5;
1165 switch (offset
& 0x1f) {
1166 case 0x00: /* SSMUX */
1167 s
->ssmux
[n
] = value
& 0x33333333;
1169 case 0x04: /* SSCTL */
1171 qemu_log_mask(LOG_UNIMP
,
1172 "ADC: Unimplemented sequence %" PRIx64
"\n",
1175 s
->ssctl
[n
] = value
;
1182 case 0x00: /* ACTSS */
1183 s
->actss
= value
& 0xf;
1188 case 0x0c: /* ISC */
1191 case 0x10: /* OSTAT */
1194 case 0x14: /* EMUX */
1197 case 0x18: /* USTAT */
1200 case 0x20: /* SSPRI */
1203 case 0x28: /* PSSI */
1204 qemu_log_mask(LOG_UNIMP
, "ADC: sample initiate unimplemented\n");
1206 case 0x30: /* SAC */
1210 qemu_log_mask(LOG_GUEST_ERROR
,
1211 "stellaris_adc: write at bad offset 0x%x\n", (int)offset
);
1213 stellaris_adc_update(s
);
1216 static const MemoryRegionOps stellaris_adc_ops
= {
1217 .read
= stellaris_adc_read
,
1218 .write
= stellaris_adc_write
,
1219 .endianness
= DEVICE_NATIVE_ENDIAN
,
1222 static const VMStateDescription vmstate_stellaris_adc
= {
1223 .name
= "stellaris_adc",
1225 .minimum_version_id
= 1,
1226 .fields
= (VMStateField
[]) {
1227 VMSTATE_UINT32(actss
, stellaris_adc_state
),
1228 VMSTATE_UINT32(ris
, stellaris_adc_state
),
1229 VMSTATE_UINT32(im
, stellaris_adc_state
),
1230 VMSTATE_UINT32(emux
, stellaris_adc_state
),
1231 VMSTATE_UINT32(ostat
, stellaris_adc_state
),
1232 VMSTATE_UINT32(ustat
, stellaris_adc_state
),
1233 VMSTATE_UINT32(sspri
, stellaris_adc_state
),
1234 VMSTATE_UINT32(sac
, stellaris_adc_state
),
1235 VMSTATE_UINT32(fifo
[0].state
, stellaris_adc_state
),
1236 VMSTATE_UINT32_ARRAY(fifo
[0].data
, stellaris_adc_state
, 16),
1237 VMSTATE_UINT32(ssmux
[0], stellaris_adc_state
),
1238 VMSTATE_UINT32(ssctl
[0], stellaris_adc_state
),
1239 VMSTATE_UINT32(fifo
[1].state
, stellaris_adc_state
),
1240 VMSTATE_UINT32_ARRAY(fifo
[1].data
, stellaris_adc_state
, 16),
1241 VMSTATE_UINT32(ssmux
[1], stellaris_adc_state
),
1242 VMSTATE_UINT32(ssctl
[1], stellaris_adc_state
),
1243 VMSTATE_UINT32(fifo
[2].state
, stellaris_adc_state
),
1244 VMSTATE_UINT32_ARRAY(fifo
[2].data
, stellaris_adc_state
, 16),
1245 VMSTATE_UINT32(ssmux
[2], stellaris_adc_state
),
1246 VMSTATE_UINT32(ssctl
[2], stellaris_adc_state
),
1247 VMSTATE_UINT32(fifo
[3].state
, stellaris_adc_state
),
1248 VMSTATE_UINT32_ARRAY(fifo
[3].data
, stellaris_adc_state
, 16),
1249 VMSTATE_UINT32(ssmux
[3], stellaris_adc_state
),
1250 VMSTATE_UINT32(ssctl
[3], stellaris_adc_state
),
1251 VMSTATE_UINT32(noise
, stellaris_adc_state
),
1252 VMSTATE_END_OF_LIST()
1256 static void stellaris_adc_init(Object
*obj
)
1258 DeviceState
*dev
= DEVICE(obj
);
1259 stellaris_adc_state
*s
= STELLARIS_ADC(obj
);
1260 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1263 for (n
= 0; n
< 4; n
++) {
1264 sysbus_init_irq(sbd
, &s
->irq
[n
]);
1267 memory_region_init_io(&s
->iomem
, obj
, &stellaris_adc_ops
, s
,
1269 sysbus_init_mmio(sbd
, &s
->iomem
);
1270 stellaris_adc_reset(s
);
1271 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
1275 static stellaris_board_info stellaris_boards
[] = {
1279 0x001f001f, /* dc0 */
1289 0x00ff007f, /* dc0 */
1294 BP_OLED_SSI
| BP_GAMEPAD
1298 static void stellaris_init(MachineState
*ms
, stellaris_board_info
*board
)
1300 static const int uart_irq
[] = {5, 6, 33, 34};
1301 static const int timer_irq
[] = {19, 21, 23, 35};
1302 static const uint32_t gpio_addr
[7] =
1303 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1304 0x40024000, 0x40025000, 0x40026000};
1305 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1307 /* Memory map of SoC devices, from
1308 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1309 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1312 * 40002000 i2c (unimplemented)
1322 * 40021000 i2c (unimplemented)
1326 * 40028000 PWM (unimplemented)
1327 * 4002c000 QEI (unimplemented)
1328 * 4002d000 QEI (unimplemented)
1334 * 4003c000 analogue comparator (unimplemented)
1336 * 400fc000 hibernation module (unimplemented)
1337 * 400fd000 flash memory control (unimplemented)
1338 * 400fe000 system control
1341 DeviceState
*gpio_dev
[7], *nvic
;
1342 qemu_irq gpio_in
[7][8];
1343 qemu_irq gpio_out
[7][8];
1349 DeviceState
*ssys_dev
;
1353 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1354 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1355 MemoryRegion
*system_memory
= get_system_memory();
1357 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1358 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1360 /* Flash programming is done via the SCU, so pretend it is ROM. */
1361 memory_region_init_rom(flash
, NULL
, "stellaris.flash", flash_size
,
1363 memory_region_add_subregion(system_memory
, 0, flash
);
1365 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1367 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1369 nvic
= qdev_new(TYPE_ARMV7M
);
1370 qdev_prop_set_uint32(nvic
, "num-irq", NUM_IRQ_LINES
);
1371 qdev_prop_set_string(nvic
, "cpu-type", ms
->cpu_type
);
1372 qdev_prop_set_bit(nvic
, "enable-bitband", true);
1373 object_property_set_link(OBJECT(nvic
), "memory",
1374 OBJECT(get_system_memory()), &error_abort
);
1375 /* This will exit with an error if the user passed us a bad cpu_type */
1376 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic
), &error_fatal
);
1378 if (board
->dc1
& (1 << 16)) {
1379 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1380 qdev_get_gpio_in(nvic
, 14),
1381 qdev_get_gpio_in(nvic
, 15),
1382 qdev_get_gpio_in(nvic
, 16),
1383 qdev_get_gpio_in(nvic
, 17),
1385 adc
= qdev_get_gpio_in(dev
, 0);
1389 for (i
= 0; i
< 4; i
++) {
1390 if (board
->dc2
& (0x10000 << i
)) {
1391 dev
= sysbus_create_simple(TYPE_STELLARIS_GPTM
,
1392 0x40030000 + i
* 0x1000,
1393 qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1394 /* TODO: This is incorrect, but we get away with it because
1395 the ADC output is only ever pulsed. */
1396 qdev_connect_gpio_out(dev
, 0, adc
);
1400 ssys_dev
= stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic
, 28),
1401 board
, nd_table
[0].macaddr
.a
);
1404 if (board
->dc1
& (1 << 3)) { /* watchdog present */
1405 dev
= qdev_new(TYPE_LUMINARY_WATCHDOG
);
1407 qdev_connect_clock_in(dev
, "WDOGCLK",
1408 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1410 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1411 sysbus_mmio_map(SYS_BUS_DEVICE(dev
),
1414 sysbus_connect_irq(SYS_BUS_DEVICE(dev
),
1416 qdev_get_gpio_in(nvic
, 18));
1420 for (i
= 0; i
< 7; i
++) {
1421 if (board
->dc4
& (1 << i
)) {
1422 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1423 qdev_get_gpio_in(nvic
,
1425 for (j
= 0; j
< 8; j
++) {
1426 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1427 gpio_out
[i
][j
] = NULL
;
1432 if (board
->dc2
& (1 << 12)) {
1433 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1434 qdev_get_gpio_in(nvic
, 8));
1435 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1436 if (board
->peripherals
& BP_OLED_I2C
) {
1437 i2c_slave_create_simple(i2c
, "ssd0303", 0x3d);
1441 for (i
= 0; i
< 4; i
++) {
1442 if (board
->dc2
& (1 << i
)) {
1443 pl011_luminary_create(0x4000c000 + i
* 0x1000,
1444 qdev_get_gpio_in(nvic
, uart_irq
[i
]),
1448 if (board
->dc2
& (1 << 4)) {
1449 dev
= sysbus_create_simple("pl022", 0x40008000,
1450 qdev_get_gpio_in(nvic
, 7));
1451 if (board
->peripherals
& BP_OLED_SSI
) {
1454 DeviceState
*ssddev
;
1456 /* Some boards have both an OLED controller and SD card connected to
1457 * the same SSI port, with the SD card chip select connected to a
1458 * GPIO pin. Technically the OLED chip select is connected to the
1459 * SSI Fss pin. We do not bother emulating that as both devices
1460 * should never be selected simultaneously, and our OLED controller
1461 * ignores stray 0xff commands that occur when deselecting the SD
1464 bus
= qdev_get_child_bus(dev
, "ssi");
1466 sddev
= ssi_create_peripheral(bus
, "ssi-sd");
1467 ssddev
= ssi_create_peripheral(bus
, "ssd0323");
1468 gpio_out
[GPIO_D
][0] = qemu_irq_split(
1469 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0),
1470 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1471 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1473 /* Make sure the select pin is high. */
1474 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1477 if (board
->dc4
& (1 << 28)) {
1480 qemu_check_nic_model(&nd_table
[0], "stellaris");
1482 enet
= qdev_new("stellaris_enet");
1483 qdev_set_nic_properties(enet
, &nd_table
[0]);
1484 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet
), &error_fatal
);
1485 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1486 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1488 if (board
->peripherals
& BP_GAMEPAD
) {
1489 qemu_irq gpad_irq
[5];
1490 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1492 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1493 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1494 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1495 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1496 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1498 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1500 for (i
= 0; i
< 7; i
++) {
1501 if (board
->dc4
& (1 << i
)) {
1502 for (j
= 0; j
< 8; j
++) {
1503 if (gpio_out
[i
][j
]) {
1504 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1510 /* Add dummy regions for the devices we don't implement yet,
1511 * so guest accesses don't cause unlogged crashes.
1513 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1514 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1515 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1516 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1517 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1518 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1519 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1520 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1522 armv7m_load_kernel(ARM_CPU(first_cpu
), ms
->kernel_filename
, flash_size
);
1525 /* FIXME: Figure out how to generate these from stellaris_boards. */
1526 static void lm3s811evb_init(MachineState
*machine
)
1528 stellaris_init(machine
, &stellaris_boards
[0]);
1531 static void lm3s6965evb_init(MachineState
*machine
)
1533 stellaris_init(machine
, &stellaris_boards
[1]);
1536 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1538 MachineClass
*mc
= MACHINE_CLASS(oc
);
1540 mc
->desc
= "Stellaris LM3S811EVB (Cortex-M3)";
1541 mc
->init
= lm3s811evb_init
;
1542 mc
->ignore_memory_transaction_failures
= true;
1543 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1546 static const TypeInfo lm3s811evb_type
= {
1547 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1548 .parent
= TYPE_MACHINE
,
1549 .class_init
= lm3s811evb_class_init
,
1552 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1554 MachineClass
*mc
= MACHINE_CLASS(oc
);
1556 mc
->desc
= "Stellaris LM3S6965EVB (Cortex-M3)";
1557 mc
->init
= lm3s6965evb_init
;
1558 mc
->ignore_memory_transaction_failures
= true;
1559 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1562 static const TypeInfo lm3s6965evb_type
= {
1563 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1564 .parent
= TYPE_MACHINE
,
1565 .class_init
= lm3s6965evb_class_init
,
1568 static void stellaris_machine_init(void)
1570 type_register_static(&lm3s811evb_type
);
1571 type_register_static(&lm3s6965evb_type
);
1574 type_init(stellaris_machine_init
)
1576 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1578 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1580 dc
->vmsd
= &vmstate_stellaris_i2c
;
1583 static const TypeInfo stellaris_i2c_info
= {
1584 .name
= TYPE_STELLARIS_I2C
,
1585 .parent
= TYPE_SYS_BUS_DEVICE
,
1586 .instance_size
= sizeof(stellaris_i2c_state
),
1587 .instance_init
= stellaris_i2c_init
,
1588 .class_init
= stellaris_i2c_class_init
,
1591 static void stellaris_gptm_class_init(ObjectClass
*klass
, void *data
)
1593 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1595 dc
->vmsd
= &vmstate_stellaris_gptm
;
1596 dc
->realize
= stellaris_gptm_realize
;
1599 static const TypeInfo stellaris_gptm_info
= {
1600 .name
= TYPE_STELLARIS_GPTM
,
1601 .parent
= TYPE_SYS_BUS_DEVICE
,
1602 .instance_size
= sizeof(gptm_state
),
1603 .instance_init
= stellaris_gptm_init
,
1604 .class_init
= stellaris_gptm_class_init
,
1607 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1609 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1611 dc
->vmsd
= &vmstate_stellaris_adc
;
1614 static const TypeInfo stellaris_adc_info
= {
1615 .name
= TYPE_STELLARIS_ADC
,
1616 .parent
= TYPE_SYS_BUS_DEVICE
,
1617 .instance_size
= sizeof(stellaris_adc_state
),
1618 .instance_init
= stellaris_adc_init
,
1619 .class_init
= stellaris_adc_class_init
,
1622 static void stellaris_sys_class_init(ObjectClass
*klass
, void *data
)
1624 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1625 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
1627 dc
->vmsd
= &vmstate_stellaris_sys
;
1628 rc
->phases
.enter
= stellaris_sys_reset_enter
;
1629 rc
->phases
.hold
= stellaris_sys_reset_hold
;
1630 rc
->phases
.exit
= stellaris_sys_reset_exit
;
1631 device_class_set_props(dc
, stellaris_sys_properties
);
1634 static const TypeInfo stellaris_sys_info
= {
1635 .name
= TYPE_STELLARIS_SYS
,
1636 .parent
= TYPE_SYS_BUS_DEVICE
,
1637 .instance_size
= sizeof(ssys_state
),
1638 .instance_init
= stellaris_sys_instance_init
,
1639 .class_init
= stellaris_sys_class_init
,
1642 static void stellaris_register_types(void)
1644 type_register_static(&stellaris_i2c_info
);
1645 type_register_static(&stellaris_gptm_info
);
1646 type_register_static(&stellaris_adc_info
);
1647 type_register_static(&stellaris_sys_info
);
1650 type_init(stellaris_register_types
)