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qemu-nbd: Add --bitmap=NAME option
[qemu/ar7.git] / tcg / mips / tcg-target.inc.c
blobbe0bc92e8e7b0b33df45a37fa4e31670bde81bc0
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #ifdef HOST_WORDS_BIGENDIAN
28 # define MIPS_BE 1
29 #else
30 # define MIPS_BE 0
31 #endif
32
33 #if TCG_TARGET_REG_BITS == 32
34 # define LO_OFF (MIPS_BE * 4)
35 # define HI_OFF (4 - LO_OFF)
36 #else
37 /* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
39 int link_error(void);
40 # define LO_OFF link_error()
41 # define HI_OFF link_error()
42 #endif
43
44 #ifdef CONFIG_DEBUG_TCG
45 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
76 "s8",
77 "ra",
78 };
79 #endif
80
81 #define TCG_TMP0 TCG_REG_AT
82 #define TCG_TMP1 TCG_REG_T9
83 #define TCG_TMP2 TCG_REG_T8
84 #define TCG_TMP3 TCG_REG_T7
85
86 #ifndef CONFIG_SOFTMMU
87 #define TCG_GUEST_BASE_REG TCG_REG_S1
88 #endif
89
90 /* check if we really need so many registers :P */
91 static const int tcg_target_reg_alloc_order[] = {
92 /* Call saved registers. */
93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
101 TCG_REG_S8,
102
103 /* Call clobbered registers. */
104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
110 TCG_REG_V1,
111 TCG_REG_V0,
112
113 /* Argument registers, opposite order of allocation. */
114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
122 };
123
124 static const TCGReg tcg_target_call_iarg_regs[] = {
125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
128 TCG_REG_A3,
129 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134 #endif
135 };
136
137 static const TCGReg tcg_target_call_oarg_regs[2] = {
138 TCG_REG_V0,
139 TCG_REG_V1
140 };
141
142 static tcg_insn_unit *tb_ret_addr;
143 static tcg_insn_unit *bswap32_addr;
144 static tcg_insn_unit *bswap32u_addr;
145 static tcg_insn_unit *bswap64_addr;
146
147 static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
148 {
149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 ptrdiff_t disp = target - (pc + 1);
151 tcg_debug_assert(disp == (int16_t)disp);
152 return disp & 0xffff;
153 }
154
155 static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
156 {
157 *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
158 }
159
160 static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
161 {
162 tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
163 return ((uintptr_t)target >> 2) & 0x3ffffff;
164 }
165
166 static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
167 {
168 *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
169 }
170
171 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
172 intptr_t value, intptr_t addend)
173 {
174 tcg_debug_assert(type == R_MIPS_PC16);
175 tcg_debug_assert(addend == 0);
176 reloc_pc16(code_ptr, (tcg_insn_unit *)value);
177 return true;
178 }
179
180 #define TCG_CT_CONST_ZERO 0x100
181 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
182 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
183 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
184 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
185 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
186
187 static inline bool is_p2m1(tcg_target_long val)
188 {
189 return val && ((val + 1) & val) == 0;
190 }
191
192 /* parse target specific constraints */
193 static const char *target_parse_constraint(TCGArgConstraint *ct,
194 const char *ct_str, TCGType type)
195 {
196 switch(*ct_str++) {
197 case 'r':
198 ct->ct |= TCG_CT_REG;
199 ct->u.regs = 0xffffffff;
200 break;
201 case 'L': /* qemu_ld input arg constraint */
202 ct->ct |= TCG_CT_REG;
203 ct->u.regs = 0xffffffff;
204 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
205 #if defined(CONFIG_SOFTMMU)
206 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
207 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
208 }
209 #endif
210 break;
211 case 'S': /* qemu_st constraint */
212 ct->ct |= TCG_CT_REG;
213 ct->u.regs = 0xffffffff;
214 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
215 #if defined(CONFIG_SOFTMMU)
216 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
217 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
218 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
219 } else {
220 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
221 }
222 #endif
223 break;
224 case 'I':
225 ct->ct |= TCG_CT_CONST_U16;
226 break;
227 case 'J':
228 ct->ct |= TCG_CT_CONST_S16;
229 break;
230 case 'K':
231 ct->ct |= TCG_CT_CONST_P2M1;
232 break;
233 case 'N':
234 ct->ct |= TCG_CT_CONST_N16;
235 break;
236 case 'W':
237 ct->ct |= TCG_CT_CONST_WSZ;
238 break;
239 case 'Z':
240 /* We are cheating a bit here, using the fact that the register
241 ZERO is also the register number 0. Hence there is no need
242 to check for const_args in each instruction. */
243 ct->ct |= TCG_CT_CONST_ZERO;
244 break;
245 default:
246 return NULL;
247 }
248 return ct_str;
249 }
250
251 /* test if a constant matches the constraint */
252 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
253 const TCGArgConstraint *arg_ct)
254 {
255 int ct;
256 ct = arg_ct->ct;
257 if (ct & TCG_CT_CONST) {
258 return 1;
259 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
260 return 1;
261 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
262 return 1;
263 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
264 return 1;
265 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
266 return 1;
267 } else if ((ct & TCG_CT_CONST_P2M1)
268 && use_mips32r2_instructions && is_p2m1(val)) {
269 return 1;
270 } else if ((ct & TCG_CT_CONST_WSZ)
271 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
272 return 1;
273 }
274 return 0;
275 }
276
277 /* instruction opcodes */
278 typedef enum {
279 OPC_J = 002 << 26,
280 OPC_JAL = 003 << 26,
281 OPC_BEQ = 004 << 26,
282 OPC_BNE = 005 << 26,
283 OPC_BLEZ = 006 << 26,
284 OPC_BGTZ = 007 << 26,
285 OPC_ADDIU = 011 << 26,
286 OPC_SLTI = 012 << 26,
287 OPC_SLTIU = 013 << 26,
288 OPC_ANDI = 014 << 26,
289 OPC_ORI = 015 << 26,
290 OPC_XORI = 016 << 26,
291 OPC_LUI = 017 << 26,
292 OPC_DADDIU = 031 << 26,
293 OPC_LB = 040 << 26,
294 OPC_LH = 041 << 26,
295 OPC_LW = 043 << 26,
296 OPC_LBU = 044 << 26,
297 OPC_LHU = 045 << 26,
298 OPC_LWU = 047 << 26,
299 OPC_SB = 050 << 26,
300 OPC_SH = 051 << 26,
301 OPC_SW = 053 << 26,
302 OPC_LD = 067 << 26,
303 OPC_SD = 077 << 26,
304
305 OPC_SPECIAL = 000 << 26,
306 OPC_SLL = OPC_SPECIAL | 000,
307 OPC_SRL = OPC_SPECIAL | 002,
308 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
309 OPC_SRA = OPC_SPECIAL | 003,
310 OPC_SLLV = OPC_SPECIAL | 004,
311 OPC_SRLV = OPC_SPECIAL | 006,
312 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
313 OPC_SRAV = OPC_SPECIAL | 007,
314 OPC_JR_R5 = OPC_SPECIAL | 010,
315 OPC_JALR = OPC_SPECIAL | 011,
316 OPC_MOVZ = OPC_SPECIAL | 012,
317 OPC_MOVN = OPC_SPECIAL | 013,
318 OPC_SYNC = OPC_SPECIAL | 017,
319 OPC_MFHI = OPC_SPECIAL | 020,
320 OPC_MFLO = OPC_SPECIAL | 022,
321 OPC_DSLLV = OPC_SPECIAL | 024,
322 OPC_DSRLV = OPC_SPECIAL | 026,
323 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
324 OPC_DSRAV = OPC_SPECIAL | 027,
325 OPC_MULT = OPC_SPECIAL | 030,
326 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
327 OPC_MUH = OPC_SPECIAL | 030 | 0300,
328 OPC_MULTU = OPC_SPECIAL | 031,
329 OPC_MULU = OPC_SPECIAL | 031 | 0200,
330 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
331 OPC_DIV = OPC_SPECIAL | 032,
332 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
333 OPC_MOD = OPC_SPECIAL | 032 | 0300,
334 OPC_DIVU = OPC_SPECIAL | 033,
335 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
336 OPC_MODU = OPC_SPECIAL | 033 | 0300,
337 OPC_DMULT = OPC_SPECIAL | 034,
338 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
339 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
340 OPC_DMULTU = OPC_SPECIAL | 035,
341 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
342 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
343 OPC_DDIV = OPC_SPECIAL | 036,
344 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
345 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
346 OPC_DDIVU = OPC_SPECIAL | 037,
347 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
348 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
349 OPC_ADDU = OPC_SPECIAL | 041,
350 OPC_SUBU = OPC_SPECIAL | 043,
351 OPC_AND = OPC_SPECIAL | 044,
352 OPC_OR = OPC_SPECIAL | 045,
353 OPC_XOR = OPC_SPECIAL | 046,
354 OPC_NOR = OPC_SPECIAL | 047,
355 OPC_SLT = OPC_SPECIAL | 052,
356 OPC_SLTU = OPC_SPECIAL | 053,
357 OPC_DADDU = OPC_SPECIAL | 055,
358 OPC_DSUBU = OPC_SPECIAL | 057,
359 OPC_SELEQZ = OPC_SPECIAL | 065,
360 OPC_SELNEZ = OPC_SPECIAL | 067,
361 OPC_DSLL = OPC_SPECIAL | 070,
362 OPC_DSRL = OPC_SPECIAL | 072,
363 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
364 OPC_DSRA = OPC_SPECIAL | 073,
365 OPC_DSLL32 = OPC_SPECIAL | 074,
366 OPC_DSRL32 = OPC_SPECIAL | 076,
367 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
368 OPC_DSRA32 = OPC_SPECIAL | 077,
369 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
370 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
371
372 OPC_REGIMM = 001 << 26,
373 OPC_BLTZ = OPC_REGIMM | (000 << 16),
374 OPC_BGEZ = OPC_REGIMM | (001 << 16),
375
376 OPC_SPECIAL2 = 034 << 26,
377 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
378 OPC_CLZ = OPC_SPECIAL2 | 040,
379 OPC_DCLZ = OPC_SPECIAL2 | 044,
380
381 OPC_SPECIAL3 = 037 << 26,
382 OPC_EXT = OPC_SPECIAL3 | 000,
383 OPC_DEXTM = OPC_SPECIAL3 | 001,
384 OPC_DEXTU = OPC_SPECIAL3 | 002,
385 OPC_DEXT = OPC_SPECIAL3 | 003,
386 OPC_INS = OPC_SPECIAL3 | 004,
387 OPC_DINSM = OPC_SPECIAL3 | 005,
388 OPC_DINSU = OPC_SPECIAL3 | 006,
389 OPC_DINS = OPC_SPECIAL3 | 007,
390 OPC_WSBH = OPC_SPECIAL3 | 00240,
391 OPC_DSBH = OPC_SPECIAL3 | 00244,
392 OPC_DSHD = OPC_SPECIAL3 | 00544,
393 OPC_SEB = OPC_SPECIAL3 | 02040,
394 OPC_SEH = OPC_SPECIAL3 | 03040,
395
396 /* MIPS r6 doesn't have JR, JALR should be used instead */
397 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
398
399 /*
400 * MIPS r6 replaces MUL with an alternative encoding which is
401 * backwards-compatible at the assembly level.
402 */
403 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
404
405 /* MIPS r6 introduced names for weaker variants of SYNC. These are
406 backward compatible to previous architecture revisions. */
407 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 5,
408 OPC_SYNC_MB = OPC_SYNC | 0x10 << 5,
409 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 5,
410 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 5,
411 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 5,
412
413 /* Aliases for convenience. */
414 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
415 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
416 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
417 ? OPC_SRL : OPC_DSRL,
418 } MIPSInsn;
419
420 /*
421 * Type reg
422 */
423 static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
424 TCGReg rd, TCGReg rs, TCGReg rt)
425 {
426 int32_t inst;
427
428 inst = opc;
429 inst |= (rs & 0x1F) << 21;
430 inst |= (rt & 0x1F) << 16;
431 inst |= (rd & 0x1F) << 11;
432 tcg_out32(s, inst);
433 }
434
435 /*
436 * Type immediate
437 */
438 static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
439 TCGReg rt, TCGReg rs, TCGArg imm)
440 {
441 int32_t inst;
442
443 inst = opc;
444 inst |= (rs & 0x1F) << 21;
445 inst |= (rt & 0x1F) << 16;
446 inst |= (imm & 0xffff);
447 tcg_out32(s, inst);
448 }
449
450 /*
451 * Type bitfield
452 */
453 static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
454 TCGReg rs, int msb, int lsb)
455 {
456 int32_t inst;
457
458 inst = opc;
459 inst |= (rs & 0x1F) << 21;
460 inst |= (rt & 0x1F) << 16;
461 inst |= (msb & 0x1F) << 11;
462 inst |= (lsb & 0x1F) << 6;
463 tcg_out32(s, inst);
464 }
465
466 static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
467 MIPSInsn oph, TCGReg rt, TCGReg rs,
468 int msb, int lsb)
469 {
470 if (lsb >= 32) {
471 opc = oph;
472 msb -= 32;
473 lsb -= 32;
474 } else if (msb >= 32) {
475 opc = opm;
476 msb -= 32;
477 }
478 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
479 }
480
481 /*
482 * Type branch
483 */
484 static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
485 TCGReg rt, TCGReg rs)
486 {
487 tcg_out_opc_imm(s, opc, rt, rs, 0);
488 }
489
490 /*
491 * Type sa
492 */
493 static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
494 TCGReg rd, TCGReg rt, TCGArg sa)
495 {
496 int32_t inst;
497
498 inst = opc;
499 inst |= (rt & 0x1F) << 16;
500 inst |= (rd & 0x1F) << 11;
501 inst |= (sa & 0x1F) << 6;
502 tcg_out32(s, inst);
503
504 }
505
506 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
507 TCGReg rd, TCGReg rt, TCGArg sa)
508 {
509 int32_t inst;
510
511 inst = (sa & 32 ? opc2 : opc1);
512 inst |= (rt & 0x1F) << 16;
513 inst |= (rd & 0x1F) << 11;
514 inst |= (sa & 0x1F) << 6;
515 tcg_out32(s, inst);
516 }
517
518 /*
519 * Type jump.
520 * Returns true if the branch was in range and the insn was emitted.
521 */
522 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
523 {
524 uintptr_t dest = (uintptr_t)target;
525 uintptr_t from = (uintptr_t)s->code_ptr + 4;
526 int32_t inst;
527
528 /* The pc-region branch happens within the 256MB region of
529 the delay slot (thus the +4). */
530 if ((from ^ dest) & -(1 << 28)) {
531 return false;
532 }
533 tcg_debug_assert((dest & 3) == 0);
534
535 inst = opc;
536 inst |= (dest >> 2) & 0x3ffffff;
537 tcg_out32(s, inst);
538 return true;
539 }
540
541 static inline void tcg_out_nop(TCGContext *s)
542 {
543 tcg_out32(s, 0);
544 }
545
546 static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
547 {
548 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
549 }
550
551 static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
552 {
553 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
554 }
555
556 static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
557 {
558 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
559 }
560
561 static inline void tcg_out_mov(TCGContext *s, TCGType type,
562 TCGReg ret, TCGReg arg)
563 {
564 /* Simple reg-reg move, optimising out the 'do nothing' case */
565 if (ret != arg) {
566 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
567 }
568 }
569
570 static void tcg_out_movi(TCGContext *s, TCGType type,
571 TCGReg ret, tcg_target_long arg)
572 {
573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
574 arg = (int32_t)arg;
575 }
576 if (arg == (int16_t)arg) {
577 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
578 return;
579 }
580 if (arg == (uint16_t)arg) {
581 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
582 return;
583 }
584 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
585 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
586 } else {
587 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
588 if (arg & 0xffff0000ull) {
589 tcg_out_dsll(s, ret, ret, 16);
590 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
591 tcg_out_dsll(s, ret, ret, 16);
592 } else {
593 tcg_out_dsll(s, ret, ret, 32);
594 }
595 }
596 if (arg & 0xffff) {
597 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
598 }
599 }
600
601 static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
602 {
603 if (use_mips32r2_instructions) {
604 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
605 } else {
606 /* ret and arg can't be register at */
607 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
608 tcg_abort();
609 }
610
611 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
612 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
613 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
614 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
615 }
616 }
617
618 static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
619 {
620 if (use_mips32r2_instructions) {
621 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
622 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
623 } else {
624 /* ret and arg can't be register at */
625 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
626 tcg_abort();
627 }
628
629 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
630 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
631 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
632 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
633 }
634 }
635
636 static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
637 {
638 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
639 tcg_debug_assert(ok);
640 }
641
642 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
643 {
644 if (use_mips32r2_instructions) {
645 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
646 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
647 } else {
648 tcg_out_bswap_subr(s, bswap32_addr);
649 /* delay slot -- never omit the insn, like tcg_out_mov might. */
650 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
651 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
652 }
653 }
654
655 static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
656 {
657 if (use_mips32r2_instructions) {
658 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
659 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
660 tcg_out_dsrl(s, ret, ret, 32);
661 } else {
662 tcg_out_bswap_subr(s, bswap32u_addr);
663 /* delay slot -- never omit the insn, like tcg_out_mov might. */
664 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
665 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
666 }
667 }
668
669 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
670 {
671 if (use_mips32r2_instructions) {
672 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
673 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
674 } else {
675 tcg_out_bswap_subr(s, bswap64_addr);
676 /* delay slot -- never omit the insn, like tcg_out_mov might. */
677 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
678 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
679 }
680 }
681
682 static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
683 {
684 if (use_mips32r2_instructions) {
685 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
686 } else {
687 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
688 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
689 }
690 }
691
692 static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
693 {
694 if (use_mips32r2_instructions) {
695 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
696 } else {
697 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
698 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
699 }
700 }
701
702 static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
703 {
704 if (use_mips32r2_instructions) {
705 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
706 } else {
707 tcg_out_dsll(s, ret, arg, 32);
708 tcg_out_dsrl(s, ret, ret, 32);
709 }
710 }
711
712 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
713 TCGReg addr, intptr_t ofs)
714 {
715 int16_t lo = ofs;
716 if (ofs != lo) {
717 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
718 if (addr != TCG_REG_ZERO) {
719 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
720 }
721 addr = TCG_TMP0;
722 }
723 tcg_out_opc_imm(s, opc, data, addr, lo);
724 }
725
726 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
727 TCGReg arg1, intptr_t arg2)
728 {
729 MIPSInsn opc = OPC_LD;
730 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
731 opc = OPC_LW;
732 }
733 tcg_out_ldst(s, opc, arg, arg1, arg2);
734 }
735
736 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
737 TCGReg arg1, intptr_t arg2)
738 {
739 MIPSInsn opc = OPC_SD;
740 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
741 opc = OPC_SW;
742 }
743 tcg_out_ldst(s, opc, arg, arg1, arg2);
744 }
745
746 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
747 TCGReg base, intptr_t ofs)
748 {
749 if (val == 0) {
750 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
751 return true;
752 }
753 return false;
754 }
755
756 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
757 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
758 bool cbh, bool is_sub)
759 {
760 TCGReg th = TCG_TMP1;
761
762 /* If we have a negative constant such that negating it would
763 make the high part zero, we can (usually) eliminate one insn. */
764 if (cbl && cbh && bh == -1 && bl != 0) {
765 bl = -bl;
766 bh = 0;
767 is_sub = !is_sub;
768 }
769
770 /* By operating on the high part first, we get to use the final
771 carry operation to move back from the temporary. */
772 if (!cbh) {
773 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
774 } else if (bh != 0 || ah == rl) {
775 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
776 } else {
777 th = ah;
778 }
779
780 /* Note that tcg optimization should eliminate the bl == 0 case. */
781 if (is_sub) {
782 if (cbl) {
783 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
784 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
785 } else {
786 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
787 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
788 }
789 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
790 } else {
791 if (cbl) {
792 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
793 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
794 } else if (rl == al && rl == bl) {
795 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
796 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
797 } else {
798 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
799 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
800 }
801 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
802 }
803 }
804
805 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
806 #define MIPS_CMP_INV 1
807 #define MIPS_CMP_SWAP 2
808
809 static const uint8_t mips_cmp_map[16] = {
810 [TCG_COND_LT] = 0,
811 [TCG_COND_LTU] = 0,
812 [TCG_COND_GE] = MIPS_CMP_INV,
813 [TCG_COND_GEU] = MIPS_CMP_INV,
814 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
815 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
816 [TCG_COND_GT] = MIPS_CMP_SWAP,
817 [TCG_COND_GTU] = MIPS_CMP_SWAP,
818 };
819
820 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
821 TCGReg arg1, TCGReg arg2)
822 {
823 MIPSInsn s_opc = OPC_SLTU;
824 int cmp_map;
825
826 switch (cond) {
827 case TCG_COND_EQ:
828 if (arg2 != 0) {
829 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
830 arg1 = ret;
831 }
832 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
833 break;
834
835 case TCG_COND_NE:
836 if (arg2 != 0) {
837 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
838 arg1 = ret;
839 }
840 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
841 break;
842
843 case TCG_COND_LT:
844 case TCG_COND_GE:
845 case TCG_COND_LE:
846 case TCG_COND_GT:
847 s_opc = OPC_SLT;
848 /* FALLTHRU */
849
850 case TCG_COND_LTU:
851 case TCG_COND_GEU:
852 case TCG_COND_LEU:
853 case TCG_COND_GTU:
854 cmp_map = mips_cmp_map[cond];
855 if (cmp_map & MIPS_CMP_SWAP) {
856 TCGReg t = arg1;
857 arg1 = arg2;
858 arg2 = t;
859 }
860 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
861 if (cmp_map & MIPS_CMP_INV) {
862 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
863 }
864 break;
865
866 default:
867 tcg_abort();
868 break;
869 }
870 }
871
872 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
873 TCGReg arg2, TCGLabel *l)
874 {
875 static const MIPSInsn b_zero[16] = {
876 [TCG_COND_LT] = OPC_BLTZ,
877 [TCG_COND_GT] = OPC_BGTZ,
878 [TCG_COND_LE] = OPC_BLEZ,
879 [TCG_COND_GE] = OPC_BGEZ,
880 };
881
882 MIPSInsn s_opc = OPC_SLTU;
883 MIPSInsn b_opc;
884 int cmp_map;
885
886 switch (cond) {
887 case TCG_COND_EQ:
888 b_opc = OPC_BEQ;
889 break;
890 case TCG_COND_NE:
891 b_opc = OPC_BNE;
892 break;
893
894 case TCG_COND_LT:
895 case TCG_COND_GT:
896 case TCG_COND_LE:
897 case TCG_COND_GE:
898 if (arg2 == 0) {
899 b_opc = b_zero[cond];
900 arg2 = arg1;
901 arg1 = 0;
902 break;
903 }
904 s_opc = OPC_SLT;
905 /* FALLTHRU */
906
907 case TCG_COND_LTU:
908 case TCG_COND_GTU:
909 case TCG_COND_LEU:
910 case TCG_COND_GEU:
911 cmp_map = mips_cmp_map[cond];
912 if (cmp_map & MIPS_CMP_SWAP) {
913 TCGReg t = arg1;
914 arg1 = arg2;
915 arg2 = t;
916 }
917 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
918 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
919 arg1 = TCG_TMP0;
920 arg2 = TCG_REG_ZERO;
921 break;
922
923 default:
924 tcg_abort();
925 break;
926 }
927
928 tcg_out_opc_br(s, b_opc, arg1, arg2);
929 if (l->has_value) {
930 reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
931 } else {
932 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
933 }
934 tcg_out_nop(s);
935 }
936
937 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
938 TCGReg al, TCGReg ah,
939 TCGReg bl, TCGReg bh)
940 {
941 /* Merge highpart comparison into AH. */
942 if (bh != 0) {
943 if (ah != 0) {
944 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
945 ah = tmp0;
946 } else {
947 ah = bh;
948 }
949 }
950 /* Merge lowpart comparison into AL. */
951 if (bl != 0) {
952 if (al != 0) {
953 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
954 al = tmp1;
955 } else {
956 al = bl;
957 }
958 }
959 /* Merge high and low part comparisons into AL. */
960 if (ah != 0) {
961 if (al != 0) {
962 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
963 al = tmp0;
964 } else {
965 al = ah;
966 }
967 }
968 return al;
969 }
970
971 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
972 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
973 {
974 TCGReg tmp0 = TCG_TMP0;
975 TCGReg tmp1 = ret;
976
977 tcg_debug_assert(ret != TCG_TMP0);
978 if (ret == ah || ret == bh) {
979 tcg_debug_assert(ret != TCG_TMP1);
980 tmp1 = TCG_TMP1;
981 }
982
983 switch (cond) {
984 case TCG_COND_EQ:
985 case TCG_COND_NE:
986 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
987 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
988 break;
989
990 default:
991 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
992 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
993 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
994 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
995 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
996 break;
997 }
998 }
999
1000 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
1001 TCGReg bl, TCGReg bh, TCGLabel *l)
1002 {
1003 TCGCond b_cond = TCG_COND_NE;
1004 TCGReg tmp = TCG_TMP1;
1005
1006 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
1007 With setcond, we emit between 3 and 10 insns and only 1 branch,
1008 which ought to get better branch prediction. */
1009 switch (cond) {
1010 case TCG_COND_EQ:
1011 case TCG_COND_NE:
1012 b_cond = cond;
1013 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
1014 break;
1015
1016 default:
1017 /* Minimize code size by preferring a compare not requiring INV. */
1018 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1019 cond = tcg_invert_cond(cond);
1020 b_cond = TCG_COND_EQ;
1021 }
1022 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1023 break;
1024 }
1025
1026 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
1027 }
1028
1029 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1030 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1031 {
1032 bool eqz = false;
1033
1034 /* If one of the values is zero, put it last to match SEL*Z instructions */
1035 if (use_mips32r6_instructions && v1 == 0) {
1036 v1 = v2;
1037 v2 = 0;
1038 cond = tcg_invert_cond(cond);
1039 }
1040
1041 switch (cond) {
1042 case TCG_COND_EQ:
1043 eqz = true;
1044 /* FALLTHRU */
1045 case TCG_COND_NE:
1046 if (c2 != 0) {
1047 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1048 c1 = TCG_TMP0;
1049 }
1050 break;
1051
1052 default:
1053 /* Minimize code size by preferring a compare not requiring INV. */
1054 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1055 cond = tcg_invert_cond(cond);
1056 eqz = true;
1057 }
1058 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1059 c1 = TCG_TMP0;
1060 break;
1061 }
1062
1063 if (use_mips32r6_instructions) {
1064 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1065 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1066
1067 if (v2 != 0) {
1068 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1069 }
1070 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1071 if (v2 != 0) {
1072 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1073 }
1074 } else {
1075 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1076
1077 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1078
1079 /* This should be guaranteed via constraints */
1080 tcg_debug_assert(v2 == ret);
1081 }
1082 }
1083
1084 static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
1085 {
1086 /* Note that the ABI requires the called function's address to be
1087 loaded into T9, even if a direct branch is in range. */
1088 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1089
1090 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1091 if (tail) {
1092 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1093 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1094 }
1095 } else {
1096 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1097 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1098 }
1099 }
1100 }
1101
1102 static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
1103 {
1104 tcg_out_call_int(s, arg, false);
1105 tcg_out_nop(s);
1106 }
1107
1108 #if defined(CONFIG_SOFTMMU)
1109 #include "tcg-ldst.inc.c"
1110
1111 static void * const qemu_ld_helpers[16] = {
1112 [MO_UB] = helper_ret_ldub_mmu,
1113 [MO_SB] = helper_ret_ldsb_mmu,
1114 [MO_LEUW] = helper_le_lduw_mmu,
1115 [MO_LESW] = helper_le_ldsw_mmu,
1116 [MO_LEUL] = helper_le_ldul_mmu,
1117 [MO_LEQ] = helper_le_ldq_mmu,
1118 [MO_BEUW] = helper_be_lduw_mmu,
1119 [MO_BESW] = helper_be_ldsw_mmu,
1120 [MO_BEUL] = helper_be_ldul_mmu,
1121 [MO_BEQ] = helper_be_ldq_mmu,
1122 #if TCG_TARGET_REG_BITS == 64
1123 [MO_LESL] = helper_le_ldsl_mmu,
1124 [MO_BESL] = helper_be_ldsl_mmu,
1125 #endif
1126 };
1127
1128 static void * const qemu_st_helpers[16] = {
1129 [MO_UB] = helper_ret_stb_mmu,
1130 [MO_LEUW] = helper_le_stw_mmu,
1131 [MO_LEUL] = helper_le_stl_mmu,
1132 [MO_LEQ] = helper_le_stq_mmu,
1133 [MO_BEUW] = helper_be_stw_mmu,
1134 [MO_BEUL] = helper_be_stl_mmu,
1135 [MO_BEQ] = helper_be_stq_mmu,
1136 };
1137
1138 /* Helper routines for marshalling helper function arguments into
1139 * the correct registers and stack.
1140 * I is where we want to put this argument, and is updated and returned
1141 * for the next call. ARG is the argument itself.
1142 *
1143 * We provide routines for arguments which are: immediate, 32 bit
1144 * value in register, 16 and 8 bit values in register (which must be zero
1145 * extended before use) and 64 bit value in a lo:hi register pair.
1146 */
1147
1148 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1149 {
1150 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1151 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1152 } else {
1153 /* For N32 and N64, the initial offset is different. But there
1154 we also have 8 argument register so we don't run out here. */
1155 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1156 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1157 }
1158 return i + 1;
1159 }
1160
1161 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1162 {
1163 TCGReg tmp = TCG_TMP0;
1164 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1165 tmp = tcg_target_call_iarg_regs[i];
1166 }
1167 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1168 return tcg_out_call_iarg_reg(s, i, tmp);
1169 }
1170
1171 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1172 {
1173 TCGReg tmp = TCG_TMP0;
1174 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1175 tmp = tcg_target_call_iarg_regs[i];
1176 }
1177 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1178 return tcg_out_call_iarg_reg(s, i, tmp);
1179 }
1180
1181 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1182 {
1183 TCGReg tmp = TCG_TMP0;
1184 if (arg == 0) {
1185 tmp = TCG_REG_ZERO;
1186 } else {
1187 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1188 tmp = tcg_target_call_iarg_regs[i];
1189 }
1190 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1191 }
1192 return tcg_out_call_iarg_reg(s, i, tmp);
1193 }
1194
1195 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1196 {
1197 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1198 i = (i + 1) & ~1;
1199 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1200 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1201 return i;
1202 }
1203
1204 /* Perform the tlb comparison operation. The complete host address is
1205 placed in BASE. Clobbers TMP0, TMP1, TMP2, A0. */
1206 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1207 TCGReg addrh, TCGMemOpIdx oi,
1208 tcg_insn_unit *label_ptr[2], bool is_load)
1209 {
1210 TCGMemOp opc = get_memop(oi);
1211 unsigned s_bits = opc & MO_SIZE;
1212 unsigned a_bits = get_alignment_bits(opc);
1213 target_ulong mask;
1214 int mem_index = get_mmuidx(oi);
1215 int cmp_off
1216 = (is_load
1217 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1218 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1219 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1220
1221 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_REG_A0, addrl,
1222 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1223 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0,
1224 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1225 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
1226
1227 /* Compensate for very large offsets. */
1228 while (add_off >= 0x8000) {
1229 /* Most target env are smaller than 32k, but a few are larger than 64k,
1230 * so handle an arbitrarily large offset.
1231 */
1232 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, TCG_REG_A0, 0x7ff0);
1233 cmp_off -= 0x7ff0;
1234 add_off -= 0x7ff0;
1235 }
1236
1237 /* We don't currently support unaligned accesses.
1238 We could do so with mips32r6. */
1239 if (a_bits < s_bits) {
1240 a_bits = s_bits;
1241 }
1242
1243 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1244
1245 /* Load the (low half) tlb comparator. Mask the page bits, keeping the
1246 alignment bits to compare against. */
1247 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1248 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
1249 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1250 } else {
1251 tcg_out_ldst(s,
1252 (TARGET_LONG_BITS == 64 ? OPC_LD
1253 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1254 TCG_TMP0, TCG_REG_A0, cmp_off);
1255 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1256 /* No second compare is required here;
1257 load the tlb addend for the fast path. */
1258 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_REG_A0, add_off);
1259 }
1260 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1261
1262 /* Zero extend a 32-bit guest address for a 64-bit host. */
1263 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1264 tcg_out_ext32u(s, base, addrl);
1265 addrl = base;
1266 }
1267
1268 label_ptr[0] = s->code_ptr;
1269 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1270
1271 /* Load and test the high half tlb comparator. */
1272 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1273 /* delay slot */
1274 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A0, cmp_off + HI_OFF);
1275
1276 /* Load the tlb addend for the fast path. */
1277 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_REG_A0, add_off);
1278
1279 label_ptr[1] = s->code_ptr;
1280 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1281 }
1282
1283 /* delay slot */
1284 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1285 }
1286
1287 static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1288 TCGType ext,
1289 TCGReg datalo, TCGReg datahi,
1290 TCGReg addrlo, TCGReg addrhi,
1291 void *raddr, tcg_insn_unit *label_ptr[2])
1292 {
1293 TCGLabelQemuLdst *label = new_ldst_label(s);
1294
1295 label->is_ld = is_ld;
1296 label->oi = oi;
1297 label->type = ext;
1298 label->datalo_reg = datalo;
1299 label->datahi_reg = datahi;
1300 label->addrlo_reg = addrlo;
1301 label->addrhi_reg = addrhi;
1302 label->raddr = raddr;
1303 label->label_ptr[0] = label_ptr[0];
1304 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1305 label->label_ptr[1] = label_ptr[1];
1306 }
1307 }
1308
1309 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1310 {
1311 TCGMemOpIdx oi = l->oi;
1312 TCGMemOp opc = get_memop(oi);
1313 TCGReg v0;
1314 int i;
1315
1316 /* resolve label address */
1317 reloc_pc16(l->label_ptr[0], s->code_ptr);
1318 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1319 reloc_pc16(l->label_ptr[1], s->code_ptr);
1320 }
1321
1322 i = 1;
1323 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1324 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1325 } else {
1326 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1327 }
1328 i = tcg_out_call_iarg_imm(s, i, oi);
1329 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1330 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1331 /* delay slot */
1332 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1333
1334 v0 = l->datalo_reg;
1335 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1336 /* We eliminated V0 from the possible output registers, so it
1337 cannot be clobbered here. So we must move V1 first. */
1338 if (MIPS_BE) {
1339 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1340 v0 = l->datahi_reg;
1341 } else {
1342 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1343 }
1344 }
1345
1346 reloc_pc16(s->code_ptr, l->raddr);
1347 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1348 /* delay slot */
1349 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1350 /* we always sign-extend 32-bit loads */
1351 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1352 } else {
1353 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1354 }
1355 }
1356
1357 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1358 {
1359 TCGMemOpIdx oi = l->oi;
1360 TCGMemOp opc = get_memop(oi);
1361 TCGMemOp s_bits = opc & MO_SIZE;
1362 int i;
1363
1364 /* resolve label address */
1365 reloc_pc16(l->label_ptr[0], s->code_ptr);
1366 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1367 reloc_pc16(l->label_ptr[1], s->code_ptr);
1368 }
1369
1370 i = 1;
1371 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1372 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1373 } else {
1374 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1375 }
1376 switch (s_bits) {
1377 case MO_8:
1378 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1379 break;
1380 case MO_16:
1381 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1382 break;
1383 case MO_32:
1384 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1385 break;
1386 case MO_64:
1387 if (TCG_TARGET_REG_BITS == 32) {
1388 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1389 } else {
1390 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1391 }
1392 break;
1393 default:
1394 tcg_abort();
1395 }
1396 i = tcg_out_call_iarg_imm(s, i, oi);
1397
1398 /* Tail call to the store helper. Thus force the return address
1399 computation to take place in the return address register. */
1400 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1401 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1402 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1403 /* delay slot */
1404 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1405 }
1406 #endif
1407
1408 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1409 TCGReg base, TCGMemOp opc, bool is_64)
1410 {
1411 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1412 case MO_UB:
1413 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1414 break;
1415 case MO_SB:
1416 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1417 break;
1418 case MO_UW | MO_BSWAP:
1419 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1420 tcg_out_bswap16(s, lo, TCG_TMP1);
1421 break;
1422 case MO_UW:
1423 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1424 break;
1425 case MO_SW | MO_BSWAP:
1426 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1427 tcg_out_bswap16s(s, lo, TCG_TMP1);
1428 break;
1429 case MO_SW:
1430 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1431 break;
1432 case MO_UL | MO_BSWAP:
1433 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1434 if (use_mips32r2_instructions) {
1435 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1436 tcg_out_bswap32u(s, lo, lo);
1437 } else {
1438 tcg_out_bswap_subr(s, bswap32u_addr);
1439 /* delay slot */
1440 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1441 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1442 }
1443 break;
1444 }
1445 /* FALLTHRU */
1446 case MO_SL | MO_BSWAP:
1447 if (use_mips32r2_instructions) {
1448 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1449 tcg_out_bswap32(s, lo, lo);
1450 } else {
1451 tcg_out_bswap_subr(s, bswap32_addr);
1452 /* delay slot */
1453 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1454 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1455 }
1456 break;
1457 case MO_UL:
1458 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1459 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1460 break;
1461 }
1462 /* FALLTHRU */
1463 case MO_SL:
1464 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1465 break;
1466 case MO_Q | MO_BSWAP:
1467 if (TCG_TARGET_REG_BITS == 64) {
1468 if (use_mips32r2_instructions) {
1469 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1470 tcg_out_bswap64(s, lo, lo);
1471 } else {
1472 tcg_out_bswap_subr(s, bswap64_addr);
1473 /* delay slot */
1474 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1475 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1476 }
1477 } else if (use_mips32r2_instructions) {
1478 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1479 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1480 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1481 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1482 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1483 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1484 } else {
1485 tcg_out_bswap_subr(s, bswap32_addr);
1486 /* delay slot */
1487 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1488 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1489 tcg_out_bswap_subr(s, bswap32_addr);
1490 /* delay slot */
1491 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1492 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1493 }
1494 break;
1495 case MO_Q:
1496 /* Prefer to load from offset 0 first, but allow for overlap. */
1497 if (TCG_TARGET_REG_BITS == 64) {
1498 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1499 } else if (MIPS_BE ? hi != base : lo == base) {
1500 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1501 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1502 } else {
1503 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1504 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1505 }
1506 break;
1507 default:
1508 tcg_abort();
1509 }
1510 }
1511
1512 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1513 {
1514 TCGReg addr_regl, addr_regh __attribute__((unused));
1515 TCGReg data_regl, data_regh;
1516 TCGMemOpIdx oi;
1517 TCGMemOp opc;
1518 #if defined(CONFIG_SOFTMMU)
1519 tcg_insn_unit *label_ptr[2];
1520 #endif
1521 TCGReg base = TCG_REG_A0;
1522
1523 data_regl = *args++;
1524 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1525 addr_regl = *args++;
1526 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1527 oi = *args++;
1528 opc = get_memop(oi);
1529
1530 #if defined(CONFIG_SOFTMMU)
1531 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1532 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1533 add_qemu_ldst_label(s, 1, oi,
1534 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1535 data_regl, data_regh, addr_regl, addr_regh,
1536 s->code_ptr, label_ptr);
1537 #else
1538 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1539 tcg_out_ext32u(s, base, addr_regl);
1540 addr_regl = base;
1541 }
1542 if (guest_base == 0 && data_regl != addr_regl) {
1543 base = addr_regl;
1544 } else if (guest_base == (int16_t)guest_base) {
1545 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1546 } else {
1547 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1548 }
1549 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1550 #endif
1551 }
1552
1553 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1554 TCGReg base, TCGMemOp opc)
1555 {
1556 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1557 if ((lo | hi) == 0) {
1558 opc &= ~MO_BSWAP;
1559 }
1560
1561 switch (opc & (MO_SIZE | MO_BSWAP)) {
1562 case MO_8:
1563 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1564 break;
1565
1566 case MO_16 | MO_BSWAP:
1567 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
1568 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
1569 lo = TCG_TMP1;
1570 /* FALLTHRU */
1571 case MO_16:
1572 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1573 break;
1574
1575 case MO_32 | MO_BSWAP:
1576 tcg_out_bswap32(s, TCG_TMP3, lo);
1577 lo = TCG_TMP3;
1578 /* FALLTHRU */
1579 case MO_32:
1580 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1581 break;
1582
1583 case MO_64 | MO_BSWAP:
1584 if (TCG_TARGET_REG_BITS == 64) {
1585 tcg_out_bswap64(s, TCG_TMP3, lo);
1586 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1587 } else if (use_mips32r2_instructions) {
1588 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1589 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1590 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1591 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1592 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1593 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1594 } else {
1595 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
1596 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1597 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
1598 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1599 }
1600 break;
1601 case MO_64:
1602 if (TCG_TARGET_REG_BITS == 64) {
1603 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1604 } else {
1605 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1606 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1607 }
1608 break;
1609
1610 default:
1611 tcg_abort();
1612 }
1613 }
1614
1615 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1616 {
1617 TCGReg addr_regl, addr_regh __attribute__((unused));
1618 TCGReg data_regl, data_regh;
1619 TCGMemOpIdx oi;
1620 TCGMemOp opc;
1621 #if defined(CONFIG_SOFTMMU)
1622 tcg_insn_unit *label_ptr[2];
1623 #endif
1624 TCGReg base = TCG_REG_A0;
1625
1626 data_regl = *args++;
1627 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1628 addr_regl = *args++;
1629 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1630 oi = *args++;
1631 opc = get_memop(oi);
1632
1633 #if defined(CONFIG_SOFTMMU)
1634 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1635 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1636 add_qemu_ldst_label(s, 0, oi,
1637 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1638 data_regl, data_regh, addr_regl, addr_regh,
1639 s->code_ptr, label_ptr);
1640 #else
1641 base = TCG_REG_A0;
1642 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1643 tcg_out_ext32u(s, base, addr_regl);
1644 addr_regl = base;
1645 }
1646 if (guest_base == 0) {
1647 base = addr_regl;
1648 } else if (guest_base == (int16_t)guest_base) {
1649 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1650 } else {
1651 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1652 }
1653 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1654 #endif
1655 }
1656
1657 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1658 {
1659 static const MIPSInsn sync[] = {
1660 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1661 as the former is an ordering barrier and the latter
1662 is a completion barrier. */
1663 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1664 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1665 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1666 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1667 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1668 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1669 };
1670 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1671 }
1672
1673 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1674 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1675 {
1676 if (use_mips32r6_instructions) {
1677 if (a2 == width) {
1678 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1679 } else {
1680 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1681 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1682 }
1683 } else {
1684 if (a2 == width) {
1685 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1686 } else if (a0 == a2) {
1687 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1688 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1689 } else if (a0 != a1) {
1690 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1691 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1692 } else {
1693 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1694 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1695 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1696 }
1697 }
1698 }
1699
1700 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1701 const TCGArg *args, const int *const_args)
1702 {
1703 MIPSInsn i1, i2;
1704 TCGArg a0, a1, a2;
1705 int c2;
1706
1707 a0 = args[0];
1708 a1 = args[1];
1709 a2 = args[2];
1710 c2 = const_args[2];
1711
1712 switch (opc) {
1713 case INDEX_op_exit_tb:
1714 {
1715 TCGReg b0 = TCG_REG_ZERO;
1716
1717 a0 = (intptr_t)a0;
1718 if (a0 & ~0xffff) {
1719 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1720 b0 = TCG_REG_V0;
1721 }
1722 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1723 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
1724 (uintptr_t)tb_ret_addr);
1725 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1726 }
1727 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1728 }
1729 break;
1730 case INDEX_op_goto_tb:
1731 if (s->tb_jmp_insn_offset) {
1732 /* direct jump method */
1733 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1734 /* Avoid clobbering the address during retranslation. */
1735 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
1736 } else {
1737 /* indirect jump method */
1738 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1739 (uintptr_t)(s->tb_jmp_target_addr + a0));
1740 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1741 }
1742 tcg_out_nop(s);
1743 set_jmp_reset_offset(s, a0);
1744 break;
1745 case INDEX_op_goto_ptr:
1746 /* jmp to the given host address (could be epilogue) */
1747 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1748 tcg_out_nop(s);
1749 break;
1750 case INDEX_op_br:
1751 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1752 arg_label(a0));
1753 break;
1754
1755 case INDEX_op_ld8u_i32:
1756 case INDEX_op_ld8u_i64:
1757 i1 = OPC_LBU;
1758 goto do_ldst;
1759 case INDEX_op_ld8s_i32:
1760 case INDEX_op_ld8s_i64:
1761 i1 = OPC_LB;
1762 goto do_ldst;
1763 case INDEX_op_ld16u_i32:
1764 case INDEX_op_ld16u_i64:
1765 i1 = OPC_LHU;
1766 goto do_ldst;
1767 case INDEX_op_ld16s_i32:
1768 case INDEX_op_ld16s_i64:
1769 i1 = OPC_LH;
1770 goto do_ldst;
1771 case INDEX_op_ld_i32:
1772 case INDEX_op_ld32s_i64:
1773 i1 = OPC_LW;
1774 goto do_ldst;
1775 case INDEX_op_ld32u_i64:
1776 i1 = OPC_LWU;
1777 goto do_ldst;
1778 case INDEX_op_ld_i64:
1779 i1 = OPC_LD;
1780 goto do_ldst;
1781 case INDEX_op_st8_i32:
1782 case INDEX_op_st8_i64:
1783 i1 = OPC_SB;
1784 goto do_ldst;
1785 case INDEX_op_st16_i32:
1786 case INDEX_op_st16_i64:
1787 i1 = OPC_SH;
1788 goto do_ldst;
1789 case INDEX_op_st_i32:
1790 case INDEX_op_st32_i64:
1791 i1 = OPC_SW;
1792 goto do_ldst;
1793 case INDEX_op_st_i64:
1794 i1 = OPC_SD;
1795 do_ldst:
1796 tcg_out_ldst(s, i1, a0, a1, a2);
1797 break;
1798
1799 case INDEX_op_add_i32:
1800 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1801 goto do_binary;
1802 case INDEX_op_add_i64:
1803 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1804 goto do_binary;
1805 case INDEX_op_or_i32:
1806 case INDEX_op_or_i64:
1807 i1 = OPC_OR, i2 = OPC_ORI;
1808 goto do_binary;
1809 case INDEX_op_xor_i32:
1810 case INDEX_op_xor_i64:
1811 i1 = OPC_XOR, i2 = OPC_XORI;
1812 do_binary:
1813 if (c2) {
1814 tcg_out_opc_imm(s, i2, a0, a1, a2);
1815 break;
1816 }
1817 do_binaryv:
1818 tcg_out_opc_reg(s, i1, a0, a1, a2);
1819 break;
1820
1821 case INDEX_op_sub_i32:
1822 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1823 goto do_subtract;
1824 case INDEX_op_sub_i64:
1825 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1826 do_subtract:
1827 if (c2) {
1828 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1829 break;
1830 }
1831 goto do_binaryv;
1832 case INDEX_op_and_i32:
1833 if (c2 && a2 != (uint16_t)a2) {
1834 int msb = ctz32(~a2) - 1;
1835 tcg_debug_assert(use_mips32r2_instructions);
1836 tcg_debug_assert(is_p2m1(a2));
1837 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1838 break;
1839 }
1840 i1 = OPC_AND, i2 = OPC_ANDI;
1841 goto do_binary;
1842 case INDEX_op_and_i64:
1843 if (c2 && a2 != (uint16_t)a2) {
1844 int msb = ctz64(~a2) - 1;
1845 tcg_debug_assert(use_mips32r2_instructions);
1846 tcg_debug_assert(is_p2m1(a2));
1847 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1848 break;
1849 }
1850 i1 = OPC_AND, i2 = OPC_ANDI;
1851 goto do_binary;
1852 case INDEX_op_nor_i32:
1853 case INDEX_op_nor_i64:
1854 i1 = OPC_NOR;
1855 goto do_binaryv;
1856
1857 case INDEX_op_mul_i32:
1858 if (use_mips32_instructions) {
1859 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1860 break;
1861 }
1862 i1 = OPC_MULT, i2 = OPC_MFLO;
1863 goto do_hilo1;
1864 case INDEX_op_mulsh_i32:
1865 if (use_mips32r6_instructions) {
1866 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1867 break;
1868 }
1869 i1 = OPC_MULT, i2 = OPC_MFHI;
1870 goto do_hilo1;
1871 case INDEX_op_muluh_i32:
1872 if (use_mips32r6_instructions) {
1873 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1874 break;
1875 }
1876 i1 = OPC_MULTU, i2 = OPC_MFHI;
1877 goto do_hilo1;
1878 case INDEX_op_div_i32:
1879 if (use_mips32r6_instructions) {
1880 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1881 break;
1882 }
1883 i1 = OPC_DIV, i2 = OPC_MFLO;
1884 goto do_hilo1;
1885 case INDEX_op_divu_i32:
1886 if (use_mips32r6_instructions) {
1887 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1888 break;
1889 }
1890 i1 = OPC_DIVU, i2 = OPC_MFLO;
1891 goto do_hilo1;
1892 case INDEX_op_rem_i32:
1893 if (use_mips32r6_instructions) {
1894 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1895 break;
1896 }
1897 i1 = OPC_DIV, i2 = OPC_MFHI;
1898 goto do_hilo1;
1899 case INDEX_op_remu_i32:
1900 if (use_mips32r6_instructions) {
1901 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1902 break;
1903 }
1904 i1 = OPC_DIVU, i2 = OPC_MFHI;
1905 goto do_hilo1;
1906 case INDEX_op_mul_i64:
1907 if (use_mips32r6_instructions) {
1908 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1909 break;
1910 }
1911 i1 = OPC_DMULT, i2 = OPC_MFLO;
1912 goto do_hilo1;
1913 case INDEX_op_mulsh_i64:
1914 if (use_mips32r6_instructions) {
1915 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1916 break;
1917 }
1918 i1 = OPC_DMULT, i2 = OPC_MFHI;
1919 goto do_hilo1;
1920 case INDEX_op_muluh_i64:
1921 if (use_mips32r6_instructions) {
1922 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1923 break;
1924 }
1925 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1926 goto do_hilo1;
1927 case INDEX_op_div_i64:
1928 if (use_mips32r6_instructions) {
1929 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1930 break;
1931 }
1932 i1 = OPC_DDIV, i2 = OPC_MFLO;
1933 goto do_hilo1;
1934 case INDEX_op_divu_i64:
1935 if (use_mips32r6_instructions) {
1936 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1937 break;
1938 }
1939 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1940 goto do_hilo1;
1941 case INDEX_op_rem_i64:
1942 if (use_mips32r6_instructions) {
1943 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1944 break;
1945 }
1946 i1 = OPC_DDIV, i2 = OPC_MFHI;
1947 goto do_hilo1;
1948 case INDEX_op_remu_i64:
1949 if (use_mips32r6_instructions) {
1950 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1951 break;
1952 }
1953 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1954 do_hilo1:
1955 tcg_out_opc_reg(s, i1, 0, a1, a2);
1956 tcg_out_opc_reg(s, i2, a0, 0, 0);
1957 break;
1958
1959 case INDEX_op_muls2_i32:
1960 i1 = OPC_MULT;
1961 goto do_hilo2;
1962 case INDEX_op_mulu2_i32:
1963 i1 = OPC_MULTU;
1964 goto do_hilo2;
1965 case INDEX_op_muls2_i64:
1966 i1 = OPC_DMULT;
1967 goto do_hilo2;
1968 case INDEX_op_mulu2_i64:
1969 i1 = OPC_DMULTU;
1970 do_hilo2:
1971 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1972 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1973 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1974 break;
1975
1976 case INDEX_op_not_i32:
1977 case INDEX_op_not_i64:
1978 i1 = OPC_NOR;
1979 goto do_unary;
1980 case INDEX_op_bswap16_i32:
1981 case INDEX_op_bswap16_i64:
1982 i1 = OPC_WSBH;
1983 goto do_unary;
1984 case INDEX_op_ext8s_i32:
1985 case INDEX_op_ext8s_i64:
1986 i1 = OPC_SEB;
1987 goto do_unary;
1988 case INDEX_op_ext16s_i32:
1989 case INDEX_op_ext16s_i64:
1990 i1 = OPC_SEH;
1991 do_unary:
1992 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1993 break;
1994
1995 case INDEX_op_bswap32_i32:
1996 tcg_out_bswap32(s, a0, a1);
1997 break;
1998 case INDEX_op_bswap32_i64:
1999 tcg_out_bswap32u(s, a0, a1);
2000 break;
2001 case INDEX_op_bswap64_i64:
2002 tcg_out_bswap64(s, a0, a1);
2003 break;
2004 case INDEX_op_extrh_i64_i32:
2005 tcg_out_dsra(s, a0, a1, 32);
2006 break;
2007 case INDEX_op_ext32s_i64:
2008 case INDEX_op_ext_i32_i64:
2009 case INDEX_op_extrl_i64_i32:
2010 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2011 break;
2012 case INDEX_op_ext32u_i64:
2013 case INDEX_op_extu_i32_i64:
2014 tcg_out_ext32u(s, a0, a1);
2015 break;
2016
2017 case INDEX_op_sar_i32:
2018 i1 = OPC_SRAV, i2 = OPC_SRA;
2019 goto do_shift;
2020 case INDEX_op_shl_i32:
2021 i1 = OPC_SLLV, i2 = OPC_SLL;
2022 goto do_shift;
2023 case INDEX_op_shr_i32:
2024 i1 = OPC_SRLV, i2 = OPC_SRL;
2025 goto do_shift;
2026 case INDEX_op_rotr_i32:
2027 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2028 do_shift:
2029 if (c2) {
2030 tcg_out_opc_sa(s, i2, a0, a1, a2);
2031 break;
2032 }
2033 do_shiftv:
2034 tcg_out_opc_reg(s, i1, a0, a2, a1);
2035 break;
2036 case INDEX_op_rotl_i32:
2037 if (c2) {
2038 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2039 } else {
2040 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2041 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2042 }
2043 break;
2044 case INDEX_op_sar_i64:
2045 if (c2) {
2046 tcg_out_dsra(s, a0, a1, a2);
2047 break;
2048 }
2049 i1 = OPC_DSRAV;
2050 goto do_shiftv;
2051 case INDEX_op_shl_i64:
2052 if (c2) {
2053 tcg_out_dsll(s, a0, a1, a2);
2054 break;
2055 }
2056 i1 = OPC_DSLLV;
2057 goto do_shiftv;
2058 case INDEX_op_shr_i64:
2059 if (c2) {
2060 tcg_out_dsrl(s, a0, a1, a2);
2061 break;
2062 }
2063 i1 = OPC_DSRLV;
2064 goto do_shiftv;
2065 case INDEX_op_rotr_i64:
2066 if (c2) {
2067 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2068 break;
2069 }
2070 i1 = OPC_DROTRV;
2071 goto do_shiftv;
2072 case INDEX_op_rotl_i64:
2073 if (c2) {
2074 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2075 } else {
2076 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2077 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2078 }
2079 break;
2080
2081 case INDEX_op_clz_i32:
2082 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2083 break;
2084 case INDEX_op_clz_i64:
2085 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2086 break;
2087
2088 case INDEX_op_deposit_i32:
2089 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2090 break;
2091 case INDEX_op_deposit_i64:
2092 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2093 args[3] + args[4] - 1, args[3]);
2094 break;
2095 case INDEX_op_extract_i32:
2096 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2097 break;
2098 case INDEX_op_extract_i64:
2099 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2100 args[3] - 1, a2);
2101 break;
2102
2103 case INDEX_op_brcond_i32:
2104 case INDEX_op_brcond_i64:
2105 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2106 break;
2107 case INDEX_op_brcond2_i32:
2108 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2109 break;
2110
2111 case INDEX_op_movcond_i32:
2112 case INDEX_op_movcond_i64:
2113 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2114 break;
2115
2116 case INDEX_op_setcond_i32:
2117 case INDEX_op_setcond_i64:
2118 tcg_out_setcond(s, args[3], a0, a1, a2);
2119 break;
2120 case INDEX_op_setcond2_i32:
2121 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2122 break;
2123
2124 case INDEX_op_qemu_ld_i32:
2125 tcg_out_qemu_ld(s, args, false);
2126 break;
2127 case INDEX_op_qemu_ld_i64:
2128 tcg_out_qemu_ld(s, args, true);
2129 break;
2130 case INDEX_op_qemu_st_i32:
2131 tcg_out_qemu_st(s, args, false);
2132 break;
2133 case INDEX_op_qemu_st_i64:
2134 tcg_out_qemu_st(s, args, true);
2135 break;
2136
2137 case INDEX_op_add2_i32:
2138 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2139 const_args[4], const_args[5], false);
2140 break;
2141 case INDEX_op_sub2_i32:
2142 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2143 const_args[4], const_args[5], true);
2144 break;
2145
2146 case INDEX_op_mb:
2147 tcg_out_mb(s, a0);
2148 break;
2149 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2150 case INDEX_op_mov_i64:
2151 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2152 case INDEX_op_movi_i64:
2153 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2154 default:
2155 tcg_abort();
2156 }
2157 }
2158
2159 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2160 {
2161 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2162 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2163 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2164 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
2165 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
2166 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
2167 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
2168 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2169 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2170 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2171 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
2172 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
2173 static const TCGTargetOpDef SZ_SZ_S
2174 = { .args_ct_str = { "SZ", "SZ", "S" } };
2175 static const TCGTargetOpDef SZ_SZ_S_S
2176 = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
2177 static const TCGTargetOpDef r_rZ_rN
2178 = { .args_ct_str = { "r", "rZ", "rN" } };
2179 static const TCGTargetOpDef r_rZ_rZ
2180 = { .args_ct_str = { "r", "rZ", "rZ" } };
2181 static const TCGTargetOpDef r_r_rIK
2182 = { .args_ct_str = { "r", "r", "rIK" } };
2183 static const TCGTargetOpDef r_r_rWZ
2184 = { .args_ct_str = { "r", "r", "rWZ" } };
2185 static const TCGTargetOpDef r_r_r_r
2186 = { .args_ct_str = { "r", "r", "r", "r" } };
2187 static const TCGTargetOpDef r_r_L_L
2188 = { .args_ct_str = { "r", "r", "L", "L" } };
2189 static const TCGTargetOpDef dep
2190 = { .args_ct_str = { "r", "0", "rZ" } };
2191 static const TCGTargetOpDef movc
2192 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
2193 static const TCGTargetOpDef movc_r6
2194 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2195 static const TCGTargetOpDef add2
2196 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
2197 static const TCGTargetOpDef br2
2198 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
2199 static const TCGTargetOpDef setc2
2200 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2201
2202 switch (op) {
2203 case INDEX_op_goto_ptr:
2204 return &r;
2205
2206 case INDEX_op_ld8u_i32:
2207 case INDEX_op_ld8s_i32:
2208 case INDEX_op_ld16u_i32:
2209 case INDEX_op_ld16s_i32:
2210 case INDEX_op_ld_i32:
2211 case INDEX_op_not_i32:
2212 case INDEX_op_bswap16_i32:
2213 case INDEX_op_bswap32_i32:
2214 case INDEX_op_ext8s_i32:
2215 case INDEX_op_ext16s_i32:
2216 case INDEX_op_extract_i32:
2217 case INDEX_op_ld8u_i64:
2218 case INDEX_op_ld8s_i64:
2219 case INDEX_op_ld16u_i64:
2220 case INDEX_op_ld16s_i64:
2221 case INDEX_op_ld32s_i64:
2222 case INDEX_op_ld32u_i64:
2223 case INDEX_op_ld_i64:
2224 case INDEX_op_not_i64:
2225 case INDEX_op_bswap16_i64:
2226 case INDEX_op_bswap32_i64:
2227 case INDEX_op_bswap64_i64:
2228 case INDEX_op_ext8s_i64:
2229 case INDEX_op_ext16s_i64:
2230 case INDEX_op_ext32s_i64:
2231 case INDEX_op_ext32u_i64:
2232 case INDEX_op_ext_i32_i64:
2233 case INDEX_op_extu_i32_i64:
2234 case INDEX_op_extrl_i64_i32:
2235 case INDEX_op_extrh_i64_i32:
2236 case INDEX_op_extract_i64:
2237 return &r_r;
2238
2239 case INDEX_op_st8_i32:
2240 case INDEX_op_st16_i32:
2241 case INDEX_op_st_i32:
2242 case INDEX_op_st8_i64:
2243 case INDEX_op_st16_i64:
2244 case INDEX_op_st32_i64:
2245 case INDEX_op_st_i64:
2246 return &rZ_r;
2247
2248 case INDEX_op_add_i32:
2249 case INDEX_op_add_i64:
2250 return &r_r_rJ;
2251 case INDEX_op_sub_i32:
2252 case INDEX_op_sub_i64:
2253 return &r_rZ_rN;
2254 case INDEX_op_mul_i32:
2255 case INDEX_op_mulsh_i32:
2256 case INDEX_op_muluh_i32:
2257 case INDEX_op_div_i32:
2258 case INDEX_op_divu_i32:
2259 case INDEX_op_rem_i32:
2260 case INDEX_op_remu_i32:
2261 case INDEX_op_nor_i32:
2262 case INDEX_op_setcond_i32:
2263 case INDEX_op_mul_i64:
2264 case INDEX_op_mulsh_i64:
2265 case INDEX_op_muluh_i64:
2266 case INDEX_op_div_i64:
2267 case INDEX_op_divu_i64:
2268 case INDEX_op_rem_i64:
2269 case INDEX_op_remu_i64:
2270 case INDEX_op_nor_i64:
2271 case INDEX_op_setcond_i64:
2272 return &r_rZ_rZ;
2273 case INDEX_op_muls2_i32:
2274 case INDEX_op_mulu2_i32:
2275 case INDEX_op_muls2_i64:
2276 case INDEX_op_mulu2_i64:
2277 return &r_r_r_r;
2278 case INDEX_op_and_i32:
2279 case INDEX_op_and_i64:
2280 return &r_r_rIK;
2281 case INDEX_op_or_i32:
2282 case INDEX_op_xor_i32:
2283 case INDEX_op_or_i64:
2284 case INDEX_op_xor_i64:
2285 return &r_r_rI;
2286 case INDEX_op_shl_i32:
2287 case INDEX_op_shr_i32:
2288 case INDEX_op_sar_i32:
2289 case INDEX_op_rotr_i32:
2290 case INDEX_op_rotl_i32:
2291 case INDEX_op_shl_i64:
2292 case INDEX_op_shr_i64:
2293 case INDEX_op_sar_i64:
2294 case INDEX_op_rotr_i64:
2295 case INDEX_op_rotl_i64:
2296 return &r_r_ri;
2297 case INDEX_op_clz_i32:
2298 case INDEX_op_clz_i64:
2299 return &r_r_rWZ;
2300
2301 case INDEX_op_deposit_i32:
2302 case INDEX_op_deposit_i64:
2303 return &dep;
2304 case INDEX_op_brcond_i32:
2305 case INDEX_op_brcond_i64:
2306 return &rZ_rZ;
2307 case INDEX_op_movcond_i32:
2308 case INDEX_op_movcond_i64:
2309 return use_mips32r6_instructions ? &movc_r6 : &movc;
2310
2311 case INDEX_op_add2_i32:
2312 case INDEX_op_sub2_i32:
2313 return &add2;
2314 case INDEX_op_setcond2_i32:
2315 return &setc2;
2316 case INDEX_op_brcond2_i32:
2317 return &br2;
2318
2319 case INDEX_op_qemu_ld_i32:
2320 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2321 ? &r_L : &r_L_L);
2322 case INDEX_op_qemu_st_i32:
2323 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2324 ? &SZ_S : &SZ_S_S);
2325 case INDEX_op_qemu_ld_i64:
2326 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2327 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
2328 case INDEX_op_qemu_st_i64:
2329 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
2330 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
2331
2332 default:
2333 return NULL;
2334 }
2335 }
2336
2337 static const int tcg_target_callee_save_regs[] = {
2338 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2339 TCG_REG_S1,
2340 TCG_REG_S2,
2341 TCG_REG_S3,
2342 TCG_REG_S4,
2343 TCG_REG_S5,
2344 TCG_REG_S6,
2345 TCG_REG_S7,
2346 TCG_REG_S8,
2347 TCG_REG_RA, /* should be last for ABI compliance */
2348 };
2349
2350 /* The Linux kernel doesn't provide any information about the available
2351 instruction set. Probe it using a signal handler. */
2352
2353
2354 #ifndef use_movnz_instructions
2355 bool use_movnz_instructions = false;
2356 #endif
2357
2358 #ifndef use_mips32_instructions
2359 bool use_mips32_instructions = false;
2360 #endif
2361
2362 #ifndef use_mips32r2_instructions
2363 bool use_mips32r2_instructions = false;
2364 #endif
2365
2366 static volatile sig_atomic_t got_sigill;
2367
2368 static void sigill_handler(int signo, siginfo_t *si, void *data)
2369 {
2370 /* Skip the faulty instruction */
2371 ucontext_t *uc = (ucontext_t *)data;
2372 uc->uc_mcontext.pc += 4;
2373
2374 got_sigill = 1;
2375 }
2376
2377 static void tcg_target_detect_isa(void)
2378 {
2379 struct sigaction sa_old, sa_new;
2380
2381 memset(&sa_new, 0, sizeof(sa_new));
2382 sa_new.sa_flags = SA_SIGINFO;
2383 sa_new.sa_sigaction = sigill_handler;
2384 sigaction(SIGILL, &sa_new, &sa_old);
2385
2386 /* Probe for movn/movz, necessary to implement movcond. */
2387 #ifndef use_movnz_instructions
2388 got_sigill = 0;
2389 asm volatile(".set push\n"
2390 ".set mips32\n"
2391 "movn $zero, $zero, $zero\n"
2392 "movz $zero, $zero, $zero\n"
2393 ".set pop\n"
2394 : : : );
2395 use_movnz_instructions = !got_sigill;
2396 #endif
2397
2398 /* Probe for MIPS32 instructions. As no subsetting is allowed
2399 by the specification, it is only necessary to probe for one
2400 of the instructions. */
2401 #ifndef use_mips32_instructions
2402 got_sigill = 0;
2403 asm volatile(".set push\n"
2404 ".set mips32\n"
2405 "mul $zero, $zero\n"
2406 ".set pop\n"
2407 : : : );
2408 use_mips32_instructions = !got_sigill;
2409 #endif
2410
2411 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2412 available. As no subsetting is allowed by the specification,
2413 it is only necessary to probe for one of the instructions. */
2414 #ifndef use_mips32r2_instructions
2415 if (use_mips32_instructions) {
2416 got_sigill = 0;
2417 asm volatile(".set push\n"
2418 ".set mips32r2\n"
2419 "seb $zero, $zero\n"
2420 ".set pop\n"
2421 : : : );
2422 use_mips32r2_instructions = !got_sigill;
2423 }
2424 #endif
2425
2426 sigaction(SIGILL, &sa_old, NULL);
2427 }
2428
2429 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2430 {
2431 uintptr_t p = (uintptr_t)s->code_ptr;
2432 if (p & 15) {
2433 p = (p + 15) & -16;
2434 s->code_ptr = (void *)p;
2435 }
2436 return s->code_ptr;
2437 }
2438
2439 /* Stack frame parameters. */
2440 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2441 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2442 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2443
2444 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2445 + TCG_TARGET_STACK_ALIGN - 1) \
2446 & -TCG_TARGET_STACK_ALIGN)
2447 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2448
2449 /* We're expecting to be able to use an immediate for frame allocation. */
2450 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2451
2452 /* Generate global QEMU prologue and epilogue code */
2453 static void tcg_target_qemu_prologue(TCGContext *s)
2454 {
2455 int i;
2456
2457 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2458
2459 /* TB prologue */
2460 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2461 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2462 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2463 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2464 }
2465
2466 #ifndef CONFIG_SOFTMMU
2467 if (guest_base) {
2468 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2469 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2470 }
2471 #endif
2472
2473 /* Call generated code */
2474 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2475 /* delay slot */
2476 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2477
2478 /*
2479 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2480 * and fall through to the rest of the epilogue.
2481 */
2482 s->code_gen_epilogue = s->code_ptr;
2483 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2484
2485 /* TB epilogue */
2486 tb_ret_addr = s->code_ptr;
2487 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2488 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2489 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2490 }
2491
2492 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2493 /* delay slot */
2494 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2495
2496 if (use_mips32r2_instructions) {
2497 return;
2498 }
2499
2500 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2501 clobbers TCG_TMP1, TCG_TMP2. */
2502
2503 /*
2504 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2505 */
2506 bswap32_addr = align_code_ptr(s);
2507 /* t3 = (ssss)d000 */
2508 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2509 /* t1 = 000a */
2510 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2511 /* t2 = 00c0 */
2512 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2513 /* t3 = d00a */
2514 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2515 /* t1 = 0abc */
2516 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2517 /* t2 = 0c00 */
2518 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2519 /* t1 = 00b0 */
2520 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2521 /* t3 = dc0a */
2522 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2523 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2524 /* t3 = dcba -- delay slot */
2525 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2526
2527 if (TCG_TARGET_REG_BITS == 32) {
2528 return;
2529 }
2530
2531 /*
2532 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2533 */
2534 bswap32u_addr = align_code_ptr(s);
2535 /* t1 = (0000)000d */
2536 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2537 /* t3 = 000a */
2538 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2539 /* t1 = (0000)d000 */
2540 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2541 /* t2 = 00c0 */
2542 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2543 /* t3 = d00a */
2544 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2545 /* t1 = 0abc */
2546 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2547 /* t2 = 0c00 */
2548 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2549 /* t1 = 00b0 */
2550 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2551 /* t3 = dc0a */
2552 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2553 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2554 /* t3 = dcba -- delay slot */
2555 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2556
2557 /*
2558 * bswap64 -- 64-bit swap. a0 = abcdefgh
2559 */
2560 bswap64_addr = align_code_ptr(s);
2561 /* t3 = h0000000 */
2562 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2563 /* t1 = 0000000a */
2564 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2565
2566 /* t2 = 000000g0 */
2567 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2568 /* t3 = h000000a */
2569 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2570 /* t1 = 00000abc */
2571 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2572 /* t2 = 0g000000 */
2573 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2574 /* t1 = 000000b0 */
2575 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2576
2577 /* t3 = hg00000a */
2578 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2579 /* t2 = 0000abcd */
2580 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2581 /* t3 = hg0000ba */
2582 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2583
2584 /* t1 = 000000c0 */
2585 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2586 /* t2 = 0000000d */
2587 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2588 /* t1 = 00000c00 */
2589 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2590 /* t2 = 0000d000 */
2591 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2592
2593 /* t3 = hg000cba */
2594 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2595 /* t1 = 00abcdef */
2596 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2597 /* t3 = hg00dcba */
2598 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2599
2600 /* t2 = 0000000f */
2601 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2602 /* t1 = 000000e0 */
2603 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2604 /* t2 = 00f00000 */
2605 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2606 /* t1 = 000e0000 */
2607 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2608
2609 /* t3 = hgf0dcba */
2610 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2611 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2612 /* t3 = hgfedcba -- delay slot */
2613 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2614 }
2615
2616 static void tcg_target_init(TCGContext *s)
2617 {
2618 tcg_target_detect_isa();
2619 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2620 if (TCG_TARGET_REG_BITS == 64) {
2621 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2622 }
2623
2624 tcg_target_call_clobber_regs = 0;
2625 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2626 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2627 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2628 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2629 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2641
2642 s->reserved_regs = 0;
2643 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2644 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2645 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2646 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2647 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2648 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2649 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2650 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2651 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2652 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2653 }
2654
2655 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
2656 uintptr_t addr)
2657 {
2658 atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
2659 flush_icache_range(jmp_addr, jmp_addr + 4);
2660 }
2661
2662 typedef struct {
2663 DebugFrameHeader h;
2664 uint8_t fde_def_cfa[4];
2665 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2666 } DebugFrame;
2667
2668 #define ELF_HOST_MACHINE EM_MIPS
2669 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2670 which is good because they're really quite complicated for MIPS. */
2671
2672 static const DebugFrame debug_frame = {
2673 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2674 .h.cie.id = -1,
2675 .h.cie.version = 1,
2676 .h.cie.code_align = 1,
2677 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2678 .h.cie.return_column = TCG_REG_RA,
2679
2680 /* Total FDE size does not include the "len" member. */
2681 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2682
2683 .fde_def_cfa = {
2684 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2685 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2686 (FRAME_SIZE >> 7)
2687 },
2688 .fde_reg_ofs = {
2689 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2690 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2691 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2692 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2693 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2694 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2695 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2696 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2697 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2698 }
2699 };
2700
2701 void tcg_register_jit(void *buf, size_t buf_size)
2702 {
2703 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2704 }
AR7 emulation for QEMU