target/mips/cp0_timer.c

   1 /*
   2  * QEMU MIPS timer support
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "hw/irq.h"
  25 #include "hw/mips/cpudevs.h"
  26 #include "qemu/timer.h"
  27 #include "sysemu/kvm.h"
  28 #include "internal.h"
  29
  30 #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
  31
  32 /* MIPS R4K timer */
  33 static void cpu_mips_timer_update(CPUMIPSState *env)
  34 {
  35     uint64_t now_ns, next_ns;
  36     uint32_t wait;
  37
  38     now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  39     wait = env->CP0_Compare - env->CP0_Count -
  40            (uint32_t)(now_ns / TIMER_PERIOD);
  41     next_ns = now_ns + (uint64_t)wait * TIMER_PERIOD;
  42     timer_mod(env->timer, next_ns);
  43 }
  44
  45 /* Expire the timer.  */
  46 static void cpu_mips_timer_expire(CPUMIPSState *env)
  47 {
  48     cpu_mips_timer_update(env);
  49     if (env->insn_flags & ISA_MIPS32R2) {
  50         env->CP0_Cause |= 1 << CP0Ca_TI;
  51     }
  52     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
  53 }
  54
  55 uint32_t cpu_mips_get_count(CPUMIPSState *env)
  56 {
  57     if (env->CP0_Cause & (1 << CP0Ca_DC)) {
  58         return env->CP0_Count;
  59     } else {
  60         uint64_t now_ns;
  61
  62         now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  63         if (timer_pending(env->timer)
  64             && timer_expired(env->timer, now_ns)) {
  65             /* The timer has already expired.  */
  66             cpu_mips_timer_expire(env);
  67         }
  68
  69         return env->CP0_Count + (uint32_t)(now_ns / TIMER_PERIOD);
  70     }
  71 }
  72
  73 void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
  74 {
  75     /*
  76      * This gets called from cpu_state_reset(), potentially before timer init.
  77      * So env->timer may be NULL, which is also the case with KVM enabled so
  78      * treat timer as disabled in that case.
  79      */
  80     if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
  81         env->CP0_Count = count;
  82     } else {
  83         /* Store new count register */
  84         env->CP0_Count = count -
  85                (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
  86         /* Update timer timer */
  87         cpu_mips_timer_update(env);
  88     }
  89 }
  90
  91 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
  92 {
  93     env->CP0_Compare = value;
  94     if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
  95         cpu_mips_timer_update(env);
  96     }
  97     if (env->insn_flags & ISA_MIPS32R2) {
  98         env->CP0_Cause &= ~(1 << CP0Ca_TI);
  99     }
 100     qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 101 }
 102
 103 void cpu_mips_start_count(CPUMIPSState *env)
 104 {
 105     cpu_mips_store_count(env, env->CP0_Count);
 106 }
 107
 108 void cpu_mips_stop_count(CPUMIPSState *env)
 109 {
 110     /* Store the current value */
 111     env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
 112                                  TIMER_PERIOD);
 113 }
 114
 115 static void mips_timer_cb(void *opaque)
 116 {
 117     CPUMIPSState *env;
 118
 119     env = opaque;
 120
 121     if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 122         return;
 123     }
 124
 125     /*
 126      * ??? This callback should occur when the counter is exactly equal to
 127      * the comparator value.  Offset the count by one to avoid immediately
 128      * retriggering the callback before any virtual time has passed.
 129      */
 130     env->CP0_Count++;
 131     cpu_mips_timer_expire(env);
 132     env->CP0_Count--;
 133 }
 134
 135 void cpu_mips_clock_init(MIPSCPU *cpu)
 136 {
 137     CPUMIPSState *env = &cpu->env;
 138
 139     /*
 140      * If we're in KVM mode, don't create the periodic timer, that is handled in
 141      * kernel.
 142      */
 143     if (!kvm_enabled()) {
 144         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
 145     }
 146 }