2 * NeXT Cube System Driver
4 * Copyright (c) 2011 Bryce Lanham
6 * This code is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published
8 * by the Free Software Foundation; either version 2 of the License,
9 * or (at your option) any later version.
12 #include "qemu/osdep.h"
13 #include "exec/hwaddr.h"
14 #include "sysemu/sysemu.h"
15 #include "sysemu/qtest.h"
17 #include "hw/m68k/next-cube.h"
18 #include "hw/boards.h"
19 #include "hw/loader.h"
20 #include "hw/scsi/esp.h"
21 #include "hw/sysbus.h"
22 #include "qom/object.h"
23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
24 #include "hw/block/fdc.h"
25 #include "hw/qdev-properties.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "ui/console.h"
29 #include "target/m68k/cpu.h"
30 #include "migration/vmstate.h"
32 /* #define DEBUG_NEXT */
34 #define DPRINTF(fmt, ...) \
35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...) do { } while (0)
40 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
41 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState
, NEXT_MACHINE
)
43 #define ENTRY 0x0100001e
44 #define RAM_SIZE 0x4000000
45 #define ROM_FILE "Rev_2.5_v66.bin"
47 typedef struct next_dma
{
60 uint32_t next_initbuf
;
64 typedef struct NextRtc
{
86 #define TYPE_NEXT_PC "next-pc"
87 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC
, NEXT_PC
)
89 /* NeXT Peripheral Controller */
91 SysBusDevice parent_obj
;
113 /* Thanks to NeXT forums for this */
115 static const uint8_t rtc_ram3[32] = {
116 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
117 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
118 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
122 static const uint8_t rtc_ram2
[32] = {
123 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
124 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
125 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
129 #define SCR2_RTCLK 0x2
130 #define SCR2_RTDATA 0x4
131 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
133 static void next_scr2_led_update(NeXTPC
*s
)
139 DPRINTF("LED flashing, possible fault!\n");
145 static void next_scr2_rtc_update(NeXTPC
*s
)
147 uint8_t old_scr2
, scr2_2
;
148 NextRtc
*rtc
= &s
->rtc
;
150 old_scr2
= extract32(s
->old_scr2
, 8, 8);
151 scr2_2
= extract32(s
->scr2
, 8, 8);
154 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */
155 if (rtc
->phase
== -1) {
158 /* If we are in going down clock... do something */
159 if (((old_scr2
& SCR2_RTCLK
) != (scr2_2
& SCR2_RTCLK
)) &&
160 ((scr2_2
& SCR2_RTCLK
) == 0)) {
161 if (rtc
->phase
< 8) {
162 rtc
->command
= (rtc
->command
<< 1) |
163 ((scr2_2
& SCR2_RTDATA
) ? 1 : 0);
165 if (rtc
->phase
>= 8 && rtc
->phase
< 16) {
166 rtc
->value
= (rtc
->value
<< 1) |
167 ((scr2_2
& SCR2_RTDATA
) ? 1 : 0);
169 /* if we read RAM register, output RT_DATA bit */
170 if (rtc
->command
<= 0x1F) {
171 scr2_2
= scr2_2
& (~SCR2_RTDATA
);
172 if (rtc
->ram
[rtc
->command
] & (0x80 >> (rtc
->phase
- 8))) {
173 scr2_2
|= SCR2_RTDATA
;
176 rtc
->retval
= (rtc
->retval
<< 1) |
177 ((scr2_2
& SCR2_RTDATA
) ? 1 : 0);
179 /* read the status 0x30 */
180 if (rtc
->command
== 0x30) {
181 scr2_2
= scr2_2
& (~SCR2_RTDATA
);
182 /* for now status = 0x98 (new rtc + FTU) */
183 if (rtc
->status
& (0x80 >> (rtc
->phase
- 8))) {
184 scr2_2
|= SCR2_RTDATA
;
187 rtc
->retval
= (rtc
->retval
<< 1) |
188 ((scr2_2
& SCR2_RTDATA
) ? 1 : 0);
190 /* read the status 0x31 */
191 if (rtc
->command
== 0x31) {
192 scr2_2
= scr2_2
& (~SCR2_RTDATA
);
193 if (rtc
->control
& (0x80 >> (rtc
->phase
- 8))) {
194 scr2_2
|= SCR2_RTDATA
;
196 rtc
->retval
= (rtc
->retval
<< 1) |
197 ((scr2_2
& SCR2_RTDATA
) ? 1 : 0);
200 if ((rtc
->command
>= 0x20) && (rtc
->command
<= 0x2F)) {
201 scr2_2
= scr2_2
& (~SCR2_RTDATA
);
203 time_t time_h
= time(NULL
);
204 struct tm
*info
= localtime(&time_h
);
207 switch (rtc
->command
) {
209 ret
= SCR2_TOBCD(info
->tm_sec
);
212 ret
= SCR2_TOBCD(info
->tm_min
);
215 ret
= SCR2_TOBCD(info
->tm_hour
);
218 ret
= SCR2_TOBCD(info
->tm_mday
);
221 ret
= SCR2_TOBCD((info
->tm_mon
+ 1));
224 ret
= SCR2_TOBCD((info
->tm_year
- 100));
229 if (ret
& (0x80 >> (rtc
->phase
- 8))) {
230 scr2_2
|= SCR2_RTDATA
;
232 rtc
->retval
= (rtc
->retval
<< 1) |
233 ((scr2_2
& SCR2_RTDATA
) ? 1 : 0);
239 if (rtc
->phase
== 16) {
240 if (rtc
->command
>= 0x80 && rtc
->command
<= 0x9F) {
241 rtc
->ram
[rtc
->command
- 0x80] = rtc
->value
;
243 /* write to x30 register */
244 if (rtc
->command
== 0xB1) {
246 if (rtc
->value
& 0x04) {
247 rtc
->status
= rtc
->status
& (~0x18);
248 s
->int_status
= s
->int_status
& (~0x04);
254 /* else end or abort */
260 s
->scr2
= deposit32(s
->scr2
, 8, 8, scr2_2
);
263 static uint64_t next_mmio_read(void *opaque
, hwaddr addr
, unsigned size
)
265 NeXTPC
*s
= NEXT_PC(opaque
);
270 /* DPRINTF("Read INT status: %x\n", s->int_status); */
275 DPRINTF("MMIO Read INT mask: %x\n", s
->int_mask
);
279 case 0xc000 ... 0xc003:
280 val
= extract32(s
->scr1
, (4 - (addr
- 0xc000) - size
) << 3,
284 case 0xd000 ... 0xd003:
285 val
= extract32(s
->scr2
, (4 - (addr
- 0xd000) - size
) << 3,
295 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx
" size %d\n", addr
, size
);
302 static void next_mmio_write(void *opaque
, hwaddr addr
, uint64_t val
,
305 NeXTPC
*s
= NEXT_PC(opaque
);
309 DPRINTF("INT Status old: %x new: %x\n", s
->int_status
,
315 DPRINTF("INT Mask old: %x new: %x\n", s
->int_mask
, (unsigned int)val
);
319 case 0xc000 ... 0xc003:
320 DPRINTF("SCR1 Write: %x\n", (unsigned int)val
);
321 s
->scr1
= deposit32(s
->scr1
, (4 - (addr
- 0xc000) - size
) << 3,
325 case 0xd000 ... 0xd003:
326 s
->scr2
= deposit32(s
->scr2
, (4 - (addr
- 0xd000) - size
) << 3,
328 next_scr2_led_update(s
);
329 next_scr2_rtc_update(s
);
330 s
->old_scr2
= s
->scr2
;
334 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx
" with 0x%x size %u\n", addr
,
335 (unsigned int)val
, size
);
339 static const MemoryRegionOps next_mmio_ops
= {
340 .read
= next_mmio_read
,
341 .write
= next_mmio_write
,
342 .valid
.min_access_size
= 1,
343 .valid
.max_access_size
= 4,
344 .endianness
= DEVICE_BIG_ENDIAN
,
347 #define SCSICSR_ENABLE 0x01
348 #define SCSICSR_RESET 0x02 /* reset scsi dma */
349 #define SCSICSR_FIFOFL 0x04
350 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
351 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
352 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
354 static uint64_t next_scr_readfn(void *opaque
, hwaddr addr
, unsigned size
)
356 NeXTPC
*s
= NEXT_PC(opaque
);
361 DPRINTF("FD read @ %x\n", (unsigned int)addr
);
362 val
= 0x40 | 0x04 | 0x2 | 0x1;
366 DPRINTF("SCSI 4020 STATUS READ %X\n", s
->scsi_csr_1
);
371 DPRINTF("SCSI 4021 STATUS READ %X\n", s
->scsi_csr_2
);
376 * These 4 registers are the hardware timer, not sure which register
377 * is the latch instead of data, but no problems so far.
379 * Hack: We need to have the LSB change consistently to make it work
381 case 0x1a000 ... 0x1a003:
382 val
= extract32(clock(), (4 - (addr
- 0x1a000) - size
) << 3,
386 /* For now return dummy byte to allow the Ethernet test to timeout */
392 DPRINTF("BMAP Read @ 0x%x size %u\n", (unsigned int)addr
, size
);
400 static void next_scr_writefn(void *opaque
, hwaddr addr
, uint64_t val
,
403 NeXTPC
*s
= NEXT_PC(opaque
);
407 DPRINTF("FDCSR Write: %x\n", value
);
409 /* qemu_irq_raise(s->fd_irq[0]); */
413 case 0x14020: /* SCSI Control Register */
414 if (val
& SCSICSR_FIFOFL
) {
415 DPRINTF("SCSICSR FIFO Flush\n");
416 /* will have to add another irq to the esp if this is needed */
417 /* esp_puflush_fifo(esp_g); */
420 if (val
& SCSICSR_ENABLE
) {
421 DPRINTF("SCSICSR Enable\n");
423 * qemu_irq_raise(s->scsi_dma);
424 * s->scsi_csr_1 = 0xc0;
425 * s->scsi_csr_1 |= 0x1;
426 * qemu_irq_pulse(s->scsi_dma);
431 * s->scsi_csr_1 &= ~SCSICSR_ENABLE;
434 if (val
& SCSICSR_RESET
) {
435 DPRINTF("SCSICSR Reset\n");
436 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
437 qemu_irq_raise(s
->scsi_reset
);
438 s
->scsi_csr_1
&= ~(SCSICSR_INTMASK
| 0x80 | 0x1);
439 qemu_irq_lower(s
->scsi_reset
);
441 if (val
& SCSICSR_DMADIR
) {
442 DPRINTF("SCSICSR DMAdir\n");
444 if (val
& SCSICSR_CPUDMA
) {
445 DPRINTF("SCSICSR CPUDMA\n");
446 /* qemu_irq_raise(s->scsi_dma); */
447 s
->int_status
|= 0x4000000;
449 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */
450 s
->int_status
&= ~(0x4000000);
451 /* qemu_irq_lower(s->scsi_dma); */
453 if (val
& SCSICSR_INTMASK
) {
454 DPRINTF("SCSICSR INTMASK\n");
456 * int_mask &= ~0x1000;
457 * s->scsi_csr_1 |= val;
458 * s->scsi_csr_1 &= ~SCSICSR_INTMASK;
459 * if (s->scsi_queued) {
460 * s->scsi_queued = 0;
461 * next_irq(s, NEXT_SCSI_I, level);
465 /* int_mask |= 0x1000; */
468 /* int_mask |= 0x1000; */
469 /* s->scsi_csr_1 |= 0x80; */
471 DPRINTF("SCSICSR Write: %x\n", val
);
472 /* s->scsi_csr_1 = val; */
475 /* Hardware timer latch - not implemented yet */
478 DPRINTF("BMAP Write @ 0x%x with 0x%x size %u\n", (unsigned int)addr
,
483 static const MemoryRegionOps next_scr_ops
= {
484 .read
= next_scr_readfn
,
485 .write
= next_scr_writefn
,
486 .valid
.min_access_size
= 1,
487 .valid
.max_access_size
= 4,
488 .endianness
= DEVICE_BIG_ENDIAN
,
491 #define NEXTDMA_SCSI(x) (0x10 + x)
492 #define NEXTDMA_FD(x) (0x10 + x)
493 #define NEXTDMA_ENTX(x) (0x110 + x)
494 #define NEXTDMA_ENRX(x) (0x150 + x)
495 #define NEXTDMA_CSR 0x0
496 #define NEXTDMA_NEXT 0x4000
497 #define NEXTDMA_LIMIT 0x4004
498 #define NEXTDMA_START 0x4008
499 #define NEXTDMA_STOP 0x400c
500 #define NEXTDMA_NEXT_INIT 0x4200
501 #define NEXTDMA_SIZE 0x4204
503 static void next_dma_write(void *opaque
, hwaddr addr
, uint64_t val
,
506 NeXTState
*next_state
= NEXT_MACHINE(opaque
);
509 case NEXTDMA_ENRX(NEXTDMA_CSR
):
510 if (val
& DMA_DEV2M
) {
511 next_state
->dma
[NEXTDMA_ENRX
].csr
|= DMA_DEV2M
;
514 if (val
& DMA_SETENABLE
) {
515 /* DPRINTF("SCSI DMA ENABLE\n"); */
516 next_state
->dma
[NEXTDMA_ENRX
].csr
|= DMA_ENABLE
;
518 if (val
& DMA_SETSUPDATE
) {
519 next_state
->dma
[NEXTDMA_ENRX
].csr
|= DMA_SUPDATE
;
521 if (val
& DMA_CLRCOMPLETE
) {
522 next_state
->dma
[NEXTDMA_ENRX
].csr
&= ~DMA_COMPLETE
;
525 if (val
& DMA_RESET
) {
526 next_state
->dma
[NEXTDMA_ENRX
].csr
&= ~(DMA_COMPLETE
| DMA_SUPDATE
|
527 DMA_ENABLE
| DMA_DEV2M
);
529 /* DPRINTF("RXCSR \tWrite: %x\n",value); */
532 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT
):
533 next_state
->dma
[NEXTDMA_ENRX
].next_initbuf
= val
;
536 case NEXTDMA_ENRX(NEXTDMA_NEXT
):
537 next_state
->dma
[NEXTDMA_ENRX
].next
= val
;
540 case NEXTDMA_ENRX(NEXTDMA_LIMIT
):
541 next_state
->dma
[NEXTDMA_ENRX
].limit
= val
;
544 case NEXTDMA_SCSI(NEXTDMA_CSR
):
545 if (val
& DMA_DEV2M
) {
546 next_state
->dma
[NEXTDMA_SCSI
].csr
|= DMA_DEV2M
;
548 if (val
& DMA_SETENABLE
) {
549 /* DPRINTF("SCSI DMA ENABLE\n"); */
550 next_state
->dma
[NEXTDMA_SCSI
].csr
|= DMA_ENABLE
;
552 if (val
& DMA_SETSUPDATE
) {
553 next_state
->dma
[NEXTDMA_SCSI
].csr
|= DMA_SUPDATE
;
555 if (val
& DMA_CLRCOMPLETE
) {
556 next_state
->dma
[NEXTDMA_SCSI
].csr
&= ~DMA_COMPLETE
;
559 if (val
& DMA_RESET
) {
560 next_state
->dma
[NEXTDMA_SCSI
].csr
&= ~(DMA_COMPLETE
| DMA_SUPDATE
|
561 DMA_ENABLE
| DMA_DEV2M
);
562 /* DPRINTF("SCSI DMA RESET\n"); */
564 /* DPRINTF("RXCSR \tWrite: %x\n",value); */
567 case NEXTDMA_SCSI(NEXTDMA_NEXT
):
568 next_state
->dma
[NEXTDMA_SCSI
].next
= val
;
571 case NEXTDMA_SCSI(NEXTDMA_LIMIT
):
572 next_state
->dma
[NEXTDMA_SCSI
].limit
= val
;
575 case NEXTDMA_SCSI(NEXTDMA_START
):
576 next_state
->dma
[NEXTDMA_SCSI
].start
= val
;
579 case NEXTDMA_SCSI(NEXTDMA_STOP
):
580 next_state
->dma
[NEXTDMA_SCSI
].stop
= val
;
583 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT
):
584 next_state
->dma
[NEXTDMA_SCSI
].next_initbuf
= val
;
588 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr
, (unsigned)value
);
592 static uint64_t next_dma_read(void *opaque
, hwaddr addr
, unsigned int size
)
594 NeXTState
*next_state
= NEXT_MACHINE(opaque
);
598 case NEXTDMA_SCSI(NEXTDMA_CSR
):
599 DPRINTF("SCSI DMA CSR READ\n");
600 val
= next_state
->dma
[NEXTDMA_SCSI
].csr
;
603 case NEXTDMA_ENRX(NEXTDMA_CSR
):
604 val
= next_state
->dma
[NEXTDMA_ENRX
].csr
;
607 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT
):
608 val
= next_state
->dma
[NEXTDMA_ENRX
].next_initbuf
;
611 case NEXTDMA_ENRX(NEXTDMA_NEXT
):
612 val
= next_state
->dma
[NEXTDMA_ENRX
].next
;
615 case NEXTDMA_ENRX(NEXTDMA_LIMIT
):
616 val
= next_state
->dma
[NEXTDMA_ENRX
].limit
;
619 case NEXTDMA_SCSI(NEXTDMA_NEXT
):
620 val
= next_state
->dma
[NEXTDMA_SCSI
].next
;
623 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT
):
624 val
= next_state
->dma
[NEXTDMA_SCSI
].next_initbuf
;
627 case NEXTDMA_SCSI(NEXTDMA_LIMIT
):
628 val
= next_state
->dma
[NEXTDMA_SCSI
].limit
;
631 case NEXTDMA_SCSI(NEXTDMA_START
):
632 val
= next_state
->dma
[NEXTDMA_SCSI
].start
;
635 case NEXTDMA_SCSI(NEXTDMA_STOP
):
636 val
= next_state
->dma
[NEXTDMA_SCSI
].stop
;
640 DPRINTF("DMA read @ %x\n", (unsigned int)addr
);
645 * once the csr's are done, subtract 0x3FEC from the addr, and that will
646 * normalize the upper registers
652 static const MemoryRegionOps next_dma_ops
= {
653 .read
= next_dma_read
,
654 .write
= next_dma_write
,
655 .impl
.min_access_size
= 4,
656 .valid
.min_access_size
= 4,
657 .valid
.max_access_size
= 4,
658 .endianness
= DEVICE_BIG_ENDIAN
,
661 static void next_irq(void *opaque
, int number
, int level
)
663 NeXTPC
*s
= NEXT_PC(opaque
);
664 M68kCPU
*cpu
= s
->cpu
;
667 /* first switch sets interrupt status */
668 /* DPRINTF("IRQ %i\n",number); */
670 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
693 /* level 5 - scc (serial) */
698 /* level 6 - audio etherrx/tx dma */
699 case NEXT_ENTX_DMA_I
:
702 case NEXT_ENRX_DMA_I
:
705 case NEXT_SCSI_DMA_I
:
717 * this HAS to be wrong, the interrupt handlers in mach and together
718 * int_status and int_mask and return if there is a hit
720 if (s
->int_mask
& (1 << shift
)) {
721 DPRINTF("%x interrupt masked @ %x\n", 1 << shift
, cpu
->env
.pc
);
725 /* second switch triggers the correct interrupt */
727 s
->int_status
|= 1 << shift
;
730 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
738 m68k_set_irq_level(cpu
, 3, 27);
741 /* level 5 - scc (serial) */
743 m68k_set_irq_level(cpu
, 5, 29);
746 /* level 6 - audio etherrx/tx dma */
747 case NEXT_ENTX_DMA_I
:
748 case NEXT_ENRX_DMA_I
:
749 case NEXT_SCSI_DMA_I
:
752 m68k_set_irq_level(cpu
, 6, 30);
756 s
->int_status
&= ~(1 << shift
);
757 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_HARD
);
761 static void nextdma_write(void *opaque
, uint8_t *buf
, int size
, int type
)
766 NeXTState
*next_state
= NEXT_MACHINE(qdev_get_machine());
768 if (type
== NEXTDMA_ENRX
|| type
== NEXTDMA_ENTX
) {
771 /* Most DMA is supposedly 16 byte aligned */
772 if ((size
% align
) != 0) {
773 size
-= size
% align
;
778 * prom sets the dma start using initbuf while the bootloader uses next
779 * so we check to see if initbuf is 0
781 if (next_state
->dma
[type
].next_initbuf
== 0) {
782 base_addr
= next_state
->dma
[type
].next
;
784 base_addr
= next_state
->dma
[type
].next_initbuf
;
787 cpu_physical_memory_write(base_addr
, buf
, size
);
789 next_state
->dma
[type
].next_initbuf
= 0;
791 /* saved limit is checked to calculate packet size by both, rom and netbsd */
792 next_state
->dma
[type
].saved_limit
= (next_state
->dma
[type
].next
+ size
);
793 next_state
->dma
[type
].saved_next
= (next_state
->dma
[type
].next
);
796 * 32 bytes under savedbase seems to be some kind of register
797 * of which the purpose is unknown as of yet
799 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */
801 if (!(next_state
->dma
[type
].csr
& DMA_SUPDATE
)) {
802 next_state
->dma
[type
].next
= next_state
->dma
[type
].start
;
803 next_state
->dma
[type
].limit
= next_state
->dma
[type
].stop
;
806 /* Set dma registers and raise an irq */
807 next_state
->dma
[type
].csr
|= DMA_COMPLETE
; /* DON'T CHANGE THIS! */
811 irq
= NEXT_SCSI_DMA_I
;
815 next_irq(opaque
, irq
, 1);
816 next_irq(opaque
, irq
, 0);
819 static void nextscsi_read(void *opaque
, uint8_t *buf
, int len
)
821 DPRINTF("SCSI READ: %x\n", len
);
825 static void nextscsi_write(void *opaque
, uint8_t *buf
, int size
)
827 DPRINTF("SCSI WRITE: %i\n", size
);
828 nextdma_write(opaque
, buf
, size
, NEXTDMA_SCSI
);
831 static void next_scsi_init(DeviceState
*pcdev
, M68kCPU
*cpu
)
833 struct NeXTPC
*next_pc
= NEXT_PC(pcdev
);
835 SysBusDevice
*sysbusdev
;
836 SysBusESPState
*sysbus_esp
;
839 dev
= qdev_new(TYPE_SYSBUS_ESP
);
840 sysbus_esp
= SYSBUS_ESP(dev
);
841 esp
= &sysbus_esp
->esp
;
842 esp
->dma_memory_read
= nextscsi_read
;
843 esp
->dma_memory_write
= nextscsi_write
;
844 esp
->dma_opaque
= pcdev
;
845 sysbus_esp
->it_shift
= 0;
846 esp
->dma_enabled
= 1;
847 sysbusdev
= SYS_BUS_DEVICE(dev
);
848 sysbus_realize_and_unref(sysbusdev
, &error_fatal
);
849 sysbus_connect_irq(sysbusdev
, 0, qdev_get_gpio_in(pcdev
, NEXT_SCSI_I
));
850 sysbus_mmio_map(sysbusdev
, 0, 0x2114000);
852 next_pc
->scsi_reset
= qdev_get_gpio_in(dev
, 0);
853 next_pc
->scsi_dma
= qdev_get_gpio_in(dev
, 1);
855 scsi_bus_legacy_handle_cmdline(&esp
->bus
);
858 static void next_escc_init(DeviceState
*pcdev
)
863 dev
= qdev_new(TYPE_ESCC
);
864 qdev_prop_set_uint32(dev
, "disabled", 0);
865 qdev_prop_set_uint32(dev
, "frequency", 9600 * 384);
866 qdev_prop_set_uint32(dev
, "it_shift", 0);
867 qdev_prop_set_bit(dev
, "bit_swap", true);
868 qdev_prop_set_chr(dev
, "chrB", serial_hd(1));
869 qdev_prop_set_chr(dev
, "chrA", serial_hd(0));
870 qdev_prop_set_uint32(dev
, "chnBtype", escc_serial
);
871 qdev_prop_set_uint32(dev
, "chnAtype", escc_serial
);
873 s
= SYS_BUS_DEVICE(dev
);
874 sysbus_realize_and_unref(s
, &error_fatal
);
875 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(pcdev
, NEXT_SCC_I
));
876 sysbus_connect_irq(s
, 1, qdev_get_gpio_in(pcdev
, NEXT_SCC_DMA_I
));
877 sysbus_mmio_map(s
, 0, 0x2118000);
880 static void next_pc_reset(DeviceState
*dev
)
882 NeXTPC
*s
= NEXT_PC(dev
);
884 /* Set internal registers to initial values */
885 /* 0x0000XX00 << vital bits */
886 s
->scr1
= 0x00011102;
887 s
->scr2
= 0x00ff0c80;
888 s
->old_scr2
= s
->scr2
;
890 s
->rtc
.status
= 0x90;
892 /* Load RTC RAM - TODO: provide possibility to load contents from file */
893 memcpy(s
->rtc
.ram
, rtc_ram2
, 32);
896 static void next_pc_realize(DeviceState
*dev
, Error
**errp
)
898 NeXTPC
*s
= NEXT_PC(dev
);
899 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
901 qdev_init_gpio_in(dev
, next_irq
, NEXT_NUM_IRQS
);
903 memory_region_init_io(&s
->mmiomem
, OBJECT(s
), &next_mmio_ops
, s
,
904 "next.mmio", 0xd0000);
905 memory_region_init_io(&s
->scrmem
, OBJECT(s
), &next_scr_ops
, s
,
906 "next.scr", 0x20000);
907 sysbus_init_mmio(sbd
, &s
->mmiomem
);
908 sysbus_init_mmio(sbd
, &s
->scrmem
);
912 * If the m68k CPU implemented its inbound irq lines as GPIO lines
913 * rather than via the m68k_set_irq_level() function we would not need
914 * this cpu link property and could instead provide outbound IRQ lines
915 * that the board could wire up to the CPU.
917 static Property next_pc_properties
[] = {
918 DEFINE_PROP_LINK("cpu", NeXTPC
, cpu
, TYPE_M68K_CPU
, M68kCPU
*),
919 DEFINE_PROP_END_OF_LIST(),
922 static const VMStateDescription next_rtc_vmstate
= {
925 .minimum_version_id
= 2,
926 .fields
= (const VMStateField
[]) {
927 VMSTATE_INT8(phase
, NextRtc
),
928 VMSTATE_UINT8_ARRAY(ram
, NextRtc
, 32),
929 VMSTATE_UINT8(command
, NextRtc
),
930 VMSTATE_UINT8(value
, NextRtc
),
931 VMSTATE_UINT8(status
, NextRtc
),
932 VMSTATE_UINT8(control
, NextRtc
),
933 VMSTATE_UINT8(retval
, NextRtc
),
934 VMSTATE_END_OF_LIST()
938 static const VMStateDescription next_pc_vmstate
= {
941 .minimum_version_id
= 2,
942 .fields
= (const VMStateField
[]) {
943 VMSTATE_UINT32(scr1
, NeXTPC
),
944 VMSTATE_UINT32(scr2
, NeXTPC
),
945 VMSTATE_UINT32(old_scr2
, NeXTPC
),
946 VMSTATE_UINT32(int_mask
, NeXTPC
),
947 VMSTATE_UINT32(int_status
, NeXTPC
),
948 VMSTATE_UINT32(led
, NeXTPC
),
949 VMSTATE_UINT8(scsi_csr_1
, NeXTPC
),
950 VMSTATE_UINT8(scsi_csr_2
, NeXTPC
),
951 VMSTATE_STRUCT(rtc
, NeXTPC
, 0, next_rtc_vmstate
, NextRtc
),
952 VMSTATE_END_OF_LIST()
956 static void next_pc_class_init(ObjectClass
*klass
, void *data
)
958 DeviceClass
*dc
= DEVICE_CLASS(klass
);
960 dc
->desc
= "NeXT Peripheral Controller";
961 dc
->realize
= next_pc_realize
;
962 dc
->reset
= next_pc_reset
;
963 device_class_set_props(dc
, next_pc_properties
);
964 dc
->vmsd
= &next_pc_vmstate
;
967 static const TypeInfo next_pc_info
= {
968 .name
= TYPE_NEXT_PC
,
969 .parent
= TYPE_SYS_BUS_DEVICE
,
970 .instance_size
= sizeof(NeXTPC
),
971 .class_init
= next_pc_class_init
,
974 static void next_cube_init(MachineState
*machine
)
976 NeXTState
*m
= NEXT_MACHINE(machine
);
979 MemoryRegion
*sysmem
= get_system_memory();
980 const char *bios_name
= machine
->firmware
?: ROM_FILE
;
983 /* Initialize the cpu core */
984 cpu
= M68K_CPU(cpu_create(machine
->cpu_type
));
986 error_report("Unable to find m68k CPU definition");
991 /* Initialize CPU registers. */
995 /* Peripheral Controller */
996 pcdev
= qdev_new(TYPE_NEXT_PC
);
997 object_property_set_link(OBJECT(pcdev
), "cpu", OBJECT(cpu
), &error_abort
);
998 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev
), &error_fatal
);
1000 /* 64MB RAM starting at 0x04000000 */
1001 memory_region_add_subregion(sysmem
, 0x04000000, machine
->ram
);
1004 sysbus_create_simple(TYPE_NEXTFB
, 0x0B000000, NULL
);
1007 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev
), 0, 0x02000000);
1009 /* BMAP IO - acts as a catch-all for now */
1010 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev
), 1, 0x02100000);
1013 memory_region_init_ram_flags_nomigrate(&m
->bmapm1
, NULL
, "next.bmapmem",
1014 64, RAM_SHARED
, &error_fatal
);
1015 memory_region_add_subregion(sysmem
, 0x020c0000, &m
->bmapm1
);
1016 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */
1017 memory_region_init_alias(&m
->bmapm2
, NULL
, "next.bmapmem2", &m
->bmapm1
,
1019 memory_region_add_subregion(sysmem
, 0x820c0000, &m
->bmapm2
);
1022 sysbus_create_simple(TYPE_NEXTKBD
, 0x0200e000, NULL
);
1025 memory_region_init_rom(&m
->rom
, NULL
, "next.rom", 0x20000, &error_fatal
);
1026 memory_region_add_subregion(sysmem
, 0x01000000, &m
->rom
);
1027 memory_region_init_alias(&m
->rom2
, NULL
, "next.rom2", &m
->rom
, 0x0,
1029 memory_region_add_subregion(sysmem
, 0x0, &m
->rom2
);
1030 if (load_image_targphys(bios_name
, 0x01000000, 0x20000) < 8) {
1031 if (!qtest_enabled()) {
1032 error_report("Failed to load firmware '%s'.", bios_name
);
1036 /* Initial PC is always at offset 4 in firmware binaries */
1037 ptr
= rom_ptr(0x01000004, 4);
1038 g_assert(ptr
!= NULL
);
1039 env
->pc
= ldl_p(ptr
);
1040 if (env
->pc
>= 0x01020000) {
1041 error_report("'%s' does not seem to be a valid firmware image.",
1048 next_escc_init(pcdev
);
1053 next_scsi_init(pcdev
, cpu
);
1056 memory_region_init_io(&m
->dmamem
, NULL
, &next_dma_ops
, machine
,
1057 "next.dma", 0x5000);
1058 memory_region_add_subregion(sysmem
, 0x02000000, &m
->dmamem
);
1061 static void next_machine_class_init(ObjectClass
*oc
, void *data
)
1063 MachineClass
*mc
= MACHINE_CLASS(oc
);
1065 mc
->desc
= "NeXT Cube";
1066 mc
->init
= next_cube_init
;
1067 mc
->block_default_type
= IF_SCSI
;
1068 mc
->default_ram_size
= RAM_SIZE
;
1069 mc
->default_ram_id
= "next.ram";
1070 mc
->default_cpu_type
= M68K_CPU_TYPE_NAME("m68040");
1073 static const TypeInfo next_typeinfo
= {
1074 .name
= TYPE_NEXT_MACHINE
,
1075 .parent
= TYPE_MACHINE
,
1076 .class_init
= next_machine_class_init
,
1077 .instance_size
= sizeof(NeXTState
),
1080 static void next_register_type(void)
1082 type_register_static(&next_typeinfo
);
1083 type_register_static(&next_pc_info
);
1086 type_init(next_register_type
)