2 * PowerPC Radix MMU mulation helpers for QEMU.
4 * Copyright (c) 2016 Suraj Jitindar Singh, IBM Corporation
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/kvm.h"
28 #include "mmu-radix64.h"
29 #include "mmu-book3s-v3.h"
31 static bool ppc_radix64_get_fully_qualified_addr(CPUPPCState
*env
, vaddr eaddr
,
32 uint64_t *lpid
, uint64_t *pid
)
34 if (msr_hv
) { /* MSR[HV] -> Hypervisor/bare metal */
35 switch (eaddr
& R_EADDR_QUADRANT
) {
36 case R_EADDR_QUADRANT0
:
38 *pid
= env
->spr
[SPR_BOOKS_PID
];
40 case R_EADDR_QUADRANT1
:
41 *lpid
= env
->spr
[SPR_LPIDR
];
42 *pid
= env
->spr
[SPR_BOOKS_PID
];
44 case R_EADDR_QUADRANT2
:
45 *lpid
= env
->spr
[SPR_LPIDR
];
48 case R_EADDR_QUADRANT3
:
53 } else { /* !MSR[HV] -> Guest */
54 switch (eaddr
& R_EADDR_QUADRANT
) {
55 case R_EADDR_QUADRANT0
: /* Guest application */
56 *lpid
= env
->spr
[SPR_LPIDR
];
57 *pid
= env
->spr
[SPR_BOOKS_PID
];
59 case R_EADDR_QUADRANT1
: /* Illegal */
60 case R_EADDR_QUADRANT2
:
62 case R_EADDR_QUADRANT3
: /* Guest OS */
63 *lpid
= env
->spr
[SPR_LPIDR
];
64 *pid
= 0; /* pid set to 0 -> addresses guest operating system */
72 static void ppc_radix64_raise_segi(PowerPCCPU
*cpu
, int rwx
, vaddr eaddr
)
74 CPUState
*cs
= CPU(cpu
);
75 CPUPPCState
*env
= &cpu
->env
;
77 if (rwx
== 2) { /* Instruction Segment Interrupt */
78 cs
->exception_index
= POWERPC_EXCP_ISEG
;
79 } else { /* Data Segment Interrupt */
80 cs
->exception_index
= POWERPC_EXCP_DSEG
;
81 env
->spr
[SPR_DAR
] = eaddr
;
86 static void ppc_radix64_raise_si(PowerPCCPU
*cpu
, int rwx
, vaddr eaddr
,
89 CPUState
*cs
= CPU(cpu
);
90 CPUPPCState
*env
= &cpu
->env
;
92 if (rwx
== 2) { /* Instruction Storage Interrupt */
93 cs
->exception_index
= POWERPC_EXCP_ISI
;
94 env
->error_code
= cause
;
95 } else { /* Data Storage Interrupt */
96 cs
->exception_index
= POWERPC_EXCP_DSI
;
97 if (rwx
== 1) { /* Write -> Store */
98 cause
|= DSISR_ISSTORE
;
100 env
->spr
[SPR_DSISR
] = cause
;
101 env
->spr
[SPR_DAR
] = eaddr
;
107 static bool ppc_radix64_check_prot(PowerPCCPU
*cpu
, int rwx
, uint64_t pte
,
108 int *fault_cause
, int *prot
)
110 CPUPPCState
*env
= &cpu
->env
;
111 const int need_prot
[] = { PAGE_READ
, PAGE_WRITE
, PAGE_EXEC
};
113 /* Check Page Attributes (pte58:59) */
114 if (((pte
& R_PTE_ATT
) == R_PTE_ATT_NI_IO
) && (rwx
== 2)) {
116 * Radix PTE entries with the non-idempotent I/O attribute are treated
119 *fault_cause
|= SRR1_NOEXEC_GUARD
;
123 /* Determine permissions allowed by Encoded Access Authority */
124 if ((pte
& R_PTE_EAA_PRIV
) && msr_pr
) { /* Insufficient Privilege */
126 } else if (msr_pr
|| (pte
& R_PTE_EAA_PRIV
)) {
127 *prot
= ppc_radix64_get_prot_eaa(pte
);
128 } else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) */
129 *prot
= ppc_radix64_get_prot_eaa(pte
);
130 *prot
&= ppc_radix64_get_prot_amr(cpu
); /* Least combined permissions */
133 /* Check if requested access type is allowed */
134 if (need_prot
[rwx
] & ~(*prot
)) { /* Page Protected for that Access */
135 *fault_cause
|= DSISR_PROTFAULT
;
142 static void ppc_radix64_set_rc(PowerPCCPU
*cpu
, int rwx
, uint64_t pte
,
143 hwaddr pte_addr
, int *prot
)
145 CPUState
*cs
= CPU(cpu
);
148 npte
= pte
| R_PTE_R
; /* Always set reference bit */
150 if (rwx
== 1) { /* Store/Write */
151 npte
|= R_PTE_C
; /* Set change bit */
154 * Treat the page as read-only for now, so that a later write
155 * will pass through this function again to set the C bit.
157 *prot
&= ~PAGE_WRITE
;
160 if (pte
^ npte
) { /* If pte has changed then write it back */
161 stq_phys(cs
->as
, pte_addr
, npte
);
165 static uint64_t ppc_radix64_walk_tree(PowerPCCPU
*cpu
, vaddr eaddr
,
166 uint64_t base_addr
, uint64_t nls
,
167 hwaddr
*raddr
, int *psize
,
168 int *fault_cause
, hwaddr
*pte_addr
)
170 CPUState
*cs
= CPU(cpu
);
173 if (nls
< 5) { /* Directory maps less than 2**5 entries */
174 *fault_cause
|= DSISR_R_BADCONFIG
;
178 /* Read page <directory/table> entry from guest address space */
179 index
= eaddr
>> (*psize
- nls
); /* Shift */
180 index
&= ((1UL << nls
) - 1); /* Mask */
181 pde
= ldq_phys(cs
->as
, base_addr
+ (index
* sizeof(pde
)));
182 if (!(pde
& R_PTE_VALID
)) { /* Invalid Entry */
183 *fault_cause
|= DSISR_NOPTE
;
189 /* Check if Leaf Entry -> Page Table Entry -> Stop the Search */
190 if (pde
& R_PTE_LEAF
) {
191 uint64_t rpn
= pde
& R_PTE_RPN
;
192 uint64_t mask
= (1UL << *psize
) - 1;
194 /* Or high bits of rpn and low bits to ea to form whole real addr */
195 *raddr
= (rpn
& ~mask
) | (eaddr
& mask
);
196 *pte_addr
= base_addr
+ (index
* sizeof(pde
));
200 /* Next Level of Radix Tree */
201 return ppc_radix64_walk_tree(cpu
, eaddr
, pde
& R_PDE_NLB
, pde
& R_PDE_NLS
,
202 raddr
, psize
, fault_cause
, pte_addr
);
205 static bool validate_pate(PowerPCCPU
*cpu
, uint64_t lpid
, ppc_v3_pate_t
*pate
)
207 CPUPPCState
*env
= &cpu
->env
;
209 if (!(pate
->dw0
& PATE0_HR
)) {
212 if (lpid
== 0 && !msr_hv
) {
215 /* More checks ... */
219 int ppc_radix64_handle_mmu_fault(PowerPCCPU
*cpu
, vaddr eaddr
, int rwx
,
222 CPUState
*cs
= CPU(cpu
);
223 CPUPPCState
*env
= &cpu
->env
;
224 PPCVirtualHypervisorClass
*vhc
;
225 hwaddr raddr
, pte_addr
;
226 uint64_t lpid
= 0, pid
= 0, offset
, size
, prtbe0
, pte
;
227 int page_size
, prot
, fault_cause
= 0;
230 assert((rwx
== 0) || (rwx
== 1) || (rwx
== 2));
231 assert(ppc64_use_proc_tbl(cpu
));
233 /* Real Mode Access */
234 if (((rwx
== 2) && (msr_ir
== 0)) || ((rwx
!= 2) && (msr_dr
== 0))) {
235 /* In real mode top 4 effective addr bits (mostly) ignored */
236 raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
238 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
239 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
, mmu_idx
,
244 /* Virtual Mode Access - get the fully qualified address */
245 if (!ppc_radix64_get_fully_qualified_addr(env
, eaddr
, &lpid
, &pid
)) {
246 ppc_radix64_raise_segi(cpu
, rwx
, eaddr
);
250 /* Get Process Table */
252 vhc
= PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
253 vhc
->get_pate(cpu
->vhyp
, &pate
);
255 if (!ppc64_v3_get_pate(cpu
, lpid
, &pate
)) {
256 ppc_radix64_raise_si(cpu
, rwx
, eaddr
, DSISR_NOPTE
);
259 if (!validate_pate(cpu
, lpid
, &pate
)) {
260 ppc_radix64_raise_si(cpu
, rwx
, eaddr
, DSISR_R_BADCONFIG
);
262 /* We don't support guest mode yet */
264 error_report("PowerNV guest support Unimplemented");
269 /* Index Process Table by PID to Find Corresponding Process Table Entry */
270 offset
= pid
* sizeof(struct prtb_entry
);
271 size
= 1ULL << ((pate
.dw1
& PATE1_R_PRTS
) + 12);
272 if (offset
>= size
) {
273 /* offset exceeds size of the process table */
274 ppc_radix64_raise_si(cpu
, rwx
, eaddr
, DSISR_NOPTE
);
277 prtbe0
= ldq_phys(cs
->as
, (pate
.dw1
& PATE1_R_PRTB
) + offset
);
279 /* Walk Radix Tree from Process Table Entry to Convert EA to RA */
280 page_size
= PRTBE_R_GET_RTS(prtbe0
);
281 pte
= ppc_radix64_walk_tree(cpu
, eaddr
& R_EADDR_MASK
,
282 prtbe0
& PRTBE_R_RPDB
, prtbe0
& PRTBE_R_RPDS
,
283 &raddr
, &page_size
, &fault_cause
, &pte_addr
);
284 if (!pte
|| ppc_radix64_check_prot(cpu
, rwx
, pte
, &fault_cause
, &prot
)) {
285 /* Couldn't get pte or access denied due to protection */
286 ppc_radix64_raise_si(cpu
, rwx
, eaddr
, fault_cause
);
290 /* Update Reference and Change Bits */
291 ppc_radix64_set_rc(cpu
, rwx
, pte
, pte_addr
, &prot
);
293 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
294 prot
, mmu_idx
, 1UL << page_size
);
298 hwaddr
ppc_radix64_get_phys_page_debug(PowerPCCPU
*cpu
, target_ulong eaddr
)
300 CPUState
*cs
= CPU(cpu
);
301 CPUPPCState
*env
= &cpu
->env
;
302 PPCVirtualHypervisorClass
*vhc
;
303 hwaddr raddr
, pte_addr
;
304 uint64_t lpid
= 0, pid
= 0, offset
, size
, prtbe0
, pte
;
305 int page_size
, fault_cause
= 0;
308 /* Handle Real Mode */
310 /* In real mode top 4 effective addr bits (mostly) ignored */
311 return eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
314 /* Virtual Mode Access - get the fully qualified address */
315 if (!ppc_radix64_get_fully_qualified_addr(env
, eaddr
, &lpid
, &pid
)) {
319 /* Get Process Table */
321 vhc
= PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
322 vhc
->get_pate(cpu
->vhyp
, &pate
);
324 if (!ppc64_v3_get_pate(cpu
, lpid
, &pate
)) {
327 if (!validate_pate(cpu
, lpid
, &pate
)) {
330 /* We don't support guest mode yet */
332 error_report("PowerNV guest support Unimplemented");
337 /* Index Process Table by PID to Find Corresponding Process Table Entry */
338 offset
= pid
* sizeof(struct prtb_entry
);
339 size
= 1ULL << ((pate
.dw1
& PATE1_R_PRTS
) + 12);
340 if (offset
>= size
) {
341 /* offset exceeds size of the process table */
344 prtbe0
= ldq_phys(cs
->as
, (pate
.dw1
& PATE1_R_PRTB
) + offset
);
346 /* Walk Radix Tree from Process Table Entry to Convert EA to RA */
347 page_size
= PRTBE_R_GET_RTS(prtbe0
);
348 pte
= ppc_radix64_walk_tree(cpu
, eaddr
& R_EADDR_MASK
,
349 prtbe0
& PRTBE_R_RPDB
, prtbe0
& PRTBE_R_RPDS
,
350 &raddr
, &page_size
, &fault_cause
, &pte_addr
);
355 return raddr
& TARGET_PAGE_MASK
;