target/arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "qemu-common.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31 #include "kvm_arm.h"
  32 #include "qapi/visitor.h"
  33
  34 static inline void set_feature(CPUARMState *env, int feature)
  35 {
  36     env->features |= 1ULL << feature;
  37 }
  38
  39 static inline void unset_feature(CPUARMState *env, int feature)
  40 {
  41     env->features &= ~(1ULL << feature);
  42 }
  43
  44 #ifndef CONFIG_USER_ONLY
  45 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  46 {
  47     ARMCPU *cpu = arm_env_get_cpu(env);
  48
  49     /* Number of cores is in [25:24]; otherwise we RAZ */
  50     return (cpu->core_count - 1) << 24;
  51 }
  52 #endif
  53
  54 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
  55 #ifndef CONFIG_USER_ONLY
  56     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  57       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  58       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  59       .writefn = arm_cp_write_ignore },
  60     { .name = "L2CTLR",
  61       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  62       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  63       .writefn = arm_cp_write_ignore },
  64 #endif
  65     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  66       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  67       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  68     { .name = "L2ECTLR",
  69       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  70       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  71     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  72       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  73       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  74     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  75       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  76       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  77     { .name = "CPUACTLR",
  78       .cp = 15, .opc1 = 0, .crm = 15,
  79       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  80     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  81       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  82       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  83     { .name = "CPUECTLR",
  84       .cp = 15, .opc1 = 1, .crm = 15,
  85       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  86     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  87       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  88       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  89     { .name = "CPUMERRSR",
  90       .cp = 15, .opc1 = 2, .crm = 15,
  91       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  92     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  93       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  94       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  95     { .name = "L2MERRSR",
  96       .cp = 15, .opc1 = 3, .crm = 15,
  97       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  98     REGINFO_SENTINEL
  99 };
 100
 101 static void aarch64_a57_initfn(Object *obj)
 102 {
 103     ARMCPU *cpu = ARM_CPU(obj);
 104
 105     cpu->dtb_compatible = "arm,cortex-a57";
 106     set_feature(&cpu->env, ARM_FEATURE_V8);
 107     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 108     set_feature(&cpu->env, ARM_FEATURE_NEON);
 109     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 110     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 111     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 112     set_feature(&cpu->env, ARM_FEATURE_EL2);
 113     set_feature(&cpu->env, ARM_FEATURE_EL3);
 114     set_feature(&cpu->env, ARM_FEATURE_PMU);
 115     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 116     cpu->midr = 0x411fd070;
 117     cpu->revidr = 0x00000000;
 118     cpu->reset_fpsid = 0x41034070;
 119     cpu->isar.mvfr0 = 0x10110222;
 120     cpu->isar.mvfr1 = 0x12111111;
 121     cpu->isar.mvfr2 = 0x00000043;
 122     cpu->ctr = 0x8444c004;
 123     cpu->reset_sctlr = 0x00c50838;
 124     cpu->id_pfr0 = 0x00000131;
 125     cpu->id_pfr1 = 0x00011011;
 126     cpu->id_dfr0 = 0x03010066;
 127     cpu->id_afr0 = 0x00000000;
 128     cpu->id_mmfr0 = 0x10101105;
 129     cpu->id_mmfr1 = 0x40000000;
 130     cpu->id_mmfr2 = 0x01260000;
 131     cpu->id_mmfr3 = 0x02102211;
 132     cpu->isar.id_isar0 = 0x02101110;
 133     cpu->isar.id_isar1 = 0x13112111;
 134     cpu->isar.id_isar2 = 0x21232042;
 135     cpu->isar.id_isar3 = 0x01112131;
 136     cpu->isar.id_isar4 = 0x00011142;
 137     cpu->isar.id_isar5 = 0x00011121;
 138     cpu->isar.id_isar6 = 0;
 139     cpu->isar.id_aa64pfr0 = 0x00002222;
 140     cpu->id_aa64dfr0 = 0x10305106;
 141     cpu->isar.id_aa64isar0 = 0x00011120;
 142     cpu->isar.id_aa64mmfr0 = 0x00001124;
 143     cpu->dbgdidr = 0x3516d000;
 144     cpu->clidr = 0x0a200023;
 145     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 146     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 147     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 148     cpu->dcz_blocksize = 4; /* 64 bytes */
 149     cpu->gic_num_lrs = 4;
 150     cpu->gic_vpribits = 5;
 151     cpu->gic_vprebits = 5;
 152     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 153 }
 154
 155 static void aarch64_a53_initfn(Object *obj)
 156 {
 157     ARMCPU *cpu = ARM_CPU(obj);
 158
 159     cpu->dtb_compatible = "arm,cortex-a53";
 160     set_feature(&cpu->env, ARM_FEATURE_V8);
 161     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 162     set_feature(&cpu->env, ARM_FEATURE_NEON);
 163     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 164     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 165     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 166     set_feature(&cpu->env, ARM_FEATURE_EL2);
 167     set_feature(&cpu->env, ARM_FEATURE_EL3);
 168     set_feature(&cpu->env, ARM_FEATURE_PMU);
 169     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 170     cpu->midr = 0x410fd034;
 171     cpu->revidr = 0x00000000;
 172     cpu->reset_fpsid = 0x41034070;
 173     cpu->isar.mvfr0 = 0x10110222;
 174     cpu->isar.mvfr1 = 0x12111111;
 175     cpu->isar.mvfr2 = 0x00000043;
 176     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 177     cpu->reset_sctlr = 0x00c50838;
 178     cpu->id_pfr0 = 0x00000131;
 179     cpu->id_pfr1 = 0x00011011;
 180     cpu->id_dfr0 = 0x03010066;
 181     cpu->id_afr0 = 0x00000000;
 182     cpu->id_mmfr0 = 0x10101105;
 183     cpu->id_mmfr1 = 0x40000000;
 184     cpu->id_mmfr2 = 0x01260000;
 185     cpu->id_mmfr3 = 0x02102211;
 186     cpu->isar.id_isar0 = 0x02101110;
 187     cpu->isar.id_isar1 = 0x13112111;
 188     cpu->isar.id_isar2 = 0x21232042;
 189     cpu->isar.id_isar3 = 0x01112131;
 190     cpu->isar.id_isar4 = 0x00011142;
 191     cpu->isar.id_isar5 = 0x00011121;
 192     cpu->isar.id_isar6 = 0;
 193     cpu->isar.id_aa64pfr0 = 0x00002222;
 194     cpu->id_aa64dfr0 = 0x10305106;
 195     cpu->isar.id_aa64isar0 = 0x00011120;
 196     cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 197     cpu->dbgdidr = 0x3516d000;
 198     cpu->clidr = 0x0a200023;
 199     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 200     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 201     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 202     cpu->dcz_blocksize = 4; /* 64 bytes */
 203     cpu->gic_num_lrs = 4;
 204     cpu->gic_vpribits = 5;
 205     cpu->gic_vprebits = 5;
 206     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 207 }
 208
 209 static void aarch64_a72_initfn(Object *obj)
 210 {
 211     ARMCPU *cpu = ARM_CPU(obj);
 212
 213     cpu->dtb_compatible = "arm,cortex-a72";
 214     set_feature(&cpu->env, ARM_FEATURE_V8);
 215     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 216     set_feature(&cpu->env, ARM_FEATURE_NEON);
 217     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 218     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 219     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 220     set_feature(&cpu->env, ARM_FEATURE_EL2);
 221     set_feature(&cpu->env, ARM_FEATURE_EL3);
 222     set_feature(&cpu->env, ARM_FEATURE_PMU);
 223     cpu->midr = 0x410fd083;
 224     cpu->revidr = 0x00000000;
 225     cpu->reset_fpsid = 0x41034080;
 226     cpu->isar.mvfr0 = 0x10110222;
 227     cpu->isar.mvfr1 = 0x12111111;
 228     cpu->isar.mvfr2 = 0x00000043;
 229     cpu->ctr = 0x8444c004;
 230     cpu->reset_sctlr = 0x00c50838;
 231     cpu->id_pfr0 = 0x00000131;
 232     cpu->id_pfr1 = 0x00011011;
 233     cpu->id_dfr0 = 0x03010066;
 234     cpu->id_afr0 = 0x00000000;
 235     cpu->id_mmfr0 = 0x10201105;
 236     cpu->id_mmfr1 = 0x40000000;
 237     cpu->id_mmfr2 = 0x01260000;
 238     cpu->id_mmfr3 = 0x02102211;
 239     cpu->isar.id_isar0 = 0x02101110;
 240     cpu->isar.id_isar1 = 0x13112111;
 241     cpu->isar.id_isar2 = 0x21232042;
 242     cpu->isar.id_isar3 = 0x01112131;
 243     cpu->isar.id_isar4 = 0x00011142;
 244     cpu->isar.id_isar5 = 0x00011121;
 245     cpu->isar.id_aa64pfr0 = 0x00002222;
 246     cpu->id_aa64dfr0 = 0x10305106;
 247     cpu->isar.id_aa64isar0 = 0x00011120;
 248     cpu->isar.id_aa64mmfr0 = 0x00001124;
 249     cpu->dbgdidr = 0x3516d000;
 250     cpu->clidr = 0x0a200023;
 251     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 252     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 253     cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 254     cpu->dcz_blocksize = 4; /* 64 bytes */
 255     cpu->gic_num_lrs = 4;
 256     cpu->gic_vpribits = 5;
 257     cpu->gic_vprebits = 5;
 258     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 259 }
 260
 261 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
 262                                void *opaque, Error **errp)
 263 {
 264     ARMCPU *cpu = ARM_CPU(obj);
 265     visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
 266 }
 267
 268 static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
 269                                void *opaque, Error **errp)
 270 {
 271     ARMCPU *cpu = ARM_CPU(obj);
 272     Error *err = NULL;
 273
 274     visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 275
 276     if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
 277         error_setg(&err, "unsupported SVE vector length");
 278         error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
 279                           ARM_MAX_VQ);
 280     }
 281     error_propagate(errp, err);
 282 }
 283
 284 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 285  * otherwise, a CPU with as many features enabled as our emulation supports.
 286  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
 287  * this only needs to handle 64 bits.
 288  */
 289 static void aarch64_max_initfn(Object *obj)
 290 {
 291     ARMCPU *cpu = ARM_CPU(obj);
 292
 293     if (kvm_enabled()) {
 294         kvm_arm_set_cpu_features_from_host(cpu);
 295     } else {
 296         uint64_t t;
 297         uint32_t u;
 298         aarch64_a57_initfn(obj);
 299
 300         t = cpu->isar.id_aa64isar0;
 301         t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
 302         t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
 303         t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
 304         t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 305         t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 306         t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 307         t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 308         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 309         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 310         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 311         t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
 312         t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 313         cpu->isar.id_aa64isar0 = t;
 314
 315         t = cpu->isar.id_aa64isar1;
 316         t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
 317         t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 318         t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
 319         t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
 320         t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
 321         t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
 322         t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 323         t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 324         t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 325         cpu->isar.id_aa64isar1 = t;
 326
 327         t = cpu->isar.id_aa64pfr0;
 328         t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 329         t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 330         t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 331         cpu->isar.id_aa64pfr0 = t;
 332
 333         t = cpu->isar.id_aa64pfr1;
 334         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
 335         cpu->isar.id_aa64pfr1 = t;
 336
 337         t = cpu->isar.id_aa64mmfr1;
 338         t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
 339         t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
 340         cpu->isar.id_aa64mmfr1 = t;
 341
 342         /* Replicate the same data to the 32-bit id registers.  */
 343         u = cpu->isar.id_isar5;
 344         u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
 345         u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
 346         u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
 347         u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
 348         u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
 349         u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
 350         cpu->isar.id_isar5 = u;
 351
 352         u = cpu->isar.id_isar6;
 353         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
 354         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 355         u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
 356         u = FIELD_DP32(u, ID_ISAR6, SB, 1);
 357         u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
 358         cpu->isar.id_isar6 = u;
 359
 360         /*
 361          * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
 362          * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,
 363          * but it is also not legal to enable SVE without support for FP16,
 364          * and enabling SVE in system mode is more useful in the short term.
 365          */
 366
 367 #ifdef CONFIG_USER_ONLY
 368         /* For usermode -cpu max we can use a larger and more efficient DCZ
 369          * blocksize since we don't have to follow what the hardware does.
 370          */
 371         cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 372         cpu->dcz_blocksize = 7; /*  512 bytes */
 373 #endif
 374
 375         cpu->sve_max_vq = ARM_MAX_VQ;
 376         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
 377                             cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
 378     }
 379 }
 380
 381 struct ARMCPUInfo {
 382     const char *name;
 383     void (*initfn)(Object *obj);
 384     void (*class_init)(ObjectClass *oc, void *data);
 385 };
 386
 387 static const ARMCPUInfo aarch64_cpus[] = {
 388     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 389     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 390     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
 391     { .name = "max",                .initfn = aarch64_max_initfn },
 392     { .name = NULL }
 393 };
 394
 395 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 396 {
 397     ARMCPU *cpu = ARM_CPU(obj);
 398
 399     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 400 }
 401
 402 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 403 {
 404     ARMCPU *cpu = ARM_CPU(obj);
 405
 406     /* At this time, this property is only allowed if KVM is enabled.  This
 407      * restriction allows us to avoid fixing up functionality that assumes a
 408      * uniform execution state like do_interrupt.
 409      */
 410     if (!kvm_enabled()) {
 411         error_setg(errp, "'aarch64' feature cannot be disabled "
 412                          "unless KVM is enabled");
 413         return;
 414     }
 415
 416     if (value == false) {
 417         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 418     } else {
 419         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 420     }
 421 }
 422
 423 static void aarch64_cpu_initfn(Object *obj)
 424 {
 425     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 426                              aarch64_cpu_set_aarch64, NULL);
 427     object_property_set_description(obj, "aarch64",
 428                                     "Set on/off to enable/disable aarch64 "
 429                                     "execution state ",
 430                                     NULL);
 431 }
 432
 433 static void aarch64_cpu_finalizefn(Object *obj)
 434 {
 435 }
 436
 437 static gchar *aarch64_gdb_arch_name(CPUState *cs)
 438 {
 439     return g_strdup("aarch64");
 440 }
 441
 442 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 443 {
 444     CPUClass *cc = CPU_CLASS(oc);
 445
 446     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 447     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 448     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 449     cc->gdb_num_core_regs = 34;
 450     cc->gdb_core_xml_file = "aarch64-core.xml";
 451     cc->gdb_arch_name = aarch64_gdb_arch_name;
 452 }
 453
 454 static void aarch64_cpu_instance_init(Object *obj)
 455 {
 456     ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
 457
 458     acc->info->initfn(obj);
 459     arm_cpu_post_init(obj);
 460 }
 461
 462 static void cpu_register_class_init(ObjectClass *oc, void *data)
 463 {
 464     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 465
 466     acc->info = data;
 467 }
 468
 469 static void aarch64_cpu_register(const ARMCPUInfo *info)
 470 {
 471     TypeInfo type_info = {
 472         .parent = TYPE_AARCH64_CPU,
 473         .instance_size = sizeof(ARMCPU),
 474         .instance_init = aarch64_cpu_instance_init,
 475         .class_size = sizeof(ARMCPUClass),
 476         .class_init = info->class_init ?: cpu_register_class_init,
 477         .class_data = (void *)info,
 478     };
 479
 480     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 481     type_register(&type_info);
 482     g_free((void *)type_info.name);
 483 }
 484
 485 static const TypeInfo aarch64_cpu_type_info = {
 486     .name = TYPE_AARCH64_CPU,
 487     .parent = TYPE_ARM_CPU,
 488     .instance_size = sizeof(ARMCPU),
 489     .instance_init = aarch64_cpu_initfn,
 490     .instance_finalize = aarch64_cpu_finalizefn,
 491     .abstract = true,
 492     .class_size = sizeof(AArch64CPUClass),
 493     .class_init = aarch64_cpu_class_init,
 494 };
 495
 496 static void aarch64_cpu_register_types(void)
 497 {
 498     const ARMCPUInfo *info = aarch64_cpus;
 499
 500     type_register_static(&aarch64_cpu_type_info);
 501
 502     while (info->name) {
 503         aarch64_cpu_register(info);
 504         info++;
 505     }
 506 }
 507
 508 type_init(aarch64_cpu_register_types)