4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
121 case ARMMMUIdx_SE20_2
:
122 case ARMMMUIdx_SE20_2_PAN
:
123 useridx
= ARMMMUIdx_SE20_0
;
126 g_assert_not_reached();
129 return arm_to_core_mmu_idx(useridx
);
132 static void reset_btype(DisasContext
*s
)
135 TCGv_i32 zero
= tcg_const_i32(0);
136 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
137 tcg_temp_free_i32(zero
);
142 static void set_btype(DisasContext
*s
, int val
)
146 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
147 tcg_debug_assert(val
>= 1 && val
<= 3);
149 tcg_val
= tcg_const_i32(val
);
150 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
151 tcg_temp_free_i32(tcg_val
);
155 void gen_a64_set_pc_im(uint64_t val
)
157 tcg_gen_movi_i64(cpu_pc
, val
);
161 * Handle Top Byte Ignore (TBI) bits.
163 * If address tagging is enabled via the TCR TBI bits:
164 * + for EL2 and EL3 there is only one TBI bit, and if it is set
165 * then the address is zero-extended, clearing bits [63:56]
166 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
167 * and TBI1 controls addressses with bit 55 == 1.
168 * If the appropriate TBI bit is set for the address then
169 * the address is sign-extended from bit 55 into bits [63:56]
171 * Here We have concatenated TBI{1,0} into tbi.
173 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
174 TCGv_i64 src
, int tbi
)
177 /* Load unmodified address */
178 tcg_gen_mov_i64(dst
, src
);
179 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
180 /* Force tag byte to all zero */
181 tcg_gen_extract_i64(dst
, src
, 0, 56);
183 /* Sign-extend from bit 55. */
184 tcg_gen_sextract_i64(dst
, src
, 0, 56);
188 /* tbi0 but !tbi1: only use the extension if positive */
189 tcg_gen_and_i64(dst
, dst
, src
);
192 /* !tbi0 but tbi1: only use the extension if negative */
193 tcg_gen_or_i64(dst
, dst
, src
);
196 /* tbi0 and tbi1: always use the extension */
199 g_assert_not_reached();
204 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
207 * If address tagging is enabled for instructions via the TCR TBI bits,
208 * then loading an address into the PC will clear out any tag.
210 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
214 * Handle MTE and/or TBI.
216 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
217 * for the tag to be present in the FAR_ELx register. But for user-only
218 * mode we do not have a TLB with which to implement this, so we must
219 * remove the top byte now.
221 * Always return a fresh temporary that we can increment independently
222 * of the write-back address.
225 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
227 TCGv_i64 clean
= new_tmp_a64(s
);
228 #ifdef CONFIG_USER_ONLY
229 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
231 tcg_gen_mov_i64(clean
, addr
);
236 /* Insert a zero tag into src, with the result at dst. */
237 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
239 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
242 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
243 MMUAccessType acc
, int log2_size
)
245 TCGv_i32 t_acc
= tcg_const_i32(acc
);
246 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
247 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
249 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
250 tcg_temp_free_i32(t_acc
);
251 tcg_temp_free_i32(t_idx
);
252 tcg_temp_free_i32(t_size
);
256 * For MTE, check a single logical or atomic access. This probes a single
257 * address, the exact one specified. The size and alignment of the access
258 * is not relevant to MTE, per se, but watchpoints do require the size,
259 * and we want to recognize those before making any other changes to state.
261 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
262 bool is_write
, bool tag_checked
,
263 int log2_size
, bool is_unpriv
,
266 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
271 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
272 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
273 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
274 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
275 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
276 tcg_desc
= tcg_const_i32(desc
);
278 ret
= new_tmp_a64(s
);
279 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
280 tcg_temp_free_i32(tcg_desc
);
284 return clean_data_tbi(s
, addr
);
287 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
288 bool tag_checked
, int log2_size
)
290 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
291 false, get_mem_index(s
));
295 * For MTE, check multiple logical sequential accesses.
297 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
298 bool tag_checked
, int size
)
300 if (tag_checked
&& s
->mte_active
[0]) {
305 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
306 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
307 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
308 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
309 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
310 tcg_desc
= tcg_const_i32(desc
);
312 ret
= new_tmp_a64(s
);
313 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
314 tcg_temp_free_i32(tcg_desc
);
318 return clean_data_tbi(s
, addr
);
321 typedef struct DisasCompare64
{
326 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
330 arm_test_cc(&c32
, cc
);
332 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
333 * properly. The NE/EQ comparisons are also fine with this choice. */
334 c64
->cond
= c32
.cond
;
335 c64
->value
= tcg_temp_new_i64();
336 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
341 static void a64_free_cc(DisasCompare64
*c64
)
343 tcg_temp_free_i64(c64
->value
);
346 static void gen_exception_internal(int excp
)
348 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
350 assert(excp_is_internal(excp
));
351 gen_helper_exception_internal(cpu_env
, tcg_excp
);
352 tcg_temp_free_i32(tcg_excp
);
355 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
357 gen_a64_set_pc_im(pc
);
358 gen_exception_internal(excp
);
359 s
->base
.is_jmp
= DISAS_NORETURN
;
362 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
366 gen_a64_set_pc_im(s
->pc_curr
);
367 tcg_syn
= tcg_const_i32(syndrome
);
368 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
369 tcg_temp_free_i32(tcg_syn
);
370 s
->base
.is_jmp
= DISAS_NORETURN
;
373 static void gen_step_complete_exception(DisasContext
*s
)
375 /* We just completed step of an insn. Move from Active-not-pending
376 * to Active-pending, and then also take the swstep exception.
377 * This corresponds to making the (IMPDEF) choice to prioritize
378 * swstep exceptions over asynchronous exceptions taken to an exception
379 * level where debug is disabled. This choice has the advantage that
380 * we do not need to maintain internal state corresponding to the
381 * ISV/EX syndrome bits between completion of the step and generation
382 * of the exception, and our syndrome information is always correct.
385 gen_swstep_exception(s
, 1, s
->is_ldex
);
386 s
->base
.is_jmp
= DISAS_NORETURN
;
389 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
391 /* No direct tb linking with singlestep (either QEMU's or the ARM
392 * debug architecture kind) or deterministic io
394 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
395 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
399 #ifndef CONFIG_USER_ONLY
400 /* Only link tbs from inside the same guest page */
401 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
409 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
411 const TranslationBlock
*tb
;
414 if (use_goto_tb(s
, n
, dest
)) {
416 gen_a64_set_pc_im(dest
);
417 tcg_gen_exit_tb(tb
, n
);
418 s
->base
.is_jmp
= DISAS_NORETURN
;
420 gen_a64_set_pc_im(dest
);
422 gen_step_complete_exception(s
);
423 } else if (s
->base
.singlestep_enabled
) {
424 gen_exception_internal(EXCP_DEBUG
);
426 tcg_gen_lookup_and_goto_ptr();
427 s
->base
.is_jmp
= DISAS_NORETURN
;
432 static void init_tmp_a64_array(DisasContext
*s
)
434 #ifdef CONFIG_DEBUG_TCG
435 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
437 s
->tmp_a64_count
= 0;
440 static void free_tmp_a64(DisasContext
*s
)
443 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
444 tcg_temp_free_i64(s
->tmp_a64
[i
]);
446 init_tmp_a64_array(s
);
449 TCGv_i64
new_tmp_a64(DisasContext
*s
)
451 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
452 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
455 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
457 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
458 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
461 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
463 TCGv_i64 t
= new_tmp_a64(s
);
464 tcg_gen_movi_i64(t
, 0);
469 * Register access functions
471 * These functions are used for directly accessing a register in where
472 * changes to the final register value are likely to be made. If you
473 * need to use a register for temporary calculation (e.g. index type
474 * operations) use the read_* form.
476 * B1.2.1 Register mappings
478 * In instruction register encoding 31 can refer to ZR (zero register) or
479 * the SP (stack pointer) depending on context. In QEMU's case we map SP
480 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
481 * This is the point of the _sp forms.
483 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
486 return new_tmp_a64_zero(s
);
492 /* register access for when 31 == SP */
493 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
498 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
499 * representing the register contents. This TCGv is an auto-freed
500 * temporary so it need not be explicitly freed, and may be modified.
502 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
504 TCGv_i64 v
= new_tmp_a64(s
);
507 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
509 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
512 tcg_gen_movi_i64(v
, 0);
517 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
519 TCGv_i64 v
= new_tmp_a64(s
);
521 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
523 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
528 /* Return the offset into CPUARMState of a slice (from
529 * the least significant end) of FP register Qn (ie
531 * (Note that this is not the same mapping as for A32; see cpu.h)
533 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
535 return vec_reg_offset(s
, regno
, 0, size
);
538 /* Offset of the high half of the 128 bit vector Qn */
539 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
541 return vec_reg_offset(s
, regno
, 1, MO_64
);
544 /* Convenience accessors for reading and writing single and double
545 * FP registers. Writing clears the upper parts of the associated
546 * 128 bit vector register, as required by the architecture.
547 * Note that unlike the GP register accessors, the values returned
548 * by the read functions must be manually freed.
550 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
552 TCGv_i64 v
= tcg_temp_new_i64();
554 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
558 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
560 TCGv_i32 v
= tcg_temp_new_i32();
562 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
566 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
568 TCGv_i32 v
= tcg_temp_new_i32();
570 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
574 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
575 * If SVE is not enabled, then there are only 128 bits in the vector.
577 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
579 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
580 unsigned vsz
= vec_full_reg_size(s
);
582 /* Nop move, with side effect of clearing the tail. */
583 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
586 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
588 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
590 tcg_gen_st_i64(v
, cpu_env
, ofs
);
591 clear_vec_high(s
, false, reg
);
594 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
596 TCGv_i64 tmp
= tcg_temp_new_i64();
598 tcg_gen_extu_i32_i64(tmp
, v
);
599 write_fp_dreg(s
, reg
, tmp
);
600 tcg_temp_free_i64(tmp
);
603 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
604 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
605 GVecGen2Fn
*gvec_fn
, int vece
)
607 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
608 is_q
? 16 : 8, vec_full_reg_size(s
));
611 /* Expand a 2-operand + immediate AdvSIMD vector operation using
612 * an expander function.
614 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
615 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
617 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
618 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
621 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
622 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
623 GVecGen3Fn
*gvec_fn
, int vece
)
625 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
626 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
629 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
630 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
631 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
633 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
634 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
635 is_q
? 16 : 8, vec_full_reg_size(s
));
638 /* Expand a 2-operand operation using an out-of-line helper. */
639 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
640 int rn
, int data
, gen_helper_gvec_2
*fn
)
642 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
643 vec_full_reg_offset(s
, rn
),
644 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
647 /* Expand a 3-operand operation using an out-of-line helper. */
648 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
649 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
651 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
652 vec_full_reg_offset(s
, rn
),
653 vec_full_reg_offset(s
, rm
),
654 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
657 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
658 * an out-of-line helper.
660 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
661 int rm
, bool is_fp16
, int data
,
662 gen_helper_gvec_3_ptr
*fn
)
664 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
665 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
666 vec_full_reg_offset(s
, rn
),
667 vec_full_reg_offset(s
, rm
), fpst
,
668 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
669 tcg_temp_free_ptr(fpst
);
672 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
673 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
674 int rm
, gen_helper_gvec_3_ptr
*fn
)
676 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
678 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
679 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
680 vec_full_reg_offset(s
, rn
),
681 vec_full_reg_offset(s
, rm
), qc_ptr
,
682 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
683 tcg_temp_free_ptr(qc_ptr
);
686 /* Expand a 4-operand operation using an out-of-line helper. */
687 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
688 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
690 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
691 vec_full_reg_offset(s
, rn
),
692 vec_full_reg_offset(s
, rm
),
693 vec_full_reg_offset(s
, ra
),
694 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
698 * Expand a 4-operand + fpstatus pointer + simd data value operation using
699 * an out-of-line helper.
701 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
702 int rm
, int ra
, bool is_fp16
, int data
,
703 gen_helper_gvec_4_ptr
*fn
)
705 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
706 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
707 vec_full_reg_offset(s
, rn
),
708 vec_full_reg_offset(s
, rm
),
709 vec_full_reg_offset(s
, ra
), fpst
,
710 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
711 tcg_temp_free_ptr(fpst
);
714 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
715 * than the 32 bit equivalent.
717 static inline void gen_set_NZ64(TCGv_i64 result
)
719 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
720 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
723 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
724 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
727 gen_set_NZ64(result
);
729 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
730 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
732 tcg_gen_movi_i32(cpu_CF
, 0);
733 tcg_gen_movi_i32(cpu_VF
, 0);
736 /* dest = T0 + T1; compute C, N, V and Z flags */
737 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
740 TCGv_i64 result
, flag
, tmp
;
741 result
= tcg_temp_new_i64();
742 flag
= tcg_temp_new_i64();
743 tmp
= tcg_temp_new_i64();
745 tcg_gen_movi_i64(tmp
, 0);
746 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
748 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
750 gen_set_NZ64(result
);
752 tcg_gen_xor_i64(flag
, result
, t0
);
753 tcg_gen_xor_i64(tmp
, t0
, t1
);
754 tcg_gen_andc_i64(flag
, flag
, tmp
);
755 tcg_temp_free_i64(tmp
);
756 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
758 tcg_gen_mov_i64(dest
, result
);
759 tcg_temp_free_i64(result
);
760 tcg_temp_free_i64(flag
);
762 /* 32 bit arithmetic */
763 TCGv_i32 t0_32
= tcg_temp_new_i32();
764 TCGv_i32 t1_32
= tcg_temp_new_i32();
765 TCGv_i32 tmp
= tcg_temp_new_i32();
767 tcg_gen_movi_i32(tmp
, 0);
768 tcg_gen_extrl_i64_i32(t0_32
, t0
);
769 tcg_gen_extrl_i64_i32(t1_32
, t1
);
770 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
771 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
772 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
773 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
774 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
775 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
777 tcg_temp_free_i32(tmp
);
778 tcg_temp_free_i32(t0_32
);
779 tcg_temp_free_i32(t1_32
);
783 /* dest = T0 - T1; compute C, N, V and Z flags */
784 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
787 /* 64 bit arithmetic */
788 TCGv_i64 result
, flag
, tmp
;
790 result
= tcg_temp_new_i64();
791 flag
= tcg_temp_new_i64();
792 tcg_gen_sub_i64(result
, t0
, t1
);
794 gen_set_NZ64(result
);
796 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
797 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
799 tcg_gen_xor_i64(flag
, result
, t0
);
800 tmp
= tcg_temp_new_i64();
801 tcg_gen_xor_i64(tmp
, t0
, t1
);
802 tcg_gen_and_i64(flag
, flag
, tmp
);
803 tcg_temp_free_i64(tmp
);
804 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
805 tcg_gen_mov_i64(dest
, result
);
806 tcg_temp_free_i64(flag
);
807 tcg_temp_free_i64(result
);
809 /* 32 bit arithmetic */
810 TCGv_i32 t0_32
= tcg_temp_new_i32();
811 TCGv_i32 t1_32
= tcg_temp_new_i32();
814 tcg_gen_extrl_i64_i32(t0_32
, t0
);
815 tcg_gen_extrl_i64_i32(t1_32
, t1
);
816 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
817 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
818 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
819 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
820 tmp
= tcg_temp_new_i32();
821 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
822 tcg_temp_free_i32(t0_32
);
823 tcg_temp_free_i32(t1_32
);
824 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
825 tcg_temp_free_i32(tmp
);
826 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
830 /* dest = T0 + T1 + CF; do not compute flags. */
831 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
833 TCGv_i64 flag
= tcg_temp_new_i64();
834 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
835 tcg_gen_add_i64(dest
, t0
, t1
);
836 tcg_gen_add_i64(dest
, dest
, flag
);
837 tcg_temp_free_i64(flag
);
840 tcg_gen_ext32u_i64(dest
, dest
);
844 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
845 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
848 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
849 result
= tcg_temp_new_i64();
850 cf_64
= tcg_temp_new_i64();
851 vf_64
= tcg_temp_new_i64();
852 tmp
= tcg_const_i64(0);
854 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
855 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
856 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
857 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
858 gen_set_NZ64(result
);
860 tcg_gen_xor_i64(vf_64
, result
, t0
);
861 tcg_gen_xor_i64(tmp
, t0
, t1
);
862 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
863 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
865 tcg_gen_mov_i64(dest
, result
);
867 tcg_temp_free_i64(tmp
);
868 tcg_temp_free_i64(vf_64
);
869 tcg_temp_free_i64(cf_64
);
870 tcg_temp_free_i64(result
);
872 TCGv_i32 t0_32
, t1_32
, tmp
;
873 t0_32
= tcg_temp_new_i32();
874 t1_32
= tcg_temp_new_i32();
875 tmp
= tcg_const_i32(0);
877 tcg_gen_extrl_i64_i32(t0_32
, t0
);
878 tcg_gen_extrl_i64_i32(t1_32
, t1
);
879 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
880 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
882 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
883 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
884 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
885 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
886 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
888 tcg_temp_free_i32(tmp
);
889 tcg_temp_free_i32(t1_32
);
890 tcg_temp_free_i32(t0_32
);
895 * Load/Store generators
899 * Store from GPR register to memory.
901 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
902 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
904 unsigned int iss_srt
,
905 bool iss_sf
, bool iss_ar
)
907 memop
= finalize_memop(s
, memop
);
908 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
913 syn
= syn_data_abort_with_iss(0,
919 0, 0, 0, 0, 0, false);
920 disas_set_insn_syndrome(s
, syn
);
924 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
925 TCGv_i64 tcg_addr
, MemOp memop
,
927 unsigned int iss_srt
,
928 bool iss_sf
, bool iss_ar
)
930 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
931 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
935 * Load from memory to GPR register
937 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
938 MemOp memop
, bool extend
, int memidx
,
939 bool iss_valid
, unsigned int iss_srt
,
940 bool iss_sf
, bool iss_ar
)
942 memop
= finalize_memop(s
, memop
);
943 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
945 if (extend
&& (memop
& MO_SIGN
)) {
946 g_assert((memop
& MO_SIZE
) <= MO_32
);
947 tcg_gen_ext32u_i64(dest
, dest
);
953 syn
= syn_data_abort_with_iss(0,
955 (memop
& MO_SIGN
) != 0,
959 0, 0, 0, 0, 0, false);
960 disas_set_insn_syndrome(s
, syn
);
964 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
965 MemOp memop
, bool extend
,
966 bool iss_valid
, unsigned int iss_srt
,
967 bool iss_sf
, bool iss_ar
)
969 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
970 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
974 * Store from FP register to memory
976 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
978 /* This writes the bottom N bits of a 128 bit wide vector to memory */
979 TCGv_i64 tmplo
= tcg_temp_new_i64();
982 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
985 mop
= finalize_memop(s
, size
);
986 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
988 bool be
= s
->be_data
== MO_BE
;
989 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
990 TCGv_i64 tmphi
= tcg_temp_new_i64();
992 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
994 mop
= s
->be_data
| MO_Q
;
995 tcg_gen_qemu_st_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
996 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
997 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
998 tcg_gen_qemu_st_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
999 get_mem_index(s
), mop
);
1001 tcg_temp_free_i64(tcg_hiaddr
);
1002 tcg_temp_free_i64(tmphi
);
1005 tcg_temp_free_i64(tmplo
);
1009 * Load from memory to FP register
1011 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1013 /* This always zero-extends and writes to a full 128 bit wide vector */
1014 TCGv_i64 tmplo
= tcg_temp_new_i64();
1015 TCGv_i64 tmphi
= NULL
;
1019 mop
= finalize_memop(s
, size
);
1020 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
1022 bool be
= s
->be_data
== MO_BE
;
1023 TCGv_i64 tcg_hiaddr
;
1025 tmphi
= tcg_temp_new_i64();
1026 tcg_hiaddr
= tcg_temp_new_i64();
1028 mop
= s
->be_data
| MO_Q
;
1029 tcg_gen_qemu_ld_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
1030 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
1031 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1032 tcg_gen_qemu_ld_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
1033 get_mem_index(s
), mop
);
1034 tcg_temp_free_i64(tcg_hiaddr
);
1037 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1038 tcg_temp_free_i64(tmplo
);
1041 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1042 tcg_temp_free_i64(tmphi
);
1044 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1048 * Vector load/store helpers.
1050 * The principal difference between this and a FP load is that we don't
1051 * zero extend as we are filling a partial chunk of the vector register.
1052 * These functions don't support 128 bit loads/stores, which would be
1053 * normal load/store operations.
1055 * The _i32 versions are useful when operating on 32 bit quantities
1056 * (eg for floating point single or using Neon helper functions).
1059 /* Get value of an element within a vector register */
1060 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1061 int element
, MemOp memop
)
1063 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1066 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1069 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1072 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1075 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1078 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1081 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1085 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1088 g_assert_not_reached();
1092 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1093 int element
, MemOp memop
)
1095 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1098 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1101 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1104 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1107 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1114 g_assert_not_reached();
1118 /* Set value of an element within a vector register */
1119 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1120 int element
, MemOp memop
)
1122 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1125 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1128 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1131 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1134 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1137 g_assert_not_reached();
1141 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1142 int destidx
, int element
, MemOp memop
)
1144 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1147 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1150 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1153 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1156 g_assert_not_reached();
1160 /* Store from vector register to memory */
1161 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1162 TCGv_i64 tcg_addr
, MemOp mop
)
1164 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1166 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1167 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1169 tcg_temp_free_i64(tcg_tmp
);
1172 /* Load from memory to vector register */
1173 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1174 TCGv_i64 tcg_addr
, MemOp mop
)
1176 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1178 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1179 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1181 tcg_temp_free_i64(tcg_tmp
);
1184 /* Check that FP/Neon access is enabled. If it is, return
1185 * true. If not, emit code to generate an appropriate exception,
1186 * and return false; the caller should not emit any code for
1187 * the instruction. Note that this check must happen after all
1188 * unallocated-encoding checks (otherwise the syndrome information
1189 * for the resulting exception will be incorrect).
1191 static bool fp_access_check(DisasContext
*s
)
1193 if (s
->fp_excp_el
) {
1194 assert(!s
->fp_access_checked
);
1195 s
->fp_access_checked
= true;
1197 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1198 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1201 s
->fp_access_checked
= true;
1205 /* Check that SVE access is enabled. If it is, return true.
1206 * If not, emit code to generate an appropriate exception and return false.
1208 bool sve_access_check(DisasContext
*s
)
1210 if (s
->sve_excp_el
) {
1211 assert(!s
->sve_access_checked
);
1212 s
->sve_access_checked
= true;
1214 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1215 syn_sve_access_trap(), s
->sve_excp_el
);
1218 s
->sve_access_checked
= true;
1219 return fp_access_check(s
);
1223 * This utility function is for doing register extension with an
1224 * optional shift. You will likely want to pass a temporary for the
1225 * destination register. See DecodeRegExtend() in the ARM ARM.
1227 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1228 int option
, unsigned int shift
)
1230 int extsize
= extract32(option
, 0, 2);
1231 bool is_signed
= extract32(option
, 2, 1);
1236 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1239 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1242 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1245 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1251 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1254 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1257 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1260 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1266 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1270 static inline void gen_check_sp_alignment(DisasContext
*s
)
1272 /* The AArch64 architecture mandates that (if enabled via PSTATE
1273 * or SCTLR bits) there is a check that SP is 16-aligned on every
1274 * SP-relative load or store (with an exception generated if it is not).
1275 * In line with general QEMU practice regarding misaligned accesses,
1276 * we omit these checks for the sake of guest program performance.
1277 * This function is provided as a hook so we can more easily add these
1278 * checks in future (possibly as a "favour catching guest program bugs
1279 * over speed" user selectable option).
1284 * This provides a simple table based table lookup decoder. It is
1285 * intended to be used when the relevant bits for decode are too
1286 * awkwardly placed and switch/if based logic would be confusing and
1287 * deeply nested. Since it's a linear search through the table, tables
1288 * should be kept small.
1290 * It returns the first handler where insn & mask == pattern, or
1291 * NULL if there is no match.
1292 * The table is terminated by an empty mask (i.e. 0)
1294 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1297 const AArch64DecodeTable
*tptr
= table
;
1299 while (tptr
->mask
) {
1300 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1301 return tptr
->disas_fn
;
1309 * The instruction disassembly implemented here matches
1310 * the instruction encoding classifications in chapter C4
1311 * of the ARM Architecture Reference Manual (DDI0487B_a);
1312 * classification names and decode diagrams here should generally
1313 * match up with those in the manual.
1316 /* Unconditional branch (immediate)
1318 * +----+-----------+-------------------------------------+
1319 * | op | 0 0 1 0 1 | imm26 |
1320 * +----+-----------+-------------------------------------+
1322 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1324 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1326 if (insn
& (1U << 31)) {
1327 /* BL Branch with link */
1328 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1331 /* B Branch / BL Branch with link */
1333 gen_goto_tb(s
, 0, addr
);
1336 /* Compare and branch (immediate)
1337 * 31 30 25 24 23 5 4 0
1338 * +----+-------------+----+---------------------+--------+
1339 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1340 * +----+-------------+----+---------------------+--------+
1342 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1344 unsigned int sf
, op
, rt
;
1346 TCGLabel
*label_match
;
1349 sf
= extract32(insn
, 31, 1);
1350 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1351 rt
= extract32(insn
, 0, 5);
1352 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1354 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1355 label_match
= gen_new_label();
1358 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1359 tcg_cmp
, 0, label_match
);
1361 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1362 gen_set_label(label_match
);
1363 gen_goto_tb(s
, 1, addr
);
1366 /* Test and branch (immediate)
1367 * 31 30 25 24 23 19 18 5 4 0
1368 * +----+-------------+----+-------+-------------+------+
1369 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1370 * +----+-------------+----+-------+-------------+------+
1372 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1374 unsigned int bit_pos
, op
, rt
;
1376 TCGLabel
*label_match
;
1379 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1380 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1381 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1382 rt
= extract32(insn
, 0, 5);
1384 tcg_cmp
= tcg_temp_new_i64();
1385 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1386 label_match
= gen_new_label();
1389 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1390 tcg_cmp
, 0, label_match
);
1391 tcg_temp_free_i64(tcg_cmp
);
1392 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1393 gen_set_label(label_match
);
1394 gen_goto_tb(s
, 1, addr
);
1397 /* Conditional branch (immediate)
1398 * 31 25 24 23 5 4 3 0
1399 * +---------------+----+---------------------+----+------+
1400 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1401 * +---------------+----+---------------------+----+------+
1403 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1408 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1409 unallocated_encoding(s
);
1412 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1413 cond
= extract32(insn
, 0, 4);
1417 /* genuinely conditional branches */
1418 TCGLabel
*label_match
= gen_new_label();
1419 arm_gen_test_cc(cond
, label_match
);
1420 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1421 gen_set_label(label_match
);
1422 gen_goto_tb(s
, 1, addr
);
1424 /* 0xe and 0xf are both "always" conditions */
1425 gen_goto_tb(s
, 0, addr
);
1429 /* HINT instruction group, including various allocated HINTs */
1430 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1431 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1433 unsigned int selector
= crm
<< 3 | op2
;
1436 unallocated_encoding(s
);
1441 case 0b00000: /* NOP */
1443 case 0b00011: /* WFI */
1444 s
->base
.is_jmp
= DISAS_WFI
;
1446 case 0b00001: /* YIELD */
1447 /* When running in MTTCG we don't generate jumps to the yield and
1448 * WFE helpers as it won't affect the scheduling of other vCPUs.
1449 * If we wanted to more completely model WFE/SEV so we don't busy
1450 * spin unnecessarily we would need to do something more involved.
1452 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1453 s
->base
.is_jmp
= DISAS_YIELD
;
1456 case 0b00010: /* WFE */
1457 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1458 s
->base
.is_jmp
= DISAS_WFE
;
1461 case 0b00100: /* SEV */
1462 case 0b00101: /* SEVL */
1463 /* we treat all as NOP at least for now */
1465 case 0b00111: /* XPACLRI */
1466 if (s
->pauth_active
) {
1467 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1470 case 0b01000: /* PACIA1716 */
1471 if (s
->pauth_active
) {
1472 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1475 case 0b01010: /* PACIB1716 */
1476 if (s
->pauth_active
) {
1477 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1480 case 0b01100: /* AUTIA1716 */
1481 if (s
->pauth_active
) {
1482 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1485 case 0b01110: /* AUTIB1716 */
1486 if (s
->pauth_active
) {
1487 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1490 case 0b11000: /* PACIAZ */
1491 if (s
->pauth_active
) {
1492 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1493 new_tmp_a64_zero(s
));
1496 case 0b11001: /* PACIASP */
1497 if (s
->pauth_active
) {
1498 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1501 case 0b11010: /* PACIBZ */
1502 if (s
->pauth_active
) {
1503 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1504 new_tmp_a64_zero(s
));
1507 case 0b11011: /* PACIBSP */
1508 if (s
->pauth_active
) {
1509 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1512 case 0b11100: /* AUTIAZ */
1513 if (s
->pauth_active
) {
1514 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1515 new_tmp_a64_zero(s
));
1518 case 0b11101: /* AUTIASP */
1519 if (s
->pauth_active
) {
1520 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1523 case 0b11110: /* AUTIBZ */
1524 if (s
->pauth_active
) {
1525 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1526 new_tmp_a64_zero(s
));
1529 case 0b11111: /* AUTIBSP */
1530 if (s
->pauth_active
) {
1531 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1535 /* default specified as NOP equivalent */
1540 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1542 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1545 /* CLREX, DSB, DMB, ISB */
1546 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1547 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1552 unallocated_encoding(s
);
1563 case 1: /* MBReqTypes_Reads */
1564 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1566 case 2: /* MBReqTypes_Writes */
1567 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1569 default: /* MBReqTypes_All */
1570 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1576 /* We need to break the TB after this insn to execute
1577 * a self-modified code correctly and also to take
1578 * any pending interrupts immediately.
1581 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1585 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1586 goto do_unallocated
;
1589 * TODO: There is no speculation barrier opcode for TCG;
1590 * MB and end the TB instead.
1592 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1593 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1598 unallocated_encoding(s
);
1603 static void gen_xaflag(void)
1605 TCGv_i32 z
= tcg_temp_new_i32();
1607 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1616 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1617 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1620 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1621 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1623 /* (!C & Z) << 31 -> -(Z & ~C) */
1624 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1625 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1628 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1630 tcg_temp_free_i32(z
);
1633 static void gen_axflag(void)
1635 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1636 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1638 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1639 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1641 tcg_gen_movi_i32(cpu_NF
, 0);
1642 tcg_gen_movi_i32(cpu_VF
, 0);
1645 /* MSR (immediate) - move immediate to processor state field */
1646 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1647 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1650 int op
= op1
<< 3 | op2
;
1652 /* End the TB by default, chaining is ok. */
1653 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1656 case 0x00: /* CFINV */
1657 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1658 goto do_unallocated
;
1660 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1661 s
->base
.is_jmp
= DISAS_NEXT
;
1664 case 0x01: /* XAFlag */
1665 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1666 goto do_unallocated
;
1669 s
->base
.is_jmp
= DISAS_NEXT
;
1672 case 0x02: /* AXFlag */
1673 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1674 goto do_unallocated
;
1677 s
->base
.is_jmp
= DISAS_NEXT
;
1680 case 0x03: /* UAO */
1681 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1682 goto do_unallocated
;
1685 set_pstate_bits(PSTATE_UAO
);
1687 clear_pstate_bits(PSTATE_UAO
);
1689 t1
= tcg_const_i32(s
->current_el
);
1690 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1691 tcg_temp_free_i32(t1
);
1694 case 0x04: /* PAN */
1695 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1696 goto do_unallocated
;
1699 set_pstate_bits(PSTATE_PAN
);
1701 clear_pstate_bits(PSTATE_PAN
);
1703 t1
= tcg_const_i32(s
->current_el
);
1704 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1705 tcg_temp_free_i32(t1
);
1708 case 0x05: /* SPSel */
1709 if (s
->current_el
== 0) {
1710 goto do_unallocated
;
1712 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1713 gen_helper_msr_i_spsel(cpu_env
, t1
);
1714 tcg_temp_free_i32(t1
);
1717 case 0x19: /* SSBS */
1718 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1719 goto do_unallocated
;
1722 set_pstate_bits(PSTATE_SSBS
);
1724 clear_pstate_bits(PSTATE_SSBS
);
1726 /* Don't need to rebuild hflags since SSBS is a nop */
1729 case 0x1a: /* DIT */
1730 if (!dc_isar_feature(aa64_dit
, s
)) {
1731 goto do_unallocated
;
1734 set_pstate_bits(PSTATE_DIT
);
1736 clear_pstate_bits(PSTATE_DIT
);
1738 /* There's no need to rebuild hflags because DIT is a nop */
1741 case 0x1e: /* DAIFSet */
1742 t1
= tcg_const_i32(crm
);
1743 gen_helper_msr_i_daifset(cpu_env
, t1
);
1744 tcg_temp_free_i32(t1
);
1747 case 0x1f: /* DAIFClear */
1748 t1
= tcg_const_i32(crm
);
1749 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1750 tcg_temp_free_i32(t1
);
1751 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1752 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1755 case 0x1c: /* TCO */
1756 if (dc_isar_feature(aa64_mte
, s
)) {
1757 /* Full MTE is enabled -- set the TCO bit as directed. */
1759 set_pstate_bits(PSTATE_TCO
);
1761 clear_pstate_bits(PSTATE_TCO
);
1763 t1
= tcg_const_i32(s
->current_el
);
1764 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1765 tcg_temp_free_i32(t1
);
1766 /* Many factors, including TCO, go into MTE_ACTIVE. */
1767 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1768 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1769 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1770 s
->base
.is_jmp
= DISAS_NEXT
;
1772 goto do_unallocated
;
1778 unallocated_encoding(s
);
1783 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1785 TCGv_i32 tmp
= tcg_temp_new_i32();
1786 TCGv_i32 nzcv
= tcg_temp_new_i32();
1788 /* build bit 31, N */
1789 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1790 /* build bit 30, Z */
1791 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1792 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1793 /* build bit 29, C */
1794 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1795 /* build bit 28, V */
1796 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1797 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1798 /* generate result */
1799 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1801 tcg_temp_free_i32(nzcv
);
1802 tcg_temp_free_i32(tmp
);
1805 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1807 TCGv_i32 nzcv
= tcg_temp_new_i32();
1809 /* take NZCV from R[t] */
1810 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1813 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1815 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1816 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1818 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1819 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1821 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1822 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1823 tcg_temp_free_i32(nzcv
);
1826 /* MRS - move from system register
1827 * MSR (register) - move to system register
1830 * These are all essentially the same insn in 'read' and 'write'
1831 * versions, with varying op0 fields.
1833 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1834 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1835 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1837 const ARMCPRegInfo
*ri
;
1840 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1841 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1842 crn
, crm
, op0
, op1
, op2
));
1845 /* Unknown register; this might be a guest error or a QEMU
1846 * unimplemented feature.
1848 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1849 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1850 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1851 unallocated_encoding(s
);
1855 /* Check access permissions */
1856 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1857 unallocated_encoding(s
);
1862 /* Emit code to perform further access permissions checks at
1863 * runtime; this may result in an exception.
1866 TCGv_i32 tcg_syn
, tcg_isread
;
1869 gen_a64_set_pc_im(s
->pc_curr
);
1870 tmpptr
= tcg_const_ptr(ri
);
1871 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1872 tcg_syn
= tcg_const_i32(syndrome
);
1873 tcg_isread
= tcg_const_i32(isread
);
1874 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1875 tcg_temp_free_ptr(tmpptr
);
1876 tcg_temp_free_i32(tcg_syn
);
1877 tcg_temp_free_i32(tcg_isread
);
1878 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1880 * The readfn or writefn might raise an exception;
1881 * synchronize the CPU state in case it does.
1883 gen_a64_set_pc_im(s
->pc_curr
);
1886 /* Handle special cases first */
1887 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1891 tcg_rt
= cpu_reg(s
, rt
);
1893 gen_get_nzcv(tcg_rt
);
1895 gen_set_nzcv(tcg_rt
);
1898 case ARM_CP_CURRENTEL
:
1899 /* Reads as current EL value from pstate, which is
1900 * guaranteed to be constant by the tb flags.
1902 tcg_rt
= cpu_reg(s
, rt
);
1903 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1906 /* Writes clear the aligned block of memory which rt points into. */
1907 if (s
->mte_active
[0]) {
1911 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1912 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1913 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1914 t_desc
= tcg_const_i32(desc
);
1916 tcg_rt
= new_tmp_a64(s
);
1917 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1918 tcg_temp_free_i32(t_desc
);
1920 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1922 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1926 TCGv_i64 clean_addr
, tag
;
1929 * DC_GVA, like DC_ZVA, requires that we supply the original
1930 * pointer for an invalid page. Probe that address first.
1932 tcg_rt
= cpu_reg(s
, rt
);
1933 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1934 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1937 /* Extract the tag from the register to match STZGM. */
1938 tag
= tcg_temp_new_i64();
1939 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1940 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1941 tcg_temp_free_i64(tag
);
1945 case ARM_CP_DC_GZVA
:
1947 TCGv_i64 clean_addr
, tag
;
1949 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1950 tcg_rt
= cpu_reg(s
, rt
);
1951 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1952 gen_helper_dc_zva(cpu_env
, clean_addr
);
1955 /* Extract the tag from the register to match STZGM. */
1956 tag
= tcg_temp_new_i64();
1957 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1958 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1959 tcg_temp_free_i64(tag
);
1966 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1968 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1972 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1976 tcg_rt
= cpu_reg(s
, rt
);
1979 if (ri
->type
& ARM_CP_CONST
) {
1980 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1981 } else if (ri
->readfn
) {
1983 tmpptr
= tcg_const_ptr(ri
);
1984 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1985 tcg_temp_free_ptr(tmpptr
);
1987 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1990 if (ri
->type
& ARM_CP_CONST
) {
1991 /* If not forbidden by access permissions, treat as WI */
1993 } else if (ri
->writefn
) {
1995 tmpptr
= tcg_const_ptr(ri
);
1996 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1997 tcg_temp_free_ptr(tmpptr
);
1999 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2003 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
2004 /* I/O operations must end the TB here (whether read or write) */
2005 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2007 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
2009 * A write to any coprocessor regiser that ends a TB
2010 * must rebuild the hflags for the next TB.
2012 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
2013 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
2014 tcg_temp_free_i32(tcg_el
);
2016 * We default to ending the TB on a coprocessor register write,
2017 * but allow this to be suppressed by the register definition
2018 * (usually only necessary to work around guest bugs).
2020 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2025 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2026 * +---------------------+---+-----+-----+-------+-------+-----+------+
2027 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2028 * +---------------------+---+-----+-----+-------+-------+-----+------+
2030 static void disas_system(DisasContext
*s
, uint32_t insn
)
2032 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2033 l
= extract32(insn
, 21, 1);
2034 op0
= extract32(insn
, 19, 2);
2035 op1
= extract32(insn
, 16, 3);
2036 crn
= extract32(insn
, 12, 4);
2037 crm
= extract32(insn
, 8, 4);
2038 op2
= extract32(insn
, 5, 3);
2039 rt
= extract32(insn
, 0, 5);
2042 if (l
|| rt
!= 31) {
2043 unallocated_encoding(s
);
2047 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2048 handle_hint(s
, insn
, op1
, op2
, crm
);
2050 case 3: /* CLREX, DSB, DMB, ISB */
2051 handle_sync(s
, insn
, op1
, op2
, crm
);
2053 case 4: /* MSR (immediate) */
2054 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2057 unallocated_encoding(s
);
2062 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2065 /* Exception generation
2067 * 31 24 23 21 20 5 4 2 1 0
2068 * +-----------------+-----+------------------------+-----+----+
2069 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2070 * +-----------------------+------------------------+----------+
2072 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2074 int opc
= extract32(insn
, 21, 3);
2075 int op2_ll
= extract32(insn
, 0, 5);
2076 int imm16
= extract32(insn
, 5, 16);
2081 /* For SVC, HVC and SMC we advance the single-step state
2082 * machine before taking the exception. This is architecturally
2083 * mandated, to ensure that single-stepping a system call
2084 * instruction works properly.
2089 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2090 syn_aa64_svc(imm16
), default_exception_el(s
));
2093 if (s
->current_el
== 0) {
2094 unallocated_encoding(s
);
2097 /* The pre HVC helper handles cases when HVC gets trapped
2098 * as an undefined insn by runtime configuration.
2100 gen_a64_set_pc_im(s
->pc_curr
);
2101 gen_helper_pre_hvc(cpu_env
);
2103 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2104 syn_aa64_hvc(imm16
), 2);
2107 if (s
->current_el
== 0) {
2108 unallocated_encoding(s
);
2111 gen_a64_set_pc_im(s
->pc_curr
);
2112 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2113 gen_helper_pre_smc(cpu_env
, tmp
);
2114 tcg_temp_free_i32(tmp
);
2116 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2117 syn_aa64_smc(imm16
), 3);
2120 unallocated_encoding(s
);
2126 unallocated_encoding(s
);
2130 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2134 unallocated_encoding(s
);
2137 /* HLT. This has two purposes.
2138 * Architecturally, it is an external halting debug instruction.
2139 * Since QEMU doesn't implement external debug, we treat this as
2140 * it is required for halting debug disabled: it will UNDEF.
2141 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2143 if (semihosting_enabled() && imm16
== 0xf000) {
2144 #ifndef CONFIG_USER_ONLY
2145 /* In system mode, don't allow userspace access to semihosting,
2146 * to provide some semblance of security (and for consistency
2147 * with our 32-bit semihosting).
2149 if (s
->current_el
== 0) {
2150 unsupported_encoding(s
, insn
);
2154 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2156 unsupported_encoding(s
, insn
);
2160 if (op2_ll
< 1 || op2_ll
> 3) {
2161 unallocated_encoding(s
);
2164 /* DCPS1, DCPS2, DCPS3 */
2165 unsupported_encoding(s
, insn
);
2168 unallocated_encoding(s
);
2173 /* Unconditional branch (register)
2174 * 31 25 24 21 20 16 15 10 9 5 4 0
2175 * +---------------+-------+-------+-------+------+-------+
2176 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2177 * +---------------+-------+-------+-------+------+-------+
2179 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2181 unsigned int opc
, op2
, op3
, rn
, op4
;
2182 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2186 opc
= extract32(insn
, 21, 4);
2187 op2
= extract32(insn
, 16, 5);
2188 op3
= extract32(insn
, 10, 6);
2189 rn
= extract32(insn
, 5, 5);
2190 op4
= extract32(insn
, 0, 5);
2193 goto do_unallocated
;
2205 goto do_unallocated
;
2207 dst
= cpu_reg(s
, rn
);
2212 if (!dc_isar_feature(aa64_pauth
, s
)) {
2213 goto do_unallocated
;
2217 if (rn
!= 0x1f || op4
!= 0x1f) {
2218 goto do_unallocated
;
2221 modifier
= cpu_X
[31];
2223 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2225 goto do_unallocated
;
2227 modifier
= new_tmp_a64_zero(s
);
2229 if (s
->pauth_active
) {
2230 dst
= new_tmp_a64(s
);
2232 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2234 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2237 dst
= cpu_reg(s
, rn
);
2242 goto do_unallocated
;
2244 gen_a64_set_pc(s
, dst
);
2245 /* BLR also needs to load return address */
2247 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2253 if (!dc_isar_feature(aa64_pauth
, s
)) {
2254 goto do_unallocated
;
2256 if ((op3
& ~1) != 2) {
2257 goto do_unallocated
;
2259 btype_mod
= opc
& 1;
2260 if (s
->pauth_active
) {
2261 dst
= new_tmp_a64(s
);
2262 modifier
= cpu_reg_sp(s
, op4
);
2264 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2266 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2269 dst
= cpu_reg(s
, rn
);
2271 gen_a64_set_pc(s
, dst
);
2272 /* BLRAA also needs to load return address */
2274 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2279 if (s
->current_el
== 0) {
2280 goto do_unallocated
;
2285 goto do_unallocated
;
2287 dst
= tcg_temp_new_i64();
2288 tcg_gen_ld_i64(dst
, cpu_env
,
2289 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2292 case 2: /* ERETAA */
2293 case 3: /* ERETAB */
2294 if (!dc_isar_feature(aa64_pauth
, s
)) {
2295 goto do_unallocated
;
2297 if (rn
!= 0x1f || op4
!= 0x1f) {
2298 goto do_unallocated
;
2300 dst
= tcg_temp_new_i64();
2301 tcg_gen_ld_i64(dst
, cpu_env
,
2302 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2303 if (s
->pauth_active
) {
2304 modifier
= cpu_X
[31];
2306 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2308 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2314 goto do_unallocated
;
2316 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2320 gen_helper_exception_return(cpu_env
, dst
);
2321 tcg_temp_free_i64(dst
);
2322 /* Must exit loop to check un-masked IRQs */
2323 s
->base
.is_jmp
= DISAS_EXIT
;
2327 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2328 goto do_unallocated
;
2330 unsupported_encoding(s
, insn
);
2336 unallocated_encoding(s
);
2340 switch (btype_mod
) {
2342 if (dc_isar_feature(aa64_bti
, s
)) {
2343 /* BR to {x16,x17} or !guard -> 1, else 3. */
2344 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2349 if (dc_isar_feature(aa64_bti
, s
)) {
2350 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2355 default: /* RET or none of the above. */
2356 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2360 s
->base
.is_jmp
= DISAS_JUMP
;
2363 /* Branches, exception generating and system instructions */
2364 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2366 switch (extract32(insn
, 25, 7)) {
2367 case 0x0a: case 0x0b:
2368 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2369 disas_uncond_b_imm(s
, insn
);
2371 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2372 disas_comp_b_imm(s
, insn
);
2374 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2375 disas_test_b_imm(s
, insn
);
2377 case 0x2a: /* Conditional branch (immediate) */
2378 disas_cond_b_imm(s
, insn
);
2380 case 0x6a: /* Exception generation / System */
2381 if (insn
& (1 << 24)) {
2382 if (extract32(insn
, 22, 2) == 0) {
2383 disas_system(s
, insn
);
2385 unallocated_encoding(s
);
2391 case 0x6b: /* Unconditional branch (register) */
2392 disas_uncond_b_reg(s
, insn
);
2395 unallocated_encoding(s
);
2401 * Load/Store exclusive instructions are implemented by remembering
2402 * the value/address loaded, and seeing if these are the same
2403 * when the store is performed. This is not actually the architecturally
2404 * mandated semantics, but it works for typical guest code sequences
2405 * and avoids having to monitor regular stores.
2407 * The store exclusive uses the atomic cmpxchg primitives to avoid
2408 * races in multi-threaded linux-user and when MTTCG softmmu is
2411 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2412 TCGv_i64 addr
, int size
, bool is_pair
)
2414 int idx
= get_mem_index(s
);
2415 MemOp memop
= s
->be_data
;
2417 g_assert(size
<= 3);
2419 g_assert(size
>= 2);
2421 /* The pair must be single-copy atomic for the doubleword. */
2422 memop
|= MO_64
| MO_ALIGN
;
2423 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2424 if (s
->be_data
== MO_LE
) {
2425 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2426 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2428 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2429 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2432 /* The pair must be single-copy atomic for *each* doubleword, not
2433 the entire quadword, however it must be quadword aligned. */
2435 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2436 memop
| MO_ALIGN_16
);
2438 TCGv_i64 addr2
= tcg_temp_new_i64();
2439 tcg_gen_addi_i64(addr2
, addr
, 8);
2440 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2441 tcg_temp_free_i64(addr2
);
2443 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2444 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2447 memop
|= size
| MO_ALIGN
;
2448 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2449 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2451 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2454 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2455 TCGv_i64 addr
, int size
, int is_pair
)
2457 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2458 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2461 * [addr + datasize] = {Rt2};
2467 * env->exclusive_addr = -1;
2469 TCGLabel
*fail_label
= gen_new_label();
2470 TCGLabel
*done_label
= gen_new_label();
2473 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2475 tmp
= tcg_temp_new_i64();
2478 if (s
->be_data
== MO_LE
) {
2479 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2481 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2483 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2484 cpu_exclusive_val
, tmp
,
2486 MO_64
| MO_ALIGN
| s
->be_data
);
2487 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2488 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2489 if (!HAVE_CMPXCHG128
) {
2490 gen_helper_exit_atomic(cpu_env
);
2491 s
->base
.is_jmp
= DISAS_NORETURN
;
2492 } else if (s
->be_data
== MO_LE
) {
2493 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2498 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2503 } else if (s
->be_data
== MO_LE
) {
2504 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2505 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2507 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2508 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2511 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2512 cpu_reg(s
, rt
), get_mem_index(s
),
2513 size
| MO_ALIGN
| s
->be_data
);
2514 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2516 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2517 tcg_temp_free_i64(tmp
);
2518 tcg_gen_br(done_label
);
2520 gen_set_label(fail_label
);
2521 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2522 gen_set_label(done_label
);
2523 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2526 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2529 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2530 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2531 int memidx
= get_mem_index(s
);
2532 TCGv_i64 clean_addr
;
2535 gen_check_sp_alignment(s
);
2537 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2538 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2539 size
| MO_ALIGN
| s
->be_data
);
2542 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2545 TCGv_i64 s1
= cpu_reg(s
, rs
);
2546 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2547 TCGv_i64 t1
= cpu_reg(s
, rt
);
2548 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2549 TCGv_i64 clean_addr
;
2550 int memidx
= get_mem_index(s
);
2553 gen_check_sp_alignment(s
);
2556 /* This is a single atomic access, despite the "pair". */
2557 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2560 TCGv_i64 cmp
= tcg_temp_new_i64();
2561 TCGv_i64 val
= tcg_temp_new_i64();
2563 if (s
->be_data
== MO_LE
) {
2564 tcg_gen_concat32_i64(val
, t1
, t2
);
2565 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2567 tcg_gen_concat32_i64(val
, t2
, t1
);
2568 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2571 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2572 MO_64
| MO_ALIGN
| s
->be_data
);
2573 tcg_temp_free_i64(val
);
2575 if (s
->be_data
== MO_LE
) {
2576 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2578 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2580 tcg_temp_free_i64(cmp
);
2581 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2582 if (HAVE_CMPXCHG128
) {
2583 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2584 if (s
->be_data
== MO_LE
) {
2585 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2586 clean_addr
, t1
, t2
);
2588 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2589 clean_addr
, t1
, t2
);
2591 tcg_temp_free_i32(tcg_rs
);
2593 gen_helper_exit_atomic(cpu_env
);
2594 s
->base
.is_jmp
= DISAS_NORETURN
;
2597 TCGv_i64 d1
= tcg_temp_new_i64();
2598 TCGv_i64 d2
= tcg_temp_new_i64();
2599 TCGv_i64 a2
= tcg_temp_new_i64();
2600 TCGv_i64 c1
= tcg_temp_new_i64();
2601 TCGv_i64 c2
= tcg_temp_new_i64();
2602 TCGv_i64 zero
= tcg_const_i64(0);
2604 /* Load the two words, in memory order. */
2605 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2606 MO_64
| MO_ALIGN_16
| s
->be_data
);
2607 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2608 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2610 /* Compare the two words, also in memory order. */
2611 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2612 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2613 tcg_gen_and_i64(c2
, c2
, c1
);
2615 /* If compare equal, write back new data, else write back old data. */
2616 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2617 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2618 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2619 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2620 tcg_temp_free_i64(a2
);
2621 tcg_temp_free_i64(c1
);
2622 tcg_temp_free_i64(c2
);
2623 tcg_temp_free_i64(zero
);
2625 /* Write back the data from memory to Rs. */
2626 tcg_gen_mov_i64(s1
, d1
);
2627 tcg_gen_mov_i64(s2
, d2
);
2628 tcg_temp_free_i64(d1
);
2629 tcg_temp_free_i64(d2
);
2633 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2634 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2636 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2638 int opc0
= extract32(opc
, 0, 1);
2642 regsize
= opc0
? 32 : 64;
2644 regsize
= size
== 3 ? 64 : 32;
2646 return regsize
== 64;
2649 /* Load/store exclusive
2651 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2652 * +-----+-------------+----+---+----+------+----+-------+------+------+
2653 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2654 * +-----+-------------+----+---+----+------+----+-------+------+------+
2656 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2657 * L: 0 -> store, 1 -> load
2658 * o2: 0 -> exclusive, 1 -> not
2659 * o1: 0 -> single register, 1 -> register pair
2660 * o0: 1 -> load-acquire/store-release, 0 -> not
2662 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2664 int rt
= extract32(insn
, 0, 5);
2665 int rn
= extract32(insn
, 5, 5);
2666 int rt2
= extract32(insn
, 10, 5);
2667 int rs
= extract32(insn
, 16, 5);
2668 int is_lasr
= extract32(insn
, 15, 1);
2669 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2670 int size
= extract32(insn
, 30, 2);
2671 TCGv_i64 clean_addr
;
2673 switch (o2_L_o1_o0
) {
2674 case 0x0: /* STXR */
2675 case 0x1: /* STLXR */
2677 gen_check_sp_alignment(s
);
2680 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2682 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2683 true, rn
!= 31, size
);
2684 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2687 case 0x4: /* LDXR */
2688 case 0x5: /* LDAXR */
2690 gen_check_sp_alignment(s
);
2692 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2693 false, rn
!= 31, size
);
2695 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2697 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2701 case 0x8: /* STLLR */
2702 if (!dc_isar_feature(aa64_lor
, s
)) {
2705 /* StoreLORelease is the same as Store-Release for QEMU. */
2707 case 0x9: /* STLR */
2708 /* Generate ISS for non-exclusive accesses including LASR. */
2710 gen_check_sp_alignment(s
);
2712 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2713 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2714 true, rn
!= 31, size
);
2715 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2716 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2717 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2720 case 0xc: /* LDLAR */
2721 if (!dc_isar_feature(aa64_lor
, s
)) {
2724 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2726 case 0xd: /* LDAR */
2727 /* Generate ISS for non-exclusive accesses including LASR. */
2729 gen_check_sp_alignment(s
);
2731 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2732 false, rn
!= 31, size
);
2733 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2734 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2735 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2736 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2739 case 0x2: case 0x3: /* CASP / STXP */
2740 if (size
& 2) { /* STXP / STLXP */
2742 gen_check_sp_alignment(s
);
2745 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2747 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2748 true, rn
!= 31, size
);
2749 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2753 && ((rt
| rs
) & 1) == 0
2754 && dc_isar_feature(aa64_atomics
, s
)) {
2756 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2761 case 0x6: case 0x7: /* CASPA / LDXP */
2762 if (size
& 2) { /* LDXP / LDAXP */
2764 gen_check_sp_alignment(s
);
2766 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2767 false, rn
!= 31, size
);
2769 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2771 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2776 && ((rt
| rs
) & 1) == 0
2777 && dc_isar_feature(aa64_atomics
, s
)) {
2778 /* CASPA / CASPAL */
2779 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2785 case 0xb: /* CASL */
2786 case 0xe: /* CASA */
2787 case 0xf: /* CASAL */
2788 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2789 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2794 unallocated_encoding(s
);
2798 * Load register (literal)
2800 * 31 30 29 27 26 25 24 23 5 4 0
2801 * +-----+-------+---+-----+-------------------+-------+
2802 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2803 * +-----+-------+---+-----+-------------------+-------+
2805 * V: 1 -> vector (simd/fp)
2806 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2807 * 10-> 32 bit signed, 11 -> prefetch
2808 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2810 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2812 int rt
= extract32(insn
, 0, 5);
2813 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2814 bool is_vector
= extract32(insn
, 26, 1);
2815 int opc
= extract32(insn
, 30, 2);
2816 bool is_signed
= false;
2818 TCGv_i64 tcg_rt
, clean_addr
;
2822 unallocated_encoding(s
);
2826 if (!fp_access_check(s
)) {
2831 /* PRFM (literal) : prefetch */
2834 size
= 2 + extract32(opc
, 0, 1);
2835 is_signed
= extract32(opc
, 1, 1);
2838 tcg_rt
= cpu_reg(s
, rt
);
2840 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2842 do_fp_ld(s
, rt
, clean_addr
, size
);
2844 /* Only unsigned 32bit loads target 32bit registers. */
2845 bool iss_sf
= opc
!= 0;
2847 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2848 false, true, rt
, iss_sf
, false);
2850 tcg_temp_free_i64(clean_addr
);
2854 * LDNP (Load Pair - non-temporal hint)
2855 * LDP (Load Pair - non vector)
2856 * LDPSW (Load Pair Signed Word - non vector)
2857 * STNP (Store Pair - non-temporal hint)
2858 * STP (Store Pair - non vector)
2859 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2860 * LDP (Load Pair of SIMD&FP)
2861 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2862 * STP (Store Pair of SIMD&FP)
2864 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2865 * +-----+-------+---+---+-------+---+-----------------------------+
2866 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2867 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2869 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2871 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2872 * V: 0 -> GPR, 1 -> Vector
2873 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2874 * 10 -> signed offset, 11 -> pre-index
2875 * L: 0 -> Store 1 -> Load
2877 * Rt, Rt2 = GPR or SIMD registers to be stored
2878 * Rn = general purpose register containing address
2879 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2881 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2883 int rt
= extract32(insn
, 0, 5);
2884 int rn
= extract32(insn
, 5, 5);
2885 int rt2
= extract32(insn
, 10, 5);
2886 uint64_t offset
= sextract64(insn
, 15, 7);
2887 int index
= extract32(insn
, 23, 2);
2888 bool is_vector
= extract32(insn
, 26, 1);
2889 bool is_load
= extract32(insn
, 22, 1);
2890 int opc
= extract32(insn
, 30, 2);
2892 bool is_signed
= false;
2893 bool postindex
= false;
2895 bool set_tag
= false;
2897 TCGv_i64 clean_addr
, dirty_addr
;
2902 unallocated_encoding(s
);
2908 } else if (opc
== 1 && !is_load
) {
2910 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2911 unallocated_encoding(s
);
2917 size
= 2 + extract32(opc
, 1, 1);
2918 is_signed
= extract32(opc
, 0, 1);
2919 if (!is_load
&& is_signed
) {
2920 unallocated_encoding(s
);
2926 case 1: /* post-index */
2931 /* signed offset with "non-temporal" hint. Since we don't emulate
2932 * caches we don't care about hints to the cache system about
2933 * data access patterns, and handle this identically to plain
2937 /* There is no non-temporal-hint version of LDPSW */
2938 unallocated_encoding(s
);
2943 case 2: /* signed offset, rn not updated */
2946 case 3: /* pre-index */
2952 if (is_vector
&& !fp_access_check(s
)) {
2956 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2959 gen_check_sp_alignment(s
);
2962 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2964 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2970 * TODO: We could rely on the stores below, at least for
2971 * system mode, if we arrange to add MO_ALIGN_16.
2973 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2974 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2975 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2977 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2981 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2982 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
2986 do_fp_ld(s
, rt
, clean_addr
, size
);
2988 do_fp_st(s
, rt
, clean_addr
, size
);
2990 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2992 do_fp_ld(s
, rt2
, clean_addr
, size
);
2994 do_fp_st(s
, rt2
, clean_addr
, size
);
2997 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2998 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
3001 TCGv_i64 tmp
= tcg_temp_new_i64();
3003 /* Do not modify tcg_rt before recognizing any exception
3004 * from the second load.
3006 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3007 false, false, 0, false, false);
3008 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3009 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3010 false, false, 0, false, false);
3012 tcg_gen_mov_i64(tcg_rt
, tmp
);
3013 tcg_temp_free_i64(tmp
);
3015 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3016 false, 0, false, false);
3017 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3018 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3019 false, 0, false, false);
3025 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3027 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3032 * Load/store (immediate post-indexed)
3033 * Load/store (immediate pre-indexed)
3034 * Load/store (unscaled immediate)
3036 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3037 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3038 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3039 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3041 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3043 * V = 0 -> non-vector
3044 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3045 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3047 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3053 int rn
= extract32(insn
, 5, 5);
3054 int imm9
= sextract32(insn
, 12, 9);
3055 int idx
= extract32(insn
, 10, 2);
3056 bool is_signed
= false;
3057 bool is_store
= false;
3058 bool is_extended
= false;
3059 bool is_unpriv
= (idx
== 2);
3060 bool iss_valid
= !is_vector
;
3065 TCGv_i64 clean_addr
, dirty_addr
;
3068 size
|= (opc
& 2) << 1;
3069 if (size
> 4 || is_unpriv
) {
3070 unallocated_encoding(s
);
3073 is_store
= ((opc
& 1) == 0);
3074 if (!fp_access_check(s
)) {
3078 if (size
== 3 && opc
== 2) {
3079 /* PRFM - prefetch */
3081 unallocated_encoding(s
);
3086 if (opc
== 3 && size
> 1) {
3087 unallocated_encoding(s
);
3090 is_store
= (opc
== 0);
3091 is_signed
= extract32(opc
, 1, 1);
3092 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3110 g_assert_not_reached();
3114 gen_check_sp_alignment(s
);
3117 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3119 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3122 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3123 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3124 writeback
|| rn
!= 31,
3125 size
, is_unpriv
, memidx
);
3129 do_fp_st(s
, rt
, clean_addr
, size
);
3131 do_fp_ld(s
, rt
, clean_addr
, size
);
3134 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3135 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3138 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3139 iss_valid
, rt
, iss_sf
, false);
3141 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3142 is_extended
, memidx
,
3143 iss_valid
, rt
, iss_sf
, false);
3148 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3150 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3152 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3157 * Load/store (register offset)
3159 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3160 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3161 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3162 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3165 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3166 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3168 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3169 * opc<0>: 0 -> store, 1 -> load
3170 * V: 1 -> vector/simd
3171 * opt: extend encoding (see DecodeRegExtend)
3172 * S: if S=1 then scale (essentially index by sizeof(size))
3173 * Rt: register to transfer into/out of
3174 * Rn: address register or SP for base
3175 * Rm: offset register or ZR for offset
3177 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3183 int rn
= extract32(insn
, 5, 5);
3184 int shift
= extract32(insn
, 12, 1);
3185 int rm
= extract32(insn
, 16, 5);
3186 int opt
= extract32(insn
, 13, 3);
3187 bool is_signed
= false;
3188 bool is_store
= false;
3189 bool is_extended
= false;
3191 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3193 if (extract32(opt
, 1, 1) == 0) {
3194 unallocated_encoding(s
);
3199 size
|= (opc
& 2) << 1;
3201 unallocated_encoding(s
);
3204 is_store
= !extract32(opc
, 0, 1);
3205 if (!fp_access_check(s
)) {
3209 if (size
== 3 && opc
== 2) {
3210 /* PRFM - prefetch */
3213 if (opc
== 3 && size
> 1) {
3214 unallocated_encoding(s
);
3217 is_store
= (opc
== 0);
3218 is_signed
= extract32(opc
, 1, 1);
3219 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3223 gen_check_sp_alignment(s
);
3225 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3227 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3228 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3230 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3231 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3235 do_fp_st(s
, rt
, clean_addr
, size
);
3237 do_fp_ld(s
, rt
, clean_addr
, size
);
3240 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3241 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3243 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3244 true, rt
, iss_sf
, false);
3246 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3247 is_extended
, true, rt
, iss_sf
, false);
3253 * Load/store (unsigned immediate)
3255 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3256 * +----+-------+---+-----+-----+------------+-------+------+
3257 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3258 * +----+-------+---+-----+-----+------------+-------+------+
3261 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3262 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3264 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3265 * opc<0>: 0 -> store, 1 -> load
3266 * Rn: base address register (inc SP)
3267 * Rt: target register
3269 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3275 int rn
= extract32(insn
, 5, 5);
3276 unsigned int imm12
= extract32(insn
, 10, 12);
3277 unsigned int offset
;
3279 TCGv_i64 clean_addr
, dirty_addr
;
3282 bool is_signed
= false;
3283 bool is_extended
= false;
3286 size
|= (opc
& 2) << 1;
3288 unallocated_encoding(s
);
3291 is_store
= !extract32(opc
, 0, 1);
3292 if (!fp_access_check(s
)) {
3296 if (size
== 3 && opc
== 2) {
3297 /* PRFM - prefetch */
3300 if (opc
== 3 && size
> 1) {
3301 unallocated_encoding(s
);
3304 is_store
= (opc
== 0);
3305 is_signed
= extract32(opc
, 1, 1);
3306 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3310 gen_check_sp_alignment(s
);
3312 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3313 offset
= imm12
<< size
;
3314 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3315 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3319 do_fp_st(s
, rt
, clean_addr
, size
);
3321 do_fp_ld(s
, rt
, clean_addr
, size
);
3324 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3325 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3327 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3328 true, rt
, iss_sf
, false);
3330 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3331 is_extended
, true, rt
, iss_sf
, false);
3336 /* Atomic memory operations
3338 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3339 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3340 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3341 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3343 * Rt: the result register
3344 * Rn: base address or SP
3345 * Rs: the source register for the operation
3346 * V: vector flag (always 0 as of v8.3)
3350 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3351 int size
, int rt
, bool is_vector
)
3353 int rs
= extract32(insn
, 16, 5);
3354 int rn
= extract32(insn
, 5, 5);
3355 int o3_opc
= extract32(insn
, 12, 4);
3356 bool r
= extract32(insn
, 22, 1);
3357 bool a
= extract32(insn
, 23, 1);
3358 TCGv_i64 tcg_rs
, clean_addr
;
3359 AtomicThreeOpFn
*fn
= NULL
;
3361 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3362 unallocated_encoding(s
);
3366 case 000: /* LDADD */
3367 fn
= tcg_gen_atomic_fetch_add_i64
;
3369 case 001: /* LDCLR */
3370 fn
= tcg_gen_atomic_fetch_and_i64
;
3372 case 002: /* LDEOR */
3373 fn
= tcg_gen_atomic_fetch_xor_i64
;
3375 case 003: /* LDSET */
3376 fn
= tcg_gen_atomic_fetch_or_i64
;
3378 case 004: /* LDSMAX */
3379 fn
= tcg_gen_atomic_fetch_smax_i64
;
3381 case 005: /* LDSMIN */
3382 fn
= tcg_gen_atomic_fetch_smin_i64
;
3384 case 006: /* LDUMAX */
3385 fn
= tcg_gen_atomic_fetch_umax_i64
;
3387 case 007: /* LDUMIN */
3388 fn
= tcg_gen_atomic_fetch_umin_i64
;
3391 fn
= tcg_gen_atomic_xchg_i64
;
3393 case 014: /* LDAPR, LDAPRH, LDAPRB */
3394 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3395 rs
!= 31 || a
!= 1 || r
!= 0) {
3396 unallocated_encoding(s
);
3401 unallocated_encoding(s
);
3406 gen_check_sp_alignment(s
);
3408 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3410 if (o3_opc
== 014) {
3412 * LDAPR* are a special case because they are a simple load, not a
3413 * fetch-and-do-something op.
3414 * The architectural consistency requirements here are weaker than
3415 * full load-acquire (we only need "load-acquire processor consistent"),
3416 * but we choose to implement them as full LDAQ.
3418 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3419 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3420 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3424 tcg_rs
= read_cpu_reg(s
, rs
, true);
3426 if (o3_opc
== 1) { /* LDCLR */
3427 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3430 /* The tcg atomic primitives are all full barriers. Therefore we
3431 * can ignore the Acquire and Release bits of this instruction.
3433 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3434 s
->be_data
| size
| MO_ALIGN
);
3438 * PAC memory operations
3440 * 31 30 27 26 24 22 21 12 11 10 5 0
3441 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3442 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3443 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3445 * Rt: the result register
3446 * Rn: base address or SP
3447 * V: vector flag (always 0 as of v8.3)
3448 * M: clear for key DA, set for key DB
3449 * W: pre-indexing flag
3452 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3453 int size
, int rt
, bool is_vector
)
3455 int rn
= extract32(insn
, 5, 5);
3456 bool is_wback
= extract32(insn
, 11, 1);
3457 bool use_key_a
= !extract32(insn
, 23, 1);
3459 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3461 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3462 unallocated_encoding(s
);
3467 gen_check_sp_alignment(s
);
3469 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3471 if (s
->pauth_active
) {
3473 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3474 new_tmp_a64_zero(s
));
3476 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3477 new_tmp_a64_zero(s
));
3481 /* Form the 10-bit signed, scaled offset. */
3482 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3483 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3484 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3486 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3487 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3488 is_wback
|| rn
!= 31, size
);
3490 tcg_rt
= cpu_reg(s
, rt
);
3491 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3492 /* extend */ false, /* iss_valid */ !is_wback
,
3493 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3496 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3501 * LDAPR/STLR (unscaled immediate)
3503 * 31 30 24 22 21 12 10 5 0
3504 * +------+-------------+-----+---+--------+-----+----+-----+
3505 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3506 * +------+-------------+-----+---+--------+-----+----+-----+
3508 * Rt: source or destination register
3510 * imm9: unscaled immediate offset
3511 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3512 * size: size of load/store
3514 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3516 int rt
= extract32(insn
, 0, 5);
3517 int rn
= extract32(insn
, 5, 5);
3518 int offset
= sextract32(insn
, 12, 9);
3519 int opc
= extract32(insn
, 22, 2);
3520 int size
= extract32(insn
, 30, 2);
3521 TCGv_i64 clean_addr
, dirty_addr
;
3522 bool is_store
= false;
3523 bool extend
= false;
3527 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3528 unallocated_encoding(s
);
3532 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3533 mop
= size
| MO_ALIGN
;
3536 case 0: /* STLURB */
3539 case 1: /* LDAPUR* */
3541 case 2: /* LDAPURS* 64-bit variant */
3543 unallocated_encoding(s
);
3548 case 3: /* LDAPURS* 32-bit variant */
3550 unallocated_encoding(s
);
3554 extend
= true; /* zero-extend 32->64 after signed load */
3557 g_assert_not_reached();
3560 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3563 gen_check_sp_alignment(s
);
3566 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3567 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3568 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3571 /* Store-Release semantics */
3572 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3573 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3576 * Load-AcquirePC semantics; we implement as the slightly more
3577 * restrictive Load-Acquire.
3579 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3580 extend
, true, rt
, iss_sf
, true);
3581 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3585 /* Load/store register (all forms) */
3586 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3588 int rt
= extract32(insn
, 0, 5);
3589 int opc
= extract32(insn
, 22, 2);
3590 bool is_vector
= extract32(insn
, 26, 1);
3591 int size
= extract32(insn
, 30, 2);
3593 switch (extract32(insn
, 24, 2)) {
3595 if (extract32(insn
, 21, 1) == 0) {
3596 /* Load/store register (unscaled immediate)
3597 * Load/store immediate pre/post-indexed
3598 * Load/store register unprivileged
3600 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3603 switch (extract32(insn
, 10, 2)) {
3605 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3608 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3611 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3616 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3619 unallocated_encoding(s
);
3622 /* AdvSIMD load/store multiple structures
3624 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3625 * +---+---+---------------+---+-------------+--------+------+------+------+
3626 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3627 * +---+---+---------------+---+-------------+--------+------+------+------+
3629 * AdvSIMD load/store multiple structures (post-indexed)
3631 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3632 * +---+---+---------------+---+---+---------+--------+------+------+------+
3633 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3634 * +---+---+---------------+---+---+---------+--------+------+------+------+
3636 * Rt: first (or only) SIMD&FP register to be transferred
3637 * Rn: base address or SP
3638 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3640 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3642 int rt
= extract32(insn
, 0, 5);
3643 int rn
= extract32(insn
, 5, 5);
3644 int rm
= extract32(insn
, 16, 5);
3645 int size
= extract32(insn
, 10, 2);
3646 int opcode
= extract32(insn
, 12, 4);
3647 bool is_store
= !extract32(insn
, 22, 1);
3648 bool is_postidx
= extract32(insn
, 23, 1);
3649 bool is_q
= extract32(insn
, 30, 1);
3650 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3651 MemOp endian
, align
, mop
;
3653 int total
; /* total bytes */
3654 int elements
; /* elements per vector */
3655 int rpt
; /* num iterations */
3656 int selem
; /* structure elements */
3659 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3660 unallocated_encoding(s
);
3664 if (!is_postidx
&& rm
!= 0) {
3665 unallocated_encoding(s
);
3669 /* From the shared decode logic */
3700 unallocated_encoding(s
);
3704 if (size
== 3 && !is_q
&& selem
!= 1) {
3706 unallocated_encoding(s
);
3710 if (!fp_access_check(s
)) {
3715 gen_check_sp_alignment(s
);
3718 /* For our purposes, bytes are always little-endian. */
3719 endian
= s
->be_data
;
3724 total
= rpt
* selem
* (is_q
? 16 : 8);
3725 tcg_rn
= cpu_reg_sp(s
, rn
);
3728 * Issue the MTE check vs the logical repeat count, before we
3729 * promote consecutive little-endian elements below.
3731 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3735 * Consecutive little-endian elements from a single register
3736 * can be promoted to a larger little-endian operation.
3739 if (selem
== 1 && endian
== MO_LE
) {
3740 align
= pow2_align(size
);
3743 if (!s
->align_mem
) {
3746 mop
= endian
| size
| align
;
3748 elements
= (is_q
? 16 : 8) >> size
;
3749 tcg_ebytes
= tcg_const_i64(1 << size
);
3750 for (r
= 0; r
< rpt
; r
++) {
3752 for (e
= 0; e
< elements
; e
++) {
3754 for (xs
= 0; xs
< selem
; xs
++) {
3755 int tt
= (rt
+ r
+ xs
) % 32;
3757 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3759 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3761 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3765 tcg_temp_free_i64(tcg_ebytes
);
3768 /* For non-quad operations, setting a slice of the low
3769 * 64 bits of the register clears the high 64 bits (in
3770 * the ARM ARM pseudocode this is implicit in the fact
3771 * that 'rval' is a 64 bit wide variable).
3772 * For quad operations, we might still need to zero the
3775 for (r
= 0; r
< rpt
* selem
; r
++) {
3776 int tt
= (rt
+ r
) % 32;
3777 clear_vec_high(s
, is_q
, tt
);
3783 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3785 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3790 /* AdvSIMD load/store single structure
3792 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3793 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3794 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3795 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3797 * AdvSIMD load/store single structure (post-indexed)
3799 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3800 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3801 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3802 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3804 * Rt: first (or only) SIMD&FP register to be transferred
3805 * Rn: base address or SP
3806 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3807 * index = encoded in Q:S:size dependent on size
3809 * lane_size = encoded in R, opc
3810 * transfer width = encoded in opc, S, size
3812 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3814 int rt
= extract32(insn
, 0, 5);
3815 int rn
= extract32(insn
, 5, 5);
3816 int rm
= extract32(insn
, 16, 5);
3817 int size
= extract32(insn
, 10, 2);
3818 int S
= extract32(insn
, 12, 1);
3819 int opc
= extract32(insn
, 13, 3);
3820 int R
= extract32(insn
, 21, 1);
3821 int is_load
= extract32(insn
, 22, 1);
3822 int is_postidx
= extract32(insn
, 23, 1);
3823 int is_q
= extract32(insn
, 30, 1);
3825 int scale
= extract32(opc
, 1, 2);
3826 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3827 bool replicate
= false;
3828 int index
= is_q
<< 3 | S
<< 2 | size
;
3830 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3833 if (extract32(insn
, 31, 1)) {
3834 unallocated_encoding(s
);
3837 if (!is_postidx
&& rm
!= 0) {
3838 unallocated_encoding(s
);
3844 if (!is_load
|| S
) {
3845 unallocated_encoding(s
);
3854 if (extract32(size
, 0, 1)) {
3855 unallocated_encoding(s
);
3861 if (extract32(size
, 1, 1)) {
3862 unallocated_encoding(s
);
3865 if (!extract32(size
, 0, 1)) {
3869 unallocated_encoding(s
);
3877 g_assert_not_reached();
3880 if (!fp_access_check(s
)) {
3885 gen_check_sp_alignment(s
);
3888 total
= selem
<< scale
;
3889 tcg_rn
= cpu_reg_sp(s
, rn
);
3891 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3893 mop
= finalize_memop(s
, scale
);
3895 tcg_ebytes
= tcg_const_i64(1 << scale
);
3896 for (xs
= 0; xs
< selem
; xs
++) {
3898 /* Load and replicate to all elements */
3899 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3901 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3902 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3903 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3905 tcg_temp_free_i64(tcg_tmp
);
3907 /* Load/store one element per register */
3909 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3911 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3914 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3917 tcg_temp_free_i64(tcg_ebytes
);
3921 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3923 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3929 * Load/Store memory tags
3931 * 31 30 29 24 22 21 12 10 5 0
3932 * +-----+-------------+-----+---+------+-----+------+------+
3933 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3934 * +-----+-------------+-----+---+------+-----+------+------+
3936 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3938 int rt
= extract32(insn
, 0, 5);
3939 int rn
= extract32(insn
, 5, 5);
3940 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3941 int op2
= extract32(insn
, 10, 2);
3942 int op1
= extract32(insn
, 22, 2);
3943 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3945 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3947 /* We checked insn bits [29:24,21] in the caller. */
3948 if (extract32(insn
, 30, 2) != 3) {
3949 goto do_unallocated
;
3953 * @index is a tri-state variable which has 3 states:
3954 * < 0 : post-index, writeback
3955 * = 0 : signed offset
3956 * > 0 : pre-index, writeback
3965 if (s
->current_el
== 0 || offset
!= 0) {
3966 goto do_unallocated
;
3968 is_mult
= is_zero
= true;
3988 if (s
->current_el
== 0 || offset
!= 0) {
3989 goto do_unallocated
;
3997 is_pair
= is_zero
= true;
4001 if (s
->current_el
== 0 || offset
!= 0) {
4002 goto do_unallocated
;
4004 is_mult
= is_load
= true;
4010 unallocated_encoding(s
);
4015 ? !dc_isar_feature(aa64_mte
, s
)
4016 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4017 goto do_unallocated
;
4021 gen_check_sp_alignment(s
);
4024 addr
= read_cpu_reg_sp(s
, rn
, true);
4026 /* pre-index or signed offset */
4027 tcg_gen_addi_i64(addr
, addr
, offset
);
4031 tcg_rt
= cpu_reg(s
, rt
);
4034 int size
= 4 << s
->dcz_blocksize
;
4037 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4040 * The non-tags portion of STZGM is mostly like DC_ZVA,
4041 * except the alignment happens before the access.
4043 clean_addr
= clean_data_tbi(s
, addr
);
4044 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4045 gen_helper_dc_zva(cpu_env
, clean_addr
);
4046 } else if (s
->ata
) {
4048 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4050 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4053 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4054 int size
= 4 << GMID_EL1_BS
;
4056 clean_addr
= clean_data_tbi(s
, addr
);
4057 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4058 gen_probe_access(s
, clean_addr
, acc
, size
);
4061 /* The result tags are zeros. */
4062 tcg_gen_movi_i64(tcg_rt
, 0);
4069 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4070 tcg_rt
= cpu_reg(s
, rt
);
4072 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4074 clean_addr
= clean_data_tbi(s
, addr
);
4075 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4076 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4079 tcg_rt
= cpu_reg_sp(s
, rt
);
4082 * For STG and ST2G, we need to check alignment and probe memory.
4083 * TODO: For STZG and STZ2G, we could rely on the stores below,
4084 * at least for system mode; user-only won't enforce alignment.
4087 gen_helper_st2g_stub(cpu_env
, addr
);
4089 gen_helper_stg_stub(cpu_env
, addr
);
4091 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4093 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4095 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4099 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4101 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4107 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4108 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4109 int mem_index
= get_mem_index(s
);
4110 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4112 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4113 MO_Q
| MO_ALIGN_16
);
4114 for (i
= 8; i
< n
; i
+= 8) {
4115 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4116 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4118 tcg_temp_free_i64(tcg_zero
);
4122 /* pre-index or post-index */
4125 tcg_gen_addi_i64(addr
, addr
, offset
);
4127 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4131 /* Loads and stores */
4132 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4134 switch (extract32(insn
, 24, 6)) {
4135 case 0x08: /* Load/store exclusive */
4136 disas_ldst_excl(s
, insn
);
4138 case 0x18: case 0x1c: /* Load register (literal) */
4139 disas_ld_lit(s
, insn
);
4141 case 0x28: case 0x29:
4142 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4143 disas_ldst_pair(s
, insn
);
4145 case 0x38: case 0x39:
4146 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4147 disas_ldst_reg(s
, insn
);
4149 case 0x0c: /* AdvSIMD load/store multiple structures */
4150 disas_ldst_multiple_struct(s
, insn
);
4152 case 0x0d: /* AdvSIMD load/store single structure */
4153 disas_ldst_single_struct(s
, insn
);
4156 if (extract32(insn
, 21, 1) != 0) {
4157 disas_ldst_tag(s
, insn
);
4158 } else if (extract32(insn
, 10, 2) == 0) {
4159 disas_ldst_ldapr_stlr(s
, insn
);
4161 unallocated_encoding(s
);
4165 unallocated_encoding(s
);
4170 /* PC-rel. addressing
4171 * 31 30 29 28 24 23 5 4 0
4172 * +----+-------+-----------+-------------------+------+
4173 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4174 * +----+-------+-----------+-------------------+------+
4176 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4178 unsigned int page
, rd
;
4182 page
= extract32(insn
, 31, 1);
4183 /* SignExtend(immhi:immlo) -> offset */
4184 offset
= sextract64(insn
, 5, 19);
4185 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4186 rd
= extract32(insn
, 0, 5);
4190 /* ADRP (page based) */
4195 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4199 * Add/subtract (immediate)
4201 * 31 30 29 28 23 22 21 10 9 5 4 0
4202 * +--+--+--+-------------+--+-------------+-----+-----+
4203 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4204 * +--+--+--+-------------+--+-------------+-----+-----+
4206 * sf: 0 -> 32bit, 1 -> 64bit
4207 * op: 0 -> add , 1 -> sub
4209 * sh: 1 -> LSL imm by 12
4211 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4213 int rd
= extract32(insn
, 0, 5);
4214 int rn
= extract32(insn
, 5, 5);
4215 uint64_t imm
= extract32(insn
, 10, 12);
4216 bool shift
= extract32(insn
, 22, 1);
4217 bool setflags
= extract32(insn
, 29, 1);
4218 bool sub_op
= extract32(insn
, 30, 1);
4219 bool is_64bit
= extract32(insn
, 31, 1);
4221 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4222 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4223 TCGv_i64 tcg_result
;
4229 tcg_result
= tcg_temp_new_i64();
4232 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4234 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4237 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4239 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4241 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4243 tcg_temp_free_i64(tcg_imm
);
4247 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4249 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4252 tcg_temp_free_i64(tcg_result
);
4256 * Add/subtract (immediate, with tags)
4258 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4259 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4260 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4261 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4263 * op: 0 -> add, 1 -> sub
4265 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4267 int rd
= extract32(insn
, 0, 5);
4268 int rn
= extract32(insn
, 5, 5);
4269 int uimm4
= extract32(insn
, 10, 4);
4270 int uimm6
= extract32(insn
, 16, 6);
4271 bool sub_op
= extract32(insn
, 30, 1);
4272 TCGv_i64 tcg_rn
, tcg_rd
;
4275 /* Test all of sf=1, S=0, o2=0, o3=0. */
4276 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4277 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4278 unallocated_encoding(s
);
4282 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4287 tcg_rn
= cpu_reg_sp(s
, rn
);
4288 tcg_rd
= cpu_reg_sp(s
, rd
);
4291 TCGv_i32 offset
= tcg_const_i32(imm
);
4292 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4294 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4295 tcg_temp_free_i32(tag_offset
);
4296 tcg_temp_free_i32(offset
);
4298 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4299 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4303 /* The input should be a value in the bottom e bits (with higher
4304 * bits zero); returns that value replicated into every element
4305 * of size e in a 64 bit integer.
4307 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4317 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4318 static inline uint64_t bitmask64(unsigned int length
)
4320 assert(length
> 0 && length
<= 64);
4321 return ~0ULL >> (64 - length
);
4324 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4325 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4326 * value (ie should cause a guest UNDEF exception), and true if they are
4327 * valid, in which case the decoded bit pattern is written to result.
4329 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4330 unsigned int imms
, unsigned int immr
)
4333 unsigned e
, levels
, s
, r
;
4336 assert(immn
< 2 && imms
< 64 && immr
< 64);
4338 /* The bit patterns we create here are 64 bit patterns which
4339 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4340 * 64 bits each. Each element contains the same value: a run
4341 * of between 1 and e-1 non-zero bits, rotated within the
4342 * element by between 0 and e-1 bits.
4344 * The element size and run length are encoded into immn (1 bit)
4345 * and imms (6 bits) as follows:
4346 * 64 bit elements: immn = 1, imms = <length of run - 1>
4347 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4348 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4349 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4350 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4351 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4352 * Notice that immn = 0, imms = 11111x is the only combination
4353 * not covered by one of the above options; this is reserved.
4354 * Further, <length of run - 1> all-ones is a reserved pattern.
4356 * In all cases the rotation is by immr % e (and immr is 6 bits).
4359 /* First determine the element size */
4360 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4362 /* This is the immn == 0, imms == 0x11111x case */
4372 /* <length of run - 1> mustn't be all-ones. */
4376 /* Create the value of one element: s+1 set bits rotated
4377 * by r within the element (which is e bits wide)...
4379 mask
= bitmask64(s
+ 1);
4381 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4382 mask
&= bitmask64(e
);
4384 /* ...then replicate the element over the whole 64 bit value */
4385 mask
= bitfield_replicate(mask
, e
);
4390 /* Logical (immediate)
4391 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4392 * +----+-----+-------------+---+------+------+------+------+
4393 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4394 * +----+-----+-------------+---+------+------+------+------+
4396 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4398 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4399 TCGv_i64 tcg_rd
, tcg_rn
;
4401 bool is_and
= false;
4403 sf
= extract32(insn
, 31, 1);
4404 opc
= extract32(insn
, 29, 2);
4405 is_n
= extract32(insn
, 22, 1);
4406 immr
= extract32(insn
, 16, 6);
4407 imms
= extract32(insn
, 10, 6);
4408 rn
= extract32(insn
, 5, 5);
4409 rd
= extract32(insn
, 0, 5);
4412 unallocated_encoding(s
);
4416 if (opc
== 0x3) { /* ANDS */
4417 tcg_rd
= cpu_reg(s
, rd
);
4419 tcg_rd
= cpu_reg_sp(s
, rd
);
4421 tcg_rn
= cpu_reg(s
, rn
);
4423 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4424 /* some immediate field values are reserved */
4425 unallocated_encoding(s
);
4430 wmask
&= 0xffffffff;
4434 case 0x3: /* ANDS */
4436 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4440 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4443 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4446 assert(FALSE
); /* must handle all above */
4450 if (!sf
&& !is_and
) {
4451 /* zero extend final result; we know we can skip this for AND
4452 * since the immediate had the high 32 bits clear.
4454 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4457 if (opc
== 3) { /* ANDS */
4458 gen_logic_CC(sf
, tcg_rd
);
4463 * Move wide (immediate)
4465 * 31 30 29 28 23 22 21 20 5 4 0
4466 * +--+-----+-------------+-----+----------------+------+
4467 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4468 * +--+-----+-------------+-----+----------------+------+
4470 * sf: 0 -> 32 bit, 1 -> 64 bit
4471 * opc: 00 -> N, 10 -> Z, 11 -> K
4472 * hw: shift/16 (0,16, and sf only 32, 48)
4474 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4476 int rd
= extract32(insn
, 0, 5);
4477 uint64_t imm
= extract32(insn
, 5, 16);
4478 int sf
= extract32(insn
, 31, 1);
4479 int opc
= extract32(insn
, 29, 2);
4480 int pos
= extract32(insn
, 21, 2) << 4;
4481 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4484 if (!sf
&& (pos
>= 32)) {
4485 unallocated_encoding(s
);
4499 tcg_gen_movi_i64(tcg_rd
, imm
);
4502 tcg_imm
= tcg_const_i64(imm
);
4503 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4504 tcg_temp_free_i64(tcg_imm
);
4506 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4510 unallocated_encoding(s
);
4516 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4517 * +----+-----+-------------+---+------+------+------+------+
4518 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4519 * +----+-----+-------------+---+------+------+------+------+
4521 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4523 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4524 TCGv_i64 tcg_rd
, tcg_tmp
;
4526 sf
= extract32(insn
, 31, 1);
4527 opc
= extract32(insn
, 29, 2);
4528 n
= extract32(insn
, 22, 1);
4529 ri
= extract32(insn
, 16, 6);
4530 si
= extract32(insn
, 10, 6);
4531 rn
= extract32(insn
, 5, 5);
4532 rd
= extract32(insn
, 0, 5);
4533 bitsize
= sf
? 64 : 32;
4535 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4536 unallocated_encoding(s
);
4540 tcg_rd
= cpu_reg(s
, rd
);
4542 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4543 to be smaller than bitsize, we'll never reference data outside the
4544 low 32-bits anyway. */
4545 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4547 /* Recognize simple(r) extractions. */
4549 /* Wd<s-r:0> = Wn<s:r> */
4550 len
= (si
- ri
) + 1;
4551 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4552 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4554 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4555 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4558 /* opc == 1, BFXIL fall through to deposit */
4559 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4562 /* Handle the ri > si case with a deposit
4563 * Wd<32+s-r,32-r> = Wn<s:0>
4566 pos
= (bitsize
- ri
) & (bitsize
- 1);
4569 if (opc
== 0 && len
< ri
) {
4570 /* SBFM: sign extend the destination field from len to fill
4571 the balance of the word. Let the deposit below insert all
4572 of those sign bits. */
4573 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4577 if (opc
== 1) { /* BFM, BFXIL */
4578 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4580 /* SBFM or UBFM: We start with zero, and we haven't modified
4581 any bits outside bitsize, therefore the zero-extension
4582 below is unneeded. */
4583 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4588 if (!sf
) { /* zero extend final result */
4589 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4594 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4595 * +----+------+-------------+---+----+------+--------+------+------+
4596 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4597 * +----+------+-------------+---+----+------+--------+------+------+
4599 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4601 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4603 sf
= extract32(insn
, 31, 1);
4604 n
= extract32(insn
, 22, 1);
4605 rm
= extract32(insn
, 16, 5);
4606 imm
= extract32(insn
, 10, 6);
4607 rn
= extract32(insn
, 5, 5);
4608 rd
= extract32(insn
, 0, 5);
4609 op21
= extract32(insn
, 29, 2);
4610 op0
= extract32(insn
, 21, 1);
4611 bitsize
= sf
? 64 : 32;
4613 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4614 unallocated_encoding(s
);
4616 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4618 tcg_rd
= cpu_reg(s
, rd
);
4620 if (unlikely(imm
== 0)) {
4621 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4622 * so an extract from bit 0 is a special case.
4625 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4627 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4630 tcg_rm
= cpu_reg(s
, rm
);
4631 tcg_rn
= cpu_reg(s
, rn
);
4634 /* Specialization to ROR happens in EXTRACT2. */
4635 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4637 TCGv_i32 t0
= tcg_temp_new_i32();
4639 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4641 tcg_gen_rotri_i32(t0
, t0
, imm
);
4643 TCGv_i32 t1
= tcg_temp_new_i32();
4644 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4645 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4646 tcg_temp_free_i32(t1
);
4648 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4649 tcg_temp_free_i32(t0
);
4655 /* Data processing - immediate */
4656 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4658 switch (extract32(insn
, 23, 6)) {
4659 case 0x20: case 0x21: /* PC-rel. addressing */
4660 disas_pc_rel_adr(s
, insn
);
4662 case 0x22: /* Add/subtract (immediate) */
4663 disas_add_sub_imm(s
, insn
);
4665 case 0x23: /* Add/subtract (immediate, with tags) */
4666 disas_add_sub_imm_with_tags(s
, insn
);
4668 case 0x24: /* Logical (immediate) */
4669 disas_logic_imm(s
, insn
);
4671 case 0x25: /* Move wide (immediate) */
4672 disas_movw_imm(s
, insn
);
4674 case 0x26: /* Bitfield */
4675 disas_bitfield(s
, insn
);
4677 case 0x27: /* Extract */
4678 disas_extract(s
, insn
);
4681 unallocated_encoding(s
);
4686 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4687 * Note that it is the caller's responsibility to ensure that the
4688 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4689 * mandated semantics for out of range shifts.
4691 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4692 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4694 switch (shift_type
) {
4695 case A64_SHIFT_TYPE_LSL
:
4696 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4698 case A64_SHIFT_TYPE_LSR
:
4699 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4701 case A64_SHIFT_TYPE_ASR
:
4703 tcg_gen_ext32s_i64(dst
, src
);
4705 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4707 case A64_SHIFT_TYPE_ROR
:
4709 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4712 t0
= tcg_temp_new_i32();
4713 t1
= tcg_temp_new_i32();
4714 tcg_gen_extrl_i64_i32(t0
, src
);
4715 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4716 tcg_gen_rotr_i32(t0
, t0
, t1
);
4717 tcg_gen_extu_i32_i64(dst
, t0
);
4718 tcg_temp_free_i32(t0
);
4719 tcg_temp_free_i32(t1
);
4723 assert(FALSE
); /* all shift types should be handled */
4727 if (!sf
) { /* zero extend final result */
4728 tcg_gen_ext32u_i64(dst
, dst
);
4732 /* Shift a TCGv src by immediate, put result in dst.
4733 * The shift amount must be in range (this should always be true as the
4734 * relevant instructions will UNDEF on bad shift immediates).
4736 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4737 enum a64_shift_type shift_type
, unsigned int shift_i
)
4739 assert(shift_i
< (sf
? 64 : 32));
4742 tcg_gen_mov_i64(dst
, src
);
4744 TCGv_i64 shift_const
;
4746 shift_const
= tcg_const_i64(shift_i
);
4747 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4748 tcg_temp_free_i64(shift_const
);
4752 /* Logical (shifted register)
4753 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4754 * +----+-----+-----------+-------+---+------+--------+------+------+
4755 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4756 * +----+-----+-----------+-------+---+------+--------+------+------+
4758 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4760 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4761 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4763 sf
= extract32(insn
, 31, 1);
4764 opc
= extract32(insn
, 29, 2);
4765 shift_type
= extract32(insn
, 22, 2);
4766 invert
= extract32(insn
, 21, 1);
4767 rm
= extract32(insn
, 16, 5);
4768 shift_amount
= extract32(insn
, 10, 6);
4769 rn
= extract32(insn
, 5, 5);
4770 rd
= extract32(insn
, 0, 5);
4772 if (!sf
&& (shift_amount
& (1 << 5))) {
4773 unallocated_encoding(s
);
4777 tcg_rd
= cpu_reg(s
, rd
);
4779 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4780 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4781 * register-register MOV and MVN, so it is worth special casing.
4783 tcg_rm
= cpu_reg(s
, rm
);
4785 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4787 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4791 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4793 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4799 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4802 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4805 tcg_rn
= cpu_reg(s
, rn
);
4807 switch (opc
| (invert
<< 2)) {
4810 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4813 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4816 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4820 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4823 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4826 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4834 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4838 gen_logic_CC(sf
, tcg_rd
);
4843 * Add/subtract (extended register)
4845 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4846 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4847 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4848 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4850 * sf: 0 -> 32bit, 1 -> 64bit
4851 * op: 0 -> add , 1 -> sub
4854 * option: extension type (see DecodeRegExtend)
4855 * imm3: optional shift to Rm
4857 * Rd = Rn + LSL(extend(Rm), amount)
4859 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4861 int rd
= extract32(insn
, 0, 5);
4862 int rn
= extract32(insn
, 5, 5);
4863 int imm3
= extract32(insn
, 10, 3);
4864 int option
= extract32(insn
, 13, 3);
4865 int rm
= extract32(insn
, 16, 5);
4866 int opt
= extract32(insn
, 22, 2);
4867 bool setflags
= extract32(insn
, 29, 1);
4868 bool sub_op
= extract32(insn
, 30, 1);
4869 bool sf
= extract32(insn
, 31, 1);
4871 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4873 TCGv_i64 tcg_result
;
4875 if (imm3
> 4 || opt
!= 0) {
4876 unallocated_encoding(s
);
4880 /* non-flag setting ops may use SP */
4882 tcg_rd
= cpu_reg_sp(s
, rd
);
4884 tcg_rd
= cpu_reg(s
, rd
);
4886 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4888 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4889 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4891 tcg_result
= tcg_temp_new_i64();
4895 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4897 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4901 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4903 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4908 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4910 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4913 tcg_temp_free_i64(tcg_result
);
4917 * Add/subtract (shifted register)
4919 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4920 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4921 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4922 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4924 * sf: 0 -> 32bit, 1 -> 64bit
4925 * op: 0 -> add , 1 -> sub
4927 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4928 * imm6: Shift amount to apply to Rm before the add/sub
4930 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4932 int rd
= extract32(insn
, 0, 5);
4933 int rn
= extract32(insn
, 5, 5);
4934 int imm6
= extract32(insn
, 10, 6);
4935 int rm
= extract32(insn
, 16, 5);
4936 int shift_type
= extract32(insn
, 22, 2);
4937 bool setflags
= extract32(insn
, 29, 1);
4938 bool sub_op
= extract32(insn
, 30, 1);
4939 bool sf
= extract32(insn
, 31, 1);
4941 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4942 TCGv_i64 tcg_rn
, tcg_rm
;
4943 TCGv_i64 tcg_result
;
4945 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4946 unallocated_encoding(s
);
4950 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4951 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4953 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4955 tcg_result
= tcg_temp_new_i64();
4959 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4961 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4965 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4967 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4972 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4974 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4977 tcg_temp_free_i64(tcg_result
);
4980 /* Data-processing (3 source)
4982 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4983 * +--+------+-----------+------+------+----+------+------+------+
4984 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4985 * +--+------+-----------+------+------+----+------+------+------+
4987 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4989 int rd
= extract32(insn
, 0, 5);
4990 int rn
= extract32(insn
, 5, 5);
4991 int ra
= extract32(insn
, 10, 5);
4992 int rm
= extract32(insn
, 16, 5);
4993 int op_id
= (extract32(insn
, 29, 3) << 4) |
4994 (extract32(insn
, 21, 3) << 1) |
4995 extract32(insn
, 15, 1);
4996 bool sf
= extract32(insn
, 31, 1);
4997 bool is_sub
= extract32(op_id
, 0, 1);
4998 bool is_high
= extract32(op_id
, 2, 1);
4999 bool is_signed
= false;
5004 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
5006 case 0x42: /* SMADDL */
5007 case 0x43: /* SMSUBL */
5008 case 0x44: /* SMULH */
5011 case 0x0: /* MADD (32bit) */
5012 case 0x1: /* MSUB (32bit) */
5013 case 0x40: /* MADD (64bit) */
5014 case 0x41: /* MSUB (64bit) */
5015 case 0x4a: /* UMADDL */
5016 case 0x4b: /* UMSUBL */
5017 case 0x4c: /* UMULH */
5020 unallocated_encoding(s
);
5025 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5026 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5027 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5028 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5031 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5033 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5036 tcg_temp_free_i64(low_bits
);
5040 tcg_op1
= tcg_temp_new_i64();
5041 tcg_op2
= tcg_temp_new_i64();
5042 tcg_tmp
= tcg_temp_new_i64();
5045 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5046 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5049 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5050 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5052 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5053 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5057 if (ra
== 31 && !is_sub
) {
5058 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5059 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5061 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5063 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5065 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5070 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5073 tcg_temp_free_i64(tcg_op1
);
5074 tcg_temp_free_i64(tcg_op2
);
5075 tcg_temp_free_i64(tcg_tmp
);
5078 /* Add/subtract (with carry)
5079 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5080 * +--+--+--+------------------------+------+-------------+------+-----+
5081 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5082 * +--+--+--+------------------------+------+-------------+------+-----+
5085 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5087 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5088 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5090 sf
= extract32(insn
, 31, 1);
5091 op
= extract32(insn
, 30, 1);
5092 setflags
= extract32(insn
, 29, 1);
5093 rm
= extract32(insn
, 16, 5);
5094 rn
= extract32(insn
, 5, 5);
5095 rd
= extract32(insn
, 0, 5);
5097 tcg_rd
= cpu_reg(s
, rd
);
5098 tcg_rn
= cpu_reg(s
, rn
);
5101 tcg_y
= new_tmp_a64(s
);
5102 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5104 tcg_y
= cpu_reg(s
, rm
);
5108 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5110 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5115 * Rotate right into flags
5116 * 31 30 29 21 15 10 5 4 0
5117 * +--+--+--+-----------------+--------+-----------+------+--+------+
5118 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5119 * +--+--+--+-----------------+--------+-----------+------+--+------+
5121 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5123 int mask
= extract32(insn
, 0, 4);
5124 int o2
= extract32(insn
, 4, 1);
5125 int rn
= extract32(insn
, 5, 5);
5126 int imm6
= extract32(insn
, 15, 6);
5127 int sf_op_s
= extract32(insn
, 29, 3);
5131 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5132 unallocated_encoding(s
);
5136 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5137 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5139 nzcv
= tcg_temp_new_i32();
5140 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5142 if (mask
& 8) { /* N */
5143 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5145 if (mask
& 4) { /* Z */
5146 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5147 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5149 if (mask
& 2) { /* C */
5150 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5152 if (mask
& 1) { /* V */
5153 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5156 tcg_temp_free_i32(nzcv
);
5160 * Evaluate into flags
5161 * 31 30 29 21 15 14 10 5 4 0
5162 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5163 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5164 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5166 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5168 int o3_mask
= extract32(insn
, 0, 5);
5169 int rn
= extract32(insn
, 5, 5);
5170 int o2
= extract32(insn
, 15, 6);
5171 int sz
= extract32(insn
, 14, 1);
5172 int sf_op_s
= extract32(insn
, 29, 3);
5176 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5177 !dc_isar_feature(aa64_condm_4
, s
)) {
5178 unallocated_encoding(s
);
5181 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5183 tmp
= tcg_temp_new_i32();
5184 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5185 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5186 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5187 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5188 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5189 tcg_temp_free_i32(tmp
);
5192 /* Conditional compare (immediate / register)
5193 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5194 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5195 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5196 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5199 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5201 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5202 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5203 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5206 if (!extract32(insn
, 29, 1)) {
5207 unallocated_encoding(s
);
5210 if (insn
& (1 << 10 | 1 << 4)) {
5211 unallocated_encoding(s
);
5214 sf
= extract32(insn
, 31, 1);
5215 op
= extract32(insn
, 30, 1);
5216 is_imm
= extract32(insn
, 11, 1);
5217 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5218 cond
= extract32(insn
, 12, 4);
5219 rn
= extract32(insn
, 5, 5);
5220 nzcv
= extract32(insn
, 0, 4);
5222 /* Set T0 = !COND. */
5223 tcg_t0
= tcg_temp_new_i32();
5224 arm_test_cc(&c
, cond
);
5225 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5228 /* Load the arguments for the new comparison. */
5230 tcg_y
= new_tmp_a64(s
);
5231 tcg_gen_movi_i64(tcg_y
, y
);
5233 tcg_y
= cpu_reg(s
, y
);
5235 tcg_rn
= cpu_reg(s
, rn
);
5237 /* Set the flags for the new comparison. */
5238 tcg_tmp
= tcg_temp_new_i64();
5240 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5242 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5244 tcg_temp_free_i64(tcg_tmp
);
5246 /* If COND was false, force the flags to #nzcv. Compute two masks
5247 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5248 * For tcg hosts that support ANDC, we can make do with just T1.
5249 * In either case, allow the tcg optimizer to delete any unused mask.
5251 tcg_t1
= tcg_temp_new_i32();
5252 tcg_t2
= tcg_temp_new_i32();
5253 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5254 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5256 if (nzcv
& 8) { /* N */
5257 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5259 if (TCG_TARGET_HAS_andc_i32
) {
5260 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5262 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5265 if (nzcv
& 4) { /* Z */
5266 if (TCG_TARGET_HAS_andc_i32
) {
5267 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5269 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5272 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5274 if (nzcv
& 2) { /* C */
5275 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5277 if (TCG_TARGET_HAS_andc_i32
) {
5278 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5280 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5283 if (nzcv
& 1) { /* V */
5284 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5286 if (TCG_TARGET_HAS_andc_i32
) {
5287 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5289 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5292 tcg_temp_free_i32(tcg_t0
);
5293 tcg_temp_free_i32(tcg_t1
);
5294 tcg_temp_free_i32(tcg_t2
);
5297 /* Conditional select
5298 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5299 * +----+----+---+-----------------+------+------+-----+------+------+
5300 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5301 * +----+----+---+-----------------+------+------+-----+------+------+
5303 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5305 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5306 TCGv_i64 tcg_rd
, zero
;
5309 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5310 /* S == 1 or op2<1> == 1 */
5311 unallocated_encoding(s
);
5314 sf
= extract32(insn
, 31, 1);
5315 else_inv
= extract32(insn
, 30, 1);
5316 rm
= extract32(insn
, 16, 5);
5317 cond
= extract32(insn
, 12, 4);
5318 else_inc
= extract32(insn
, 10, 1);
5319 rn
= extract32(insn
, 5, 5);
5320 rd
= extract32(insn
, 0, 5);
5322 tcg_rd
= cpu_reg(s
, rd
);
5324 a64_test_cc(&c
, cond
);
5325 zero
= tcg_const_i64(0);
5327 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5329 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5331 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5334 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5335 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5336 if (else_inv
&& else_inc
) {
5337 tcg_gen_neg_i64(t_false
, t_false
);
5338 } else if (else_inv
) {
5339 tcg_gen_not_i64(t_false
, t_false
);
5340 } else if (else_inc
) {
5341 tcg_gen_addi_i64(t_false
, t_false
, 1);
5343 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5346 tcg_temp_free_i64(zero
);
5350 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5354 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5355 unsigned int rn
, unsigned int rd
)
5357 TCGv_i64 tcg_rd
, tcg_rn
;
5358 tcg_rd
= cpu_reg(s
, rd
);
5359 tcg_rn
= cpu_reg(s
, rn
);
5362 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5364 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5365 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5366 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5367 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5368 tcg_temp_free_i32(tcg_tmp32
);
5372 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5373 unsigned int rn
, unsigned int rd
)
5375 TCGv_i64 tcg_rd
, tcg_rn
;
5376 tcg_rd
= cpu_reg(s
, rd
);
5377 tcg_rn
= cpu_reg(s
, rn
);
5380 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5382 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5383 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5384 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5385 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5386 tcg_temp_free_i32(tcg_tmp32
);
5390 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5391 unsigned int rn
, unsigned int rd
)
5393 TCGv_i64 tcg_rd
, tcg_rn
;
5394 tcg_rd
= cpu_reg(s
, rd
);
5395 tcg_rn
= cpu_reg(s
, rn
);
5398 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5400 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5401 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5402 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5403 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5404 tcg_temp_free_i32(tcg_tmp32
);
5408 /* REV with sf==1, opcode==3 ("REV64") */
5409 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5410 unsigned int rn
, unsigned int rd
)
5413 unallocated_encoding(s
);
5416 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5419 /* REV with sf==0, opcode==2
5420 * REV32 (sf==1, opcode==2)
5422 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5423 unsigned int rn
, unsigned int rd
)
5425 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5428 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5429 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5431 /* bswap32_i64 requires zero high word */
5432 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
5433 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
5434 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
5435 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
5436 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5438 tcg_temp_free_i64(tcg_tmp
);
5440 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
5441 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5445 /* REV16 (opcode==1) */
5446 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5447 unsigned int rn
, unsigned int rd
)
5449 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5450 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5451 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5452 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5454 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5455 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5456 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5457 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5458 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5460 tcg_temp_free_i64(mask
);
5461 tcg_temp_free_i64(tcg_tmp
);
5464 /* Data-processing (1 source)
5465 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5466 * +----+---+---+-----------------+---------+--------+------+------+
5467 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5468 * +----+---+---+-----------------+---------+--------+------+------+
5470 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5472 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5475 if (extract32(insn
, 29, 1)) {
5476 unallocated_encoding(s
);
5480 sf
= extract32(insn
, 31, 1);
5481 opcode
= extract32(insn
, 10, 6);
5482 opcode2
= extract32(insn
, 16, 5);
5483 rn
= extract32(insn
, 5, 5);
5484 rd
= extract32(insn
, 0, 5);
5486 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5488 switch (MAP(sf
, opcode2
, opcode
)) {
5489 case MAP(0, 0x00, 0x00): /* RBIT */
5490 case MAP(1, 0x00, 0x00):
5491 handle_rbit(s
, sf
, rn
, rd
);
5493 case MAP(0, 0x00, 0x01): /* REV16 */
5494 case MAP(1, 0x00, 0x01):
5495 handle_rev16(s
, sf
, rn
, rd
);
5497 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5498 case MAP(1, 0x00, 0x02):
5499 handle_rev32(s
, sf
, rn
, rd
);
5501 case MAP(1, 0x00, 0x03): /* REV64 */
5502 handle_rev64(s
, sf
, rn
, rd
);
5504 case MAP(0, 0x00, 0x04): /* CLZ */
5505 case MAP(1, 0x00, 0x04):
5506 handle_clz(s
, sf
, rn
, rd
);
5508 case MAP(0, 0x00, 0x05): /* CLS */
5509 case MAP(1, 0x00, 0x05):
5510 handle_cls(s
, sf
, rn
, rd
);
5512 case MAP(1, 0x01, 0x00): /* PACIA */
5513 if (s
->pauth_active
) {
5514 tcg_rd
= cpu_reg(s
, rd
);
5515 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5516 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5517 goto do_unallocated
;
5520 case MAP(1, 0x01, 0x01): /* PACIB */
5521 if (s
->pauth_active
) {
5522 tcg_rd
= cpu_reg(s
, rd
);
5523 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5524 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5525 goto do_unallocated
;
5528 case MAP(1, 0x01, 0x02): /* PACDA */
5529 if (s
->pauth_active
) {
5530 tcg_rd
= cpu_reg(s
, rd
);
5531 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5532 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5533 goto do_unallocated
;
5536 case MAP(1, 0x01, 0x03): /* PACDB */
5537 if (s
->pauth_active
) {
5538 tcg_rd
= cpu_reg(s
, rd
);
5539 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5540 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5541 goto do_unallocated
;
5544 case MAP(1, 0x01, 0x04): /* AUTIA */
5545 if (s
->pauth_active
) {
5546 tcg_rd
= cpu_reg(s
, rd
);
5547 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5548 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5549 goto do_unallocated
;
5552 case MAP(1, 0x01, 0x05): /* AUTIB */
5553 if (s
->pauth_active
) {
5554 tcg_rd
= cpu_reg(s
, rd
);
5555 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5556 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5557 goto do_unallocated
;
5560 case MAP(1, 0x01, 0x06): /* AUTDA */
5561 if (s
->pauth_active
) {
5562 tcg_rd
= cpu_reg(s
, rd
);
5563 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5564 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5565 goto do_unallocated
;
5568 case MAP(1, 0x01, 0x07): /* AUTDB */
5569 if (s
->pauth_active
) {
5570 tcg_rd
= cpu_reg(s
, rd
);
5571 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5572 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5573 goto do_unallocated
;
5576 case MAP(1, 0x01, 0x08): /* PACIZA */
5577 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5578 goto do_unallocated
;
5579 } else if (s
->pauth_active
) {
5580 tcg_rd
= cpu_reg(s
, rd
);
5581 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5584 case MAP(1, 0x01, 0x09): /* PACIZB */
5585 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5586 goto do_unallocated
;
5587 } else if (s
->pauth_active
) {
5588 tcg_rd
= cpu_reg(s
, rd
);
5589 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5592 case MAP(1, 0x01, 0x0a): /* PACDZA */
5593 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5594 goto do_unallocated
;
5595 } else if (s
->pauth_active
) {
5596 tcg_rd
= cpu_reg(s
, rd
);
5597 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5600 case MAP(1, 0x01, 0x0b): /* PACDZB */
5601 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5602 goto do_unallocated
;
5603 } else if (s
->pauth_active
) {
5604 tcg_rd
= cpu_reg(s
, rd
);
5605 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5608 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5609 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5610 goto do_unallocated
;
5611 } else if (s
->pauth_active
) {
5612 tcg_rd
= cpu_reg(s
, rd
);
5613 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5616 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5617 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5618 goto do_unallocated
;
5619 } else if (s
->pauth_active
) {
5620 tcg_rd
= cpu_reg(s
, rd
);
5621 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5624 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5625 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5626 goto do_unallocated
;
5627 } else if (s
->pauth_active
) {
5628 tcg_rd
= cpu_reg(s
, rd
);
5629 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5632 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5633 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5634 goto do_unallocated
;
5635 } else if (s
->pauth_active
) {
5636 tcg_rd
= cpu_reg(s
, rd
);
5637 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5640 case MAP(1, 0x01, 0x10): /* XPACI */
5641 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5642 goto do_unallocated
;
5643 } else if (s
->pauth_active
) {
5644 tcg_rd
= cpu_reg(s
, rd
);
5645 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5648 case MAP(1, 0x01, 0x11): /* XPACD */
5649 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5650 goto do_unallocated
;
5651 } else if (s
->pauth_active
) {
5652 tcg_rd
= cpu_reg(s
, rd
);
5653 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5658 unallocated_encoding(s
);
5665 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5666 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5668 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5669 tcg_rd
= cpu_reg(s
, rd
);
5671 if (!sf
&& is_signed
) {
5672 tcg_n
= new_tmp_a64(s
);
5673 tcg_m
= new_tmp_a64(s
);
5674 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5675 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5677 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5678 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5682 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5684 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5687 if (!sf
) { /* zero extend final result */
5688 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5692 /* LSLV, LSRV, ASRV, RORV */
5693 static void handle_shift_reg(DisasContext
*s
,
5694 enum a64_shift_type shift_type
, unsigned int sf
,
5695 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5697 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5698 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5699 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5701 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5702 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5703 tcg_temp_free_i64(tcg_shift
);
5706 /* CRC32[BHWX], CRC32C[BHWX] */
5707 static void handle_crc32(DisasContext
*s
,
5708 unsigned int sf
, unsigned int sz
, bool crc32c
,
5709 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5711 TCGv_i64 tcg_acc
, tcg_val
;
5714 if (!dc_isar_feature(aa64_crc32
, s
)
5715 || (sf
== 1 && sz
!= 3)
5716 || (sf
== 0 && sz
== 3)) {
5717 unallocated_encoding(s
);
5722 tcg_val
= cpu_reg(s
, rm
);
5736 g_assert_not_reached();
5738 tcg_val
= new_tmp_a64(s
);
5739 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5742 tcg_acc
= cpu_reg(s
, rn
);
5743 tcg_bytes
= tcg_const_i32(1 << sz
);
5746 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5748 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5751 tcg_temp_free_i32(tcg_bytes
);
5754 /* Data-processing (2 source)
5755 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5756 * +----+---+---+-----------------+------+--------+------+------+
5757 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5758 * +----+---+---+-----------------+------+--------+------+------+
5760 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5762 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5763 sf
= extract32(insn
, 31, 1);
5764 setflag
= extract32(insn
, 29, 1);
5765 rm
= extract32(insn
, 16, 5);
5766 opcode
= extract32(insn
, 10, 6);
5767 rn
= extract32(insn
, 5, 5);
5768 rd
= extract32(insn
, 0, 5);
5770 if (setflag
&& opcode
!= 0) {
5771 unallocated_encoding(s
);
5776 case 0: /* SUBP(S) */
5777 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5778 goto do_unallocated
;
5780 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5782 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5783 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5784 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5785 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5786 tcg_d
= cpu_reg(s
, rd
);
5789 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5791 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5796 handle_div(s
, false, sf
, rm
, rn
, rd
);
5799 handle_div(s
, true, sf
, rm
, rn
, rd
);
5802 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5803 goto do_unallocated
;
5806 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5807 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5809 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5814 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5815 goto do_unallocated
;
5817 TCGv_i64 t1
= tcg_const_i64(1);
5818 TCGv_i64 t2
= tcg_temp_new_i64();
5820 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5821 tcg_gen_shl_i64(t1
, t1
, t2
);
5822 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5824 tcg_temp_free_i64(t1
);
5825 tcg_temp_free_i64(t2
);
5829 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5832 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5835 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5838 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5840 case 12: /* PACGA */
5841 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5842 goto do_unallocated
;
5844 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5845 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5854 case 23: /* CRC32 */
5856 int sz
= extract32(opcode
, 0, 2);
5857 bool crc32c
= extract32(opcode
, 2, 1);
5858 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5863 unallocated_encoding(s
);
5869 * Data processing - register
5870 * 31 30 29 28 25 21 20 16 10 0
5871 * +--+---+--+---+-------+-----+-------+-------+---------+
5872 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5873 * +--+---+--+---+-------+-----+-------+-------+---------+
5875 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5877 int op0
= extract32(insn
, 30, 1);
5878 int op1
= extract32(insn
, 28, 1);
5879 int op2
= extract32(insn
, 21, 4);
5880 int op3
= extract32(insn
, 10, 6);
5885 /* Add/sub (extended register) */
5886 disas_add_sub_ext_reg(s
, insn
);
5888 /* Add/sub (shifted register) */
5889 disas_add_sub_reg(s
, insn
);
5892 /* Logical (shifted register) */
5893 disas_logic_reg(s
, insn
);
5901 case 0x00: /* Add/subtract (with carry) */
5902 disas_adc_sbc(s
, insn
);
5905 case 0x01: /* Rotate right into flags */
5907 disas_rotate_right_into_flags(s
, insn
);
5910 case 0x02: /* Evaluate into flags */
5914 disas_evaluate_into_flags(s
, insn
);
5918 goto do_unallocated
;
5922 case 0x2: /* Conditional compare */
5923 disas_cc(s
, insn
); /* both imm and reg forms */
5926 case 0x4: /* Conditional select */
5927 disas_cond_select(s
, insn
);
5930 case 0x6: /* Data-processing */
5931 if (op0
) { /* (1 source) */
5932 disas_data_proc_1src(s
, insn
);
5933 } else { /* (2 source) */
5934 disas_data_proc_2src(s
, insn
);
5937 case 0x8 ... 0xf: /* (3 source) */
5938 disas_data_proc_3src(s
, insn
);
5943 unallocated_encoding(s
);
5948 static void handle_fp_compare(DisasContext
*s
, int size
,
5949 unsigned int rn
, unsigned int rm
,
5950 bool cmp_with_zero
, bool signal_all_nans
)
5952 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5953 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5955 if (size
== MO_64
) {
5956 TCGv_i64 tcg_vn
, tcg_vm
;
5958 tcg_vn
= read_fp_dreg(s
, rn
);
5959 if (cmp_with_zero
) {
5960 tcg_vm
= tcg_const_i64(0);
5962 tcg_vm
= read_fp_dreg(s
, rm
);
5964 if (signal_all_nans
) {
5965 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5967 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5969 tcg_temp_free_i64(tcg_vn
);
5970 tcg_temp_free_i64(tcg_vm
);
5972 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5973 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5975 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5976 if (cmp_with_zero
) {
5977 tcg_gen_movi_i32(tcg_vm
, 0);
5979 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5984 if (signal_all_nans
) {
5985 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5987 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5991 if (signal_all_nans
) {
5992 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5994 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5998 g_assert_not_reached();
6001 tcg_temp_free_i32(tcg_vn
);
6002 tcg_temp_free_i32(tcg_vm
);
6005 tcg_temp_free_ptr(fpst
);
6007 gen_set_nzcv(tcg_flags
);
6009 tcg_temp_free_i64(tcg_flags
);
6012 /* Floating point compare
6013 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
6014 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6015 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
6016 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6018 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
6020 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
6023 mos
= extract32(insn
, 29, 3);
6024 type
= extract32(insn
, 22, 2);
6025 rm
= extract32(insn
, 16, 5);
6026 op
= extract32(insn
, 14, 2);
6027 rn
= extract32(insn
, 5, 5);
6028 opc
= extract32(insn
, 3, 2);
6029 op2r
= extract32(insn
, 0, 3);
6031 if (mos
|| op
|| op2r
) {
6032 unallocated_encoding(s
);
6045 if (dc_isar_feature(aa64_fp16
, s
)) {
6050 unallocated_encoding(s
);
6054 if (!fp_access_check(s
)) {
6058 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6061 /* Floating point conditional compare
6062 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6063 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6064 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6065 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6067 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6069 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6071 TCGLabel
*label_continue
= NULL
;
6074 mos
= extract32(insn
, 29, 3);
6075 type
= extract32(insn
, 22, 2);
6076 rm
= extract32(insn
, 16, 5);
6077 cond
= extract32(insn
, 12, 4);
6078 rn
= extract32(insn
, 5, 5);
6079 op
= extract32(insn
, 4, 1);
6080 nzcv
= extract32(insn
, 0, 4);
6083 unallocated_encoding(s
);
6096 if (dc_isar_feature(aa64_fp16
, s
)) {
6101 unallocated_encoding(s
);
6105 if (!fp_access_check(s
)) {
6109 if (cond
< 0x0e) { /* not always */
6110 TCGLabel
*label_match
= gen_new_label();
6111 label_continue
= gen_new_label();
6112 arm_gen_test_cc(cond
, label_match
);
6114 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6115 gen_set_nzcv(tcg_flags
);
6116 tcg_temp_free_i64(tcg_flags
);
6117 tcg_gen_br(label_continue
);
6118 gen_set_label(label_match
);
6121 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6124 gen_set_label(label_continue
);
6128 /* Floating point conditional select
6129 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6130 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6131 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6132 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6134 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6136 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6137 TCGv_i64 t_true
, t_false
, t_zero
;
6141 mos
= extract32(insn
, 29, 3);
6142 type
= extract32(insn
, 22, 2);
6143 rm
= extract32(insn
, 16, 5);
6144 cond
= extract32(insn
, 12, 4);
6145 rn
= extract32(insn
, 5, 5);
6146 rd
= extract32(insn
, 0, 5);
6149 unallocated_encoding(s
);
6162 if (dc_isar_feature(aa64_fp16
, s
)) {
6167 unallocated_encoding(s
);
6171 if (!fp_access_check(s
)) {
6175 /* Zero extend sreg & hreg inputs to 64 bits now. */
6176 t_true
= tcg_temp_new_i64();
6177 t_false
= tcg_temp_new_i64();
6178 read_vec_element(s
, t_true
, rn
, 0, sz
);
6179 read_vec_element(s
, t_false
, rm
, 0, sz
);
6181 a64_test_cc(&c
, cond
);
6182 t_zero
= tcg_const_i64(0);
6183 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6184 tcg_temp_free_i64(t_zero
);
6185 tcg_temp_free_i64(t_false
);
6188 /* Note that sregs & hregs write back zeros to the high bits,
6189 and we've already done the zero-extension. */
6190 write_fp_dreg(s
, rd
, t_true
);
6191 tcg_temp_free_i64(t_true
);
6194 /* Floating-point data-processing (1 source) - half precision */
6195 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6197 TCGv_ptr fpst
= NULL
;
6198 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6199 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6202 case 0x0: /* FMOV */
6203 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6205 case 0x1: /* FABS */
6206 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6208 case 0x2: /* FNEG */
6209 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6211 case 0x3: /* FSQRT */
6212 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6213 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6215 case 0x8: /* FRINTN */
6216 case 0x9: /* FRINTP */
6217 case 0xa: /* FRINTM */
6218 case 0xb: /* FRINTZ */
6219 case 0xc: /* FRINTA */
6221 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6222 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6224 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6225 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6227 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6228 tcg_temp_free_i32(tcg_rmode
);
6231 case 0xe: /* FRINTX */
6232 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6233 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6235 case 0xf: /* FRINTI */
6236 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6237 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6243 write_fp_sreg(s
, rd
, tcg_res
);
6246 tcg_temp_free_ptr(fpst
);
6248 tcg_temp_free_i32(tcg_op
);
6249 tcg_temp_free_i32(tcg_res
);
6252 /* Floating-point data-processing (1 source) - single precision */
6253 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6255 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6256 TCGv_i32 tcg_op
, tcg_res
;
6260 tcg_op
= read_fp_sreg(s
, rn
);
6261 tcg_res
= tcg_temp_new_i32();
6264 case 0x0: /* FMOV */
6265 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6267 case 0x1: /* FABS */
6268 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6270 case 0x2: /* FNEG */
6271 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6273 case 0x3: /* FSQRT */
6274 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6276 case 0x8: /* FRINTN */
6277 case 0x9: /* FRINTP */
6278 case 0xa: /* FRINTM */
6279 case 0xb: /* FRINTZ */
6280 case 0xc: /* FRINTA */
6281 rmode
= arm_rmode_to_sf(opcode
& 7);
6282 gen_fpst
= gen_helper_rints
;
6284 case 0xe: /* FRINTX */
6285 gen_fpst
= gen_helper_rints_exact
;
6287 case 0xf: /* FRINTI */
6288 gen_fpst
= gen_helper_rints
;
6290 case 0x10: /* FRINT32Z */
6291 rmode
= float_round_to_zero
;
6292 gen_fpst
= gen_helper_frint32_s
;
6294 case 0x11: /* FRINT32X */
6295 gen_fpst
= gen_helper_frint32_s
;
6297 case 0x12: /* FRINT64Z */
6298 rmode
= float_round_to_zero
;
6299 gen_fpst
= gen_helper_frint64_s
;
6301 case 0x13: /* FRINT64X */
6302 gen_fpst
= gen_helper_frint64_s
;
6305 g_assert_not_reached();
6308 fpst
= fpstatus_ptr(FPST_FPCR
);
6310 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6311 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6312 gen_fpst(tcg_res
, tcg_op
, fpst
);
6313 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6314 tcg_temp_free_i32(tcg_rmode
);
6316 gen_fpst(tcg_res
, tcg_op
, fpst
);
6318 tcg_temp_free_ptr(fpst
);
6321 write_fp_sreg(s
, rd
, tcg_res
);
6322 tcg_temp_free_i32(tcg_op
);
6323 tcg_temp_free_i32(tcg_res
);
6326 /* Floating-point data-processing (1 source) - double precision */
6327 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6329 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6330 TCGv_i64 tcg_op
, tcg_res
;
6335 case 0x0: /* FMOV */
6336 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6340 tcg_op
= read_fp_dreg(s
, rn
);
6341 tcg_res
= tcg_temp_new_i64();
6344 case 0x1: /* FABS */
6345 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6347 case 0x2: /* FNEG */
6348 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6350 case 0x3: /* FSQRT */
6351 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6353 case 0x8: /* FRINTN */
6354 case 0x9: /* FRINTP */
6355 case 0xa: /* FRINTM */
6356 case 0xb: /* FRINTZ */
6357 case 0xc: /* FRINTA */
6358 rmode
= arm_rmode_to_sf(opcode
& 7);
6359 gen_fpst
= gen_helper_rintd
;
6361 case 0xe: /* FRINTX */
6362 gen_fpst
= gen_helper_rintd_exact
;
6364 case 0xf: /* FRINTI */
6365 gen_fpst
= gen_helper_rintd
;
6367 case 0x10: /* FRINT32Z */
6368 rmode
= float_round_to_zero
;
6369 gen_fpst
= gen_helper_frint32_d
;
6371 case 0x11: /* FRINT32X */
6372 gen_fpst
= gen_helper_frint32_d
;
6374 case 0x12: /* FRINT64Z */
6375 rmode
= float_round_to_zero
;
6376 gen_fpst
= gen_helper_frint64_d
;
6378 case 0x13: /* FRINT64X */
6379 gen_fpst
= gen_helper_frint64_d
;
6382 g_assert_not_reached();
6385 fpst
= fpstatus_ptr(FPST_FPCR
);
6387 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6388 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6389 gen_fpst(tcg_res
, tcg_op
, fpst
);
6390 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6391 tcg_temp_free_i32(tcg_rmode
);
6393 gen_fpst(tcg_res
, tcg_op
, fpst
);
6395 tcg_temp_free_ptr(fpst
);
6398 write_fp_dreg(s
, rd
, tcg_res
);
6399 tcg_temp_free_i64(tcg_op
);
6400 tcg_temp_free_i64(tcg_res
);
6403 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6404 int rd
, int rn
, int dtype
, int ntype
)
6409 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6411 /* Single to double */
6412 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6413 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6414 write_fp_dreg(s
, rd
, tcg_rd
);
6415 tcg_temp_free_i64(tcg_rd
);
6417 /* Single to half */
6418 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6419 TCGv_i32 ahp
= get_ahp_flag();
6420 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6422 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6423 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6424 write_fp_sreg(s
, rd
, tcg_rd
);
6425 tcg_temp_free_i32(tcg_rd
);
6426 tcg_temp_free_i32(ahp
);
6427 tcg_temp_free_ptr(fpst
);
6429 tcg_temp_free_i32(tcg_rn
);
6434 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6435 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6437 /* Double to single */
6438 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6440 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6441 TCGv_i32 ahp
= get_ahp_flag();
6442 /* Double to half */
6443 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6444 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6445 tcg_temp_free_ptr(fpst
);
6446 tcg_temp_free_i32(ahp
);
6448 write_fp_sreg(s
, rd
, tcg_rd
);
6449 tcg_temp_free_i32(tcg_rd
);
6450 tcg_temp_free_i64(tcg_rn
);
6455 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6456 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6457 TCGv_i32 tcg_ahp
= get_ahp_flag();
6458 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6460 /* Half to single */
6461 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6462 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6463 write_fp_sreg(s
, rd
, tcg_rd
);
6464 tcg_temp_free_i32(tcg_rd
);
6466 /* Half to double */
6467 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6468 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6469 write_fp_dreg(s
, rd
, tcg_rd
);
6470 tcg_temp_free_i64(tcg_rd
);
6472 tcg_temp_free_i32(tcg_rn
);
6473 tcg_temp_free_ptr(tcg_fpst
);
6474 tcg_temp_free_i32(tcg_ahp
);
6482 /* Floating point data-processing (1 source)
6483 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6484 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6485 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6486 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6488 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6490 int mos
= extract32(insn
, 29, 3);
6491 int type
= extract32(insn
, 22, 2);
6492 int opcode
= extract32(insn
, 15, 6);
6493 int rn
= extract32(insn
, 5, 5);
6494 int rd
= extract32(insn
, 0, 5);
6497 unallocated_encoding(s
);
6502 case 0x4: case 0x5: case 0x7:
6504 /* FCVT between half, single and double precision */
6505 int dtype
= extract32(opcode
, 0, 2);
6506 if (type
== 2 || dtype
== type
) {
6507 unallocated_encoding(s
);
6510 if (!fp_access_check(s
)) {
6514 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6518 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6519 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6520 unallocated_encoding(s
);
6527 /* 32-to-32 and 64-to-64 ops */
6530 if (!fp_access_check(s
)) {
6533 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6536 if (!fp_access_check(s
)) {
6539 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6542 if (!dc_isar_feature(aa64_fp16
, s
)) {
6543 unallocated_encoding(s
);
6547 if (!fp_access_check(s
)) {
6550 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6553 unallocated_encoding(s
);
6558 unallocated_encoding(s
);
6563 /* Floating-point data-processing (2 source) - single precision */
6564 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6565 int rd
, int rn
, int rm
)
6572 tcg_res
= tcg_temp_new_i32();
6573 fpst
= fpstatus_ptr(FPST_FPCR
);
6574 tcg_op1
= read_fp_sreg(s
, rn
);
6575 tcg_op2
= read_fp_sreg(s
, rm
);
6578 case 0x0: /* FMUL */
6579 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6581 case 0x1: /* FDIV */
6582 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6584 case 0x2: /* FADD */
6585 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6587 case 0x3: /* FSUB */
6588 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6590 case 0x4: /* FMAX */
6591 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6593 case 0x5: /* FMIN */
6594 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6596 case 0x6: /* FMAXNM */
6597 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6599 case 0x7: /* FMINNM */
6600 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6602 case 0x8: /* FNMUL */
6603 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6604 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6608 write_fp_sreg(s
, rd
, tcg_res
);
6610 tcg_temp_free_ptr(fpst
);
6611 tcg_temp_free_i32(tcg_op1
);
6612 tcg_temp_free_i32(tcg_op2
);
6613 tcg_temp_free_i32(tcg_res
);
6616 /* Floating-point data-processing (2 source) - double precision */
6617 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6618 int rd
, int rn
, int rm
)
6625 tcg_res
= tcg_temp_new_i64();
6626 fpst
= fpstatus_ptr(FPST_FPCR
);
6627 tcg_op1
= read_fp_dreg(s
, rn
);
6628 tcg_op2
= read_fp_dreg(s
, rm
);
6631 case 0x0: /* FMUL */
6632 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6634 case 0x1: /* FDIV */
6635 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6637 case 0x2: /* FADD */
6638 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6640 case 0x3: /* FSUB */
6641 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6643 case 0x4: /* FMAX */
6644 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6646 case 0x5: /* FMIN */
6647 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6649 case 0x6: /* FMAXNM */
6650 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6652 case 0x7: /* FMINNM */
6653 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6655 case 0x8: /* FNMUL */
6656 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6657 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6661 write_fp_dreg(s
, rd
, tcg_res
);
6663 tcg_temp_free_ptr(fpst
);
6664 tcg_temp_free_i64(tcg_op1
);
6665 tcg_temp_free_i64(tcg_op2
);
6666 tcg_temp_free_i64(tcg_res
);
6669 /* Floating-point data-processing (2 source) - half precision */
6670 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6671 int rd
, int rn
, int rm
)
6678 tcg_res
= tcg_temp_new_i32();
6679 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6680 tcg_op1
= read_fp_hreg(s
, rn
);
6681 tcg_op2
= read_fp_hreg(s
, rm
);
6684 case 0x0: /* FMUL */
6685 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6687 case 0x1: /* FDIV */
6688 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6690 case 0x2: /* FADD */
6691 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6693 case 0x3: /* FSUB */
6694 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6696 case 0x4: /* FMAX */
6697 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6699 case 0x5: /* FMIN */
6700 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6702 case 0x6: /* FMAXNM */
6703 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6705 case 0x7: /* FMINNM */
6706 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6708 case 0x8: /* FNMUL */
6709 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6710 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6713 g_assert_not_reached();
6716 write_fp_sreg(s
, rd
, tcg_res
);
6718 tcg_temp_free_ptr(fpst
);
6719 tcg_temp_free_i32(tcg_op1
);
6720 tcg_temp_free_i32(tcg_op2
);
6721 tcg_temp_free_i32(tcg_res
);
6724 /* Floating point data-processing (2 source)
6725 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6726 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6727 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6728 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6730 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6732 int mos
= extract32(insn
, 29, 3);
6733 int type
= extract32(insn
, 22, 2);
6734 int rd
= extract32(insn
, 0, 5);
6735 int rn
= extract32(insn
, 5, 5);
6736 int rm
= extract32(insn
, 16, 5);
6737 int opcode
= extract32(insn
, 12, 4);
6739 if (opcode
> 8 || mos
) {
6740 unallocated_encoding(s
);
6746 if (!fp_access_check(s
)) {
6749 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6752 if (!fp_access_check(s
)) {
6755 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6758 if (!dc_isar_feature(aa64_fp16
, s
)) {
6759 unallocated_encoding(s
);
6762 if (!fp_access_check(s
)) {
6765 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6768 unallocated_encoding(s
);
6772 /* Floating-point data-processing (3 source) - single precision */
6773 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6774 int rd
, int rn
, int rm
, int ra
)
6776 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6777 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6778 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6780 tcg_op1
= read_fp_sreg(s
, rn
);
6781 tcg_op2
= read_fp_sreg(s
, rm
);
6782 tcg_op3
= read_fp_sreg(s
, ra
);
6784 /* These are fused multiply-add, and must be done as one
6785 * floating point operation with no rounding between the
6786 * multiplication and addition steps.
6787 * NB that doing the negations here as separate steps is
6788 * correct : an input NaN should come out with its sign bit
6789 * flipped if it is a negated-input.
6792 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6796 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6799 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6801 write_fp_sreg(s
, rd
, tcg_res
);
6803 tcg_temp_free_ptr(fpst
);
6804 tcg_temp_free_i32(tcg_op1
);
6805 tcg_temp_free_i32(tcg_op2
);
6806 tcg_temp_free_i32(tcg_op3
);
6807 tcg_temp_free_i32(tcg_res
);
6810 /* Floating-point data-processing (3 source) - double precision */
6811 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6812 int rd
, int rn
, int rm
, int ra
)
6814 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6815 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6816 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6818 tcg_op1
= read_fp_dreg(s
, rn
);
6819 tcg_op2
= read_fp_dreg(s
, rm
);
6820 tcg_op3
= read_fp_dreg(s
, ra
);
6822 /* These are fused multiply-add, and must be done as one
6823 * floating point operation with no rounding between the
6824 * multiplication and addition steps.
6825 * NB that doing the negations here as separate steps is
6826 * correct : an input NaN should come out with its sign bit
6827 * flipped if it is a negated-input.
6830 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6834 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6837 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6839 write_fp_dreg(s
, rd
, tcg_res
);
6841 tcg_temp_free_ptr(fpst
);
6842 tcg_temp_free_i64(tcg_op1
);
6843 tcg_temp_free_i64(tcg_op2
);
6844 tcg_temp_free_i64(tcg_op3
);
6845 tcg_temp_free_i64(tcg_res
);
6848 /* Floating-point data-processing (3 source) - half precision */
6849 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6850 int rd
, int rn
, int rm
, int ra
)
6852 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6853 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6854 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6856 tcg_op1
= read_fp_hreg(s
, rn
);
6857 tcg_op2
= read_fp_hreg(s
, rm
);
6858 tcg_op3
= read_fp_hreg(s
, ra
);
6860 /* These are fused multiply-add, and must be done as one
6861 * floating point operation with no rounding between the
6862 * multiplication and addition steps.
6863 * NB that doing the negations here as separate steps is
6864 * correct : an input NaN should come out with its sign bit
6865 * flipped if it is a negated-input.
6868 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6872 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6875 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6877 write_fp_sreg(s
, rd
, tcg_res
);
6879 tcg_temp_free_ptr(fpst
);
6880 tcg_temp_free_i32(tcg_op1
);
6881 tcg_temp_free_i32(tcg_op2
);
6882 tcg_temp_free_i32(tcg_op3
);
6883 tcg_temp_free_i32(tcg_res
);
6886 /* Floating point data-processing (3 source)
6887 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6888 * +---+---+---+-----------+------+----+------+----+------+------+------+
6889 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6890 * +---+---+---+-----------+------+----+------+----+------+------+------+
6892 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6894 int mos
= extract32(insn
, 29, 3);
6895 int type
= extract32(insn
, 22, 2);
6896 int rd
= extract32(insn
, 0, 5);
6897 int rn
= extract32(insn
, 5, 5);
6898 int ra
= extract32(insn
, 10, 5);
6899 int rm
= extract32(insn
, 16, 5);
6900 bool o0
= extract32(insn
, 15, 1);
6901 bool o1
= extract32(insn
, 21, 1);
6904 unallocated_encoding(s
);
6910 if (!fp_access_check(s
)) {
6913 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6916 if (!fp_access_check(s
)) {
6919 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6922 if (!dc_isar_feature(aa64_fp16
, s
)) {
6923 unallocated_encoding(s
);
6926 if (!fp_access_check(s
)) {
6929 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6932 unallocated_encoding(s
);
6936 /* Floating point immediate
6937 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6938 * +---+---+---+-----------+------+---+------------+-------+------+------+
6939 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6940 * +---+---+---+-----------+------+---+------------+-------+------+------+
6942 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6944 int rd
= extract32(insn
, 0, 5);
6945 int imm5
= extract32(insn
, 5, 5);
6946 int imm8
= extract32(insn
, 13, 8);
6947 int type
= extract32(insn
, 22, 2);
6948 int mos
= extract32(insn
, 29, 3);
6954 unallocated_encoding(s
);
6967 if (dc_isar_feature(aa64_fp16
, s
)) {
6972 unallocated_encoding(s
);
6976 if (!fp_access_check(s
)) {
6980 imm
= vfp_expand_imm(sz
, imm8
);
6982 tcg_res
= tcg_const_i64(imm
);
6983 write_fp_dreg(s
, rd
, tcg_res
);
6984 tcg_temp_free_i64(tcg_res
);
6987 /* Handle floating point <=> fixed point conversions. Note that we can
6988 * also deal with fp <=> integer conversions as a special case (scale == 64)
6989 * OPTME: consider handling that special case specially or at least skipping
6990 * the call to scalbn in the helpers for zero shifts.
6992 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6993 bool itof
, int rmode
, int scale
, int sf
, int type
)
6995 bool is_signed
= !(opcode
& 1);
6996 TCGv_ptr tcg_fpstatus
;
6997 TCGv_i32 tcg_shift
, tcg_single
;
6998 TCGv_i64 tcg_double
;
7000 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
7002 tcg_shift
= tcg_const_i32(64 - scale
);
7005 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
7007 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
7010 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
7012 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
7015 tcg_int
= tcg_extend
;
7019 case 1: /* float64 */
7020 tcg_double
= tcg_temp_new_i64();
7022 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
7023 tcg_shift
, tcg_fpstatus
);
7025 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
7026 tcg_shift
, tcg_fpstatus
);
7028 write_fp_dreg(s
, rd
, tcg_double
);
7029 tcg_temp_free_i64(tcg_double
);
7032 case 0: /* float32 */
7033 tcg_single
= tcg_temp_new_i32();
7035 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
7036 tcg_shift
, tcg_fpstatus
);
7038 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
7039 tcg_shift
, tcg_fpstatus
);
7041 write_fp_sreg(s
, rd
, tcg_single
);
7042 tcg_temp_free_i32(tcg_single
);
7045 case 3: /* float16 */
7046 tcg_single
= tcg_temp_new_i32();
7048 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7049 tcg_shift
, tcg_fpstatus
);
7051 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7052 tcg_shift
, tcg_fpstatus
);
7054 write_fp_sreg(s
, rd
, tcg_single
);
7055 tcg_temp_free_i32(tcg_single
);
7059 g_assert_not_reached();
7062 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7065 if (extract32(opcode
, 2, 1)) {
7066 /* There are too many rounding modes to all fit into rmode,
7067 * so FCVTA[US] is a special case.
7069 rmode
= FPROUNDING_TIEAWAY
;
7072 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7074 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7077 case 1: /* float64 */
7078 tcg_double
= read_fp_dreg(s
, rn
);
7081 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7082 tcg_shift
, tcg_fpstatus
);
7084 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7085 tcg_shift
, tcg_fpstatus
);
7089 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7090 tcg_shift
, tcg_fpstatus
);
7092 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7093 tcg_shift
, tcg_fpstatus
);
7097 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7099 tcg_temp_free_i64(tcg_double
);
7102 case 0: /* float32 */
7103 tcg_single
= read_fp_sreg(s
, rn
);
7106 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7107 tcg_shift
, tcg_fpstatus
);
7109 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7110 tcg_shift
, tcg_fpstatus
);
7113 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7115 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7116 tcg_shift
, tcg_fpstatus
);
7118 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7119 tcg_shift
, tcg_fpstatus
);
7121 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7122 tcg_temp_free_i32(tcg_dest
);
7124 tcg_temp_free_i32(tcg_single
);
7127 case 3: /* float16 */
7128 tcg_single
= read_fp_sreg(s
, rn
);
7131 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7132 tcg_shift
, tcg_fpstatus
);
7134 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7135 tcg_shift
, tcg_fpstatus
);
7138 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7140 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7141 tcg_shift
, tcg_fpstatus
);
7143 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7144 tcg_shift
, tcg_fpstatus
);
7146 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7147 tcg_temp_free_i32(tcg_dest
);
7149 tcg_temp_free_i32(tcg_single
);
7153 g_assert_not_reached();
7156 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7157 tcg_temp_free_i32(tcg_rmode
);
7160 tcg_temp_free_ptr(tcg_fpstatus
);
7161 tcg_temp_free_i32(tcg_shift
);
7164 /* Floating point <-> fixed point conversions
7165 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7166 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7167 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7168 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7170 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7172 int rd
= extract32(insn
, 0, 5);
7173 int rn
= extract32(insn
, 5, 5);
7174 int scale
= extract32(insn
, 10, 6);
7175 int opcode
= extract32(insn
, 16, 3);
7176 int rmode
= extract32(insn
, 19, 2);
7177 int type
= extract32(insn
, 22, 2);
7178 bool sbit
= extract32(insn
, 29, 1);
7179 bool sf
= extract32(insn
, 31, 1);
7182 if (sbit
|| (!sf
&& scale
< 32)) {
7183 unallocated_encoding(s
);
7188 case 0: /* float32 */
7189 case 1: /* float64 */
7191 case 3: /* float16 */
7192 if (dc_isar_feature(aa64_fp16
, s
)) {
7197 unallocated_encoding(s
);
7201 switch ((rmode
<< 3) | opcode
) {
7202 case 0x2: /* SCVTF */
7203 case 0x3: /* UCVTF */
7206 case 0x18: /* FCVTZS */
7207 case 0x19: /* FCVTZU */
7211 unallocated_encoding(s
);
7215 if (!fp_access_check(s
)) {
7219 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7222 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7224 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7225 * without conversion.
7229 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7235 tmp
= tcg_temp_new_i64();
7236 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7237 write_fp_dreg(s
, rd
, tmp
);
7238 tcg_temp_free_i64(tmp
);
7242 write_fp_dreg(s
, rd
, tcg_rn
);
7245 /* 64 bit to top half. */
7246 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7247 clear_vec_high(s
, true, rd
);
7251 tmp
= tcg_temp_new_i64();
7252 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7253 write_fp_dreg(s
, rd
, tmp
);
7254 tcg_temp_free_i64(tmp
);
7257 g_assert_not_reached();
7260 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7265 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7269 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7272 /* 64 bits from top half */
7273 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7277 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7280 g_assert_not_reached();
7285 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7287 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7288 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7290 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7292 tcg_temp_free_ptr(fpstatus
);
7294 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7295 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7296 tcg_gen_movi_i32(cpu_CF
, 0);
7297 tcg_gen_movi_i32(cpu_NF
, 0);
7298 tcg_gen_movi_i32(cpu_VF
, 0);
7300 tcg_temp_free_i64(t
);
7303 /* Floating point <-> integer conversions
7304 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7305 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7306 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7307 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7309 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7311 int rd
= extract32(insn
, 0, 5);
7312 int rn
= extract32(insn
, 5, 5);
7313 int opcode
= extract32(insn
, 16, 3);
7314 int rmode
= extract32(insn
, 19, 2);
7315 int type
= extract32(insn
, 22, 2);
7316 bool sbit
= extract32(insn
, 29, 1);
7317 bool sf
= extract32(insn
, 31, 1);
7321 goto do_unallocated
;
7329 case 4: /* FCVTAS */
7330 case 5: /* FCVTAU */
7332 goto do_unallocated
;
7335 case 0: /* FCVT[NPMZ]S */
7336 case 1: /* FCVT[NPMZ]U */
7338 case 0: /* float32 */
7339 case 1: /* float64 */
7341 case 3: /* float16 */
7342 if (!dc_isar_feature(aa64_fp16
, s
)) {
7343 goto do_unallocated
;
7347 goto do_unallocated
;
7349 if (!fp_access_check(s
)) {
7352 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7356 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7357 case 0b01100110: /* FMOV half <-> 32-bit int */
7359 case 0b11100110: /* FMOV half <-> 64-bit int */
7361 if (!dc_isar_feature(aa64_fp16
, s
)) {
7362 goto do_unallocated
;
7365 case 0b00000110: /* FMOV 32-bit */
7367 case 0b10100110: /* FMOV 64-bit */
7369 case 0b11001110: /* FMOV top half of 128-bit */
7371 if (!fp_access_check(s
)) {
7375 handle_fmov(s
, rd
, rn
, type
, itof
);
7378 case 0b00111110: /* FJCVTZS */
7379 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7380 goto do_unallocated
;
7381 } else if (fp_access_check(s
)) {
7382 handle_fjcvtzs(s
, rd
, rn
);
7388 unallocated_encoding(s
);
7395 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7396 * 31 30 29 28 25 24 0
7397 * +---+---+---+---------+-----------------------------+
7398 * | | 0 | | 1 1 1 1 | |
7399 * +---+---+---+---------+-----------------------------+
7401 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7403 if (extract32(insn
, 24, 1)) {
7404 /* Floating point data-processing (3 source) */
7405 disas_fp_3src(s
, insn
);
7406 } else if (extract32(insn
, 21, 1) == 0) {
7407 /* Floating point to fixed point conversions */
7408 disas_fp_fixed_conv(s
, insn
);
7410 switch (extract32(insn
, 10, 2)) {
7412 /* Floating point conditional compare */
7413 disas_fp_ccomp(s
, insn
);
7416 /* Floating point data-processing (2 source) */
7417 disas_fp_2src(s
, insn
);
7420 /* Floating point conditional select */
7421 disas_fp_csel(s
, insn
);
7424 switch (ctz32(extract32(insn
, 12, 4))) {
7425 case 0: /* [15:12] == xxx1 */
7426 /* Floating point immediate */
7427 disas_fp_imm(s
, insn
);
7429 case 1: /* [15:12] == xx10 */
7430 /* Floating point compare */
7431 disas_fp_compare(s
, insn
);
7433 case 2: /* [15:12] == x100 */
7434 /* Floating point data-processing (1 source) */
7435 disas_fp_1src(s
, insn
);
7437 case 3: /* [15:12] == 1000 */
7438 unallocated_encoding(s
);
7440 default: /* [15:12] == 0000 */
7441 /* Floating point <-> integer conversions */
7442 disas_fp_int_conv(s
, insn
);
7450 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7453 /* Extract 64 bits from the middle of two concatenated 64 bit
7454 * vector register slices left:right. The extracted bits start
7455 * at 'pos' bits into the right (least significant) side.
7456 * We return the result in tcg_right, and guarantee not to
7459 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7460 assert(pos
> 0 && pos
< 64);
7462 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7463 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7464 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7466 tcg_temp_free_i64(tcg_tmp
);
7470 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7471 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7472 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7473 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7475 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7477 int is_q
= extract32(insn
, 30, 1);
7478 int op2
= extract32(insn
, 22, 2);
7479 int imm4
= extract32(insn
, 11, 4);
7480 int rm
= extract32(insn
, 16, 5);
7481 int rn
= extract32(insn
, 5, 5);
7482 int rd
= extract32(insn
, 0, 5);
7483 int pos
= imm4
<< 3;
7484 TCGv_i64 tcg_resl
, tcg_resh
;
7486 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7487 unallocated_encoding(s
);
7491 if (!fp_access_check(s
)) {
7495 tcg_resh
= tcg_temp_new_i64();
7496 tcg_resl
= tcg_temp_new_i64();
7498 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7499 * either extracting 128 bits from a 128:128 concatenation, or
7500 * extracting 64 bits from a 64:64 concatenation.
7503 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7505 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7506 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7514 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7515 EltPosns
*elt
= eltposns
;
7522 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7524 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7527 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7528 tcg_hh
= tcg_temp_new_i64();
7529 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7530 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7531 tcg_temp_free_i64(tcg_hh
);
7535 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7536 tcg_temp_free_i64(tcg_resl
);
7538 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7540 tcg_temp_free_i64(tcg_resh
);
7541 clear_vec_high(s
, is_q
, rd
);
7545 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7546 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7547 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7548 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7550 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7552 int op2
= extract32(insn
, 22, 2);
7553 int is_q
= extract32(insn
, 30, 1);
7554 int rm
= extract32(insn
, 16, 5);
7555 int rn
= extract32(insn
, 5, 5);
7556 int rd
= extract32(insn
, 0, 5);
7557 int is_tbx
= extract32(insn
, 12, 1);
7558 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7561 unallocated_encoding(s
);
7565 if (!fp_access_check(s
)) {
7569 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7570 vec_full_reg_offset(s
, rm
), cpu_env
,
7571 is_q
? 16 : 8, vec_full_reg_size(s
),
7572 (len
<< 6) | (is_tbx
<< 5) | rn
,
7573 gen_helper_simd_tblx
);
7577 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7578 * +---+---+-------------+------+---+------+---+------------------+------+
7579 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7580 * +---+---+-------------+------+---+------+---+------------------+------+
7582 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7584 int rd
= extract32(insn
, 0, 5);
7585 int rn
= extract32(insn
, 5, 5);
7586 int rm
= extract32(insn
, 16, 5);
7587 int size
= extract32(insn
, 22, 2);
7588 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7589 * bit 2 indicates 1 vs 2 variant of the insn.
7591 int opcode
= extract32(insn
, 12, 2);
7592 bool part
= extract32(insn
, 14, 1);
7593 bool is_q
= extract32(insn
, 30, 1);
7594 int esize
= 8 << size
;
7596 int datasize
= is_q
? 128 : 64;
7597 int elements
= datasize
/ esize
;
7598 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7600 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7601 unallocated_encoding(s
);
7605 if (!fp_access_check(s
)) {
7609 tcg_resl
= tcg_const_i64(0);
7610 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7611 tcg_res
= tcg_temp_new_i64();
7613 for (i
= 0; i
< elements
; i
++) {
7615 case 1: /* UZP1/2 */
7617 int midpoint
= elements
/ 2;
7619 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7621 read_vec_element(s
, tcg_res
, rm
,
7622 2 * (i
- midpoint
) + part
, size
);
7626 case 2: /* TRN1/2 */
7628 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7630 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7633 case 3: /* ZIP1/2 */
7635 int base
= part
* elements
/ 2;
7637 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7639 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7644 g_assert_not_reached();
7649 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7650 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7652 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7653 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7657 tcg_temp_free_i64(tcg_res
);
7659 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7660 tcg_temp_free_i64(tcg_resl
);
7663 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7664 tcg_temp_free_i64(tcg_resh
);
7666 clear_vec_high(s
, is_q
, rd
);
7670 * do_reduction_op helper
7672 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7673 * important for correct NaN propagation that we do these
7674 * operations in exactly the order specified by the pseudocode.
7676 * This is a recursive function, TCG temps should be freed by the
7677 * calling function once it is done with the values.
7679 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7680 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7682 if (esize
== size
) {
7684 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7687 /* We should have one register left here */
7688 assert(ctpop8(vmap
) == 1);
7689 element
= ctz32(vmap
);
7690 assert(element
< 8);
7692 tcg_elem
= tcg_temp_new_i32();
7693 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7696 int bits
= size
/ 2;
7697 int shift
= ctpop8(vmap
) / 2;
7698 int vmap_lo
= (vmap
>> shift
) & vmap
;
7699 int vmap_hi
= (vmap
& ~vmap_lo
);
7700 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7702 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7703 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7704 tcg_res
= tcg_temp_new_i32();
7707 case 0x0c: /* fmaxnmv half-precision */
7708 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7710 case 0x0f: /* fmaxv half-precision */
7711 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7713 case 0x1c: /* fminnmv half-precision */
7714 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7716 case 0x1f: /* fminv half-precision */
7717 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7719 case 0x2c: /* fmaxnmv */
7720 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7722 case 0x2f: /* fmaxv */
7723 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7725 case 0x3c: /* fminnmv */
7726 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7728 case 0x3f: /* fminv */
7729 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7732 g_assert_not_reached();
7735 tcg_temp_free_i32(tcg_hi
);
7736 tcg_temp_free_i32(tcg_lo
);
7741 /* AdvSIMD across lanes
7742 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7743 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7744 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7745 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7747 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7749 int rd
= extract32(insn
, 0, 5);
7750 int rn
= extract32(insn
, 5, 5);
7751 int size
= extract32(insn
, 22, 2);
7752 int opcode
= extract32(insn
, 12, 5);
7753 bool is_q
= extract32(insn
, 30, 1);
7754 bool is_u
= extract32(insn
, 29, 1);
7756 bool is_min
= false;
7760 TCGv_i64 tcg_res
, tcg_elt
;
7763 case 0x1b: /* ADDV */
7765 unallocated_encoding(s
);
7769 case 0x3: /* SADDLV, UADDLV */
7770 case 0xa: /* SMAXV, UMAXV */
7771 case 0x1a: /* SMINV, UMINV */
7772 if (size
== 3 || (size
== 2 && !is_q
)) {
7773 unallocated_encoding(s
);
7777 case 0xc: /* FMAXNMV, FMINNMV */
7778 case 0xf: /* FMAXV, FMINV */
7779 /* Bit 1 of size field encodes min vs max and the actual size
7780 * depends on the encoding of the U bit. If not set (and FP16
7781 * enabled) then we do half-precision float instead of single
7784 is_min
= extract32(size
, 1, 1);
7786 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7788 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7789 unallocated_encoding(s
);
7796 unallocated_encoding(s
);
7800 if (!fp_access_check(s
)) {
7805 elements
= (is_q
? 128 : 64) / esize
;
7807 tcg_res
= tcg_temp_new_i64();
7808 tcg_elt
= tcg_temp_new_i64();
7810 /* These instructions operate across all lanes of a vector
7811 * to produce a single result. We can guarantee that a 64
7812 * bit intermediate is sufficient:
7813 * + for [US]ADDLV the maximum element size is 32 bits, and
7814 * the result type is 64 bits
7815 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7816 * same as the element size, which is 32 bits at most
7817 * For the integer operations we can choose to work at 64
7818 * or 32 bits and truncate at the end; for simplicity
7819 * we use 64 bits always. The floating point
7820 * ops do require 32 bit intermediates, though.
7823 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7825 for (i
= 1; i
< elements
; i
++) {
7826 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7829 case 0x03: /* SADDLV / UADDLV */
7830 case 0x1b: /* ADDV */
7831 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7833 case 0x0a: /* SMAXV / UMAXV */
7835 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7837 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7840 case 0x1a: /* SMINV / UMINV */
7842 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7844 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7848 g_assert_not_reached();
7853 /* Floating point vector reduction ops which work across 32
7854 * bit (single) or 16 bit (half-precision) intermediates.
7855 * Note that correct NaN propagation requires that we do these
7856 * operations in exactly the order specified by the pseudocode.
7858 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7859 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7860 int vmap
= (1 << elements
) - 1;
7861 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7862 (is_q
? 128 : 64), vmap
, fpst
);
7863 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7864 tcg_temp_free_i32(tcg_res32
);
7865 tcg_temp_free_ptr(fpst
);
7868 tcg_temp_free_i64(tcg_elt
);
7870 /* Now truncate the result to the width required for the final output */
7871 if (opcode
== 0x03) {
7872 /* SADDLV, UADDLV: result is 2*esize */
7878 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7881 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7884 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7889 g_assert_not_reached();
7892 write_fp_dreg(s
, rd
, tcg_res
);
7893 tcg_temp_free_i64(tcg_res
);
7896 /* DUP (Element, Vector)
7898 * 31 30 29 21 20 16 15 10 9 5 4 0
7899 * +---+---+-------------------+--------+-------------+------+------+
7900 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7901 * +---+---+-------------------+--------+-------------+------+------+
7903 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7905 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7908 int size
= ctz32(imm5
);
7911 if (size
> 3 || (size
== 3 && !is_q
)) {
7912 unallocated_encoding(s
);
7916 if (!fp_access_check(s
)) {
7920 index
= imm5
>> (size
+ 1);
7921 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7922 vec_reg_offset(s
, rn
, index
, size
),
7923 is_q
? 16 : 8, vec_full_reg_size(s
));
7926 /* DUP (element, scalar)
7927 * 31 21 20 16 15 10 9 5 4 0
7928 * +-----------------------+--------+-------------+------+------+
7929 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7930 * +-----------------------+--------+-------------+------+------+
7932 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7935 int size
= ctz32(imm5
);
7940 unallocated_encoding(s
);
7944 if (!fp_access_check(s
)) {
7948 index
= imm5
>> (size
+ 1);
7950 /* This instruction just extracts the specified element and
7951 * zero-extends it into the bottom of the destination register.
7953 tmp
= tcg_temp_new_i64();
7954 read_vec_element(s
, tmp
, rn
, index
, size
);
7955 write_fp_dreg(s
, rd
, tmp
);
7956 tcg_temp_free_i64(tmp
);
7961 * 31 30 29 21 20 16 15 10 9 5 4 0
7962 * +---+---+-------------------+--------+-------------+------+------+
7963 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7964 * +---+---+-------------------+--------+-------------+------+------+
7966 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7968 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7971 int size
= ctz32(imm5
);
7972 uint32_t dofs
, oprsz
, maxsz
;
7974 if (size
> 3 || ((size
== 3) && !is_q
)) {
7975 unallocated_encoding(s
);
7979 if (!fp_access_check(s
)) {
7983 dofs
= vec_full_reg_offset(s
, rd
);
7984 oprsz
= is_q
? 16 : 8;
7985 maxsz
= vec_full_reg_size(s
);
7987 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7992 * 31 21 20 16 15 14 11 10 9 5 4 0
7993 * +-----------------------+--------+------------+---+------+------+
7994 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7995 * +-----------------------+--------+------------+---+------+------+
7997 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7998 * index: encoded in imm5<4:size+1>
8000 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
8003 int size
= ctz32(imm5
);
8004 int src_index
, dst_index
;
8008 unallocated_encoding(s
);
8012 if (!fp_access_check(s
)) {
8016 dst_index
= extract32(imm5
, 1+size
, 5);
8017 src_index
= extract32(imm4
, size
, 4);
8019 tmp
= tcg_temp_new_i64();
8021 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8022 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8024 tcg_temp_free_i64(tmp
);
8026 /* INS is considered a 128-bit write for SVE. */
8027 clear_vec_high(s
, true, rd
);
8033 * 31 21 20 16 15 10 9 5 4 0
8034 * +-----------------------+--------+-------------+------+------+
8035 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8036 * +-----------------------+--------+-------------+------+------+
8038 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8039 * index: encoded in imm5<4:size+1>
8041 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8043 int size
= ctz32(imm5
);
8047 unallocated_encoding(s
);
8051 if (!fp_access_check(s
)) {
8055 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8056 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8058 /* INS is considered a 128-bit write for SVE. */
8059 clear_vec_high(s
, true, rd
);
8066 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8067 * +---+---+-------------------+--------+-------------+------+------+
8068 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8069 * +---+---+-------------------+--------+-------------+------+------+
8071 * U: unsigned when set
8072 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8074 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8075 int rn
, int rd
, int imm5
)
8077 int size
= ctz32(imm5
);
8081 /* Check for UnallocatedEncodings */
8083 if (size
> 2 || (size
== 2 && !is_q
)) {
8084 unallocated_encoding(s
);
8089 || (size
< 3 && is_q
)
8090 || (size
== 3 && !is_q
)) {
8091 unallocated_encoding(s
);
8096 if (!fp_access_check(s
)) {
8100 element
= extract32(imm5
, 1+size
, 4);
8102 tcg_rd
= cpu_reg(s
, rd
);
8103 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8104 if (is_signed
&& !is_q
) {
8105 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8110 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8111 * +---+---+----+-----------------+------+---+------+---+------+------+
8112 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8113 * +---+---+----+-----------------+------+---+------+---+------+------+
8115 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8117 int rd
= extract32(insn
, 0, 5);
8118 int rn
= extract32(insn
, 5, 5);
8119 int imm4
= extract32(insn
, 11, 4);
8120 int op
= extract32(insn
, 29, 1);
8121 int is_q
= extract32(insn
, 30, 1);
8122 int imm5
= extract32(insn
, 16, 5);
8127 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8129 unallocated_encoding(s
);
8134 /* DUP (element - vector) */
8135 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8139 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8144 handle_simd_insg(s
, rd
, rn
, imm5
);
8146 unallocated_encoding(s
);
8151 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8152 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8155 unallocated_encoding(s
);
8161 /* AdvSIMD modified immediate
8162 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8163 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8164 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8165 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8167 * There are a number of operations that can be carried out here:
8168 * MOVI - move (shifted) imm into register
8169 * MVNI - move inverted (shifted) imm into register
8170 * ORR - bitwise OR of (shifted) imm with register
8171 * BIC - bitwise clear of (shifted) imm with register
8172 * With ARMv8.2 we also have:
8173 * FMOV half-precision
8175 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8177 int rd
= extract32(insn
, 0, 5);
8178 int cmode
= extract32(insn
, 12, 4);
8179 int cmode_3_1
= extract32(cmode
, 1, 3);
8180 int cmode_0
= extract32(cmode
, 0, 1);
8181 int o2
= extract32(insn
, 11, 1);
8182 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8183 bool is_neg
= extract32(insn
, 29, 1);
8184 bool is_q
= extract32(insn
, 30, 1);
8187 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8188 /* Check for FMOV (vector, immediate) - half-precision */
8189 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8190 unallocated_encoding(s
);
8195 if (!fp_access_check(s
)) {
8199 /* See AdvSIMDExpandImm() in ARM ARM */
8200 switch (cmode_3_1
) {
8201 case 0: /* Replicate(Zeros(24):imm8, 2) */
8202 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
8203 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
8204 case 3: /* Replicate(imm8:Zeros(24), 2) */
8206 int shift
= cmode_3_1
* 8;
8207 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
8210 case 4: /* Replicate(Zeros(8):imm8, 4) */
8211 case 5: /* Replicate(imm8:Zeros(8), 4) */
8213 int shift
= (cmode_3_1
& 0x1) * 8;
8214 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
8219 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
8220 imm
= (abcdefgh
<< 16) | 0xffff;
8222 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
8223 imm
= (abcdefgh
<< 8) | 0xff;
8225 imm
= bitfield_replicate(imm
, 32);
8228 if (!cmode_0
&& !is_neg
) {
8229 imm
= bitfield_replicate(abcdefgh
, 8);
8230 } else if (!cmode_0
&& is_neg
) {
8233 for (i
= 0; i
< 8; i
++) {
8234 if ((abcdefgh
) & (1 << i
)) {
8235 imm
|= 0xffULL
<< (i
* 8);
8238 } else if (cmode_0
) {
8240 imm
= (abcdefgh
& 0x3f) << 48;
8241 if (abcdefgh
& 0x80) {
8242 imm
|= 0x8000000000000000ULL
;
8244 if (abcdefgh
& 0x40) {
8245 imm
|= 0x3fc0000000000000ULL
;
8247 imm
|= 0x4000000000000000ULL
;
8251 /* FMOV (vector, immediate) - half-precision */
8252 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8253 /* now duplicate across the lanes */
8254 imm
= bitfield_replicate(imm
, 16);
8256 imm
= (abcdefgh
& 0x3f) << 19;
8257 if (abcdefgh
& 0x80) {
8260 if (abcdefgh
& 0x40) {
8271 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
8272 g_assert_not_reached();
8275 if (cmode_3_1
!= 7 && is_neg
) {
8279 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8280 /* MOVI or MVNI, with MVNI negation handled above. */
8281 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8282 vec_full_reg_size(s
), imm
);
8284 /* ORR or BIC, with BIC negation to AND handled above. */
8286 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8288 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8293 /* AdvSIMD scalar copy
8294 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8295 * +-----+----+-----------------+------+---+------+---+------+------+
8296 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8297 * +-----+----+-----------------+------+---+------+---+------+------+
8299 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8301 int rd
= extract32(insn
, 0, 5);
8302 int rn
= extract32(insn
, 5, 5);
8303 int imm4
= extract32(insn
, 11, 4);
8304 int imm5
= extract32(insn
, 16, 5);
8305 int op
= extract32(insn
, 29, 1);
8307 if (op
!= 0 || imm4
!= 0) {
8308 unallocated_encoding(s
);
8312 /* DUP (element, scalar) */
8313 handle_simd_dupes(s
, rd
, rn
, imm5
);
8316 /* AdvSIMD scalar pairwise
8317 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8318 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8319 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8320 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8322 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8324 int u
= extract32(insn
, 29, 1);
8325 int size
= extract32(insn
, 22, 2);
8326 int opcode
= extract32(insn
, 12, 5);
8327 int rn
= extract32(insn
, 5, 5);
8328 int rd
= extract32(insn
, 0, 5);
8331 /* For some ops (the FP ones), size[1] is part of the encoding.
8332 * For ADDP strictly it is not but size[1] is always 1 for valid
8335 opcode
|= (extract32(size
, 1, 1) << 5);
8338 case 0x3b: /* ADDP */
8339 if (u
|| size
!= 3) {
8340 unallocated_encoding(s
);
8343 if (!fp_access_check(s
)) {
8349 case 0xc: /* FMAXNMP */
8350 case 0xd: /* FADDP */
8351 case 0xf: /* FMAXP */
8352 case 0x2c: /* FMINNMP */
8353 case 0x2f: /* FMINP */
8354 /* FP op, size[0] is 32 or 64 bit*/
8356 if (!dc_isar_feature(aa64_fp16
, s
)) {
8357 unallocated_encoding(s
);
8363 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8366 if (!fp_access_check(s
)) {
8370 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8373 unallocated_encoding(s
);
8377 if (size
== MO_64
) {
8378 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8379 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8380 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8382 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8383 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8386 case 0x3b: /* ADDP */
8387 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8389 case 0xc: /* FMAXNMP */
8390 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8392 case 0xd: /* FADDP */
8393 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8395 case 0xf: /* FMAXP */
8396 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8398 case 0x2c: /* FMINNMP */
8399 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8401 case 0x2f: /* FMINP */
8402 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8405 g_assert_not_reached();
8408 write_fp_dreg(s
, rd
, tcg_res
);
8410 tcg_temp_free_i64(tcg_op1
);
8411 tcg_temp_free_i64(tcg_op2
);
8412 tcg_temp_free_i64(tcg_res
);
8414 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8415 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8416 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8418 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8419 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8421 if (size
== MO_16
) {
8423 case 0xc: /* FMAXNMP */
8424 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8426 case 0xd: /* FADDP */
8427 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8429 case 0xf: /* FMAXP */
8430 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8432 case 0x2c: /* FMINNMP */
8433 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8435 case 0x2f: /* FMINP */
8436 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8439 g_assert_not_reached();
8443 case 0xc: /* FMAXNMP */
8444 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8446 case 0xd: /* FADDP */
8447 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8449 case 0xf: /* FMAXP */
8450 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8452 case 0x2c: /* FMINNMP */
8453 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8455 case 0x2f: /* FMINP */
8456 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8459 g_assert_not_reached();
8463 write_fp_sreg(s
, rd
, tcg_res
);
8465 tcg_temp_free_i32(tcg_op1
);
8466 tcg_temp_free_i32(tcg_op2
);
8467 tcg_temp_free_i32(tcg_res
);
8471 tcg_temp_free_ptr(fpst
);
8476 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8478 * This code is handles the common shifting code and is used by both
8479 * the vector and scalar code.
8481 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8482 TCGv_i64 tcg_rnd
, bool accumulate
,
8483 bool is_u
, int size
, int shift
)
8485 bool extended_result
= false;
8486 bool round
= tcg_rnd
!= NULL
;
8488 TCGv_i64 tcg_src_hi
;
8490 if (round
&& size
== 3) {
8491 extended_result
= true;
8492 ext_lshift
= 64 - shift
;
8493 tcg_src_hi
= tcg_temp_new_i64();
8494 } else if (shift
== 64) {
8495 if (!accumulate
&& is_u
) {
8496 /* result is zero */
8497 tcg_gen_movi_i64(tcg_res
, 0);
8502 /* Deal with the rounding step */
8504 if (extended_result
) {
8505 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8507 /* take care of sign extending tcg_res */
8508 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8509 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8510 tcg_src
, tcg_src_hi
,
8513 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8517 tcg_temp_free_i64(tcg_zero
);
8519 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8523 /* Now do the shift right */
8524 if (round
&& extended_result
) {
8525 /* extended case, >64 bit precision required */
8526 if (ext_lshift
== 0) {
8527 /* special case, only high bits matter */
8528 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8530 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8531 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8532 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8537 /* essentially shifting in 64 zeros */
8538 tcg_gen_movi_i64(tcg_src
, 0);
8540 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8544 /* effectively extending the sign-bit */
8545 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8547 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8553 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8555 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8558 if (extended_result
) {
8559 tcg_temp_free_i64(tcg_src_hi
);
8563 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8564 static void handle_scalar_simd_shri(DisasContext
*s
,
8565 bool is_u
, int immh
, int immb
,
8566 int opcode
, int rn
, int rd
)
8569 int immhb
= immh
<< 3 | immb
;
8570 int shift
= 2 * (8 << size
) - immhb
;
8571 bool accumulate
= false;
8573 bool insert
= false;
8578 if (!extract32(immh
, 3, 1)) {
8579 unallocated_encoding(s
);
8583 if (!fp_access_check(s
)) {
8588 case 0x02: /* SSRA / USRA (accumulate) */
8591 case 0x04: /* SRSHR / URSHR (rounding) */
8594 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8595 accumulate
= round
= true;
8597 case 0x08: /* SRI */
8603 uint64_t round_const
= 1ULL << (shift
- 1);
8604 tcg_round
= tcg_const_i64(round_const
);
8609 tcg_rn
= read_fp_dreg(s
, rn
);
8610 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8613 /* shift count same as element size is valid but does nothing;
8614 * special case to avoid potential shift by 64.
8616 int esize
= 8 << size
;
8617 if (shift
!= esize
) {
8618 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8619 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8622 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8623 accumulate
, is_u
, size
, shift
);
8626 write_fp_dreg(s
, rd
, tcg_rd
);
8628 tcg_temp_free_i64(tcg_rn
);
8629 tcg_temp_free_i64(tcg_rd
);
8631 tcg_temp_free_i64(tcg_round
);
8635 /* SHL/SLI - Scalar shift left */
8636 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8637 int immh
, int immb
, int opcode
,
8640 int size
= 32 - clz32(immh
) - 1;
8641 int immhb
= immh
<< 3 | immb
;
8642 int shift
= immhb
- (8 << size
);
8646 if (!extract32(immh
, 3, 1)) {
8647 unallocated_encoding(s
);
8651 if (!fp_access_check(s
)) {
8655 tcg_rn
= read_fp_dreg(s
, rn
);
8656 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8659 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8661 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8664 write_fp_dreg(s
, rd
, tcg_rd
);
8666 tcg_temp_free_i64(tcg_rn
);
8667 tcg_temp_free_i64(tcg_rd
);
8670 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8671 * (signed/unsigned) narrowing */
8672 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8673 bool is_u_shift
, bool is_u_narrow
,
8674 int immh
, int immb
, int opcode
,
8677 int immhb
= immh
<< 3 | immb
;
8678 int size
= 32 - clz32(immh
) - 1;
8679 int esize
= 8 << size
;
8680 int shift
= (2 * esize
) - immhb
;
8681 int elements
= is_scalar
? 1 : (64 / esize
);
8682 bool round
= extract32(opcode
, 0, 1);
8683 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8684 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8685 TCGv_i32 tcg_rd_narrowed
;
8688 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8689 { gen_helper_neon_narrow_sat_s8
,
8690 gen_helper_neon_unarrow_sat8
},
8691 { gen_helper_neon_narrow_sat_s16
,
8692 gen_helper_neon_unarrow_sat16
},
8693 { gen_helper_neon_narrow_sat_s32
,
8694 gen_helper_neon_unarrow_sat32
},
8697 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8698 gen_helper_neon_narrow_sat_u8
,
8699 gen_helper_neon_narrow_sat_u16
,
8700 gen_helper_neon_narrow_sat_u32
,
8703 NeonGenNarrowEnvFn
*narrowfn
;
8709 if (extract32(immh
, 3, 1)) {
8710 unallocated_encoding(s
);
8714 if (!fp_access_check(s
)) {
8719 narrowfn
= unsigned_narrow_fns
[size
];
8721 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8724 tcg_rn
= tcg_temp_new_i64();
8725 tcg_rd
= tcg_temp_new_i64();
8726 tcg_rd_narrowed
= tcg_temp_new_i32();
8727 tcg_final
= tcg_const_i64(0);
8730 uint64_t round_const
= 1ULL << (shift
- 1);
8731 tcg_round
= tcg_const_i64(round_const
);
8736 for (i
= 0; i
< elements
; i
++) {
8737 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8738 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8739 false, is_u_shift
, size
+1, shift
);
8740 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8741 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8742 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8746 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8748 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8752 tcg_temp_free_i64(tcg_round
);
8754 tcg_temp_free_i64(tcg_rn
);
8755 tcg_temp_free_i64(tcg_rd
);
8756 tcg_temp_free_i32(tcg_rd_narrowed
);
8757 tcg_temp_free_i64(tcg_final
);
8759 clear_vec_high(s
, is_q
, rd
);
8762 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8763 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8764 bool src_unsigned
, bool dst_unsigned
,
8765 int immh
, int immb
, int rn
, int rd
)
8767 int immhb
= immh
<< 3 | immb
;
8768 int size
= 32 - clz32(immh
) - 1;
8769 int shift
= immhb
- (8 << size
);
8773 assert(!(scalar
&& is_q
));
8776 if (!is_q
&& extract32(immh
, 3, 1)) {
8777 unallocated_encoding(s
);
8781 /* Since we use the variable-shift helpers we must
8782 * replicate the shift count into each element of
8783 * the tcg_shift value.
8787 shift
|= shift
<< 8;
8790 shift
|= shift
<< 16;
8796 g_assert_not_reached();
8800 if (!fp_access_check(s
)) {
8805 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8806 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8807 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8808 { NULL
, gen_helper_neon_qshl_u64
},
8810 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8811 int maxpass
= is_q
? 2 : 1;
8813 for (pass
= 0; pass
< maxpass
; pass
++) {
8814 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8816 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8817 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8818 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8820 tcg_temp_free_i64(tcg_op
);
8822 tcg_temp_free_i64(tcg_shift
);
8823 clear_vec_high(s
, is_q
, rd
);
8825 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8826 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8828 { gen_helper_neon_qshl_s8
,
8829 gen_helper_neon_qshl_s16
,
8830 gen_helper_neon_qshl_s32
},
8831 { gen_helper_neon_qshlu_s8
,
8832 gen_helper_neon_qshlu_s16
,
8833 gen_helper_neon_qshlu_s32
}
8835 { NULL
, NULL
, NULL
},
8836 { gen_helper_neon_qshl_u8
,
8837 gen_helper_neon_qshl_u16
,
8838 gen_helper_neon_qshl_u32
}
8841 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8842 MemOp memop
= scalar
? size
: MO_32
;
8843 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8845 for (pass
= 0; pass
< maxpass
; pass
++) {
8846 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8848 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8849 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8853 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8856 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8861 g_assert_not_reached();
8863 write_fp_sreg(s
, rd
, tcg_op
);
8865 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8868 tcg_temp_free_i32(tcg_op
);
8870 tcg_temp_free_i32(tcg_shift
);
8873 clear_vec_high(s
, is_q
, rd
);
8878 /* Common vector code for handling integer to FP conversion */
8879 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8880 int elements
, int is_signed
,
8881 int fracbits
, int size
)
8883 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8884 TCGv_i32 tcg_shift
= NULL
;
8886 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8889 if (fracbits
|| size
== MO_64
) {
8890 tcg_shift
= tcg_const_i32(fracbits
);
8893 if (size
== MO_64
) {
8894 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8895 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8897 for (pass
= 0; pass
< elements
; pass
++) {
8898 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8901 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8902 tcg_shift
, tcg_fpst
);
8904 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8905 tcg_shift
, tcg_fpst
);
8907 if (elements
== 1) {
8908 write_fp_dreg(s
, rd
, tcg_double
);
8910 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8914 tcg_temp_free_i64(tcg_int64
);
8915 tcg_temp_free_i64(tcg_double
);
8918 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8919 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8921 for (pass
= 0; pass
< elements
; pass
++) {
8922 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8928 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8929 tcg_shift
, tcg_fpst
);
8931 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8932 tcg_shift
, tcg_fpst
);
8936 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8938 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8945 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8946 tcg_shift
, tcg_fpst
);
8948 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8949 tcg_shift
, tcg_fpst
);
8953 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8955 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8960 g_assert_not_reached();
8963 if (elements
== 1) {
8964 write_fp_sreg(s
, rd
, tcg_float
);
8966 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8970 tcg_temp_free_i32(tcg_int32
);
8971 tcg_temp_free_i32(tcg_float
);
8974 tcg_temp_free_ptr(tcg_fpst
);
8976 tcg_temp_free_i32(tcg_shift
);
8979 clear_vec_high(s
, elements
<< size
== 16, rd
);
8982 /* UCVTF/SCVTF - Integer to FP conversion */
8983 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8984 bool is_q
, bool is_u
,
8985 int immh
, int immb
, int opcode
,
8988 int size
, elements
, fracbits
;
8989 int immhb
= immh
<< 3 | immb
;
8993 if (!is_scalar
&& !is_q
) {
8994 unallocated_encoding(s
);
8997 } else if (immh
& 4) {
8999 } else if (immh
& 2) {
9001 if (!dc_isar_feature(aa64_fp16
, s
)) {
9002 unallocated_encoding(s
);
9006 /* immh == 0 would be a failure of the decode logic */
9007 g_assert(immh
== 1);
9008 unallocated_encoding(s
);
9015 elements
= (8 << is_q
) >> size
;
9017 fracbits
= (16 << size
) - immhb
;
9019 if (!fp_access_check(s
)) {
9023 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
9026 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
9027 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
9028 bool is_q
, bool is_u
,
9029 int immh
, int immb
, int rn
, int rd
)
9031 int immhb
= immh
<< 3 | immb
;
9032 int pass
, size
, fracbits
;
9033 TCGv_ptr tcg_fpstatus
;
9034 TCGv_i32 tcg_rmode
, tcg_shift
;
9038 if (!is_scalar
&& !is_q
) {
9039 unallocated_encoding(s
);
9042 } else if (immh
& 0x4) {
9044 } else if (immh
& 0x2) {
9046 if (!dc_isar_feature(aa64_fp16
, s
)) {
9047 unallocated_encoding(s
);
9051 /* Should have split out AdvSIMD modified immediate earlier. */
9053 unallocated_encoding(s
);
9057 if (!fp_access_check(s
)) {
9061 assert(!(is_scalar
&& is_q
));
9063 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9064 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9065 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9066 fracbits
= (16 << size
) - immhb
;
9067 tcg_shift
= tcg_const_i32(fracbits
);
9069 if (size
== MO_64
) {
9070 int maxpass
= is_scalar
? 1 : 2;
9072 for (pass
= 0; pass
< maxpass
; pass
++) {
9073 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9075 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9077 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9079 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9081 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9082 tcg_temp_free_i64(tcg_op
);
9084 clear_vec_high(s
, is_q
, rd
);
9086 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9087 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9092 fn
= gen_helper_vfp_touhh
;
9094 fn
= gen_helper_vfp_toshh
;
9099 fn
= gen_helper_vfp_touls
;
9101 fn
= gen_helper_vfp_tosls
;
9105 g_assert_not_reached();
9108 for (pass
= 0; pass
< maxpass
; pass
++) {
9109 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9111 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9112 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9114 write_fp_sreg(s
, rd
, tcg_op
);
9116 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9118 tcg_temp_free_i32(tcg_op
);
9121 clear_vec_high(s
, is_q
, rd
);
9125 tcg_temp_free_ptr(tcg_fpstatus
);
9126 tcg_temp_free_i32(tcg_shift
);
9127 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9128 tcg_temp_free_i32(tcg_rmode
);
9131 /* AdvSIMD scalar shift by immediate
9132 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9133 * +-----+---+-------------+------+------+--------+---+------+------+
9134 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9135 * +-----+---+-------------+------+------+--------+---+------+------+
9137 * This is the scalar version so it works on a fixed sized registers
9139 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9141 int rd
= extract32(insn
, 0, 5);
9142 int rn
= extract32(insn
, 5, 5);
9143 int opcode
= extract32(insn
, 11, 5);
9144 int immb
= extract32(insn
, 16, 3);
9145 int immh
= extract32(insn
, 19, 4);
9146 bool is_u
= extract32(insn
, 29, 1);
9149 unallocated_encoding(s
);
9154 case 0x08: /* SRI */
9156 unallocated_encoding(s
);
9160 case 0x00: /* SSHR / USHR */
9161 case 0x02: /* SSRA / USRA */
9162 case 0x04: /* SRSHR / URSHR */
9163 case 0x06: /* SRSRA / URSRA */
9164 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9166 case 0x0a: /* SHL / SLI */
9167 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9169 case 0x1c: /* SCVTF, UCVTF */
9170 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9173 case 0x10: /* SQSHRUN, SQSHRUN2 */
9174 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9176 unallocated_encoding(s
);
9179 handle_vec_simd_sqshrn(s
, true, false, false, true,
9180 immh
, immb
, opcode
, rn
, rd
);
9182 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9183 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9184 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9185 immh
, immb
, opcode
, rn
, rd
);
9187 case 0xc: /* SQSHLU */
9189 unallocated_encoding(s
);
9192 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9194 case 0xe: /* SQSHL, UQSHL */
9195 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9197 case 0x1f: /* FCVTZS, FCVTZU */
9198 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9201 unallocated_encoding(s
);
9206 /* AdvSIMD scalar three different
9207 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9208 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9209 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9210 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9212 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9214 bool is_u
= extract32(insn
, 29, 1);
9215 int size
= extract32(insn
, 22, 2);
9216 int opcode
= extract32(insn
, 12, 4);
9217 int rm
= extract32(insn
, 16, 5);
9218 int rn
= extract32(insn
, 5, 5);
9219 int rd
= extract32(insn
, 0, 5);
9222 unallocated_encoding(s
);
9227 case 0x9: /* SQDMLAL, SQDMLAL2 */
9228 case 0xb: /* SQDMLSL, SQDMLSL2 */
9229 case 0xd: /* SQDMULL, SQDMULL2 */
9230 if (size
== 0 || size
== 3) {
9231 unallocated_encoding(s
);
9236 unallocated_encoding(s
);
9240 if (!fp_access_check(s
)) {
9245 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9246 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9247 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9249 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9250 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9252 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9253 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9256 case 0xd: /* SQDMULL, SQDMULL2 */
9258 case 0xb: /* SQDMLSL, SQDMLSL2 */
9259 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9261 case 0x9: /* SQDMLAL, SQDMLAL2 */
9262 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9263 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9267 g_assert_not_reached();
9270 write_fp_dreg(s
, rd
, tcg_res
);
9272 tcg_temp_free_i64(tcg_op1
);
9273 tcg_temp_free_i64(tcg_op2
);
9274 tcg_temp_free_i64(tcg_res
);
9276 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9277 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9278 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9280 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9281 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9284 case 0xd: /* SQDMULL, SQDMULL2 */
9286 case 0xb: /* SQDMLSL, SQDMLSL2 */
9287 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9289 case 0x9: /* SQDMLAL, SQDMLAL2 */
9291 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9292 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9293 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9295 tcg_temp_free_i64(tcg_op3
);
9299 g_assert_not_reached();
9302 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9303 write_fp_dreg(s
, rd
, tcg_res
);
9305 tcg_temp_free_i32(tcg_op1
);
9306 tcg_temp_free_i32(tcg_op2
);
9307 tcg_temp_free_i64(tcg_res
);
9311 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9312 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9314 /* Handle 64x64->64 opcodes which are shared between the scalar
9315 * and vector 3-same groups. We cover every opcode where size == 3
9316 * is valid in either the three-reg-same (integer, not pairwise)
9317 * or scalar-three-reg-same groups.
9322 case 0x1: /* SQADD */
9324 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9326 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9329 case 0x5: /* SQSUB */
9331 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9333 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9336 case 0x6: /* CMGT, CMHI */
9337 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9338 * We implement this using setcond (test) and then negating.
9340 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9342 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9343 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9345 case 0x7: /* CMGE, CMHS */
9346 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9348 case 0x11: /* CMTST, CMEQ */
9353 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9355 case 0x8: /* SSHL, USHL */
9357 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9359 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9362 case 0x9: /* SQSHL, UQSHL */
9364 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9366 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9369 case 0xa: /* SRSHL, URSHL */
9371 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9373 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9376 case 0xb: /* SQRSHL, UQRSHL */
9378 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9380 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9383 case 0x10: /* ADD, SUB */
9385 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9387 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9391 g_assert_not_reached();
9395 /* Handle the 3-same-operands float operations; shared by the scalar
9396 * and vector encodings. The caller must filter out any encodings
9397 * not allocated for the encoding it is dealing with.
9399 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9400 int fpopcode
, int rd
, int rn
, int rm
)
9403 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9405 for (pass
= 0; pass
< elements
; pass
++) {
9408 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9409 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9410 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9412 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9413 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9416 case 0x39: /* FMLS */
9417 /* As usual for ARM, separate negation for fused multiply-add */
9418 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9420 case 0x19: /* FMLA */
9421 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9422 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9425 case 0x18: /* FMAXNM */
9426 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9428 case 0x1a: /* FADD */
9429 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9431 case 0x1b: /* FMULX */
9432 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9434 case 0x1c: /* FCMEQ */
9435 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9437 case 0x1e: /* FMAX */
9438 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9440 case 0x1f: /* FRECPS */
9441 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9443 case 0x38: /* FMINNM */
9444 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9446 case 0x3a: /* FSUB */
9447 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9449 case 0x3e: /* FMIN */
9450 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9452 case 0x3f: /* FRSQRTS */
9453 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9455 case 0x5b: /* FMUL */
9456 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9458 case 0x5c: /* FCMGE */
9459 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9461 case 0x5d: /* FACGE */
9462 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9464 case 0x5f: /* FDIV */
9465 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9467 case 0x7a: /* FABD */
9468 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9469 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9471 case 0x7c: /* FCMGT */
9472 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9474 case 0x7d: /* FACGT */
9475 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9478 g_assert_not_reached();
9481 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9483 tcg_temp_free_i64(tcg_res
);
9484 tcg_temp_free_i64(tcg_op1
);
9485 tcg_temp_free_i64(tcg_op2
);
9488 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9489 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9490 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9492 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9493 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9496 case 0x39: /* FMLS */
9497 /* As usual for ARM, separate negation for fused multiply-add */
9498 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9500 case 0x19: /* FMLA */
9501 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9502 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9505 case 0x1a: /* FADD */
9506 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9508 case 0x1b: /* FMULX */
9509 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9511 case 0x1c: /* FCMEQ */
9512 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9514 case 0x1e: /* FMAX */
9515 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9517 case 0x1f: /* FRECPS */
9518 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9520 case 0x18: /* FMAXNM */
9521 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9523 case 0x38: /* FMINNM */
9524 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9526 case 0x3a: /* FSUB */
9527 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9529 case 0x3e: /* FMIN */
9530 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9532 case 0x3f: /* FRSQRTS */
9533 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9535 case 0x5b: /* FMUL */
9536 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9538 case 0x5c: /* FCMGE */
9539 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9541 case 0x5d: /* FACGE */
9542 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9544 case 0x5f: /* FDIV */
9545 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9547 case 0x7a: /* FABD */
9548 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9549 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9551 case 0x7c: /* FCMGT */
9552 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9554 case 0x7d: /* FACGT */
9555 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9558 g_assert_not_reached();
9561 if (elements
== 1) {
9562 /* scalar single so clear high part */
9563 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9565 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9566 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9567 tcg_temp_free_i64(tcg_tmp
);
9569 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9572 tcg_temp_free_i32(tcg_res
);
9573 tcg_temp_free_i32(tcg_op1
);
9574 tcg_temp_free_i32(tcg_op2
);
9578 tcg_temp_free_ptr(fpst
);
9580 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9583 /* AdvSIMD scalar three same
9584 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9585 * +-----+---+-----------+------+---+------+--------+---+------+------+
9586 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9587 * +-----+---+-----------+------+---+------+--------+---+------+------+
9589 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9591 int rd
= extract32(insn
, 0, 5);
9592 int rn
= extract32(insn
, 5, 5);
9593 int opcode
= extract32(insn
, 11, 5);
9594 int rm
= extract32(insn
, 16, 5);
9595 int size
= extract32(insn
, 22, 2);
9596 bool u
= extract32(insn
, 29, 1);
9599 if (opcode
>= 0x18) {
9600 /* Floating point: U, size[1] and opcode indicate operation */
9601 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9603 case 0x1b: /* FMULX */
9604 case 0x1f: /* FRECPS */
9605 case 0x3f: /* FRSQRTS */
9606 case 0x5d: /* FACGE */
9607 case 0x7d: /* FACGT */
9608 case 0x1c: /* FCMEQ */
9609 case 0x5c: /* FCMGE */
9610 case 0x7c: /* FCMGT */
9611 case 0x7a: /* FABD */
9614 unallocated_encoding(s
);
9618 if (!fp_access_check(s
)) {
9622 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9627 case 0x1: /* SQADD, UQADD */
9628 case 0x5: /* SQSUB, UQSUB */
9629 case 0x9: /* SQSHL, UQSHL */
9630 case 0xb: /* SQRSHL, UQRSHL */
9632 case 0x8: /* SSHL, USHL */
9633 case 0xa: /* SRSHL, URSHL */
9634 case 0x6: /* CMGT, CMHI */
9635 case 0x7: /* CMGE, CMHS */
9636 case 0x11: /* CMTST, CMEQ */
9637 case 0x10: /* ADD, SUB (vector) */
9639 unallocated_encoding(s
);
9643 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9644 if (size
!= 1 && size
!= 2) {
9645 unallocated_encoding(s
);
9650 unallocated_encoding(s
);
9654 if (!fp_access_check(s
)) {
9658 tcg_rd
= tcg_temp_new_i64();
9661 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9662 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9664 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9665 tcg_temp_free_i64(tcg_rn
);
9666 tcg_temp_free_i64(tcg_rm
);
9668 /* Do a single operation on the lowest element in the vector.
9669 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9670 * no side effects for all these operations.
9671 * OPTME: special-purpose helpers would avoid doing some
9672 * unnecessary work in the helper for the 8 and 16 bit cases.
9674 NeonGenTwoOpEnvFn
*genenvfn
;
9675 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9676 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9677 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9679 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9680 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9683 case 0x1: /* SQADD, UQADD */
9685 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9686 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9687 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9688 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9690 genenvfn
= fns
[size
][u
];
9693 case 0x5: /* SQSUB, UQSUB */
9695 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9696 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9697 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9698 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9700 genenvfn
= fns
[size
][u
];
9703 case 0x9: /* SQSHL, UQSHL */
9705 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9706 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9707 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9708 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9710 genenvfn
= fns
[size
][u
];
9713 case 0xb: /* SQRSHL, UQRSHL */
9715 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9716 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9717 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9718 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9720 genenvfn
= fns
[size
][u
];
9723 case 0x16: /* SQDMULH, SQRDMULH */
9725 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9726 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9727 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9729 assert(size
== 1 || size
== 2);
9730 genenvfn
= fns
[size
- 1][u
];
9734 g_assert_not_reached();
9737 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9738 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9739 tcg_temp_free_i32(tcg_rd32
);
9740 tcg_temp_free_i32(tcg_rn
);
9741 tcg_temp_free_i32(tcg_rm
);
9744 write_fp_dreg(s
, rd
, tcg_rd
);
9746 tcg_temp_free_i64(tcg_rd
);
9749 /* AdvSIMD scalar three same FP16
9750 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9751 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9752 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9753 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9754 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9755 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9757 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9760 int rd
= extract32(insn
, 0, 5);
9761 int rn
= extract32(insn
, 5, 5);
9762 int opcode
= extract32(insn
, 11, 3);
9763 int rm
= extract32(insn
, 16, 5);
9764 bool u
= extract32(insn
, 29, 1);
9765 bool a
= extract32(insn
, 23, 1);
9766 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9773 case 0x03: /* FMULX */
9774 case 0x04: /* FCMEQ (reg) */
9775 case 0x07: /* FRECPS */
9776 case 0x0f: /* FRSQRTS */
9777 case 0x14: /* FCMGE (reg) */
9778 case 0x15: /* FACGE */
9779 case 0x1a: /* FABD */
9780 case 0x1c: /* FCMGT (reg) */
9781 case 0x1d: /* FACGT */
9784 unallocated_encoding(s
);
9788 if (!dc_isar_feature(aa64_fp16
, s
)) {
9789 unallocated_encoding(s
);
9792 if (!fp_access_check(s
)) {
9796 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9798 tcg_op1
= read_fp_hreg(s
, rn
);
9799 tcg_op2
= read_fp_hreg(s
, rm
);
9800 tcg_res
= tcg_temp_new_i32();
9803 case 0x03: /* FMULX */
9804 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9806 case 0x04: /* FCMEQ (reg) */
9807 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9809 case 0x07: /* FRECPS */
9810 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9812 case 0x0f: /* FRSQRTS */
9813 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9815 case 0x14: /* FCMGE (reg) */
9816 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9818 case 0x15: /* FACGE */
9819 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9821 case 0x1a: /* FABD */
9822 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9823 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9825 case 0x1c: /* FCMGT (reg) */
9826 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9828 case 0x1d: /* FACGT */
9829 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9832 g_assert_not_reached();
9835 write_fp_sreg(s
, rd
, tcg_res
);
9838 tcg_temp_free_i32(tcg_res
);
9839 tcg_temp_free_i32(tcg_op1
);
9840 tcg_temp_free_i32(tcg_op2
);
9841 tcg_temp_free_ptr(fpst
);
9844 /* AdvSIMD scalar three same extra
9845 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9846 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9847 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9848 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9850 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9853 int rd
= extract32(insn
, 0, 5);
9854 int rn
= extract32(insn
, 5, 5);
9855 int opcode
= extract32(insn
, 11, 4);
9856 int rm
= extract32(insn
, 16, 5);
9857 int size
= extract32(insn
, 22, 2);
9858 bool u
= extract32(insn
, 29, 1);
9859 TCGv_i32 ele1
, ele2
, ele3
;
9863 switch (u
* 16 + opcode
) {
9864 case 0x10: /* SQRDMLAH (vector) */
9865 case 0x11: /* SQRDMLSH (vector) */
9866 if (size
!= 1 && size
!= 2) {
9867 unallocated_encoding(s
);
9870 feature
= dc_isar_feature(aa64_rdm
, s
);
9873 unallocated_encoding(s
);
9877 unallocated_encoding(s
);
9880 if (!fp_access_check(s
)) {
9884 /* Do a single operation on the lowest element in the vector.
9885 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9886 * with no side effects for all these operations.
9887 * OPTME: special-purpose helpers would avoid doing some
9888 * unnecessary work in the helper for the 16 bit cases.
9890 ele1
= tcg_temp_new_i32();
9891 ele2
= tcg_temp_new_i32();
9892 ele3
= tcg_temp_new_i32();
9894 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9895 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9896 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9899 case 0x0: /* SQRDMLAH */
9901 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9903 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9906 case 0x1: /* SQRDMLSH */
9908 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9910 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9914 g_assert_not_reached();
9916 tcg_temp_free_i32(ele1
);
9917 tcg_temp_free_i32(ele2
);
9919 res
= tcg_temp_new_i64();
9920 tcg_gen_extu_i32_i64(res
, ele3
);
9921 tcg_temp_free_i32(ele3
);
9923 write_fp_dreg(s
, rd
, res
);
9924 tcg_temp_free_i64(res
);
9927 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9928 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9929 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9931 /* Handle 64->64 opcodes which are shared between the scalar and
9932 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9933 * is valid in either group and also the double-precision fp ops.
9934 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9940 case 0x4: /* CLS, CLZ */
9942 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9944 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9948 /* This opcode is shared with CNT and RBIT but we have earlier
9949 * enforced that size == 3 if and only if this is the NOT insn.
9951 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9953 case 0x7: /* SQABS, SQNEG */
9955 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9957 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9960 case 0xa: /* CMLT */
9961 /* 64 bit integer comparison against zero, result is
9962 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9967 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9968 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9970 case 0x8: /* CMGT, CMGE */
9971 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9973 case 0x9: /* CMEQ, CMLE */
9974 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9976 case 0xb: /* ABS, NEG */
9978 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9980 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9983 case 0x2f: /* FABS */
9984 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9986 case 0x6f: /* FNEG */
9987 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9989 case 0x7f: /* FSQRT */
9990 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9992 case 0x1a: /* FCVTNS */
9993 case 0x1b: /* FCVTMS */
9994 case 0x1c: /* FCVTAS */
9995 case 0x3a: /* FCVTPS */
9996 case 0x3b: /* FCVTZS */
9998 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9999 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10000 tcg_temp_free_i32(tcg_shift
);
10003 case 0x5a: /* FCVTNU */
10004 case 0x5b: /* FCVTMU */
10005 case 0x5c: /* FCVTAU */
10006 case 0x7a: /* FCVTPU */
10007 case 0x7b: /* FCVTZU */
10009 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10010 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10011 tcg_temp_free_i32(tcg_shift
);
10014 case 0x18: /* FRINTN */
10015 case 0x19: /* FRINTM */
10016 case 0x38: /* FRINTP */
10017 case 0x39: /* FRINTZ */
10018 case 0x58: /* FRINTA */
10019 case 0x79: /* FRINTI */
10020 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10022 case 0x59: /* FRINTX */
10023 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10025 case 0x1e: /* FRINT32Z */
10026 case 0x5e: /* FRINT32X */
10027 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10029 case 0x1f: /* FRINT64Z */
10030 case 0x5f: /* FRINT64X */
10031 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10034 g_assert_not_reached();
10038 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
10039 bool is_scalar
, bool is_u
, bool is_q
,
10040 int size
, int rn
, int rd
)
10042 bool is_double
= (size
== MO_64
);
10045 if (!fp_access_check(s
)) {
10049 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
10052 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10053 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10054 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10055 NeonGenTwoDoubleOpFn
*genfn
;
10060 case 0x2e: /* FCMLT (zero) */
10063 case 0x2c: /* FCMGT (zero) */
10064 genfn
= gen_helper_neon_cgt_f64
;
10066 case 0x2d: /* FCMEQ (zero) */
10067 genfn
= gen_helper_neon_ceq_f64
;
10069 case 0x6d: /* FCMLE (zero) */
10072 case 0x6c: /* FCMGE (zero) */
10073 genfn
= gen_helper_neon_cge_f64
;
10076 g_assert_not_reached();
10079 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10080 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10082 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10084 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10086 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10088 tcg_temp_free_i64(tcg_res
);
10089 tcg_temp_free_i64(tcg_zero
);
10090 tcg_temp_free_i64(tcg_op
);
10092 clear_vec_high(s
, !is_scalar
, rd
);
10094 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10095 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10096 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10097 NeonGenTwoSingleOpFn
*genfn
;
10099 int pass
, maxpasses
;
10101 if (size
== MO_16
) {
10103 case 0x2e: /* FCMLT (zero) */
10106 case 0x2c: /* FCMGT (zero) */
10107 genfn
= gen_helper_advsimd_cgt_f16
;
10109 case 0x2d: /* FCMEQ (zero) */
10110 genfn
= gen_helper_advsimd_ceq_f16
;
10112 case 0x6d: /* FCMLE (zero) */
10115 case 0x6c: /* FCMGE (zero) */
10116 genfn
= gen_helper_advsimd_cge_f16
;
10119 g_assert_not_reached();
10123 case 0x2e: /* FCMLT (zero) */
10126 case 0x2c: /* FCMGT (zero) */
10127 genfn
= gen_helper_neon_cgt_f32
;
10129 case 0x2d: /* FCMEQ (zero) */
10130 genfn
= gen_helper_neon_ceq_f32
;
10132 case 0x6d: /* FCMLE (zero) */
10135 case 0x6c: /* FCMGE (zero) */
10136 genfn
= gen_helper_neon_cge_f32
;
10139 g_assert_not_reached();
10146 int vector_size
= 8 << is_q
;
10147 maxpasses
= vector_size
>> size
;
10150 for (pass
= 0; pass
< maxpasses
; pass
++) {
10151 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10153 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10155 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10158 write_fp_sreg(s
, rd
, tcg_res
);
10160 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10163 tcg_temp_free_i32(tcg_res
);
10164 tcg_temp_free_i32(tcg_zero
);
10165 tcg_temp_free_i32(tcg_op
);
10167 clear_vec_high(s
, is_q
, rd
);
10171 tcg_temp_free_ptr(fpst
);
10174 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10175 bool is_scalar
, bool is_u
, bool is_q
,
10176 int size
, int rn
, int rd
)
10178 bool is_double
= (size
== 3);
10179 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10182 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10183 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10186 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10187 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10189 case 0x3d: /* FRECPE */
10190 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10192 case 0x3f: /* FRECPX */
10193 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10195 case 0x7d: /* FRSQRTE */
10196 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10199 g_assert_not_reached();
10201 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10203 tcg_temp_free_i64(tcg_res
);
10204 tcg_temp_free_i64(tcg_op
);
10205 clear_vec_high(s
, !is_scalar
, rd
);
10207 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10208 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10209 int pass
, maxpasses
;
10214 maxpasses
= is_q
? 4 : 2;
10217 for (pass
= 0; pass
< maxpasses
; pass
++) {
10218 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10221 case 0x3c: /* URECPE */
10222 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10224 case 0x3d: /* FRECPE */
10225 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10227 case 0x3f: /* FRECPX */
10228 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10230 case 0x7d: /* FRSQRTE */
10231 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10234 g_assert_not_reached();
10238 write_fp_sreg(s
, rd
, tcg_res
);
10240 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10243 tcg_temp_free_i32(tcg_res
);
10244 tcg_temp_free_i32(tcg_op
);
10246 clear_vec_high(s
, is_q
, rd
);
10249 tcg_temp_free_ptr(fpst
);
10252 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10253 int opcode
, bool u
, bool is_q
,
10254 int size
, int rn
, int rd
)
10256 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10257 * in the source becomes a size element in the destination).
10260 TCGv_i32 tcg_res
[2];
10261 int destelt
= is_q
? 2 : 0;
10262 int passes
= scalar
? 1 : 2;
10265 tcg_res
[1] = tcg_const_i32(0);
10268 for (pass
= 0; pass
< passes
; pass
++) {
10269 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10270 NeonGenNarrowFn
*genfn
= NULL
;
10271 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10274 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10276 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10278 tcg_res
[pass
] = tcg_temp_new_i32();
10281 case 0x12: /* XTN, SQXTUN */
10283 static NeonGenNarrowFn
* const xtnfns
[3] = {
10284 gen_helper_neon_narrow_u8
,
10285 gen_helper_neon_narrow_u16
,
10286 tcg_gen_extrl_i64_i32
,
10288 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10289 gen_helper_neon_unarrow_sat8
,
10290 gen_helper_neon_unarrow_sat16
,
10291 gen_helper_neon_unarrow_sat32
,
10294 genenvfn
= sqxtunfns
[size
];
10296 genfn
= xtnfns
[size
];
10300 case 0x14: /* SQXTN, UQXTN */
10302 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10303 { gen_helper_neon_narrow_sat_s8
,
10304 gen_helper_neon_narrow_sat_u8
},
10305 { gen_helper_neon_narrow_sat_s16
,
10306 gen_helper_neon_narrow_sat_u16
},
10307 { gen_helper_neon_narrow_sat_s32
,
10308 gen_helper_neon_narrow_sat_u32
},
10310 genenvfn
= fns
[size
][u
];
10313 case 0x16: /* FCVTN, FCVTN2 */
10314 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10316 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10318 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10319 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10320 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10321 TCGv_i32 ahp
= get_ahp_flag();
10323 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10324 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10325 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10326 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10327 tcg_temp_free_i32(tcg_lo
);
10328 tcg_temp_free_i32(tcg_hi
);
10329 tcg_temp_free_ptr(fpst
);
10330 tcg_temp_free_i32(ahp
);
10333 case 0x56: /* FCVTXN, FCVTXN2 */
10334 /* 64 bit to 32 bit float conversion
10335 * with von Neumann rounding (round to odd)
10338 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10341 g_assert_not_reached();
10345 genfn(tcg_res
[pass
], tcg_op
);
10346 } else if (genenvfn
) {
10347 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10350 tcg_temp_free_i64(tcg_op
);
10353 for (pass
= 0; pass
< 2; pass
++) {
10354 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10355 tcg_temp_free_i32(tcg_res
[pass
]);
10357 clear_vec_high(s
, is_q
, rd
);
10360 /* Remaining saturating accumulating ops */
10361 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10362 bool is_q
, int size
, int rn
, int rd
)
10364 bool is_double
= (size
== 3);
10367 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10368 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10371 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10372 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10373 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10375 if (is_u
) { /* USQADD */
10376 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10377 } else { /* SUQADD */
10378 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10380 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10382 tcg_temp_free_i64(tcg_rd
);
10383 tcg_temp_free_i64(tcg_rn
);
10384 clear_vec_high(s
, !is_scalar
, rd
);
10386 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10387 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10388 int pass
, maxpasses
;
10393 maxpasses
= is_q
? 4 : 2;
10396 for (pass
= 0; pass
< maxpasses
; pass
++) {
10398 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10399 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10401 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10402 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10405 if (is_u
) { /* USQADD */
10408 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10411 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10414 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10417 g_assert_not_reached();
10419 } else { /* SUQADD */
10422 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10425 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10428 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10431 g_assert_not_reached();
10436 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10437 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10438 tcg_temp_free_i64(tcg_zero
);
10440 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10442 tcg_temp_free_i32(tcg_rd
);
10443 tcg_temp_free_i32(tcg_rn
);
10444 clear_vec_high(s
, is_q
, rd
);
10448 /* AdvSIMD scalar two reg misc
10449 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10450 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10451 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10452 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10454 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10456 int rd
= extract32(insn
, 0, 5);
10457 int rn
= extract32(insn
, 5, 5);
10458 int opcode
= extract32(insn
, 12, 5);
10459 int size
= extract32(insn
, 22, 2);
10460 bool u
= extract32(insn
, 29, 1);
10461 bool is_fcvt
= false;
10463 TCGv_i32 tcg_rmode
;
10464 TCGv_ptr tcg_fpstatus
;
10467 case 0x3: /* USQADD / SUQADD*/
10468 if (!fp_access_check(s
)) {
10471 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10473 case 0x7: /* SQABS / SQNEG */
10475 case 0xa: /* CMLT */
10477 unallocated_encoding(s
);
10481 case 0x8: /* CMGT, CMGE */
10482 case 0x9: /* CMEQ, CMLE */
10483 case 0xb: /* ABS, NEG */
10485 unallocated_encoding(s
);
10489 case 0x12: /* SQXTUN */
10491 unallocated_encoding(s
);
10495 case 0x14: /* SQXTN, UQXTN */
10497 unallocated_encoding(s
);
10500 if (!fp_access_check(s
)) {
10503 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10506 case 0x16 ... 0x1d:
10508 /* Floating point: U, size[1] and opcode indicate operation;
10509 * size[0] indicates single or double precision.
10511 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10512 size
= extract32(size
, 0, 1) ? 3 : 2;
10514 case 0x2c: /* FCMGT (zero) */
10515 case 0x2d: /* FCMEQ (zero) */
10516 case 0x2e: /* FCMLT (zero) */
10517 case 0x6c: /* FCMGE (zero) */
10518 case 0x6d: /* FCMLE (zero) */
10519 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10521 case 0x1d: /* SCVTF */
10522 case 0x5d: /* UCVTF */
10524 bool is_signed
= (opcode
== 0x1d);
10525 if (!fp_access_check(s
)) {
10528 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10531 case 0x3d: /* FRECPE */
10532 case 0x3f: /* FRECPX */
10533 case 0x7d: /* FRSQRTE */
10534 if (!fp_access_check(s
)) {
10537 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10539 case 0x1a: /* FCVTNS */
10540 case 0x1b: /* FCVTMS */
10541 case 0x3a: /* FCVTPS */
10542 case 0x3b: /* FCVTZS */
10543 case 0x5a: /* FCVTNU */
10544 case 0x5b: /* FCVTMU */
10545 case 0x7a: /* FCVTPU */
10546 case 0x7b: /* FCVTZU */
10548 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10550 case 0x1c: /* FCVTAS */
10551 case 0x5c: /* FCVTAU */
10552 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10554 rmode
= FPROUNDING_TIEAWAY
;
10556 case 0x56: /* FCVTXN, FCVTXN2 */
10558 unallocated_encoding(s
);
10561 if (!fp_access_check(s
)) {
10564 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10567 unallocated_encoding(s
);
10572 unallocated_encoding(s
);
10576 if (!fp_access_check(s
)) {
10581 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10582 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10583 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10586 tcg_fpstatus
= NULL
;
10590 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10591 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10593 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10594 write_fp_dreg(s
, rd
, tcg_rd
);
10595 tcg_temp_free_i64(tcg_rd
);
10596 tcg_temp_free_i64(tcg_rn
);
10598 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10599 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10601 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10604 case 0x7: /* SQABS, SQNEG */
10606 NeonGenOneOpEnvFn
*genfn
;
10607 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10608 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10609 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10610 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10612 genfn
= fns
[size
][u
];
10613 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10616 case 0x1a: /* FCVTNS */
10617 case 0x1b: /* FCVTMS */
10618 case 0x1c: /* FCVTAS */
10619 case 0x3a: /* FCVTPS */
10620 case 0x3b: /* FCVTZS */
10622 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10623 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10624 tcg_temp_free_i32(tcg_shift
);
10627 case 0x5a: /* FCVTNU */
10628 case 0x5b: /* FCVTMU */
10629 case 0x5c: /* FCVTAU */
10630 case 0x7a: /* FCVTPU */
10631 case 0x7b: /* FCVTZU */
10633 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10634 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10635 tcg_temp_free_i32(tcg_shift
);
10639 g_assert_not_reached();
10642 write_fp_sreg(s
, rd
, tcg_rd
);
10643 tcg_temp_free_i32(tcg_rd
);
10644 tcg_temp_free_i32(tcg_rn
);
10648 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10649 tcg_temp_free_i32(tcg_rmode
);
10650 tcg_temp_free_ptr(tcg_fpstatus
);
10654 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10655 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10656 int immh
, int immb
, int opcode
, int rn
, int rd
)
10658 int size
= 32 - clz32(immh
) - 1;
10659 int immhb
= immh
<< 3 | immb
;
10660 int shift
= 2 * (8 << size
) - immhb
;
10661 GVecGen2iFn
*gvec_fn
;
10663 if (extract32(immh
, 3, 1) && !is_q
) {
10664 unallocated_encoding(s
);
10667 tcg_debug_assert(size
<= 3);
10669 if (!fp_access_check(s
)) {
10674 case 0x02: /* SSRA / USRA (accumulate) */
10675 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10678 case 0x08: /* SRI */
10679 gvec_fn
= gen_gvec_sri
;
10682 case 0x00: /* SSHR / USHR */
10684 if (shift
== 8 << size
) {
10685 /* Shift count the same size as element size produces zero. */
10686 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10687 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10690 gvec_fn
= tcg_gen_gvec_shri
;
10692 /* Shift count the same size as element size produces all sign. */
10693 if (shift
== 8 << size
) {
10696 gvec_fn
= tcg_gen_gvec_sari
;
10700 case 0x04: /* SRSHR / URSHR (rounding) */
10701 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10704 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10705 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10709 g_assert_not_reached();
10712 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10715 /* SHL/SLI - Vector shift left */
10716 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10717 int immh
, int immb
, int opcode
, int rn
, int rd
)
10719 int size
= 32 - clz32(immh
) - 1;
10720 int immhb
= immh
<< 3 | immb
;
10721 int shift
= immhb
- (8 << size
);
10723 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10724 assert(size
>= 0 && size
<= 3);
10726 if (extract32(immh
, 3, 1) && !is_q
) {
10727 unallocated_encoding(s
);
10731 if (!fp_access_check(s
)) {
10736 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10738 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10742 /* USHLL/SHLL - Vector shift left with widening */
10743 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10744 int immh
, int immb
, int opcode
, int rn
, int rd
)
10746 int size
= 32 - clz32(immh
) - 1;
10747 int immhb
= immh
<< 3 | immb
;
10748 int shift
= immhb
- (8 << size
);
10750 int esize
= 8 << size
;
10751 int elements
= dsize
/esize
;
10752 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10753 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10757 unallocated_encoding(s
);
10761 if (!fp_access_check(s
)) {
10765 /* For the LL variants the store is larger than the load,
10766 * so if rd == rn we would overwrite parts of our input.
10767 * So load everything right now and use shifts in the main loop.
10769 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10771 for (i
= 0; i
< elements
; i
++) {
10772 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10773 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10774 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10775 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10779 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10780 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10781 int immh
, int immb
, int opcode
, int rn
, int rd
)
10783 int immhb
= immh
<< 3 | immb
;
10784 int size
= 32 - clz32(immh
) - 1;
10786 int esize
= 8 << size
;
10787 int elements
= dsize
/esize
;
10788 int shift
= (2 * esize
) - immhb
;
10789 bool round
= extract32(opcode
, 0, 1);
10790 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10791 TCGv_i64 tcg_round
;
10794 if (extract32(immh
, 3, 1)) {
10795 unallocated_encoding(s
);
10799 if (!fp_access_check(s
)) {
10803 tcg_rn
= tcg_temp_new_i64();
10804 tcg_rd
= tcg_temp_new_i64();
10805 tcg_final
= tcg_temp_new_i64();
10806 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10809 uint64_t round_const
= 1ULL << (shift
- 1);
10810 tcg_round
= tcg_const_i64(round_const
);
10815 for (i
= 0; i
< elements
; i
++) {
10816 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10817 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10818 false, true, size
+1, shift
);
10820 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10824 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10826 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10829 tcg_temp_free_i64(tcg_round
);
10831 tcg_temp_free_i64(tcg_rn
);
10832 tcg_temp_free_i64(tcg_rd
);
10833 tcg_temp_free_i64(tcg_final
);
10835 clear_vec_high(s
, is_q
, rd
);
10839 /* AdvSIMD shift by immediate
10840 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10841 * +---+---+---+-------------+------+------+--------+---+------+------+
10842 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10843 * +---+---+---+-------------+------+------+--------+---+------+------+
10845 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10847 int rd
= extract32(insn
, 0, 5);
10848 int rn
= extract32(insn
, 5, 5);
10849 int opcode
= extract32(insn
, 11, 5);
10850 int immb
= extract32(insn
, 16, 3);
10851 int immh
= extract32(insn
, 19, 4);
10852 bool is_u
= extract32(insn
, 29, 1);
10853 bool is_q
= extract32(insn
, 30, 1);
10855 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10859 case 0x08: /* SRI */
10861 unallocated_encoding(s
);
10865 case 0x00: /* SSHR / USHR */
10866 case 0x02: /* SSRA / USRA (accumulate) */
10867 case 0x04: /* SRSHR / URSHR (rounding) */
10868 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10869 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10871 case 0x0a: /* SHL / SLI */
10872 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10874 case 0x10: /* SHRN */
10875 case 0x11: /* RSHRN / SQRSHRUN */
10877 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10880 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10883 case 0x12: /* SQSHRN / UQSHRN */
10884 case 0x13: /* SQRSHRN / UQRSHRN */
10885 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10888 case 0x14: /* SSHLL / USHLL */
10889 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10891 case 0x1c: /* SCVTF / UCVTF */
10892 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10895 case 0xc: /* SQSHLU */
10897 unallocated_encoding(s
);
10900 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10902 case 0xe: /* SQSHL, UQSHL */
10903 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10905 case 0x1f: /* FCVTZS/ FCVTZU */
10906 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10909 unallocated_encoding(s
);
10914 /* Generate code to do a "long" addition or subtraction, ie one done in
10915 * TCGv_i64 on vector lanes twice the width specified by size.
10917 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10918 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10920 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10921 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10922 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10923 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10925 NeonGenTwo64OpFn
*genfn
;
10928 genfn
= fns
[size
][is_sub
];
10929 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10932 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10933 int opcode
, int rd
, int rn
, int rm
)
10935 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10936 TCGv_i64 tcg_res
[2];
10939 tcg_res
[0] = tcg_temp_new_i64();
10940 tcg_res
[1] = tcg_temp_new_i64();
10942 /* Does this op do an adding accumulate, a subtracting accumulate,
10943 * or no accumulate at all?
10961 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10962 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10965 /* size == 2 means two 32x32->64 operations; this is worth special
10966 * casing because we can generally handle it inline.
10969 for (pass
= 0; pass
< 2; pass
++) {
10970 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10971 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10972 TCGv_i64 tcg_passres
;
10973 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10975 int elt
= pass
+ is_q
* 2;
10977 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10978 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10981 tcg_passres
= tcg_res
[pass
];
10983 tcg_passres
= tcg_temp_new_i64();
10987 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10988 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10990 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10991 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10993 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10994 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10996 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10997 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10999 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
11000 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
11001 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
11003 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
11004 tcg_temp_free_i64(tcg_tmp1
);
11005 tcg_temp_free_i64(tcg_tmp2
);
11008 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11009 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11010 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11011 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11013 case 9: /* SQDMLAL, SQDMLAL2 */
11014 case 11: /* SQDMLSL, SQDMLSL2 */
11015 case 13: /* SQDMULL, SQDMULL2 */
11016 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11017 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
11018 tcg_passres
, tcg_passres
);
11021 g_assert_not_reached();
11024 if (opcode
== 9 || opcode
== 11) {
11025 /* saturating accumulate ops */
11027 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
11029 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
11030 tcg_res
[pass
], tcg_passres
);
11031 } else if (accop
> 0) {
11032 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11033 } else if (accop
< 0) {
11034 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11038 tcg_temp_free_i64(tcg_passres
);
11041 tcg_temp_free_i64(tcg_op1
);
11042 tcg_temp_free_i64(tcg_op2
);
11045 /* size 0 or 1, generally helper functions */
11046 for (pass
= 0; pass
< 2; pass
++) {
11047 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11048 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11049 TCGv_i64 tcg_passres
;
11050 int elt
= pass
+ is_q
* 2;
11052 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
11053 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11056 tcg_passres
= tcg_res
[pass
];
11058 tcg_passres
= tcg_temp_new_i64();
11062 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11063 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11065 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11066 static NeonGenWidenFn
* const widenfns
[2][2] = {
11067 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11068 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11070 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11072 widenfn(tcg_op2_64
, tcg_op2
);
11073 widenfn(tcg_passres
, tcg_op1
);
11074 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11075 tcg_passres
, tcg_op2_64
);
11076 tcg_temp_free_i64(tcg_op2_64
);
11079 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11080 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11083 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11085 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11089 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11091 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11095 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11096 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11097 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11100 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11102 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11106 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11108 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11112 case 9: /* SQDMLAL, SQDMLAL2 */
11113 case 11: /* SQDMLSL, SQDMLSL2 */
11114 case 13: /* SQDMULL, SQDMULL2 */
11116 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11117 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11118 tcg_passres
, tcg_passres
);
11121 g_assert_not_reached();
11123 tcg_temp_free_i32(tcg_op1
);
11124 tcg_temp_free_i32(tcg_op2
);
11127 if (opcode
== 9 || opcode
== 11) {
11128 /* saturating accumulate ops */
11130 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11132 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11136 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11137 tcg_res
[pass
], tcg_passres
);
11139 tcg_temp_free_i64(tcg_passres
);
11144 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11145 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11146 tcg_temp_free_i64(tcg_res
[0]);
11147 tcg_temp_free_i64(tcg_res
[1]);
11150 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11151 int opcode
, int rd
, int rn
, int rm
)
11153 TCGv_i64 tcg_res
[2];
11154 int part
= is_q
? 2 : 0;
11157 for (pass
= 0; pass
< 2; pass
++) {
11158 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11159 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11160 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11161 static NeonGenWidenFn
* const widenfns
[3][2] = {
11162 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11163 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11164 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11166 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11168 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11169 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11170 widenfn(tcg_op2_wide
, tcg_op2
);
11171 tcg_temp_free_i32(tcg_op2
);
11172 tcg_res
[pass
] = tcg_temp_new_i64();
11173 gen_neon_addl(size
, (opcode
== 3),
11174 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11175 tcg_temp_free_i64(tcg_op1
);
11176 tcg_temp_free_i64(tcg_op2_wide
);
11179 for (pass
= 0; pass
< 2; pass
++) {
11180 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11181 tcg_temp_free_i64(tcg_res
[pass
]);
11185 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11187 tcg_gen_addi_i64(in
, in
, 1U << 31);
11188 tcg_gen_extrh_i64_i32(res
, in
);
11191 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11192 int opcode
, int rd
, int rn
, int rm
)
11194 TCGv_i32 tcg_res
[2];
11195 int part
= is_q
? 2 : 0;
11198 for (pass
= 0; pass
< 2; pass
++) {
11199 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11200 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11201 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11202 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11203 { gen_helper_neon_narrow_high_u8
,
11204 gen_helper_neon_narrow_round_high_u8
},
11205 { gen_helper_neon_narrow_high_u16
,
11206 gen_helper_neon_narrow_round_high_u16
},
11207 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11209 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11211 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11212 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11214 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11216 tcg_temp_free_i64(tcg_op1
);
11217 tcg_temp_free_i64(tcg_op2
);
11219 tcg_res
[pass
] = tcg_temp_new_i32();
11220 gennarrow(tcg_res
[pass
], tcg_wideres
);
11221 tcg_temp_free_i64(tcg_wideres
);
11224 for (pass
= 0; pass
< 2; pass
++) {
11225 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11226 tcg_temp_free_i32(tcg_res
[pass
]);
11228 clear_vec_high(s
, is_q
, rd
);
11231 /* AdvSIMD three different
11232 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11233 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11234 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11235 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11237 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11239 /* Instructions in this group fall into three basic classes
11240 * (in each case with the operation working on each element in
11241 * the input vectors):
11242 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11244 * (2) wide 64 x 128 -> 128
11245 * (3) narrowing 128 x 128 -> 64
11246 * Here we do initial decode, catch unallocated cases and
11247 * dispatch to separate functions for each class.
11249 int is_q
= extract32(insn
, 30, 1);
11250 int is_u
= extract32(insn
, 29, 1);
11251 int size
= extract32(insn
, 22, 2);
11252 int opcode
= extract32(insn
, 12, 4);
11253 int rm
= extract32(insn
, 16, 5);
11254 int rn
= extract32(insn
, 5, 5);
11255 int rd
= extract32(insn
, 0, 5);
11258 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11259 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11260 /* 64 x 128 -> 128 */
11262 unallocated_encoding(s
);
11265 if (!fp_access_check(s
)) {
11268 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11270 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11271 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11272 /* 128 x 128 -> 64 */
11274 unallocated_encoding(s
);
11277 if (!fp_access_check(s
)) {
11280 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11282 case 14: /* PMULL, PMULL2 */
11284 unallocated_encoding(s
);
11288 case 0: /* PMULL.P8 */
11289 if (!fp_access_check(s
)) {
11292 /* The Q field specifies lo/hi half input for this insn. */
11293 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11294 gen_helper_neon_pmull_h
);
11297 case 3: /* PMULL.P64 */
11298 if (!dc_isar_feature(aa64_pmull
, s
)) {
11299 unallocated_encoding(s
);
11302 if (!fp_access_check(s
)) {
11305 /* The Q field specifies lo/hi half input for this insn. */
11306 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11307 gen_helper_gvec_pmull_q
);
11311 unallocated_encoding(s
);
11315 case 9: /* SQDMLAL, SQDMLAL2 */
11316 case 11: /* SQDMLSL, SQDMLSL2 */
11317 case 13: /* SQDMULL, SQDMULL2 */
11318 if (is_u
|| size
== 0) {
11319 unallocated_encoding(s
);
11323 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11324 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11325 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11326 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11327 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11328 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11329 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11330 /* 64 x 64 -> 128 */
11332 unallocated_encoding(s
);
11335 if (!fp_access_check(s
)) {
11339 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11342 /* opcode 15 not allocated */
11343 unallocated_encoding(s
);
11348 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11349 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11351 int rd
= extract32(insn
, 0, 5);
11352 int rn
= extract32(insn
, 5, 5);
11353 int rm
= extract32(insn
, 16, 5);
11354 int size
= extract32(insn
, 22, 2);
11355 bool is_u
= extract32(insn
, 29, 1);
11356 bool is_q
= extract32(insn
, 30, 1);
11358 if (!fp_access_check(s
)) {
11362 switch (size
+ 4 * is_u
) {
11364 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11367 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11370 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11373 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11376 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11379 case 5: /* BSL bitwise select */
11380 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11382 case 6: /* BIT, bitwise insert if true */
11383 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11385 case 7: /* BIF, bitwise insert if false */
11386 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11390 g_assert_not_reached();
11394 /* Pairwise op subgroup of C3.6.16.
11396 * This is called directly or via the handle_3same_float for float pairwise
11397 * operations where the opcode and size are calculated differently.
11399 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11400 int size
, int rn
, int rm
, int rd
)
11405 /* Floating point operations need fpst */
11406 if (opcode
>= 0x58) {
11407 fpst
= fpstatus_ptr(FPST_FPCR
);
11412 if (!fp_access_check(s
)) {
11416 /* These operations work on the concatenated rm:rn, with each pair of
11417 * adjacent elements being operated on to produce an element in the result.
11420 TCGv_i64 tcg_res
[2];
11422 for (pass
= 0; pass
< 2; pass
++) {
11423 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11424 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11425 int passreg
= (pass
== 0) ? rn
: rm
;
11427 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11428 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11429 tcg_res
[pass
] = tcg_temp_new_i64();
11432 case 0x17: /* ADDP */
11433 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11435 case 0x58: /* FMAXNMP */
11436 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11438 case 0x5a: /* FADDP */
11439 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11441 case 0x5e: /* FMAXP */
11442 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11444 case 0x78: /* FMINNMP */
11445 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11447 case 0x7e: /* FMINP */
11448 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11451 g_assert_not_reached();
11454 tcg_temp_free_i64(tcg_op1
);
11455 tcg_temp_free_i64(tcg_op2
);
11458 for (pass
= 0; pass
< 2; pass
++) {
11459 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11460 tcg_temp_free_i64(tcg_res
[pass
]);
11463 int maxpass
= is_q
? 4 : 2;
11464 TCGv_i32 tcg_res
[4];
11466 for (pass
= 0; pass
< maxpass
; pass
++) {
11467 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11468 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11469 NeonGenTwoOpFn
*genfn
= NULL
;
11470 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11471 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11473 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11474 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11475 tcg_res
[pass
] = tcg_temp_new_i32();
11478 case 0x17: /* ADDP */
11480 static NeonGenTwoOpFn
* const fns
[3] = {
11481 gen_helper_neon_padd_u8
,
11482 gen_helper_neon_padd_u16
,
11488 case 0x14: /* SMAXP, UMAXP */
11490 static NeonGenTwoOpFn
* const fns
[3][2] = {
11491 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11492 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11493 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11495 genfn
= fns
[size
][u
];
11498 case 0x15: /* SMINP, UMINP */
11500 static NeonGenTwoOpFn
* const fns
[3][2] = {
11501 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11502 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11503 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11505 genfn
= fns
[size
][u
];
11508 /* The FP operations are all on single floats (32 bit) */
11509 case 0x58: /* FMAXNMP */
11510 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11512 case 0x5a: /* FADDP */
11513 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11515 case 0x5e: /* FMAXP */
11516 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11518 case 0x78: /* FMINNMP */
11519 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11521 case 0x7e: /* FMINP */
11522 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11525 g_assert_not_reached();
11528 /* FP ops called directly, otherwise call now */
11530 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11533 tcg_temp_free_i32(tcg_op1
);
11534 tcg_temp_free_i32(tcg_op2
);
11537 for (pass
= 0; pass
< maxpass
; pass
++) {
11538 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11539 tcg_temp_free_i32(tcg_res
[pass
]);
11541 clear_vec_high(s
, is_q
, rd
);
11545 tcg_temp_free_ptr(fpst
);
11549 /* Floating point op subgroup of C3.6.16. */
11550 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11552 /* For floating point ops, the U, size[1] and opcode bits
11553 * together indicate the operation. size[0] indicates single
11556 int fpopcode
= extract32(insn
, 11, 5)
11557 | (extract32(insn
, 23, 1) << 5)
11558 | (extract32(insn
, 29, 1) << 6);
11559 int is_q
= extract32(insn
, 30, 1);
11560 int size
= extract32(insn
, 22, 1);
11561 int rm
= extract32(insn
, 16, 5);
11562 int rn
= extract32(insn
, 5, 5);
11563 int rd
= extract32(insn
, 0, 5);
11565 int datasize
= is_q
? 128 : 64;
11566 int esize
= 32 << size
;
11567 int elements
= datasize
/ esize
;
11569 if (size
== 1 && !is_q
) {
11570 unallocated_encoding(s
);
11574 switch (fpopcode
) {
11575 case 0x58: /* FMAXNMP */
11576 case 0x5a: /* FADDP */
11577 case 0x5e: /* FMAXP */
11578 case 0x78: /* FMINNMP */
11579 case 0x7e: /* FMINP */
11580 if (size
&& !is_q
) {
11581 unallocated_encoding(s
);
11584 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11587 case 0x1b: /* FMULX */
11588 case 0x1f: /* FRECPS */
11589 case 0x3f: /* FRSQRTS */
11590 case 0x5d: /* FACGE */
11591 case 0x7d: /* FACGT */
11592 case 0x19: /* FMLA */
11593 case 0x39: /* FMLS */
11594 case 0x18: /* FMAXNM */
11595 case 0x1a: /* FADD */
11596 case 0x1c: /* FCMEQ */
11597 case 0x1e: /* FMAX */
11598 case 0x38: /* FMINNM */
11599 case 0x3a: /* FSUB */
11600 case 0x3e: /* FMIN */
11601 case 0x5b: /* FMUL */
11602 case 0x5c: /* FCMGE */
11603 case 0x5f: /* FDIV */
11604 case 0x7a: /* FABD */
11605 case 0x7c: /* FCMGT */
11606 if (!fp_access_check(s
)) {
11609 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11612 case 0x1d: /* FMLAL */
11613 case 0x3d: /* FMLSL */
11614 case 0x59: /* FMLAL2 */
11615 case 0x79: /* FMLSL2 */
11616 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11617 unallocated_encoding(s
);
11620 if (fp_access_check(s
)) {
11621 int is_s
= extract32(insn
, 23, 1);
11622 int is_2
= extract32(insn
, 29, 1);
11623 int data
= (is_2
<< 1) | is_s
;
11624 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11625 vec_full_reg_offset(s
, rn
),
11626 vec_full_reg_offset(s
, rm
), cpu_env
,
11627 is_q
? 16 : 8, vec_full_reg_size(s
),
11628 data
, gen_helper_gvec_fmlal_a64
);
11633 unallocated_encoding(s
);
11638 /* Integer op subgroup of C3.6.16. */
11639 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11641 int is_q
= extract32(insn
, 30, 1);
11642 int u
= extract32(insn
, 29, 1);
11643 int size
= extract32(insn
, 22, 2);
11644 int opcode
= extract32(insn
, 11, 5);
11645 int rm
= extract32(insn
, 16, 5);
11646 int rn
= extract32(insn
, 5, 5);
11647 int rd
= extract32(insn
, 0, 5);
11652 case 0x13: /* MUL, PMUL */
11653 if (u
&& size
!= 0) {
11654 unallocated_encoding(s
);
11658 case 0x0: /* SHADD, UHADD */
11659 case 0x2: /* SRHADD, URHADD */
11660 case 0x4: /* SHSUB, UHSUB */
11661 case 0xc: /* SMAX, UMAX */
11662 case 0xd: /* SMIN, UMIN */
11663 case 0xe: /* SABD, UABD */
11664 case 0xf: /* SABA, UABA */
11665 case 0x12: /* MLA, MLS */
11667 unallocated_encoding(s
);
11671 case 0x16: /* SQDMULH, SQRDMULH */
11672 if (size
== 0 || size
== 3) {
11673 unallocated_encoding(s
);
11678 if (size
== 3 && !is_q
) {
11679 unallocated_encoding(s
);
11685 if (!fp_access_check(s
)) {
11690 case 0x01: /* SQADD, UQADD */
11692 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11694 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11697 case 0x05: /* SQSUB, UQSUB */
11699 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11701 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11704 case 0x08: /* SSHL, USHL */
11706 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11708 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11711 case 0x0c: /* SMAX, UMAX */
11713 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11715 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11718 case 0x0d: /* SMIN, UMIN */
11720 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11722 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11725 case 0xe: /* SABD, UABD */
11727 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11729 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11732 case 0xf: /* SABA, UABA */
11734 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11736 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11739 case 0x10: /* ADD, SUB */
11741 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11743 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11746 case 0x13: /* MUL, PMUL */
11747 if (!u
) { /* MUL */
11748 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11749 } else { /* PMUL */
11750 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11753 case 0x12: /* MLA, MLS */
11755 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11757 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11760 case 0x16: /* SQDMULH, SQRDMULH */
11762 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11763 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11764 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11766 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11770 if (!u
) { /* CMTST */
11771 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11775 cond
= TCG_COND_EQ
;
11777 case 0x06: /* CMGT, CMHI */
11778 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11780 case 0x07: /* CMGE, CMHS */
11781 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11783 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11784 vec_full_reg_offset(s
, rn
),
11785 vec_full_reg_offset(s
, rm
),
11786 is_q
? 16 : 8, vec_full_reg_size(s
));
11792 for (pass
= 0; pass
< 2; pass
++) {
11793 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11794 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11795 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11797 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11798 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11800 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11802 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11804 tcg_temp_free_i64(tcg_res
);
11805 tcg_temp_free_i64(tcg_op1
);
11806 tcg_temp_free_i64(tcg_op2
);
11809 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11810 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11811 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11812 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11813 NeonGenTwoOpFn
*genfn
= NULL
;
11814 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11816 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11817 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11820 case 0x0: /* SHADD, UHADD */
11822 static NeonGenTwoOpFn
* const fns
[3][2] = {
11823 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11824 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11825 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11827 genfn
= fns
[size
][u
];
11830 case 0x2: /* SRHADD, URHADD */
11832 static NeonGenTwoOpFn
* const fns
[3][2] = {
11833 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11834 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11835 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11837 genfn
= fns
[size
][u
];
11840 case 0x4: /* SHSUB, UHSUB */
11842 static NeonGenTwoOpFn
* const fns
[3][2] = {
11843 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11844 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11845 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11847 genfn
= fns
[size
][u
];
11850 case 0x9: /* SQSHL, UQSHL */
11852 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11853 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11854 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11855 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11857 genenvfn
= fns
[size
][u
];
11860 case 0xa: /* SRSHL, URSHL */
11862 static NeonGenTwoOpFn
* const fns
[3][2] = {
11863 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11864 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11865 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11867 genfn
= fns
[size
][u
];
11870 case 0xb: /* SQRSHL, UQRSHL */
11872 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11873 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11874 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11875 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11877 genenvfn
= fns
[size
][u
];
11881 g_assert_not_reached();
11885 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11887 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11890 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11892 tcg_temp_free_i32(tcg_res
);
11893 tcg_temp_free_i32(tcg_op1
);
11894 tcg_temp_free_i32(tcg_op2
);
11897 clear_vec_high(s
, is_q
, rd
);
11900 /* AdvSIMD three same
11901 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11902 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11903 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11904 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11906 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11908 int opcode
= extract32(insn
, 11, 5);
11911 case 0x3: /* logic ops */
11912 disas_simd_3same_logic(s
, insn
);
11914 case 0x17: /* ADDP */
11915 case 0x14: /* SMAXP, UMAXP */
11916 case 0x15: /* SMINP, UMINP */
11918 /* Pairwise operations */
11919 int is_q
= extract32(insn
, 30, 1);
11920 int u
= extract32(insn
, 29, 1);
11921 int size
= extract32(insn
, 22, 2);
11922 int rm
= extract32(insn
, 16, 5);
11923 int rn
= extract32(insn
, 5, 5);
11924 int rd
= extract32(insn
, 0, 5);
11925 if (opcode
== 0x17) {
11926 if (u
|| (size
== 3 && !is_q
)) {
11927 unallocated_encoding(s
);
11932 unallocated_encoding(s
);
11936 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11939 case 0x18 ... 0x31:
11940 /* floating point ops, sz[1] and U are part of opcode */
11941 disas_simd_3same_float(s
, insn
);
11944 disas_simd_3same_int(s
, insn
);
11950 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11952 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11953 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11954 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11955 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11957 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11958 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11961 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11963 int opcode
, fpopcode
;
11964 int is_q
, u
, a
, rm
, rn
, rd
;
11965 int datasize
, elements
;
11968 bool pairwise
= false;
11970 if (!dc_isar_feature(aa64_fp16
, s
)) {
11971 unallocated_encoding(s
);
11975 if (!fp_access_check(s
)) {
11979 /* For these floating point ops, the U, a and opcode bits
11980 * together indicate the operation.
11982 opcode
= extract32(insn
, 11, 3);
11983 u
= extract32(insn
, 29, 1);
11984 a
= extract32(insn
, 23, 1);
11985 is_q
= extract32(insn
, 30, 1);
11986 rm
= extract32(insn
, 16, 5);
11987 rn
= extract32(insn
, 5, 5);
11988 rd
= extract32(insn
, 0, 5);
11990 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11991 datasize
= is_q
? 128 : 64;
11992 elements
= datasize
/ 16;
11994 switch (fpopcode
) {
11995 case 0x10: /* FMAXNMP */
11996 case 0x12: /* FADDP */
11997 case 0x16: /* FMAXP */
11998 case 0x18: /* FMINNMP */
11999 case 0x1e: /* FMINP */
12004 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
12007 int maxpass
= is_q
? 8 : 4;
12008 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12009 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12010 TCGv_i32 tcg_res
[8];
12012 for (pass
= 0; pass
< maxpass
; pass
++) {
12013 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
12014 int passelt
= (pass
<< 1) & (maxpass
- 1);
12016 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
12017 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
12018 tcg_res
[pass
] = tcg_temp_new_i32();
12020 switch (fpopcode
) {
12021 case 0x10: /* FMAXNMP */
12022 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12025 case 0x12: /* FADDP */
12026 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12028 case 0x16: /* FMAXP */
12029 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12031 case 0x18: /* FMINNMP */
12032 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12035 case 0x1e: /* FMINP */
12036 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12039 g_assert_not_reached();
12043 for (pass
= 0; pass
< maxpass
; pass
++) {
12044 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12045 tcg_temp_free_i32(tcg_res
[pass
]);
12048 tcg_temp_free_i32(tcg_op1
);
12049 tcg_temp_free_i32(tcg_op2
);
12052 for (pass
= 0; pass
< elements
; pass
++) {
12053 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12054 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12055 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12057 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12058 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12060 switch (fpopcode
) {
12061 case 0x0: /* FMAXNM */
12062 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12064 case 0x1: /* FMLA */
12065 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12066 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12069 case 0x2: /* FADD */
12070 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12072 case 0x3: /* FMULX */
12073 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12075 case 0x4: /* FCMEQ */
12076 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12078 case 0x6: /* FMAX */
12079 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12081 case 0x7: /* FRECPS */
12082 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12084 case 0x8: /* FMINNM */
12085 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12087 case 0x9: /* FMLS */
12088 /* As usual for ARM, separate negation for fused multiply-add */
12089 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12090 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12091 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12094 case 0xa: /* FSUB */
12095 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12097 case 0xe: /* FMIN */
12098 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12100 case 0xf: /* FRSQRTS */
12101 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12103 case 0x13: /* FMUL */
12104 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12106 case 0x14: /* FCMGE */
12107 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12109 case 0x15: /* FACGE */
12110 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12112 case 0x17: /* FDIV */
12113 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12115 case 0x1a: /* FABD */
12116 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12117 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12119 case 0x1c: /* FCMGT */
12120 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12122 case 0x1d: /* FACGT */
12123 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12126 fprintf(stderr
, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64
"\n",
12127 __func__
, insn
, fpopcode
, s
->pc_curr
);
12128 g_assert_not_reached();
12131 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12132 tcg_temp_free_i32(tcg_res
);
12133 tcg_temp_free_i32(tcg_op1
);
12134 tcg_temp_free_i32(tcg_op2
);
12138 tcg_temp_free_ptr(fpst
);
12140 clear_vec_high(s
, is_q
, rd
);
12143 /* AdvSIMD three same extra
12144 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12145 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12146 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12147 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12149 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12151 int rd
= extract32(insn
, 0, 5);
12152 int rn
= extract32(insn
, 5, 5);
12153 int opcode
= extract32(insn
, 11, 4);
12154 int rm
= extract32(insn
, 16, 5);
12155 int size
= extract32(insn
, 22, 2);
12156 bool u
= extract32(insn
, 29, 1);
12157 bool is_q
= extract32(insn
, 30, 1);
12161 switch (u
* 16 + opcode
) {
12162 case 0x10: /* SQRDMLAH (vector) */
12163 case 0x11: /* SQRDMLSH (vector) */
12164 if (size
!= 1 && size
!= 2) {
12165 unallocated_encoding(s
);
12168 feature
= dc_isar_feature(aa64_rdm
, s
);
12170 case 0x02: /* SDOT (vector) */
12171 case 0x12: /* UDOT (vector) */
12172 if (size
!= MO_32
) {
12173 unallocated_encoding(s
);
12176 feature
= dc_isar_feature(aa64_dp
, s
);
12178 case 0x03: /* USDOT */
12179 if (size
!= MO_32
) {
12180 unallocated_encoding(s
);
12183 feature
= dc_isar_feature(aa64_i8mm
, s
);
12185 case 0x04: /* SMMLA */
12186 case 0x14: /* UMMLA */
12187 case 0x05: /* USMMLA */
12188 if (!is_q
|| size
!= MO_32
) {
12189 unallocated_encoding(s
);
12192 feature
= dc_isar_feature(aa64_i8mm
, s
);
12194 case 0x18: /* FCMLA, #0 */
12195 case 0x19: /* FCMLA, #90 */
12196 case 0x1a: /* FCMLA, #180 */
12197 case 0x1b: /* FCMLA, #270 */
12198 case 0x1c: /* FCADD, #90 */
12199 case 0x1e: /* FCADD, #270 */
12201 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12202 || (size
== 3 && !is_q
)) {
12203 unallocated_encoding(s
);
12206 feature
= dc_isar_feature(aa64_fcma
, s
);
12209 unallocated_encoding(s
);
12213 unallocated_encoding(s
);
12216 if (!fp_access_check(s
)) {
12221 case 0x0: /* SQRDMLAH (vector) */
12222 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12225 case 0x1: /* SQRDMLSH (vector) */
12226 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12229 case 0x2: /* SDOT / UDOT */
12230 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
12231 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12234 case 0x3: /* USDOT */
12235 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
12238 case 0x04: /* SMMLA, UMMLA */
12239 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
12240 u
? gen_helper_gvec_ummla_b
12241 : gen_helper_gvec_smmla_b
);
12243 case 0x05: /* USMMLA */
12244 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
12247 case 0x8: /* FCMLA, #0 */
12248 case 0x9: /* FCMLA, #90 */
12249 case 0xa: /* FCMLA, #180 */
12250 case 0xb: /* FCMLA, #270 */
12251 rot
= extract32(opcode
, 0, 2);
12254 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
12255 gen_helper_gvec_fcmlah
);
12258 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12259 gen_helper_gvec_fcmlas
);
12262 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12263 gen_helper_gvec_fcmlad
);
12266 g_assert_not_reached();
12270 case 0xc: /* FCADD, #90 */
12271 case 0xe: /* FCADD, #270 */
12272 rot
= extract32(opcode
, 1, 1);
12275 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12276 gen_helper_gvec_fcaddh
);
12279 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12280 gen_helper_gvec_fcadds
);
12283 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12284 gen_helper_gvec_fcaddd
);
12287 g_assert_not_reached();
12292 g_assert_not_reached();
12296 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12297 int size
, int rn
, int rd
)
12299 /* Handle 2-reg-misc ops which are widening (so each size element
12300 * in the source becomes a 2*size element in the destination.
12301 * The only instruction like this is FCVTL.
12306 /* 32 -> 64 bit fp conversion */
12307 TCGv_i64 tcg_res
[2];
12308 int srcelt
= is_q
? 2 : 0;
12310 for (pass
= 0; pass
< 2; pass
++) {
12311 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12312 tcg_res
[pass
] = tcg_temp_new_i64();
12314 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12315 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12316 tcg_temp_free_i32(tcg_op
);
12318 for (pass
= 0; pass
< 2; pass
++) {
12319 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12320 tcg_temp_free_i64(tcg_res
[pass
]);
12323 /* 16 -> 32 bit fp conversion */
12324 int srcelt
= is_q
? 4 : 0;
12325 TCGv_i32 tcg_res
[4];
12326 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12327 TCGv_i32 ahp
= get_ahp_flag();
12329 for (pass
= 0; pass
< 4; pass
++) {
12330 tcg_res
[pass
] = tcg_temp_new_i32();
12332 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12333 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12336 for (pass
= 0; pass
< 4; pass
++) {
12337 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12338 tcg_temp_free_i32(tcg_res
[pass
]);
12341 tcg_temp_free_ptr(fpst
);
12342 tcg_temp_free_i32(ahp
);
12346 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12347 bool is_q
, int size
, int rn
, int rd
)
12349 int op
= (opcode
<< 1) | u
;
12350 int opsz
= op
+ size
;
12351 int grp_size
= 3 - opsz
;
12352 int dsize
= is_q
? 128 : 64;
12356 unallocated_encoding(s
);
12360 if (!fp_access_check(s
)) {
12365 /* Special case bytes, use bswap op on each group of elements */
12366 int groups
= dsize
/ (8 << grp_size
);
12368 for (i
= 0; i
< groups
; i
++) {
12369 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12371 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12372 switch (grp_size
) {
12374 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
12377 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
12380 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12383 g_assert_not_reached();
12385 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12386 tcg_temp_free_i64(tcg_tmp
);
12388 clear_vec_high(s
, is_q
, rd
);
12390 int revmask
= (1 << grp_size
) - 1;
12391 int esize
= 8 << size
;
12392 int elements
= dsize
/ esize
;
12393 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12394 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12395 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12397 for (i
= 0; i
< elements
; i
++) {
12398 int e_rev
= (i
& 0xf) ^ revmask
;
12399 int off
= e_rev
* esize
;
12400 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12402 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12403 tcg_rn
, off
- 64, esize
);
12405 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12408 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12409 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12411 tcg_temp_free_i64(tcg_rd_hi
);
12412 tcg_temp_free_i64(tcg_rd
);
12413 tcg_temp_free_i64(tcg_rn
);
12417 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12418 bool is_q
, int size
, int rn
, int rd
)
12420 /* Implement the pairwise operations from 2-misc:
12421 * SADDLP, UADDLP, SADALP, UADALP.
12422 * These all add pairs of elements in the input to produce a
12423 * double-width result element in the output (possibly accumulating).
12425 bool accum
= (opcode
== 0x6);
12426 int maxpass
= is_q
? 2 : 1;
12428 TCGv_i64 tcg_res
[2];
12431 /* 32 + 32 -> 64 op */
12432 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12434 for (pass
= 0; pass
< maxpass
; pass
++) {
12435 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12436 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12438 tcg_res
[pass
] = tcg_temp_new_i64();
12440 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12441 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12442 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12444 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12445 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12448 tcg_temp_free_i64(tcg_op1
);
12449 tcg_temp_free_i64(tcg_op2
);
12452 for (pass
= 0; pass
< maxpass
; pass
++) {
12453 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12454 NeonGenOne64OpFn
*genfn
;
12455 static NeonGenOne64OpFn
* const fns
[2][2] = {
12456 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12457 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12460 genfn
= fns
[size
][u
];
12462 tcg_res
[pass
] = tcg_temp_new_i64();
12464 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12465 genfn(tcg_res
[pass
], tcg_op
);
12468 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12470 gen_helper_neon_addl_u16(tcg_res
[pass
],
12471 tcg_res
[pass
], tcg_op
);
12473 gen_helper_neon_addl_u32(tcg_res
[pass
],
12474 tcg_res
[pass
], tcg_op
);
12477 tcg_temp_free_i64(tcg_op
);
12481 tcg_res
[1] = tcg_const_i64(0);
12483 for (pass
= 0; pass
< 2; pass
++) {
12484 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12485 tcg_temp_free_i64(tcg_res
[pass
]);
12489 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12491 /* Implement SHLL and SHLL2 */
12493 int part
= is_q
? 2 : 0;
12494 TCGv_i64 tcg_res
[2];
12496 for (pass
= 0; pass
< 2; pass
++) {
12497 static NeonGenWidenFn
* const widenfns
[3] = {
12498 gen_helper_neon_widen_u8
,
12499 gen_helper_neon_widen_u16
,
12500 tcg_gen_extu_i32_i64
,
12502 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12503 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12505 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12506 tcg_res
[pass
] = tcg_temp_new_i64();
12507 widenfn(tcg_res
[pass
], tcg_op
);
12508 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12510 tcg_temp_free_i32(tcg_op
);
12513 for (pass
= 0; pass
< 2; pass
++) {
12514 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12515 tcg_temp_free_i64(tcg_res
[pass
]);
12519 /* AdvSIMD two reg misc
12520 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12521 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12522 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12523 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12525 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12527 int size
= extract32(insn
, 22, 2);
12528 int opcode
= extract32(insn
, 12, 5);
12529 bool u
= extract32(insn
, 29, 1);
12530 bool is_q
= extract32(insn
, 30, 1);
12531 int rn
= extract32(insn
, 5, 5);
12532 int rd
= extract32(insn
, 0, 5);
12533 bool need_fpstatus
= false;
12534 bool need_rmode
= false;
12536 TCGv_i32 tcg_rmode
;
12537 TCGv_ptr tcg_fpstatus
;
12540 case 0x0: /* REV64, REV32 */
12541 case 0x1: /* REV16 */
12542 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12544 case 0x5: /* CNT, NOT, RBIT */
12545 if (u
&& size
== 0) {
12548 } else if (u
&& size
== 1) {
12551 } else if (!u
&& size
== 0) {
12555 unallocated_encoding(s
);
12557 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12558 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12560 unallocated_encoding(s
);
12563 if (!fp_access_check(s
)) {
12567 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12569 case 0x4: /* CLS, CLZ */
12571 unallocated_encoding(s
);
12575 case 0x2: /* SADDLP, UADDLP */
12576 case 0x6: /* SADALP, UADALP */
12578 unallocated_encoding(s
);
12581 if (!fp_access_check(s
)) {
12584 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12586 case 0x13: /* SHLL, SHLL2 */
12587 if (u
== 0 || size
== 3) {
12588 unallocated_encoding(s
);
12591 if (!fp_access_check(s
)) {
12594 handle_shll(s
, is_q
, size
, rn
, rd
);
12596 case 0xa: /* CMLT */
12598 unallocated_encoding(s
);
12602 case 0x8: /* CMGT, CMGE */
12603 case 0x9: /* CMEQ, CMLE */
12604 case 0xb: /* ABS, NEG */
12605 if (size
== 3 && !is_q
) {
12606 unallocated_encoding(s
);
12610 case 0x3: /* SUQADD, USQADD */
12611 if (size
== 3 && !is_q
) {
12612 unallocated_encoding(s
);
12615 if (!fp_access_check(s
)) {
12618 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12620 case 0x7: /* SQABS, SQNEG */
12621 if (size
== 3 && !is_q
) {
12622 unallocated_encoding(s
);
12627 case 0x16 ... 0x1f:
12629 /* Floating point: U, size[1] and opcode indicate operation;
12630 * size[0] indicates single or double precision.
12632 int is_double
= extract32(size
, 0, 1);
12633 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12634 size
= is_double
? 3 : 2;
12636 case 0x2f: /* FABS */
12637 case 0x6f: /* FNEG */
12638 if (size
== 3 && !is_q
) {
12639 unallocated_encoding(s
);
12643 case 0x1d: /* SCVTF */
12644 case 0x5d: /* UCVTF */
12646 bool is_signed
= (opcode
== 0x1d) ? true : false;
12647 int elements
= is_double
? 2 : is_q
? 4 : 2;
12648 if (is_double
&& !is_q
) {
12649 unallocated_encoding(s
);
12652 if (!fp_access_check(s
)) {
12655 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12658 case 0x2c: /* FCMGT (zero) */
12659 case 0x2d: /* FCMEQ (zero) */
12660 case 0x2e: /* FCMLT (zero) */
12661 case 0x6c: /* FCMGE (zero) */
12662 case 0x6d: /* FCMLE (zero) */
12663 if (size
== 3 && !is_q
) {
12664 unallocated_encoding(s
);
12667 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12669 case 0x7f: /* FSQRT */
12670 if (size
== 3 && !is_q
) {
12671 unallocated_encoding(s
);
12675 case 0x1a: /* FCVTNS */
12676 case 0x1b: /* FCVTMS */
12677 case 0x3a: /* FCVTPS */
12678 case 0x3b: /* FCVTZS */
12679 case 0x5a: /* FCVTNU */
12680 case 0x5b: /* FCVTMU */
12681 case 0x7a: /* FCVTPU */
12682 case 0x7b: /* FCVTZU */
12683 need_fpstatus
= true;
12685 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12686 if (size
== 3 && !is_q
) {
12687 unallocated_encoding(s
);
12691 case 0x5c: /* FCVTAU */
12692 case 0x1c: /* FCVTAS */
12693 need_fpstatus
= true;
12695 rmode
= FPROUNDING_TIEAWAY
;
12696 if (size
== 3 && !is_q
) {
12697 unallocated_encoding(s
);
12701 case 0x3c: /* URECPE */
12703 unallocated_encoding(s
);
12707 case 0x3d: /* FRECPE */
12708 case 0x7d: /* FRSQRTE */
12709 if (size
== 3 && !is_q
) {
12710 unallocated_encoding(s
);
12713 if (!fp_access_check(s
)) {
12716 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12718 case 0x56: /* FCVTXN, FCVTXN2 */
12720 unallocated_encoding(s
);
12724 case 0x16: /* FCVTN, FCVTN2 */
12725 /* handle_2misc_narrow does a 2*size -> size operation, but these
12726 * instructions encode the source size rather than dest size.
12728 if (!fp_access_check(s
)) {
12731 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12733 case 0x17: /* FCVTL, FCVTL2 */
12734 if (!fp_access_check(s
)) {
12737 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12739 case 0x18: /* FRINTN */
12740 case 0x19: /* FRINTM */
12741 case 0x38: /* FRINTP */
12742 case 0x39: /* FRINTZ */
12744 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12746 case 0x59: /* FRINTX */
12747 case 0x79: /* FRINTI */
12748 need_fpstatus
= true;
12749 if (size
== 3 && !is_q
) {
12750 unallocated_encoding(s
);
12754 case 0x58: /* FRINTA */
12756 rmode
= FPROUNDING_TIEAWAY
;
12757 need_fpstatus
= true;
12758 if (size
== 3 && !is_q
) {
12759 unallocated_encoding(s
);
12763 case 0x7c: /* URSQRTE */
12765 unallocated_encoding(s
);
12769 case 0x1e: /* FRINT32Z */
12770 case 0x1f: /* FRINT64Z */
12772 rmode
= FPROUNDING_ZERO
;
12774 case 0x5e: /* FRINT32X */
12775 case 0x5f: /* FRINT64X */
12776 need_fpstatus
= true;
12777 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12778 unallocated_encoding(s
);
12783 unallocated_encoding(s
);
12789 unallocated_encoding(s
);
12793 if (!fp_access_check(s
)) {
12797 if (need_fpstatus
|| need_rmode
) {
12798 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12800 tcg_fpstatus
= NULL
;
12803 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12804 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12811 if (u
&& size
== 0) { /* NOT */
12812 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12816 case 0x8: /* CMGT, CMGE */
12818 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12820 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12823 case 0x9: /* CMEQ, CMLE */
12825 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12827 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12830 case 0xa: /* CMLT */
12831 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12834 if (u
) { /* ABS, NEG */
12835 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12837 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12843 /* All 64-bit element operations can be shared with scalar 2misc */
12846 /* Coverity claims (size == 3 && !is_q) has been eliminated
12847 * from all paths leading to here.
12849 tcg_debug_assert(is_q
);
12850 for (pass
= 0; pass
< 2; pass
++) {
12851 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12852 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12854 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12856 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12857 tcg_rmode
, tcg_fpstatus
);
12859 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12861 tcg_temp_free_i64(tcg_res
);
12862 tcg_temp_free_i64(tcg_op
);
12867 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12868 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12869 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12871 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12874 /* Special cases for 32 bit elements */
12876 case 0x4: /* CLS */
12878 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12880 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12883 case 0x7: /* SQABS, SQNEG */
12885 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12887 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12890 case 0x2f: /* FABS */
12891 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12893 case 0x6f: /* FNEG */
12894 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12896 case 0x7f: /* FSQRT */
12897 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12899 case 0x1a: /* FCVTNS */
12900 case 0x1b: /* FCVTMS */
12901 case 0x1c: /* FCVTAS */
12902 case 0x3a: /* FCVTPS */
12903 case 0x3b: /* FCVTZS */
12905 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12906 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12907 tcg_shift
, tcg_fpstatus
);
12908 tcg_temp_free_i32(tcg_shift
);
12911 case 0x5a: /* FCVTNU */
12912 case 0x5b: /* FCVTMU */
12913 case 0x5c: /* FCVTAU */
12914 case 0x7a: /* FCVTPU */
12915 case 0x7b: /* FCVTZU */
12917 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12918 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12919 tcg_shift
, tcg_fpstatus
);
12920 tcg_temp_free_i32(tcg_shift
);
12923 case 0x18: /* FRINTN */
12924 case 0x19: /* FRINTM */
12925 case 0x38: /* FRINTP */
12926 case 0x39: /* FRINTZ */
12927 case 0x58: /* FRINTA */
12928 case 0x79: /* FRINTI */
12929 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12931 case 0x59: /* FRINTX */
12932 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12934 case 0x7c: /* URSQRTE */
12935 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12937 case 0x1e: /* FRINT32Z */
12938 case 0x5e: /* FRINT32X */
12939 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12941 case 0x1f: /* FRINT64Z */
12942 case 0x5f: /* FRINT64X */
12943 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12946 g_assert_not_reached();
12949 /* Use helpers for 8 and 16 bit elements */
12951 case 0x5: /* CNT, RBIT */
12952 /* For these two insns size is part of the opcode specifier
12953 * (handled earlier); they always operate on byte elements.
12956 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12958 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12961 case 0x7: /* SQABS, SQNEG */
12963 NeonGenOneOpEnvFn
*genfn
;
12964 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12965 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12966 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12968 genfn
= fns
[size
][u
];
12969 genfn(tcg_res
, cpu_env
, tcg_op
);
12972 case 0x4: /* CLS, CLZ */
12975 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12977 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12981 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12983 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12988 g_assert_not_reached();
12992 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12994 tcg_temp_free_i32(tcg_res
);
12995 tcg_temp_free_i32(tcg_op
);
12998 clear_vec_high(s
, is_q
, rd
);
13001 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13002 tcg_temp_free_i32(tcg_rmode
);
13004 if (need_fpstatus
) {
13005 tcg_temp_free_ptr(tcg_fpstatus
);
13009 /* AdvSIMD [scalar] two register miscellaneous (FP16)
13011 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
13012 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13013 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
13014 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13015 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
13016 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
13018 * This actually covers two groups where scalar access is governed by
13019 * bit 28. A bunch of the instructions (float to integral) only exist
13020 * in the vector form and are un-allocated for the scalar decode. Also
13021 * in the scalar decode Q is always 1.
13023 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
13025 int fpop
, opcode
, a
, u
;
13029 bool only_in_vector
= false;
13032 TCGv_i32 tcg_rmode
= NULL
;
13033 TCGv_ptr tcg_fpstatus
= NULL
;
13034 bool need_rmode
= false;
13035 bool need_fpst
= true;
13038 if (!dc_isar_feature(aa64_fp16
, s
)) {
13039 unallocated_encoding(s
);
13043 rd
= extract32(insn
, 0, 5);
13044 rn
= extract32(insn
, 5, 5);
13046 a
= extract32(insn
, 23, 1);
13047 u
= extract32(insn
, 29, 1);
13048 is_scalar
= extract32(insn
, 28, 1);
13049 is_q
= extract32(insn
, 30, 1);
13051 opcode
= extract32(insn
, 12, 5);
13052 fpop
= deposit32(opcode
, 5, 1, a
);
13053 fpop
= deposit32(fpop
, 6, 1, u
);
13056 case 0x1d: /* SCVTF */
13057 case 0x5d: /* UCVTF */
13064 elements
= (is_q
? 8 : 4);
13067 if (!fp_access_check(s
)) {
13070 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13074 case 0x2c: /* FCMGT (zero) */
13075 case 0x2d: /* FCMEQ (zero) */
13076 case 0x2e: /* FCMLT (zero) */
13077 case 0x6c: /* FCMGE (zero) */
13078 case 0x6d: /* FCMLE (zero) */
13079 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13081 case 0x3d: /* FRECPE */
13082 case 0x3f: /* FRECPX */
13084 case 0x18: /* FRINTN */
13086 only_in_vector
= true;
13087 rmode
= FPROUNDING_TIEEVEN
;
13089 case 0x19: /* FRINTM */
13091 only_in_vector
= true;
13092 rmode
= FPROUNDING_NEGINF
;
13094 case 0x38: /* FRINTP */
13096 only_in_vector
= true;
13097 rmode
= FPROUNDING_POSINF
;
13099 case 0x39: /* FRINTZ */
13101 only_in_vector
= true;
13102 rmode
= FPROUNDING_ZERO
;
13104 case 0x58: /* FRINTA */
13106 only_in_vector
= true;
13107 rmode
= FPROUNDING_TIEAWAY
;
13109 case 0x59: /* FRINTX */
13110 case 0x79: /* FRINTI */
13111 only_in_vector
= true;
13112 /* current rounding mode */
13114 case 0x1a: /* FCVTNS */
13116 rmode
= FPROUNDING_TIEEVEN
;
13118 case 0x1b: /* FCVTMS */
13120 rmode
= FPROUNDING_NEGINF
;
13122 case 0x1c: /* FCVTAS */
13124 rmode
= FPROUNDING_TIEAWAY
;
13126 case 0x3a: /* FCVTPS */
13128 rmode
= FPROUNDING_POSINF
;
13130 case 0x3b: /* FCVTZS */
13132 rmode
= FPROUNDING_ZERO
;
13134 case 0x5a: /* FCVTNU */
13136 rmode
= FPROUNDING_TIEEVEN
;
13138 case 0x5b: /* FCVTMU */
13140 rmode
= FPROUNDING_NEGINF
;
13142 case 0x5c: /* FCVTAU */
13144 rmode
= FPROUNDING_TIEAWAY
;
13146 case 0x7a: /* FCVTPU */
13148 rmode
= FPROUNDING_POSINF
;
13150 case 0x7b: /* FCVTZU */
13152 rmode
= FPROUNDING_ZERO
;
13154 case 0x2f: /* FABS */
13155 case 0x6f: /* FNEG */
13158 case 0x7d: /* FRSQRTE */
13159 case 0x7f: /* FSQRT (vector) */
13162 fprintf(stderr
, "%s: insn 0x%04x fpop 0x%2x\n", __func__
, insn
, fpop
);
13163 g_assert_not_reached();
13167 /* Check additional constraints for the scalar encoding */
13170 unallocated_encoding(s
);
13173 /* FRINTxx is only in the vector form */
13174 if (only_in_vector
) {
13175 unallocated_encoding(s
);
13180 if (!fp_access_check(s
)) {
13184 if (need_rmode
|| need_fpst
) {
13185 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13189 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13190 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13194 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13195 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13198 case 0x1a: /* FCVTNS */
13199 case 0x1b: /* FCVTMS */
13200 case 0x1c: /* FCVTAS */
13201 case 0x3a: /* FCVTPS */
13202 case 0x3b: /* FCVTZS */
13203 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13205 case 0x3d: /* FRECPE */
13206 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13208 case 0x3f: /* FRECPX */
13209 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13211 case 0x5a: /* FCVTNU */
13212 case 0x5b: /* FCVTMU */
13213 case 0x5c: /* FCVTAU */
13214 case 0x7a: /* FCVTPU */
13215 case 0x7b: /* FCVTZU */
13216 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13218 case 0x6f: /* FNEG */
13219 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13221 case 0x7d: /* FRSQRTE */
13222 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13225 g_assert_not_reached();
13228 /* limit any sign extension going on */
13229 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13230 write_fp_sreg(s
, rd
, tcg_res
);
13232 tcg_temp_free_i32(tcg_res
);
13233 tcg_temp_free_i32(tcg_op
);
13235 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13236 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13237 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13239 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13242 case 0x1a: /* FCVTNS */
13243 case 0x1b: /* FCVTMS */
13244 case 0x1c: /* FCVTAS */
13245 case 0x3a: /* FCVTPS */
13246 case 0x3b: /* FCVTZS */
13247 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13249 case 0x3d: /* FRECPE */
13250 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13252 case 0x5a: /* FCVTNU */
13253 case 0x5b: /* FCVTMU */
13254 case 0x5c: /* FCVTAU */
13255 case 0x7a: /* FCVTPU */
13256 case 0x7b: /* FCVTZU */
13257 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13259 case 0x18: /* FRINTN */
13260 case 0x19: /* FRINTM */
13261 case 0x38: /* FRINTP */
13262 case 0x39: /* FRINTZ */
13263 case 0x58: /* FRINTA */
13264 case 0x79: /* FRINTI */
13265 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13267 case 0x59: /* FRINTX */
13268 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13270 case 0x2f: /* FABS */
13271 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13273 case 0x6f: /* FNEG */
13274 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13276 case 0x7d: /* FRSQRTE */
13277 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13279 case 0x7f: /* FSQRT */
13280 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13283 g_assert_not_reached();
13286 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13288 tcg_temp_free_i32(tcg_res
);
13289 tcg_temp_free_i32(tcg_op
);
13292 clear_vec_high(s
, is_q
, rd
);
13296 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13297 tcg_temp_free_i32(tcg_rmode
);
13300 if (tcg_fpstatus
) {
13301 tcg_temp_free_ptr(tcg_fpstatus
);
13305 /* AdvSIMD scalar x indexed element
13306 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13307 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13308 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13309 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13310 * AdvSIMD vector x indexed element
13311 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13312 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13313 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13314 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13316 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13318 /* This encoding has two kinds of instruction:
13319 * normal, where we perform elt x idxelt => elt for each
13320 * element in the vector
13321 * long, where we perform elt x idxelt and generate a result of
13322 * double the width of the input element
13323 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13325 bool is_scalar
= extract32(insn
, 28, 1);
13326 bool is_q
= extract32(insn
, 30, 1);
13327 bool u
= extract32(insn
, 29, 1);
13328 int size
= extract32(insn
, 22, 2);
13329 int l
= extract32(insn
, 21, 1);
13330 int m
= extract32(insn
, 20, 1);
13331 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13332 int rm
= extract32(insn
, 16, 4);
13333 int opcode
= extract32(insn
, 12, 4);
13334 int h
= extract32(insn
, 11, 1);
13335 int rn
= extract32(insn
, 5, 5);
13336 int rd
= extract32(insn
, 0, 5);
13337 bool is_long
= false;
13339 bool is_fp16
= false;
13343 switch (16 * u
+ opcode
) {
13344 case 0x08: /* MUL */
13345 case 0x10: /* MLA */
13346 case 0x14: /* MLS */
13348 unallocated_encoding(s
);
13352 case 0x02: /* SMLAL, SMLAL2 */
13353 case 0x12: /* UMLAL, UMLAL2 */
13354 case 0x06: /* SMLSL, SMLSL2 */
13355 case 0x16: /* UMLSL, UMLSL2 */
13356 case 0x0a: /* SMULL, SMULL2 */
13357 case 0x1a: /* UMULL, UMULL2 */
13359 unallocated_encoding(s
);
13364 case 0x03: /* SQDMLAL, SQDMLAL2 */
13365 case 0x07: /* SQDMLSL, SQDMLSL2 */
13366 case 0x0b: /* SQDMULL, SQDMULL2 */
13369 case 0x0c: /* SQDMULH */
13370 case 0x0d: /* SQRDMULH */
13372 case 0x01: /* FMLA */
13373 case 0x05: /* FMLS */
13374 case 0x09: /* FMUL */
13375 case 0x19: /* FMULX */
13378 case 0x1d: /* SQRDMLAH */
13379 case 0x1f: /* SQRDMLSH */
13380 if (!dc_isar_feature(aa64_rdm
, s
)) {
13381 unallocated_encoding(s
);
13385 case 0x0e: /* SDOT */
13386 case 0x1e: /* UDOT */
13387 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13388 unallocated_encoding(s
);
13392 case 0x0f: /* SUDOT, USDOT */
13393 if (is_scalar
|| (size
& 1) || !dc_isar_feature(aa64_i8mm
, s
)) {
13394 unallocated_encoding(s
);
13399 case 0x11: /* FCMLA #0 */
13400 case 0x13: /* FCMLA #90 */
13401 case 0x15: /* FCMLA #180 */
13402 case 0x17: /* FCMLA #270 */
13403 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13404 unallocated_encoding(s
);
13409 case 0x00: /* FMLAL */
13410 case 0x04: /* FMLSL */
13411 case 0x18: /* FMLAL2 */
13412 case 0x1c: /* FMLSL2 */
13413 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13414 unallocated_encoding(s
);
13418 /* is_fp, but we pass cpu_env not fp_status. */
13421 unallocated_encoding(s
);
13426 case 1: /* normal fp */
13427 /* convert insn encoded size to MemOp size */
13429 case 0: /* half-precision */
13433 case MO_32
: /* single precision */
13434 case MO_64
: /* double precision */
13437 unallocated_encoding(s
);
13442 case 2: /* complex fp */
13443 /* Each indexable element is a complex pair. */
13448 unallocated_encoding(s
);
13456 unallocated_encoding(s
);
13461 default: /* integer */
13465 unallocated_encoding(s
);
13470 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13471 unallocated_encoding(s
);
13475 /* Given MemOp size, adjust register and indexing. */
13478 index
= h
<< 2 | l
<< 1 | m
;
13481 index
= h
<< 1 | l
;
13486 unallocated_encoding(s
);
13493 g_assert_not_reached();
13496 if (!fp_access_check(s
)) {
13501 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13506 switch (16 * u
+ opcode
) {
13507 case 0x0e: /* SDOT */
13508 case 0x1e: /* UDOT */
13509 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13510 u
? gen_helper_gvec_udot_idx_b
13511 : gen_helper_gvec_sdot_idx_b
);
13513 case 0x0f: /* SUDOT, USDOT */
13514 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13515 extract32(insn
, 23, 1)
13516 ? gen_helper_gvec_usdot_idx_b
13517 : gen_helper_gvec_sudot_idx_b
);
13520 case 0x11: /* FCMLA #0 */
13521 case 0x13: /* FCMLA #90 */
13522 case 0x15: /* FCMLA #180 */
13523 case 0x17: /* FCMLA #270 */
13525 int rot
= extract32(insn
, 13, 2);
13526 int data
= (index
<< 2) | rot
;
13527 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
13528 vec_full_reg_offset(s
, rn
),
13529 vec_full_reg_offset(s
, rm
),
13530 vec_full_reg_offset(s
, rd
), fpst
,
13531 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13533 ? gen_helper_gvec_fcmlas_idx
13534 : gen_helper_gvec_fcmlah_idx
);
13535 tcg_temp_free_ptr(fpst
);
13539 case 0x00: /* FMLAL */
13540 case 0x04: /* FMLSL */
13541 case 0x18: /* FMLAL2 */
13542 case 0x1c: /* FMLSL2 */
13544 int is_s
= extract32(opcode
, 2, 1);
13546 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13547 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13548 vec_full_reg_offset(s
, rn
),
13549 vec_full_reg_offset(s
, rm
), cpu_env
,
13550 is_q
? 16 : 8, vec_full_reg_size(s
),
13551 data
, gen_helper_gvec_fmlal_idx_a64
);
13555 case 0x08: /* MUL */
13556 if (!is_long
&& !is_scalar
) {
13557 static gen_helper_gvec_3
* const fns
[3] = {
13558 gen_helper_gvec_mul_idx_h
,
13559 gen_helper_gvec_mul_idx_s
,
13560 gen_helper_gvec_mul_idx_d
,
13562 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13563 vec_full_reg_offset(s
, rn
),
13564 vec_full_reg_offset(s
, rm
),
13565 is_q
? 16 : 8, vec_full_reg_size(s
),
13566 index
, fns
[size
- 1]);
13571 case 0x10: /* MLA */
13572 if (!is_long
&& !is_scalar
) {
13573 static gen_helper_gvec_4
* const fns
[3] = {
13574 gen_helper_gvec_mla_idx_h
,
13575 gen_helper_gvec_mla_idx_s
,
13576 gen_helper_gvec_mla_idx_d
,
13578 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13579 vec_full_reg_offset(s
, rn
),
13580 vec_full_reg_offset(s
, rm
),
13581 vec_full_reg_offset(s
, rd
),
13582 is_q
? 16 : 8, vec_full_reg_size(s
),
13583 index
, fns
[size
- 1]);
13588 case 0x14: /* MLS */
13589 if (!is_long
&& !is_scalar
) {
13590 static gen_helper_gvec_4
* const fns
[3] = {
13591 gen_helper_gvec_mls_idx_h
,
13592 gen_helper_gvec_mls_idx_s
,
13593 gen_helper_gvec_mls_idx_d
,
13595 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13596 vec_full_reg_offset(s
, rn
),
13597 vec_full_reg_offset(s
, rm
),
13598 vec_full_reg_offset(s
, rd
),
13599 is_q
? 16 : 8, vec_full_reg_size(s
),
13600 index
, fns
[size
- 1]);
13607 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13610 assert(is_fp
&& is_q
&& !is_long
);
13612 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13614 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13615 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13616 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13618 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13620 switch (16 * u
+ opcode
) {
13621 case 0x05: /* FMLS */
13622 /* As usual for ARM, separate negation for fused multiply-add */
13623 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13625 case 0x01: /* FMLA */
13626 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13627 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13629 case 0x09: /* FMUL */
13630 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13632 case 0x19: /* FMULX */
13633 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13636 g_assert_not_reached();
13639 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13640 tcg_temp_free_i64(tcg_op
);
13641 tcg_temp_free_i64(tcg_res
);
13644 tcg_temp_free_i64(tcg_idx
);
13645 clear_vec_high(s
, !is_scalar
, rd
);
13646 } else if (!is_long
) {
13647 /* 32 bit floating point, or 16 or 32 bit integer.
13648 * For the 16 bit scalar case we use the usual Neon helpers and
13649 * rely on the fact that 0 op 0 == 0 with no side effects.
13651 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13652 int pass
, maxpasses
;
13657 maxpasses
= is_q
? 4 : 2;
13660 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13662 if (size
== 1 && !is_scalar
) {
13663 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13664 * the index into both halves of the 32 bit tcg_idx and then use
13665 * the usual Neon helpers.
13667 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13670 for (pass
= 0; pass
< maxpasses
; pass
++) {
13671 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13672 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13674 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13676 switch (16 * u
+ opcode
) {
13677 case 0x08: /* MUL */
13678 case 0x10: /* MLA */
13679 case 0x14: /* MLS */
13681 static NeonGenTwoOpFn
* const fns
[2][2] = {
13682 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13683 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13685 NeonGenTwoOpFn
*genfn
;
13686 bool is_sub
= opcode
== 0x4;
13689 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13691 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13693 if (opcode
== 0x8) {
13696 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13697 genfn
= fns
[size
- 1][is_sub
];
13698 genfn(tcg_res
, tcg_op
, tcg_res
);
13701 case 0x05: /* FMLS */
13702 case 0x01: /* FMLA */
13703 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13704 is_scalar
? size
: MO_32
);
13707 if (opcode
== 0x5) {
13708 /* As usual for ARM, separate negation for fused
13710 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13713 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13716 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13721 if (opcode
== 0x5) {
13722 /* As usual for ARM, separate negation for
13723 * fused multiply-add */
13724 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13726 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13730 g_assert_not_reached();
13733 case 0x09: /* FMUL */
13737 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13740 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13745 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13748 g_assert_not_reached();
13751 case 0x19: /* FMULX */
13755 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13758 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13763 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13766 g_assert_not_reached();
13769 case 0x0c: /* SQDMULH */
13771 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13774 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13778 case 0x0d: /* SQRDMULH */
13780 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13783 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13787 case 0x1d: /* SQRDMLAH */
13788 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13789 is_scalar
? size
: MO_32
);
13791 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13792 tcg_op
, tcg_idx
, tcg_res
);
13794 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13795 tcg_op
, tcg_idx
, tcg_res
);
13798 case 0x1f: /* SQRDMLSH */
13799 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13800 is_scalar
? size
: MO_32
);
13802 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13803 tcg_op
, tcg_idx
, tcg_res
);
13805 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13806 tcg_op
, tcg_idx
, tcg_res
);
13810 g_assert_not_reached();
13814 write_fp_sreg(s
, rd
, tcg_res
);
13816 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13819 tcg_temp_free_i32(tcg_op
);
13820 tcg_temp_free_i32(tcg_res
);
13823 tcg_temp_free_i32(tcg_idx
);
13824 clear_vec_high(s
, is_q
, rd
);
13826 /* long ops: 16x16->32 or 32x32->64 */
13827 TCGv_i64 tcg_res
[2];
13829 bool satop
= extract32(opcode
, 0, 1);
13830 MemOp memop
= MO_32
;
13837 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13839 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13841 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13842 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13843 TCGv_i64 tcg_passres
;
13849 passelt
= pass
+ (is_q
* 2);
13852 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13854 tcg_res
[pass
] = tcg_temp_new_i64();
13856 if (opcode
== 0xa || opcode
== 0xb) {
13857 /* Non-accumulating ops */
13858 tcg_passres
= tcg_res
[pass
];
13860 tcg_passres
= tcg_temp_new_i64();
13863 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13864 tcg_temp_free_i64(tcg_op
);
13867 /* saturating, doubling */
13868 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13869 tcg_passres
, tcg_passres
);
13872 if (opcode
== 0xa || opcode
== 0xb) {
13876 /* Accumulating op: handle accumulate step */
13877 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13880 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13881 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13883 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13884 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13886 case 0x7: /* SQDMLSL, SQDMLSL2 */
13887 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13889 case 0x3: /* SQDMLAL, SQDMLAL2 */
13890 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13895 g_assert_not_reached();
13897 tcg_temp_free_i64(tcg_passres
);
13899 tcg_temp_free_i64(tcg_idx
);
13901 clear_vec_high(s
, !is_scalar
, rd
);
13903 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13906 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13909 /* The simplest way to handle the 16x16 indexed ops is to
13910 * duplicate the index into both halves of the 32 bit tcg_idx
13911 * and then use the usual Neon helpers.
13913 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13916 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13917 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13918 TCGv_i64 tcg_passres
;
13921 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13923 read_vec_element_i32(s
, tcg_op
, rn
,
13924 pass
+ (is_q
* 2), MO_32
);
13927 tcg_res
[pass
] = tcg_temp_new_i64();
13929 if (opcode
== 0xa || opcode
== 0xb) {
13930 /* Non-accumulating ops */
13931 tcg_passres
= tcg_res
[pass
];
13933 tcg_passres
= tcg_temp_new_i64();
13936 if (memop
& MO_SIGN
) {
13937 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13939 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13942 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13943 tcg_passres
, tcg_passres
);
13945 tcg_temp_free_i32(tcg_op
);
13947 if (opcode
== 0xa || opcode
== 0xb) {
13951 /* Accumulating op: handle accumulate step */
13952 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13955 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13956 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13959 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13960 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13963 case 0x7: /* SQDMLSL, SQDMLSL2 */
13964 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13966 case 0x3: /* SQDMLAL, SQDMLAL2 */
13967 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13972 g_assert_not_reached();
13974 tcg_temp_free_i64(tcg_passres
);
13976 tcg_temp_free_i32(tcg_idx
);
13979 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13984 tcg_res
[1] = tcg_const_i64(0);
13987 for (pass
= 0; pass
< 2; pass
++) {
13988 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13989 tcg_temp_free_i64(tcg_res
[pass
]);
13994 tcg_temp_free_ptr(fpst
);
13999 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14000 * +-----------------+------+-----------+--------+-----+------+------+
14001 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14002 * +-----------------+------+-----------+--------+-----+------+------+
14004 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
14006 int size
= extract32(insn
, 22, 2);
14007 int opcode
= extract32(insn
, 12, 5);
14008 int rn
= extract32(insn
, 5, 5);
14009 int rd
= extract32(insn
, 0, 5);
14011 gen_helper_gvec_2
*genfn2
= NULL
;
14012 gen_helper_gvec_3
*genfn3
= NULL
;
14014 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
14015 unallocated_encoding(s
);
14020 case 0x4: /* AESE */
14022 genfn3
= gen_helper_crypto_aese
;
14024 case 0x6: /* AESMC */
14026 genfn2
= gen_helper_crypto_aesmc
;
14028 case 0x5: /* AESD */
14030 genfn3
= gen_helper_crypto_aese
;
14032 case 0x7: /* AESIMC */
14034 genfn2
= gen_helper_crypto_aesmc
;
14037 unallocated_encoding(s
);
14041 if (!fp_access_check(s
)) {
14045 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
14047 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
14051 /* Crypto three-reg SHA
14052 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
14053 * +-----------------+------+---+------+---+--------+-----+------+------+
14054 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
14055 * +-----------------+------+---+------+---+--------+-----+------+------+
14057 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
14059 int size
= extract32(insn
, 22, 2);
14060 int opcode
= extract32(insn
, 12, 3);
14061 int rm
= extract32(insn
, 16, 5);
14062 int rn
= extract32(insn
, 5, 5);
14063 int rd
= extract32(insn
, 0, 5);
14064 gen_helper_gvec_3
*genfn
;
14068 unallocated_encoding(s
);
14073 case 0: /* SHA1C */
14074 genfn
= gen_helper_crypto_sha1c
;
14075 feature
= dc_isar_feature(aa64_sha1
, s
);
14077 case 1: /* SHA1P */
14078 genfn
= gen_helper_crypto_sha1p
;
14079 feature
= dc_isar_feature(aa64_sha1
, s
);
14081 case 2: /* SHA1M */
14082 genfn
= gen_helper_crypto_sha1m
;
14083 feature
= dc_isar_feature(aa64_sha1
, s
);
14085 case 3: /* SHA1SU0 */
14086 genfn
= gen_helper_crypto_sha1su0
;
14087 feature
= dc_isar_feature(aa64_sha1
, s
);
14089 case 4: /* SHA256H */
14090 genfn
= gen_helper_crypto_sha256h
;
14091 feature
= dc_isar_feature(aa64_sha256
, s
);
14093 case 5: /* SHA256H2 */
14094 genfn
= gen_helper_crypto_sha256h2
;
14095 feature
= dc_isar_feature(aa64_sha256
, s
);
14097 case 6: /* SHA256SU1 */
14098 genfn
= gen_helper_crypto_sha256su1
;
14099 feature
= dc_isar_feature(aa64_sha256
, s
);
14102 unallocated_encoding(s
);
14107 unallocated_encoding(s
);
14111 if (!fp_access_check(s
)) {
14114 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14117 /* Crypto two-reg SHA
14118 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14119 * +-----------------+------+-----------+--------+-----+------+------+
14120 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14121 * +-----------------+------+-----------+--------+-----+------+------+
14123 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14125 int size
= extract32(insn
, 22, 2);
14126 int opcode
= extract32(insn
, 12, 5);
14127 int rn
= extract32(insn
, 5, 5);
14128 int rd
= extract32(insn
, 0, 5);
14129 gen_helper_gvec_2
*genfn
;
14133 unallocated_encoding(s
);
14138 case 0: /* SHA1H */
14139 feature
= dc_isar_feature(aa64_sha1
, s
);
14140 genfn
= gen_helper_crypto_sha1h
;
14142 case 1: /* SHA1SU1 */
14143 feature
= dc_isar_feature(aa64_sha1
, s
);
14144 genfn
= gen_helper_crypto_sha1su1
;
14146 case 2: /* SHA256SU0 */
14147 feature
= dc_isar_feature(aa64_sha256
, s
);
14148 genfn
= gen_helper_crypto_sha256su0
;
14151 unallocated_encoding(s
);
14156 unallocated_encoding(s
);
14160 if (!fp_access_check(s
)) {
14163 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14166 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14168 tcg_gen_rotli_i64(d
, m
, 1);
14169 tcg_gen_xor_i64(d
, d
, n
);
14172 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14174 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14175 tcg_gen_xor_vec(vece
, d
, d
, n
);
14178 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14179 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14181 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14182 static const GVecGen3 op
= {
14183 .fni8
= gen_rax1_i64
,
14184 .fniv
= gen_rax1_vec
,
14185 .opt_opc
= vecop_list
,
14186 .fno
= gen_helper_crypto_rax1
,
14189 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14192 /* Crypto three-reg SHA512
14193 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14194 * +-----------------------+------+---+---+-----+--------+------+------+
14195 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14196 * +-----------------------+------+---+---+-----+--------+------+------+
14198 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14200 int opcode
= extract32(insn
, 10, 2);
14201 int o
= extract32(insn
, 14, 1);
14202 int rm
= extract32(insn
, 16, 5);
14203 int rn
= extract32(insn
, 5, 5);
14204 int rd
= extract32(insn
, 0, 5);
14206 gen_helper_gvec_3
*oolfn
= NULL
;
14207 GVecGen3Fn
*gvecfn
= NULL
;
14211 case 0: /* SHA512H */
14212 feature
= dc_isar_feature(aa64_sha512
, s
);
14213 oolfn
= gen_helper_crypto_sha512h
;
14215 case 1: /* SHA512H2 */
14216 feature
= dc_isar_feature(aa64_sha512
, s
);
14217 oolfn
= gen_helper_crypto_sha512h2
;
14219 case 2: /* SHA512SU1 */
14220 feature
= dc_isar_feature(aa64_sha512
, s
);
14221 oolfn
= gen_helper_crypto_sha512su1
;
14224 feature
= dc_isar_feature(aa64_sha3
, s
);
14225 gvecfn
= gen_gvec_rax1
;
14228 g_assert_not_reached();
14232 case 0: /* SM3PARTW1 */
14233 feature
= dc_isar_feature(aa64_sm3
, s
);
14234 oolfn
= gen_helper_crypto_sm3partw1
;
14236 case 1: /* SM3PARTW2 */
14237 feature
= dc_isar_feature(aa64_sm3
, s
);
14238 oolfn
= gen_helper_crypto_sm3partw2
;
14240 case 2: /* SM4EKEY */
14241 feature
= dc_isar_feature(aa64_sm4
, s
);
14242 oolfn
= gen_helper_crypto_sm4ekey
;
14245 unallocated_encoding(s
);
14251 unallocated_encoding(s
);
14255 if (!fp_access_check(s
)) {
14260 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14262 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14266 /* Crypto two-reg SHA512
14267 * 31 12 11 10 9 5 4 0
14268 * +-----------------------------------------+--------+------+------+
14269 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14270 * +-----------------------------------------+--------+------+------+
14272 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14274 int opcode
= extract32(insn
, 10, 2);
14275 int rn
= extract32(insn
, 5, 5);
14276 int rd
= extract32(insn
, 0, 5);
14280 case 0: /* SHA512SU0 */
14281 feature
= dc_isar_feature(aa64_sha512
, s
);
14284 feature
= dc_isar_feature(aa64_sm4
, s
);
14287 unallocated_encoding(s
);
14292 unallocated_encoding(s
);
14296 if (!fp_access_check(s
)) {
14301 case 0: /* SHA512SU0 */
14302 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14305 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14308 g_assert_not_reached();
14312 /* Crypto four-register
14313 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14314 * +-------------------+-----+------+---+------+------+------+
14315 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14316 * +-------------------+-----+------+---+------+------+------+
14318 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14320 int op0
= extract32(insn
, 21, 2);
14321 int rm
= extract32(insn
, 16, 5);
14322 int ra
= extract32(insn
, 10, 5);
14323 int rn
= extract32(insn
, 5, 5);
14324 int rd
= extract32(insn
, 0, 5);
14330 feature
= dc_isar_feature(aa64_sha3
, s
);
14332 case 2: /* SM3SS1 */
14333 feature
= dc_isar_feature(aa64_sm3
, s
);
14336 unallocated_encoding(s
);
14341 unallocated_encoding(s
);
14345 if (!fp_access_check(s
)) {
14350 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14353 tcg_op1
= tcg_temp_new_i64();
14354 tcg_op2
= tcg_temp_new_i64();
14355 tcg_op3
= tcg_temp_new_i64();
14356 tcg_res
[0] = tcg_temp_new_i64();
14357 tcg_res
[1] = tcg_temp_new_i64();
14359 for (pass
= 0; pass
< 2; pass
++) {
14360 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14361 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14362 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14366 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14369 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14371 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14373 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14374 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14376 tcg_temp_free_i64(tcg_op1
);
14377 tcg_temp_free_i64(tcg_op2
);
14378 tcg_temp_free_i64(tcg_op3
);
14379 tcg_temp_free_i64(tcg_res
[0]);
14380 tcg_temp_free_i64(tcg_res
[1]);
14382 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14384 tcg_op1
= tcg_temp_new_i32();
14385 tcg_op2
= tcg_temp_new_i32();
14386 tcg_op3
= tcg_temp_new_i32();
14387 tcg_res
= tcg_temp_new_i32();
14388 tcg_zero
= tcg_const_i32(0);
14390 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14391 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14392 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14394 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14395 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14396 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14397 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14399 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14400 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14401 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14402 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14404 tcg_temp_free_i32(tcg_op1
);
14405 tcg_temp_free_i32(tcg_op2
);
14406 tcg_temp_free_i32(tcg_op3
);
14407 tcg_temp_free_i32(tcg_res
);
14408 tcg_temp_free_i32(tcg_zero
);
14413 * 31 21 20 16 15 10 9 5 4 0
14414 * +-----------------------+------+--------+------+------+
14415 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14416 * +-----------------------+------+--------+------+------+
14418 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14420 int rm
= extract32(insn
, 16, 5);
14421 int imm6
= extract32(insn
, 10, 6);
14422 int rn
= extract32(insn
, 5, 5);
14423 int rd
= extract32(insn
, 0, 5);
14425 if (!dc_isar_feature(aa64_sha3
, s
)) {
14426 unallocated_encoding(s
);
14430 if (!fp_access_check(s
)) {
14434 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
14435 vec_full_reg_offset(s
, rn
),
14436 vec_full_reg_offset(s
, rm
), imm6
, 16,
14437 vec_full_reg_size(s
));
14440 /* Crypto three-reg imm2
14441 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14442 * +-----------------------+------+-----+------+--------+------+------+
14443 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14444 * +-----------------------+------+-----+------+--------+------+------+
14446 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14448 static gen_helper_gvec_3
* const fns
[4] = {
14449 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14450 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14452 int opcode
= extract32(insn
, 10, 2);
14453 int imm2
= extract32(insn
, 12, 2);
14454 int rm
= extract32(insn
, 16, 5);
14455 int rn
= extract32(insn
, 5, 5);
14456 int rd
= extract32(insn
, 0, 5);
14458 if (!dc_isar_feature(aa64_sm3
, s
)) {
14459 unallocated_encoding(s
);
14463 if (!fp_access_check(s
)) {
14467 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14470 /* C3.6 Data processing - SIMD, inc Crypto
14472 * As the decode gets a little complex we are using a table based
14473 * approach for this part of the decode.
14475 static const AArch64DecodeTable data_proc_simd
[] = {
14476 /* pattern , mask , fn */
14477 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14478 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14479 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14480 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14481 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14482 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14483 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14484 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14485 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14486 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14487 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14488 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14489 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14490 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14491 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14492 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14493 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14494 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14495 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14496 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14497 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14498 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14499 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14500 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14501 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14502 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14503 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14504 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14505 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14506 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14507 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14508 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14509 { 0x00000000, 0x00000000, NULL
}
14512 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14514 /* Note that this is called with all non-FP cases from
14515 * table C3-6 so it must UNDEF for entries not specifically
14516 * allocated to instructions in that table.
14518 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14522 unallocated_encoding(s
);
14526 /* C3.6 Data processing - SIMD and floating point */
14527 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14529 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14530 disas_data_proc_fp(s
, insn
);
14532 /* SIMD, including crypto */
14533 disas_data_proc_simd(s
, insn
);
14539 * @env: The cpu environment
14540 * @s: The DisasContext
14542 * Return true if the page is guarded.
14544 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14546 uint64_t addr
= s
->base
.pc_first
;
14547 #ifdef CONFIG_USER_ONLY
14548 return page_get_flags(addr
) & PAGE_BTI
;
14550 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14551 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14552 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14555 * We test this immediately after reading an insn, which means
14556 * that any normal page must be in the TLB. The only exception
14557 * would be for executing from flash or device memory, which
14558 * does not retain the TLB entry.
14560 * FIXME: Assume false for those, for now. We could use
14561 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14562 * table entry even for that case.
14564 return (tlb_hit(entry
->addr_code
, addr
) &&
14565 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14570 * btype_destination_ok:
14571 * @insn: The instruction at the branch destination
14572 * @bt: SCTLR_ELx.BT
14573 * @btype: PSTATE.BTYPE, and is non-zero
14575 * On a guarded page, there are a limited number of insns
14576 * that may be present at the branch target:
14577 * - branch target identifiers,
14578 * - paciasp, pacibsp,
14581 * Anything else causes a Branch Target Exception.
14583 * Return true if the branch is compatible, false to raise BTITRAP.
14585 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14587 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14589 switch (extract32(insn
, 5, 7)) {
14590 case 0b011001: /* PACIASP */
14591 case 0b011011: /* PACIBSP */
14593 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14594 * with btype == 3. Otherwise all btype are ok.
14596 return !bt
|| btype
!= 3;
14597 case 0b100000: /* BTI */
14598 /* Not compatible with any btype. */
14600 case 0b100010: /* BTI c */
14601 /* Not compatible with btype == 3 */
14603 case 0b100100: /* BTI j */
14604 /* Not compatible with btype == 2 */
14606 case 0b100110: /* BTI jc */
14607 /* Compatible with any btype. */
14611 switch (insn
& 0xffe0001fu
) {
14612 case 0xd4200000u
: /* BRK */
14613 case 0xd4400000u
: /* HLT */
14614 /* Give priority to the breakpoint exception. */
14621 /* C3.1 A64 instruction index by encoding */
14622 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14626 s
->pc_curr
= s
->base
.pc_next
;
14627 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14629 s
->base
.pc_next
+= 4;
14631 s
->fp_access_checked
= false;
14632 s
->sve_access_checked
= false;
14634 if (dc_isar_feature(aa64_bti
, s
)) {
14635 if (s
->base
.num_insns
== 1) {
14637 * At the first insn of the TB, compute s->guarded_page.
14638 * We delayed computing this until successfully reading
14639 * the first insn of the TB, above. This (mostly) ensures
14640 * that the softmmu tlb entry has been populated, and the
14641 * page table GP bit is available.
14643 * Note that we need to compute this even if btype == 0,
14644 * because this value is used for BR instructions later
14645 * where ENV is not available.
14647 s
->guarded_page
= is_guarded_page(env
, s
);
14649 /* First insn can have btype set to non-zero. */
14650 tcg_debug_assert(s
->btype
>= 0);
14653 * Note that the Branch Target Exception has fairly high
14654 * priority -- below debugging exceptions but above most
14655 * everything else. This allows us to handle this now
14656 * instead of waiting until the insn is otherwise decoded.
14660 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14661 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14662 syn_btitrap(s
->btype
),
14663 default_exception_el(s
));
14667 /* Not the first insn: btype must be 0. */
14668 tcg_debug_assert(s
->btype
== 0);
14672 switch (extract32(insn
, 25, 4)) {
14673 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14674 unallocated_encoding(s
);
14677 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14678 unallocated_encoding(s
);
14681 case 0x8: case 0x9: /* Data processing - immediate */
14682 disas_data_proc_imm(s
, insn
);
14684 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14685 disas_b_exc_sys(s
, insn
);
14690 case 0xe: /* Loads and stores */
14691 disas_ldst(s
, insn
);
14694 case 0xd: /* Data processing - register */
14695 disas_data_proc_reg(s
, insn
);
14698 case 0xf: /* Data processing - SIMD and floating point */
14699 disas_data_proc_simd_fp(s
, insn
);
14702 assert(FALSE
); /* all 15 cases should be handled above */
14706 /* if we allocated any temporaries, free them here */
14710 * After execution of most insns, btype is reset to 0.
14711 * Note that we set btype == -1 when the insn sets btype.
14713 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14718 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14721 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14722 CPUARMState
*env
= cpu
->env_ptr
;
14723 ARMCPU
*arm_cpu
= env_archcpu(env
);
14724 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14725 int bound
, core_mmu_idx
;
14727 dc
->isar
= &arm_cpu
->isar
;
14731 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14732 * there is no secure EL1, so we route exceptions to EL3.
14734 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14735 !arm_el_is_aa64(env
, 3);
14738 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14739 dc
->condexec_mask
= 0;
14740 dc
->condexec_cond
= 0;
14741 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14742 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14743 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14744 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14745 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14746 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14747 #if !defined(CONFIG_USER_ONLY)
14748 dc
->user
= (dc
->current_el
== 0);
14750 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14751 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14752 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14753 dc
->sve_len
= (EX_TBFLAG_A64(tb_flags
, ZCR_LEN
) + 1) * 16;
14754 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14755 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14756 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14757 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14758 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14759 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14760 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14762 dc
->vec_stride
= 0;
14763 dc
->cp_regs
= arm_cpu
->cp_regs
;
14764 dc
->features
= env
->features
;
14765 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14767 #ifdef CONFIG_USER_ONLY
14768 /* In sve_probe_page, we assume TBI is enabled. */
14769 tcg_debug_assert(dc
->tbid
& 1);
14772 /* Single step state. The code-generation logic here is:
14774 * generate code with no special handling for single-stepping (except
14775 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14776 * this happens anyway because those changes are all system register or
14778 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14779 * emit code for one insn
14780 * emit code to clear PSTATE.SS
14781 * emit code to generate software step exception for completed step
14782 * end TB (as usual for having generated an exception)
14783 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14784 * emit code to generate a software step exception
14787 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14788 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14789 dc
->is_ldex
= false;
14790 dc
->debug_target_el
= EX_TBFLAG_ANY(tb_flags
, DEBUG_TARGET_EL
);
14792 /* Bound the number of insns to execute to those left on the page. */
14793 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14795 /* If architectural single step active, limit to 1. */
14796 if (dc
->ss_active
) {
14799 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14801 init_tmp_a64_array(dc
);
14804 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14808 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14810 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14812 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14813 dc
->insn_start
= tcg_last_op();
14816 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14817 const CPUBreakpoint
*bp
)
14819 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14821 if (bp
->flags
& BP_CPU
) {
14822 gen_a64_set_pc_im(dc
->base
.pc_next
);
14823 gen_helper_check_breakpoints(cpu_env
);
14824 /* End the TB early; it likely won't be executed */
14825 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14827 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14828 /* The address covered by the breakpoint must be
14829 included in [tb->pc, tb->pc + tb->size) in order
14830 to for it to be properly cleared -- thus we
14831 increment the PC here so that the logic setting
14832 tb->size below does the right thing. */
14833 dc
->base
.pc_next
+= 4;
14834 dc
->base
.is_jmp
= DISAS_NORETURN
;
14840 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14842 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14843 CPUARMState
*env
= cpu
->env_ptr
;
14845 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14846 /* Singlestep state is Active-pending.
14847 * If we're in this state at the start of a TB then either
14848 * a) we just took an exception to an EL which is being debugged
14849 * and this is the first insn in the exception handler
14850 * b) debug exceptions were masked and we just unmasked them
14851 * without changing EL (eg by clearing PSTATE.D)
14852 * In either case we're going to take a swstep exception in the
14853 * "did not step an insn" case, and so the syndrome ISV and EX
14854 * bits should be zero.
14856 assert(dc
->base
.num_insns
== 1);
14857 gen_swstep_exception(dc
, 0, 0);
14858 dc
->base
.is_jmp
= DISAS_NORETURN
;
14860 disas_a64_insn(env
, dc
);
14863 translator_loop_temp_check(&dc
->base
);
14866 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14868 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14870 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14871 /* Note that this means single stepping WFI doesn't halt the CPU.
14872 * For conditional branch insns this is harmless unreachable code as
14873 * gen_goto_tb() has already handled emitting the debug exception
14874 * (and thus a tb-jump is not possible when singlestepping).
14876 switch (dc
->base
.is_jmp
) {
14878 gen_a64_set_pc_im(dc
->base
.pc_next
);
14882 if (dc
->base
.singlestep_enabled
) {
14883 gen_exception_internal(EXCP_DEBUG
);
14885 gen_step_complete_exception(dc
);
14888 case DISAS_NORETURN
:
14892 switch (dc
->base
.is_jmp
) {
14894 case DISAS_TOO_MANY
:
14895 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14898 case DISAS_UPDATE_EXIT
:
14899 gen_a64_set_pc_im(dc
->base
.pc_next
);
14902 tcg_gen_exit_tb(NULL
, 0);
14904 case DISAS_UPDATE_NOCHAIN
:
14905 gen_a64_set_pc_im(dc
->base
.pc_next
);
14908 tcg_gen_lookup_and_goto_ptr();
14910 case DISAS_NORETURN
:
14914 gen_a64_set_pc_im(dc
->base
.pc_next
);
14915 gen_helper_wfe(cpu_env
);
14918 gen_a64_set_pc_im(dc
->base
.pc_next
);
14919 gen_helper_yield(cpu_env
);
14923 /* This is a special case because we don't want to just halt the CPU
14924 * if trying to debug across a WFI.
14926 TCGv_i32 tmp
= tcg_const_i32(4);
14928 gen_a64_set_pc_im(dc
->base
.pc_next
);
14929 gen_helper_wfi(cpu_env
, tmp
);
14930 tcg_temp_free_i32(tmp
);
14931 /* The helper doesn't necessarily throw an exception, but we
14932 * must go back to the main loop to check for interrupts anyway.
14934 tcg_gen_exit_tb(NULL
, 0);
14941 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14944 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14946 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14947 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14950 const TranslatorOps aarch64_translator_ops
= {
14951 .init_disas_context
= aarch64_tr_init_disas_context
,
14952 .tb_start
= aarch64_tr_tb_start
,
14953 .insn_start
= aarch64_tr_insn_start
,
14954 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14955 .translate_insn
= aarch64_tr_translate_insn
,
14956 .tb_stop
= aarch64_tr_tb_stop
,
14957 .disas_log
= aarch64_tr_disas_log
,